Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of a semiconductor device and the semiconductor device, and the method comprises the steps: manufacturing a first wafer which comprises a base layer and a target structure layer, the first side of the base layer is provided with an accommodation groove, and the target structure layer is partially or completely located in the accommodation groove; dividing the target structure layer into a normal area and a deviation area according to the height of the upper surface of the target structure layer relative to the first side; according to the deviation of the height of the deviation area on the first wafer relative to the height of the normal area, the volume of the accommodating groove corresponding to the deviation area on the second wafer is correspondingly designed; and manufacturing a second wafer, wherein at least the part of the target structure layer of the second wafer and the part of the target structure layer of the first wafer are manufactured under the same process condition. By increasing or reducing the volume of the accommodating groove on the second wafer, the height of the upper surface of the target structure layer can be controlled, the film thickness consistency of the target structure layer is improved, and the yield of the semiconductor device is improved.

Description

[0001] This application is a divisional application filed on November 16, 2023, with application number 202311535788.1 and invention name “Method for manufacturing semiconductor device and semiconductor device”. Technical Field

[0002] The present application belongs to the field of semiconductor manufacturing technology, and specifically relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0003] When manufacturing semiconductor devices, it is often necessary to form a target structure layer on a substrate or one or more structure layers on the substrate. A groove is formed on the substrate or one or more structure layers on the substrate, and the target structure layer is partially or completely formed in the groove.

[0004] Limited by the groove structure of the substrate or one or more structural layers on the substrate, and the manufacturing process of the target structural layer, the film layer height consistency of the target structural layer is poor, resulting in a decrease in the yield of the semiconductor device. Summary of the invention

[0005] The purpose of the present application is to provide a method for manufacturing a semiconductor device and a semiconductor device, so as to improve the yield rate of the semiconductor device.

[0006] In order to achieve the above object, the present application provides a method for manufacturing a semiconductor device, comprising:

[0007] Produce a first wafer, the first wafer is a wafer sample, the first wafer includes a transistor, the transistor includes a base layer and a target structure layer formed on one side of the base layer, a receiving groove is provided on the first side of the base layer, the target structure layer is partially or completely located in the receiving groove, the target structure layer includes a silicon germanium body, the transistor includes a gate, the gate is located on the first side, a gap is formed between adjacent gates, an overflow portion of the silicon germanium body is located in the gap between adjacent gates, the silicon germanium body includes a seed layer and an epitaxial layer, the seed layer is formed on the inner side wall of the receiving groove, the epitaxial layer is formed in the seed layer and outside the receiving groove, the epitaxial layer is formed by an epitaxial growth process, and the epitaxial layer of the second wafer and the epitaxial layer of the first wafer are produced by the same process conditions;

[0008] Dividing the target structure layer into a normal area and a deviation area according to the height of the upper surface of the target structure layer relative to the first side, wherein the height of the deviation area is greater than or less than the height of the normal area;

[0009] According to the deviation of the height of the deviation area on the first wafer relative to the height of the normal area, the volume of the receiving groove corresponding to the deviation area on the second wafer is designed accordingly, and the second wafer is a positive wafer;

[0010] The second wafer is manufactured, and at least a portion of the target structure layer of the second wafer and a portion of the target structure layer of the first wafer are manufactured using the same process conditions.

[0011] Optionally, the target structure layer is partially located in the accommodating groove, and the accommodating groove is a rectangular groove or a convex hexagonal groove. The target structure layer includes a buried portion and an overflow portion, the buried portion is buried in the base layer, and the overflow portion is exposed on the first side. The height of the target structure layer relative to the first side is equal to the thickness of the overflow portion.

[0012] Optionally, the volume of the receiving groove corresponding to the deviation area on the correspondingly designed second wafer includes:

[0013] Setting a thickness H_bulk1 of the overflow portion corresponding to the deviation area when manufacturing the second wafer;

[0014] Calculate the cross-sectional area S_bulk1 of the overflow portion in the extending direction of the gap between adjacent gates according to the thickness H_bulk1 of the overflow portion;

[0015] The cross-sectional area S_Trench1 of the receiving trench on the second wafer in the direction of extension of the gap between adjacent gates is calculated according to the cross-sectional area S_SiGe of the silicon germanium body in the direction of extension of the gap between adjacent gates and the cross-sectional area S_bulk1 of the overflow portion.

[0016] Optionally, the accommodating groove is a convex hexagonal groove, and the cross-sectional area S_bulk1 of the overflow portion is:

[0017]

[0018] Wherein, OP is the width of the gap between adjacent gates, and α is the top angle of the overflow portion.

[0019] Optionally, the cross-sectional area S_Trench1 of the accommodating groove is:

[0020] S_Trench1=S_SiGe-S_bulk1.

[0021] Optionally, the cross-sectional areas S_Trench1 and L_Trench1 of the accommodating grooves meet the following formula:

[0022]

[0023] Wherein, L_Trench0 is the cross-sectional perimeter of the receiving groove corresponding to the deviation area of ​​the first wafer in the extending direction of the gap between adjacent gates, and L_Trench1 is the cross-sectional perimeter of the receiving groove corresponding to the deviation area of ​​the second wafer in the extending direction of the gap between adjacent gates.

[0024] Optionally, the gate includes a gate electrode and a side wall between the gate electrode and the receiving groove, the receiving groove is a convex hexagonal groove, and the cross-sectional perimeter L_Trench of the receiving groove in the extension direction of the gap between adjacent gates is calculated by the following perimeter calculation formula:

[0025]

[0026] Wherein, BCD is the length of the lower side of the cross section of the receiving groove, S2G is the width of the side wall, T2G is the distance between the receiving groove and the gate electrode in the gap width direction between adjacent gates, RCD is the depth of the receiving groove, the receiving groove includes an upper isosceles trapezoidal area away from the base layer and a lower isosceles trapezoidal area close to the base layer, and SMD is the height of the upper isosceles trapezoidal area;

[0027] The cross-sectional perimeter L_Trench0 and the cross-sectional perimeter L_Trench1 are both calculated using the perimeter calculation formula.

[0028] Optionally, the volume of the receiving groove corresponding to the deviation area on the correspondingly designed second wafer includes:

[0029] Calculating the cross-sectional perimeter L_Trench1 of the receiving groove according to the cross-sectional area S_Trench1, and calculating the cross-sectional perimeter L_Trench0 of the receiving groove of the first wafer;

[0030] Substitute the cross-sectional perimeter L_Trench1 and the cross-sectional perimeter L_Trench0 into the calculation formula of the cross-sectional area S_Trench1 of the receiving groove to calculate the expected cross-sectional area S_bulk1 of the overflow portion;

[0031] When the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements, the accommodating groove is formed according to the cross-sectional area S_Trench1 of the accommodating groove; when the expected cross-sectional area S_bulk1 of the overflow portion does not meet the design requirements, the thickness H_bulk1 of the overflow portion and the corresponding cross-sectional area S_bulk1 of the overflow portion are redesigned until the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements.

[0032] Optionally, the deviation area includes a thin area, and the corresponding design of the volume of the receiving groove corresponding to the deviation area on the second wafer includes: reducing the volume of the receiving groove corresponding to the thin area on the second wafer;

[0033] Alternatively, the deviation area includes a thicker area, and the corresponding design of the volume of the receiving groove corresponding to the deviation area on the second wafer includes: increasing the volume of the receiving groove corresponding to the thicker area on the second wafer.

[0034] Optionally, the deviation area includes a thicker area and a thinner area, and the process for forming the target structure layer includes chemical vapor deposition or physical vapor deposition; before the volume of the receiving groove corresponding to the deviation area on the correspondingly designed second wafer is determined, the steps are as follows:

[0035] When the thinned area of ​​the target structure layer of at least the first wafer is 0, the method for manufacturing the semiconductor device includes:

[0036] reducing the thickness of the target structure layer formed when manufacturing the second wafer, and then dividing the normal area and the deviation area according to the target structure layer to be formed;

[0037] When the thickest area of ​​the target structure layer of at least the first wafer is 0, the method for manufacturing the semiconductor device includes:

[0038] increasing the thickness of the target structure layer formed when manufacturing the second wafer, and then dividing the normal area and the deviation area according to the target structure layer expected to be formed;

[0039] The method for adjusting the thickness of the target structure layer formed when manufacturing the second wafer includes adjusting the time for forming the target structure layer, the reaction temperature for forming the target structure layer, and the reaction gas flow rate.

[0040] The present application also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method.

[0041] The semiconductor device manufacturing method and the semiconductor device disclosed in the present application have the following beneficial effects:

[0042] The manufacturing method of the semiconductor device in the present application includes: manufacturing a first wafer, the first wafer includes a base layer and a target structure layer, a first side of the base layer is provided with a receiving groove, and the target structure layer is partially or completely located in the receiving groove; according to the height of the upper surface of the target structure layer relative to the first side, the target structure layer is divided into a normal area and a deviation area; according to the height of the deviation area of ​​the target structure layer on the first wafer, the volume of the receiving groove corresponding to the deviation area on the second wafer is designed; and then the second wafer is manufactured using the same process conditions. Since the target structure layers of the first wafer and the second wafer are manufactured using the same process conditions, the volume distributions of the two are approximately equal. By increasing or decreasing the volume of the receiving groove on the second wafer, the upper surface height of the target structure layer can be controlled so that almost all areas of the target structure layer are within the value range of the normal area, that is, the consistency of the film thickness of the target structure layer is improved, thereby improving the yield of the semiconductor device.

[0043] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0044] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 It is a flow chart of a method for manufacturing a semiconductor device in an embodiment of the present application.

[0047] Figure 2 It is a schematic diagram of the structure of a semiconductor device in an embodiment of the present application.

[0048] Figure 3 It is a schematic diagram of the target structure layer partitioning of the first wafer in the embodiment of the present application.

[0049] Figure 4 It is a schematic diagram of the structure of a semiconductor device having a P-type transistor in an embodiment of the present application.

[0050] Figure 5 It is a schematic diagram of forming a silicon germanium body in an embodiment of the present application.

[0051] Description of reference numerals:

[0052] 100, substrate; 101, first side; 110, receiving groove;

[0053] 200, target structure layer; 201, normal area; 202, thin area; 203, thick area; 210, seed layer; 220, epitaxial layer; 221, buried part; 222, overflow part;

[0054] 300, gate insulating layer; 400, gate electrode; 500, sidewall; 600, cap; 700, metal layer;

[0055] 10. Wafer; 20. Reaction chamber. DETAILED DESCRIPTION

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0057] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0058] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0059] See also Figure 1 and Figure 2 As shown, the method for manufacturing a semiconductor device in this embodiment includes:

[0060] S100: Produce a first wafer, the first wafer includes a transistor, the transistor includes a base layer and a target structure layer 200 formed on a first side of the base layer, a first side 101 of the base layer is provided with a receiving groove 110, and the target structure layer 200 is partially or completely located in the receiving groove 110.

[0061] The base layer may include a substrate 100, that is, the target structure layer 200 may be directly formed on the substrate 100; the base layer may also include a substrate 100 and one or more functional layers formed on the substrate 100, and the target structure layer 200 is formed on the functional layer on a side away from the substrate 100. The target structure layer 200 may be formed by processes such as chemical vapor deposition and physical vapor deposition, and chemical vapor deposition includes epitaxial growth. In this embodiment, the specific formation process of the target structure layer 200 is not limited.

[0062] S200 : dividing the target structure layer 200 into a normal area 201 and a deviation area according to the height of the upper surface of the target structure layer 200 relative to the first side 101 , wherein the height of the deviation area is greater than or less than the height of the normal area 201 .

[0063] It should be noted that, in this embodiment, the height of the target structure layer 200 and the height of its normal area 201 and deviation area all refer to the height relative to the first side 101. The upper surface of the target structure layer 200 may be higher or lower than the first side 101. When the upper surface of the target structure layer 200 is higher than the first side 101, the height of the upper surface of the target structure layer 200 relative to the first side 101 is a positive value; when the upper surface of the target structure layer 200 is lower than the first side 101, the height of the upper surface of the target structure layer 200 relative to the first side 101 is a negative value. The normal area 201 is the value range of the height of the upper surface of the target structure layer 200 relative to the first side 101 when the semiconductor device is qualified. On the first wafer, the area of ​​the target structure layer 200 located in the normal area 201 is greater than or equal to 0.

[0064] S300 : Designing the volume of the receiving groove 110 corresponding to the deviation area on the second wafer according to the deviation of the height of the deviation area on the first wafer relative to the height of the normal area 201 .

[0065] The first wafer is a wafer sample or a wafer produced in a previous batch, and the second wafer is a wafer positive or a wafer produced in a subsequent batch. The upper surface height of the target structure layer 200 may be higher than the upper limit of the value interval or lower than the lower limit of the value interval, and the volume of the receiving groove 110 corresponding to the deviation area on the second wafer is designed accordingly, that is, the volume of the receiving groove 110 corresponding to the deviation area on the second wafer is increased or decreased.

[0066] S400: manufacturing a second wafer, wherein at least a portion of the target structure layer 200 of the second wafer and a portion of the target structure layer 200 of the first wafer are manufactured using the same process conditions.

[0067] The same process conditions include the same film forming equipment, the same process method and the same process parameters, but are not limited thereto, as long as the target structure layer 200 with the same morphological structure can be formed.

[0068] It should be noted that the target structure layer 200 can be a structure layer formed by one process, and the target structure layer 200 can also be two or more structure layers formed by two or more processes. At least part of the target structure layer 200 of the second wafer and part of the target structure layer 200 of the first wafer are made using the same process conditions, that is, when the target structure layer 200 includes two or more structure layers, at least one of the structure layers is made using the same process conditions.

[0069] During the manufacturing of existing semiconductor devices, due to the fact that the receiving grooves of the substrate 100 or one or more functional layers on the substrate 100 are groove structures and the manufacturing process of the target structure layer 200, the film thickness consistency of the target structure layer 200 is poor, resulting in a decrease in the yield of the semiconductor device.

[0070] The method for manufacturing a semiconductor device in this embodiment includes: manufacturing a first wafer, the first wafer including a base layer and a target structure layer 200, a first side 101 of the base layer is provided with a receiving groove 110, and the target structure layer 200 is partially or completely located in the receiving groove 110; dividing the target structure layer 200 into a normal area 201 and a deviation area according to the height of the upper surface of the target structure layer 200 relative to the first side 101; designing the volume of the receiving groove 110 corresponding to the deviation area on the second wafer according to the height of the deviation area of ​​the target structure layer 200 on the first wafer; and then manufacturing a second wafer using the same process conditions. Since the target structure layers 200 of the first wafer and the second wafer are manufactured using the same process conditions, the volume distributions of the two are approximately equal. By increasing or decreasing the volume of the receiving groove 110 corresponding to the deviation area on the second wafer, the upper surface height of the target structure layer 200 can be controlled, so that almost all areas of the target structure layer 200 are within the value range of the normal area 201, that is, the consistency of the film thickness of the target structure layer 200 is improved, thereby improving the yield of the semiconductor device.

[0071] In some embodiments, the target structure layer 200 is partially located in the receiving groove 110. The target structure layer 200 includes a buried portion 221 and an overflow portion 222, wherein the buried portion 221 is buried in the base layer, and the overflow portion 222 is exposed at the first side 101 of the base layer, and the height of the target structure layer 200 relative to the first side 101 is equal to the thickness of the overflow portion 222.

[0072] The target structure layer 200 includes a buried portion 221 and an overflow portion 222. The buried portion 221 fills the receiving groove 110. At this time, by increasing or decreasing the volume of the receiving groove 110 on the second wafer and controlling the thickness of the overflow portion 222, the thickness of the overflow portion 222 can be more accurately controlled.

[0073] In some embodiments, the deviation region includes a thin region 202, and the volume of the receiving groove 110 corresponding to the deviation region on the second wafer is designed to include:

[0074] The volume of the receiving groove 110 corresponding to the thinned area 202 on the second wafer is reduced.

[0075] In addition, the deviation area also includes a thicker area 203, and the volume of the corresponding accommodating groove 110 of the deviation area on the second wafer is designed to include:

[0076] The volume of the receiving groove 110 corresponding to the thicker area 203 on the second wafer is increased.

[0077] Since the target structure layer 200 of the first wafer and the second wafer are manufactured under the same process conditions, the volume distribution of the two is approximately equal. For the thin area 202 of the target structure layer 200, the volume of the receiving groove 110 corresponding to the thin area 202 is reduced when manufacturing the second wafer, which can reduce the volume of the buried portion 221 of the corresponding thin area 202 of the target structure layer 200, thereby increasing the thickness of the overflow portion 222 of the corresponding thin area 202 of the target structure layer 200; Thick area 203, when making the second wafer, the volume of the accommodating groove 110 corresponding to the thin area 202 is increased, which can increase the volume of the buried part 221 of the target structure layer 200 corresponding to the thin area 202, thereby reducing the thickness of the overflow part 222 of the target structure layer 200 corresponding to the thick area 203, thereby improving the thickness uniformity of the overflow part 222, so that almost all areas of the target structure layer 200 of the second wafer are within the value range of the normal area 201, thereby improving the yield of the semiconductor device.

[0078] In some embodiments, when at least the thin area 202 of the target structure layer 200 is 0 and the thick area 203 is not 0, before designing the volume of the accommodating groove 110 corresponding to the deviation area on the second wafer, the method for manufacturing the semiconductor device includes: reducing the thickness of the target structure layer 200 formed when manufacturing the second wafer, and then dividing the normal area 201 and the deviation area according to the target structure layer 200 to be formed.

[0079] At least the thin area 202 of the target structure layer 200 of the first wafer is 0, that is, the target structure layer 200 has a normal area 201 and a thick area 203, or the target structure layer 200 is thick as a whole. At this time, the time for forming the target structure layer 200 when making the second wafer can be reduced to reduce the thickness of the target structure layer 200, and then the normal area 201 and the deviation area are divided according to the expected target structure layer 200. The thickness of the overflow part 222 is adjusted by adjusting the volume of the accommodating groove 110 to reduce the thickness of the overflow part 222 of the corresponding thick area 203 of the target structure layer 200, so that almost all areas of the target structure layer 200 are within the value range of the normal area 201.

[0080] Correspondingly, when the thick area 203 of the target structure layer 200 of at least the first wafer is 0 and the thin area 202 is not 0, before designing the volume of the accommodating groove 110 corresponding to the deviation area on the second wafer, the method for manufacturing the semiconductor device includes: increasing the thickness of the target structure layer 200 formed when manufacturing the second wafer.

[0081] At least the thick area 203 of the target structural layer 200 is 0, that is, the target structural layer 200 has a normal area 201 and a thin area 202, or the target structural layer 200 is thin as a whole. At this time, the time for forming the target structural layer 200 when making the second wafer can be increased to increase the thickness of the target structural layer 200, and then the normal area 201 and the deviation area are divided according to the expected target structural layer 200. The thickness of the overflow part 222 is adjusted by adjusting the volume of the accommodating groove 110, and the thickness of the overflow part 222 of the target structural layer 200 corresponding to the thin area 202 is increased, so that almost all areas of the target structural layer 200 are within the value range of the normal area 201.

[0082] It should be noted that the thickness of the target structure layer 200 is mainly affected by the formation time of the target structure layer 200. The thickness of the target structure layer 200 can be adjusted by increasing or decreasing the time for forming the target structure layer 200, but is not limited to this. The thickness of the target structure layer 200 can also be adjusted by adjusting the temperature, reaction gas flow rate, etc., depending on the specific situation.

[0083] By means of the above, the adjustment ratio of the receiving groove 110 in the thicker area 203 and the thinner area 202 is reduced, thereby reducing the process difficulty of adjusting the size of the receiving groove 110. For example, when the size of the receiving groove 110 changes slightly, the control difficulty of the etching process for forming the receiving groove 110 is reduced.

[0084] For example, in order to achieve stronger performance, semiconductor devices are moving towards smaller feature sizes and higher component density. Therefore, the gate of the metal-oxide-semiconductor field-effect transistor (MOS) has become thinner and shorter than before, affecting the electrical performance of the semiconductor device. At the same time, limited by the inherent characteristics of silicon materials, the speed of devices based on silicon processes has approached the physical limit.

[0085] The use of embedded silicon germanium (Embedded SiGe) technology to manufacture P-type metal oxide semiconductor transistors (PMOS, hereinafter referred to as P-type transistors) can enhance the carrier mobility of P-type transistors, thereby greatly improving the performance of P-type transistors and P-type transistor semiconductor devices.

[0086] See also Figure 4In the illustrated embodiment, the P-type transistor semiconductor device is fabricated using embedded silicon germanium technology. The P-type transistor semiconductor device includes a channel located in a substrate 100, a silicon germanium body (SiGe) as a source and drain, and a gate. The substrate 100 is a single crystal material. The gate includes a gate insulating layer 300 and a gate electrode 400. Optionally, the gate also includes a sidewall 500. Optionally, the PMOS also includes a cap 600 and a metal layer 700. The gate electrode 400 is formed on a first side 101 of the substrate 100, the gate insulating layer 300 is formed between the gate electrode 400 and the substrate 100, and the sidewall 500 is formed on both sides of the gate electrode 400. A receiving groove 110 as a source and drain trench is formed on both sides of the gate, that is, on both sides of the gate electrode 400 and its sidewall 500.

[0087] Exemplarily, the receiving groove 110 is formed by anisotropic wet etching. Since the substrate 100 or the functional material layer on the substrate 100, that is, the base layer, is a single crystal material, and different crystal orientations have different etching rates under the same etchant, a polygonal source-drain trench is generated. Figure 4 In the embodiment shown, the source-drain groove is a convex hexagonal groove, commonly known as a sigma groove, and the silicon germanium body is at least partially formed in the convex hexagonal groove. In other embodiments, according to different crystal orientations of the substrate 100, the source-drain groove can also be formed as a rectangular groove, that is, the sidewall of the source-drain groove is perpendicular to the bottom surface.

[0088] The cap 600 is formed on the side of the silicon germanium body away from the substrate 100, and the metal layer 700 is formed on the side of the cap 600 and the gate electrode 400 away from the substrate 100. The cap 600 is, for example, a highly doped single crystal silicon layer, and the dopant includes, for example, boron. The material of the metal layer 700 includes, for example, at least one of refractory metals such as nickel (Ni), tungsten (W), and titanium (Ti). Optionally, the metal layer 700 undergoes a silicidation reaction with the cap 600 and the gate electrode 400 made of polysilicon to form a metal silicide, thereby improving the contact between the metal and the source and drain regions and the gate electrode. In other embodiments, the metal layer 700 is in direct contact with the target structure layer 200, and forms a metal silicide through a silicidation reaction.

[0089] When manufacturing a P-type transistor semiconductor device, a gate insulating layer 300, a gate electrode 400 and a spacer 500 are first formed on a substrate 100, a convex hexagonal groove and a silicon germanium body are then formed, and finally a cap 600 and a metal layer 700 are formed. The silicon germanium body can be formed by an epitaxial growth process.

[0090] See also Figure 5As shown, the wafer 10 is placed in the reaction chamber 20 of the epitaxial growth equipment, and the reaction gas is introduced from one side of the first direction and flows out from the other side of the first direction. Affected by many conditions such as reaction temperature, temperature field, gas flow rate and gas flow field, the thickness consistency of the silicon germanium body film layer is poor. Especially in the edge area of ​​the wafer 10, the consistency difference of the silicon germanium body film layer is more obvious. Some epitaxial growth equipment can introduce a small amount of reaction gas along the second direction, and the second direction is perpendicular to the first direction, but the introduction of reaction gas along the second direction can only improve the thickness consistency of the silicon germanium body film layer in the edge area of ​​the wafer 10 to a certain extent.

[0091] The applicant has found that when the height of the upper surface of the silicon germanium body is low, for example, its height after epitaxy is lower than the first side 101 of the substrate 100, or the silicidation reaction between the metal layer 700 and the target structure layer 200 consumes more thickness of the target structure layer 200, so that the upper surface of the target structure layer 200 after the silicidation reaction is lower than the first side 101 of the substrate 100, or after the silicidation reaction between the metal layer 700 and the cap 600 consumes all of the cap 600, it further consumes too much thickness of the target structure layer 200, so that the upper surface of the target structure layer 200 after the silicidation reaction is lower than the first side 101 of the substrate 100, the metal ions in the metal layer 700 are easily diffused into the channel between the adjacent silicon germanium bodies, resulting in a decrease in the yield of the P-type transistor semiconductor device. In addition to the upper surface of the target structure layer 200 being lower than the first side 101 of the substrate 100, when the thickness of the overflow portion 222 is insufficient, the metal ions in the metal layer 700 are also easily diffused into the channel between the adjacent silicon germanium bodies.

[0092] When the method for manufacturing a semiconductor device in this embodiment is used to manufacture a P-type transistor semiconductor device, the receiving groove 110 is a convex hexagonal groove, and the target structure layer 200 includes a silicon germanium body. The transistor includes a gate, which is located on the first side 101 of the substrate 100, and a gap is formed between adjacent gates, and the overflow portion 222 of the silicon germanium body is located in the gap between adjacent gates. The target structure layer 200 includes a silicon germanium body, and the lower limit of the value range of the normal area 201 of the target structure layer 200 is greater than 0, that is, the thickness of the overflow portion 222 is greater than 0. It can be understood that when the height of the upper surface of the target structure layer 200 relative to the first side 101 is outside the value range of the normal area 201, it is a deviation area.

[0093] The method for manufacturing a semiconductor device in this embodiment is used to manufacture the silicon germanium body of a P-type transistor semiconductor device, which can ensure that the upper surface of the silicon germanium body is uniformly higher than the first side 101 of the substrate 100, avoid the overflow portion 222 being too thin, and prevent the metal ions in the metal layer 700 from diffusing into the channel between adjacent silicon germanium bodies, thereby improving the yield of the P-type transistor semiconductor device.

[0094] See also Figure 2 and Figure 4As shown, the silicon germanium body includes a seed layer 210 and an epitaxial layer 220. The seed layer 210 is formed on the inner side wall of the receiving groove 110, and the epitaxial layer 220 is formed in the seed layer 210 and outside the receiving groove 110. The epitaxial layer 220 is formed by an epitaxial growth process, and at least the epitaxial layer 220 of the second wafer and the epitaxial layer 220 of the first wafer are made by the same process conditions. The overflow portion 222 is the portion of the epitaxial layer 220 located outside the receiving groove 110, and the buried portion 221 includes the portion of the epitaxial layer 220 located inside the receiving groove 110 and the seed layer 210.

[0095] Since the volume of the epitaxial layer 220 in the SiGe body is larger than that of the seed layer 210 , the epitaxial layer 220 of the second wafer and the epitaxial layer 220 of the first wafer are made using the same process conditions, which can ensure that the volume distribution of the SiGe body remains approximately unchanged.

[0096] See also Figure 1 and Figure 2 As shown, the volume of the corresponding accommodating groove 110 of the deviation area on the second wafer is designed to include:

[0097] When manufacturing the second wafer, the thickness H_bulk1 of the overflow portion 222 corresponding to the deviation area is set;

[0098] According to the thickness H_bulk1 of the overflow portion 222 , the cross-sectional area S_bulk1 of the overflow portion 222 in the extending direction of the gap between adjacent gate electrodes is calculated;

[0099] The cross-sectional area S_Trench1 of the second on-wafer receiving trench 110 in the direction of extension of the gap between adjacent gates is calculated according to the cross-sectional area S_SiGe of the silicon germanium body in the direction of extension of the gap between adjacent gates and the cross-sectional area S_bulk1 of the overflow portion 222 .

[0100] The silicon germanium body of the first wafer and the silicon germanium body of the second wafer are made using the same process conditions, and the volume distribution of the two is approximately equal. By adjusting the volume of the receiving groove 110 corresponding to the deviation area, the thickness H_bulk1 of the overflow portion 222 can be adjusted to be within the value range of the normal area 201. The cross-sectional area S_Trench1 of the receiving groove 110 is equal to the cross-sectional area of ​​the buried portion 221, and the cross-sectional area S_Trench1 of the receiving groove 110 can be calculated based on the cross-sectional area S_bulk1 of the overflow portion 222. The length of the receiving groove 110 along the extension direction of the gap between adjacent gates is almost unchanged, so the volume of the receiving groove 110 is determined by the cross-sectional area of ​​the receiving groove 110.

[0101] In this embodiment, the receiving groove 110 is a convex hexagonal groove, and the receiving groove 110 includes an upper isosceles trapezoidal area away from the substrate 100 and a lower isosceles trapezoidal area close to the substrate 100. The cross-sectional area S_Trench of the receiving groove 110 is calculated as follows:

[0102]

[0103] Among them, OP is the width of the gap between the gates, that is, the upper side length of the cross section of the accommodating groove 110, BCD is the lower side length of the cross section of the accommodating groove 110, S2G is the width of the side wall 500, T2G is the distance between the accommodating groove 110 and the gate electrode 400 in the direction of the gap width between adjacent gates, RCD is the depth of the accommodating groove 110, and SMD is the height of the upper isosceles trapezoidal area.

[0104] According to the above cross-sectional area calculation formula of the receiving groove 110, the cross-sectional area S_Trench0 of the receiving groove 110 of the first wafer can be calculated, and the depth RCD of the receiving groove 110 can also be calculated according to the cross-sectional area S_Trench1 of the receiving groove 110 of the second wafer. The reasons are as follows:

[0105] Since the sidewall 500 is hardly etched during the etching of the receiving groove 110, the width OP of the gap between adjacent gates is almost unchanged before and after the etching of the receiving groove 110. The receiving groove 110 is formed by etching the upper surface of the substrate 100 exposed by the adjacent gates, and the etching method is, for example, anisotropic wet etching. Since the substrate 100 or the functional material layer on the substrate 100, that is, the base layer, is a single crystal material, when anisotropic wet etchants, such as TMAH, are used, the etching rates of substrates 100 with different crystal orientations are very different under the same etchant, thus producing a polygonal receiving groove 110. Figure 2 In the illustrated embodiment, the receiving groove 110 is a convex hexagon, and the inclination angles of the sides of the convex hexagon are all related to the crystal orientation, that is, they have a fixed inclination angle relative to the surface of the substrate 100. According to the above geometric relationship, the lower side length BCD of the cross section of the receiving groove 110, the width S2G of the sidewall 500, the distance T2G between the receiving groove 110 and the gate electrode 400 in the gap width direction between adjacent gates, the depth RCD of the receiving groove 110, and the height SMD of the upper isosceles trapezoidal area are all related dimensions. According to the cross-sectional area S_Trench1 of the receiving groove 110 of the second wafer, the etching depth RCD of the receiving groove 110 can be calculated.

[0106] In summary, the thickness H_bulk1 of the overflow portion 222 is set when manufacturing the second wafer, and the cross-sectional area S_Trench1 of the receiving groove 110 is calculated according to the thickness H_bulk1 of the overflow portion 222. The etching depth RCD of the receiving groove 110 can be further calculated. The receiving groove 110 is etched according to the etching depth RCD of the receiving groove 110. For example, the etching depth can be controlled by controlling the etching time, the etchant concentration distribution, and the regional etching. The distribution range of the silicon germanium body in the value range of the normal area 201 can be increased, thereby improving the yield of the P-type transistor semiconductor device.

[0107] In some embodiments, the cross-sectional area S_bulk1 of the overflow portion 222 is:

[0108]

[0109] For the first wafer, OP is the width of the gap between adjacent gates, and α is the top angle of the overflow portion 222. When at least the epitaxial layer 220 in the target structure layer 200 is prepared by an epitaxial process, the crystal orientation of the epitaxial layer 220 may be related to the crystal orientation of the substrate 100, so the top angle α of the epitaxial layer 220 formed is a fixed value related to the crystal orientation of the substrate 100. In other embodiments, the angle of the top angle α of the epitaxial layer 220 may change due to the deposition process or other adjustment means, and the present invention is not specifically limited, but it can be understood that the same top angle α should be generated under the same process conditions.

[0110] The SiGe body of the first wafer and the SiGe body of the second wafer are manufactured using the same process conditions, and the top angles of the overflow portions 222 of the two are approximately equal. Therefore, the cross-sectional area S_bulk1 of the overflow portion 222 can be calculated according to the thickness H_bulk1 of the overflow portion 222 set when manufacturing the second wafer.

[0111] For example, the cross-sectional area S_Trench1 of the receiving groove 110 is:

[0112] S_Trench1=S_SiGe-S_bulk1.

[0113] The cross-sectional area S_Trench1 of the receiving groove 110 is calculated by subtracting the cross-sectional area S_bulk1 of the overflow portion 222 from the cross-sectional area S_SiGe of the silicon germanium body. The calculation method is simpler.

[0114] In some embodiments, the cross-sectional areas S_Trench1 and L_Trench1 of the receiving trench 110 of the second wafer meet the following formulas:

[0115]

[0116] Wherein, L_Trench0 is the cross-sectional perimeter of the receiving groove corresponding to the deviation area of ​​the first wafer in the extending direction of the gap between adjacent gates, and L_Trench1 is the cross-sectional perimeter of the receiving groove corresponding to the deviation area of ​​the second wafer in the extending direction of the gap between adjacent gates.

[0117] By substituting the formula for the relationship between the cross-sectional perimeter L_Trench, S_Trench and each side length, as well as the values ​​of S_SiGe, S_bulk1 and L_Trench0 into the calculation formula for the cross-sectional area S_Trench1 of the groove 110 of the second wafer, the etching depth RCD of the groove 110 can be solved and calculated. By etching the groove 110 according to the etching depth RCD of the groove 110, the distribution range of the silicon germanium body within the value range of the normal area 201 can be increased, thereby improving the yield of the P-type transistor semiconductor device.

[0118] Since the cross-sectional area of ​​the receiving groove 110 changes, the perimeter will also change accordingly, and the perimeter of the cross section of the receiving groove 110 will affect the overall speed of epitaxial growth, that is, the longer the cross-sectional perimeter of the receiving groove 110, the larger the epitaxial area of ​​the target structure layer 200 in the receiving groove 110 during the epitaxial process, and the larger the volume of the generated target structure layer 200 under the same epitaxial process time. Therefore, when calculating the cross-sectional area S_Trench1 of the receiving groove 110, the influence of the change in the perimeter of the receiving groove 110 is considered, and the corrected S_Trench1 is obtained, which can further improve the calculation accuracy of the cross-sectional area of ​​the receiving groove 110.

[0119] In some embodiments, the cross-sectional perimeter L_Trench of the accommodating trench 110 in the direction of the gap between adjacent gates is calculated by the following perimeter calculation formula:

[0120]

[0121] The section perimeter L_Trench0 and the section perimeter L_Trench1 are both calculated using the above perimeter calculation formula.

[0122] Although the receiving groove 110 is a convex hexagonal groove, the seed layer 210 is formed on the inner side wall of the receiving groove 110. When the epitaxial layer 220 grows, it grows from the inner side of the seed layer 210 to the outside of the receiving groove 110. Since the seed layer 210 does not exist at the opening of the receiving groove 110, that is, the upper side of the cross section, only the lower side and the side of the receiving groove 110 will affect the epitaxial growth volume change rate of the epitaxial layer 220. Therefore, when calculating the cross-sectional perimeter of the receiving groove 110, its upper side is not included, which can further improve the calculation accuracy of the cross-sectional area of ​​the receiving groove 110.

[0123] In some embodiments, the volume of the receiving groove 110 corresponding to the deviation area on the second wafer is designed to include:

[0124] Calculate the cross-sectional perimeter L_Trench1 of the receiving groove 110 according to the cross-sectional area S_Trench1 thereof, and calculate the cross-sectional perimeter L_Trench0 of the receiving groove 110 of the first wafer;

[0125] Substitute the cross-sectional perimeter L_Trench1 and the cross-sectional perimeter L_Trench0 into the calculation formula of the cross-sectional area S_Trench1 of the receiving groove 110 to calculate the expected cross-sectional area S_bulk1 of the overflow portion;

[0126] When the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements, the accommodating groove 110 is formed according to the cross-sectional area S_Trench1 of the accommodating groove 110. When the expected cross-sectional area S_bulk1 of the overflow portion does not meet the design requirements, the thickness H_bulk1 of the overflow portion and the corresponding cross-sectional area S_bulk1 of the overflow portion are redesigned until the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements.

[0127] In this embodiment, the cross-sectional perimeter L_Trench1 and the cross-sectional perimeter L_Trench0 are substituted into the calculation formula of the cross-sectional area S_Trench1 of the receiving groove, the expected cross-sectional area S_bulk1 of the overflow portion is calculated, and then it is verified whether the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements, so that it is simpler to obtain the cross-sectional area S_Trench1 of the receiving groove 110 and the corresponding etching depth RCD.

[0128] In some embodiments, when the cross-sectional area of ​​the receiving groove 110 is adjusted according to the above method, the cross-sectional area of ​​the receiving groove 110 is adjusted by a smaller ratio, so that the height uniformity of the overflow portion can be improved.

[0129] In other embodiments, the shape of the receiving groove 110 is rectangular, and the present invention is also applicable, only the geometric formula for calculating the area and the perimeter is different. In this embodiment, according to the etching principle, what needs to be changed is the depth of the groove and the lateral opening width. It can be understood that the large difference in etching rate on different crystal directions can cause the etching degree on the surface of the receiving groove 110 corresponding to some crystal directions to be negligible.

[0130] The present application also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method disclosed above.

[0131] When manufacturing the semiconductor device in this embodiment, a first wafer is first manufactured, the first wafer includes a base layer and a target structure layer 200, a first side 101 of the base layer is provided with a receiving groove 110, the target structure layer 200 is partially or completely located in the receiving groove 110, and the target structure layer 200 is divided into a normal area 201 and a deviation area according to the height of the upper surface of the target structure layer 200 relative to the first side 101, and the volume of the receiving groove 110 corresponding to the deviation area on the second wafer is designed according to the height of the deviation area of ​​the target structure layer 200 on the first wafer, and then the second wafer is manufactured using the same process conditions. Since the target structure layers 200 of the first wafer and the second wafer are manufactured using the same process conditions, the volume distributions of the two are approximately equal, and by increasing or decreasing the volume of the receiving groove 110 on the second wafer, the upper surface height of the target structure layer 200 can be controlled, so that almost all areas of the target structure layer 200 are within the value range of the normal area 201, that is, the consistency of the film thickness of the target structure layer 200 is improved, thereby improving the yield of the semiconductor device.

[0132] The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0133] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0134] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0135] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Produce a first wafer, the first wafer is a wafer sample, the first wafer includes a transistor, the transistor includes a base layer and a target structure layer formed on one side of the base layer, a receiving groove is provided on the first side of the base layer, the target structure layer is partially or completely located in the receiving groove, the target structure layer includes a silicon germanium body, the transistor includes a gate, the gate is located on the first side, a gap is formed between adjacent gates, an overflow portion of the silicon germanium body is located in the gap between adjacent gates, the silicon germanium body includes a seed layer and an epitaxial layer, the seed layer is formed on the inner side wall of the receiving groove, the epitaxial layer is formed in the seed layer and outside the receiving groove, the epitaxial layer is formed by an epitaxial growth process, and the epitaxial layer of the second wafer and the epitaxial layer of the first wafer are produced by the same process conditions; Dividing the target structure layer into a normal area and a deviation area according to the height of the upper surface of the target structure layer relative to the first side, wherein the height of the deviation area is greater than or less than the height of the normal area; According to the deviation of the height of the deviation area on the first wafer relative to the height of the normal area, the volume of the receiving groove corresponding to the deviation area on the second wafer is designed accordingly, and the second wafer is a positive wafer; The second wafer is manufactured, and at least a portion of the target structure layer of the second wafer and a portion of the target structure layer of the first wafer are manufactured using the same process conditions.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The target structure layer is partially located in the accommodating groove, and the accommodating groove is a rectangular groove or a convex hexagonal groove. The target structure layer includes a buried portion and an overflow portion, the buried portion is buried in the base layer, and the overflow portion is exposed on the first side. The height of the target structure layer relative to the first side is equal to the thickness of the overflow portion.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The volume of the accommodating groove corresponding to the deviation area on the correspondingly designed second wafer includes: Setting a thickness H_bulk1 of the overflow portion corresponding to the deviation area when manufacturing the second wafer; Calculate the cross-sectional area S_bulk1 of the overflow portion in the extending direction of the gap between adjacent gates according to the thickness H_bulk1 of the overflow portion; The cross-sectional area S_Trench1 of the receiving trench on the second wafer in the direction of extension of the gap between adjacent gates is calculated according to the cross-sectional area S_SiGe of the silicon germanium body in the direction of extension of the gap between adjacent gates and the cross-sectional area S_bulk1 of the overflow portion.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The accommodating groove is a convex hexagonal groove, and the cross-sectional area S_bulk1 of the overflow portion is: Wherein, OP is the width of the gap between adjacent gates, and α is the top angle of the overflow portion.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: The cross-sectional area S_Trench1 of the accommodating groove is: S_Trench1=S_SiGe-S_bulk1.

6. The method for manufacturing a semiconductor device according to claim 3, wherein: The cross-sectional areas S_Trench1 and L_Trench1 of the accommodating grooves conform to the following formula: Wherein, L_Trench0 is the cross-sectional perimeter of the receiving groove corresponding to the deviation area of ​​the first wafer in the extending direction of the gap between adjacent gates, and L_Trench1 is the cross-sectional perimeter of the receiving groove corresponding to the deviation area of ​​the second wafer in the extending direction of the gap between adjacent gates.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The gate includes a gate electrode and a side wall between the gate electrode and the receiving groove. The receiving groove is a convex hexagonal groove. The cross-sectional perimeter L_Trench of the receiving groove in the extending direction of the gap between adjacent gates is calculated by the following perimeter calculation formula: Wherein, BCD is the length of the lower side of the cross section of the receiving groove, S2G is the width of the side wall, T2G is the distance between the receiving groove and the gate electrode in the gap width direction between adjacent gates, RCD is the depth of the receiving groove, the receiving groove includes an upper isosceles trapezoidal area away from the base layer and a lower isosceles trapezoidal area close to the base layer, and SMD is the height of the upper isosceles trapezoidal area; The cross-sectional perimeter L_Trench0 and the cross-sectional perimeter L_Trench1 are both calculated using the perimeter calculation formula.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The volume of the accommodating groove corresponding to the deviation area on the correspondingly designed second wafer includes: Calculating the cross-sectional perimeter L_Trench1 of the receiving groove according to the cross-sectional area S_Trench1, and calculating the cross-sectional perimeter L_Trench0 of the receiving groove of the first wafer; Substitute the cross-sectional perimeter L_Trench1 and the cross-sectional perimeter L_Trench0 into the calculation formula of the cross-sectional area S_Trench1 of the receiving groove to calculate the expected cross-sectional area S_bulk1 of the overflow portion; When the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements, the accommodating groove is formed according to the cross-sectional area S_Trench1 of the accommodating groove; when the expected cross-sectional area S_bulk1 of the overflow portion does not meet the design requirements, the thickness H_bulk1 of the overflow portion and the corresponding cross-sectional area S_bulk1 of the overflow portion are redesigned until the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The deviation area includes a thin area, and the corresponding design of the volume of the receiving groove corresponding to the deviation area on the second wafer includes: reducing the volume of the receiving groove corresponding to the thin area on the second wafer; Alternatively, the deviation area includes a thicker area, and the corresponding design of the volume of the receiving groove corresponding to the deviation area on the second wafer includes: increasing the volume of the receiving groove corresponding to the thicker area on the second wafer.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The deviation area includes a thicker area and a thinner area, and the process for forming the target structure layer includes chemical vapor deposition or physical vapor deposition; before the volume of the receiving groove corresponding to the deviation area on the correspondingly designed second wafer is determined, the method comprises the following steps: When the thinned area of ​​the target structure layer of at least the first wafer is 0, the method for manufacturing the semiconductor device includes: reducing the thickness of the target structure layer formed when manufacturing the second wafer, and then dividing the normal area and the deviation area according to the target structure layer to be formed; When the thickest area of ​​the target structure layer of at least the first wafer is 0, the method for manufacturing the semiconductor device includes: increasing the thickness of the target structure layer formed when manufacturing the second wafer, and then dividing the normal area and the deviation area according to the target structure layer expected to be formed; The method for adjusting the thickness of the target structure layer formed when manufacturing the second wafer includes adjusting the time for forming the target structure layer, the reaction temperature for forming the target structure layer, and the reaction gas flow rate.

11. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 10.

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