Semiconductor device and preparation method
By forming groove sides with normals not parallel in GaN HEMT devices and filling the ohmic contact electrodes, the problem of difficult to reduce ohmic contact resistance in traditional processes is solved, and a lower ohmic contact resistance value and a larger etching process are achieved. window.
Patent Information
- Application Number
- CN202411558241.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-02-07
AI Technical Summary
The traditional ion implantation-etching ohmic process is difficult to further reduce the ohmic contact resistance of GaN HEMT devices, and the etching process window is limited.
By forming a normal near the depth position of the two-dimensional electron gas, the groove side of the plane where the two-dimensional electron gas is located, and the ohmic contact electrode is filled with the improved groove, thereby increasing the side wall of the ohmic contact electrode and ion implantation. contact area.
The contact resistance of the ohmic contact electrode and the ion implantation region is reduced, the ohmic contact resistance value is reduced, and the etching process window is expanded.
Smart Images
Figure CN119403170A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art
[0002] GaN HEMT (High Electron Mobility Transistor) devices are increasingly used in high-power power electronic devices and high-power RF devices due to their high mobility and high carrier concentration. Figure 1 The GaN HEMT device shown includes a stacked substrate 1, a GaN layer 2, and an AlGaN layer 3. Since its conductive channel is a two-dimensional electron gas 4 (2DEG) formed by the polarization effect, the two-dimensional electron gas 4 is distributed at the interface between the AlGaN layer 3 and the GaN layer 2, and it is impossible to directly make an electrode on the surface of the wafer to form an ohmic contact. Therefore, forming a low-ohmic contact has become one of the key research technologies. The ion implantation-etching ohmic process is a method commonly used to form an ohmic contact in GaN HEMT devices. It forms a highly doped ion implantation area by implanting donor impurities such as Si, and further etches part of the AlGaN layer 3 and the GaN layer 2, so that the ohmic metal 6 is closer to the two-dimensional electron gas 4, thereby obtaining a good ohmic contact.
[0003] In this ion implantation-etching ohmic process, the contact between the ohmic metal 6 and the two-dimensional electron gas 4 mainly relies on the bottom and sidewall of the ohmic metal 6 to contact the ion implantation area, and the ion implantation area is in contact with the two-dimensional electron gas 4, so as to achieve a good low resistance ohmic. However, in the traditional ion implantation-etching ohmic process, the etching morphology is not specially designed. This design can only change the resistance value of the ohmic contact resistance by optimizing the etching depth. After obtaining the optimal etching depth, it is often difficult to further reduce the ohmic contact resistance without adjusting other processes. Summary of the invention
[0004] The purpose of the present application is to provide a semiconductor device and a preparation method, which can reduce the contact resistance between the ohmic contact electrode and the ion implantation area by increasing the contact area between the side wall of the ohmic contact electrode and the ion implantation area, thereby reducing the ohmic contact resistance; at the same time, it can increase the etching process window.
[0005] To achieve the above object, the present application provides a semiconductor device, comprising: an ohmic contact electrode, and a substrate, a channel layer and a barrier layer sequentially arranged along a thickness direction;
[0006] A two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer; an ion implantation region is formed between the barrier layer and at least a portion of the channel layer, and the ion implantation region is in contact with the two-dimensional electron gas;
[0007] A first groove is formed on the surface of the ion implantation region facing away from the substrate; within a preset etching depth range, the first groove has a side whose normal is not parallel to the plane where the two-dimensional electron gas is located; the preset etching depth range at least includes the depth position of the two-dimensional electron gas; and the ohmic contact electrode fills the first groove.
[0008] Optionally, the first groove includes a first side surface and a second side surface; the first side surface is a side surface within a range from a top of the first groove to a preset etching depth position; the second side surface is a side surface within a range from the preset etching depth position to a bottom of the first groove; the preset etching depth position is higher than a depth position of the two-dimensional electron gas;
[0009] A normal line of at least part of the second side surface is not parallel to the plane where the two-dimensional electron gas is located.
[0010] Optionally, the normal lines at each position on the second side face form a same preset angle with the plane where the two-dimensional electron gas is located, and the preset angle is an acute angle.
[0011] Optionally, the first groove includes an arc-shaped bottom surface; the arc-shaped bottom surface is formed by being surrounded by two second side surfaces in the width direction of the first groove; the second side surface is an arc surface, and the normal at each position on the arc surface is at a different preset angle with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying.
[0012] Optionally, the second side surface is formed with at least one step, and each of the steps includes a first surface and a second surface.
[0013] Optionally, a second groove is formed on the second side surface, the bottom of the second groove extends toward the two-dimensional electron gas, the second side surface is an arc surface, the normals at various positions on the arc surface are at different preset angles with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying.
[0014] To achieve the above objectives, the present application also provides a method for preparing a semiconductor device, comprising:
[0015] Growing a channel layer and a barrier layer in sequence along a thickness direction on a substrate, forming a two-dimensional electron gas at an interface between the channel layer and the barrier layer;
[0016] forming an ion implantation region in the barrier layer and at least a portion of the channel layer by ion implantation; wherein the ion implantation region is in contact with the two-dimensional electron gas;
[0017] Etching a surface of the ion implantation region away from the substrate to form a first groove, so that within a preset etching depth range, the first groove has a side whose normal is not parallel to the plane where the two-dimensional electron gas is located; the preset etching depth range at least includes the depth position of the two-dimensional electron gas;
[0018] The ohmic contact electrode is deposited in the first groove so that the ohmic contact electrode fills the first groove.
[0019] Optionally, etching a surface of the ion implantation region away from the substrate to form a first groove includes:
[0020] The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0021] After the first side is formed, the surface of the ion implantation area facing away from the substrate is etched by a dry etching method. During the etching process, the etching morphology of the first groove is controlled by controlling the etching rate and the selectivity of the barrier layer and the channel layer to form the second side. The normal of each position on the second side is at the same preset angle with the plane where the two-dimensional electron gas is located, and the angle is an acute angle.
[0022] Optionally, etching a surface of the ion implantation region away from the substrate to form a first groove includes:
[0023] The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0024] After the first side surface is formed, the surface of the ion implantation region facing away from the substrate is etched by a dry etching method. During the etching process, the etching morphology of the first groove is controlled by dynamically adjusting the etching rates and the selectivity of the barrier layer and the channel layer to form an arc-shaped bottom surface; the arc-shaped bottom surface is formed by being surrounded by two second side surfaces in the width direction of the first groove; the second side surface is an arc surface, and the normals at various positions on the arc surface are at different preset angles with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying.
[0025] Optionally, etching a surface of the ion implantation region away from the substrate to form a first groove includes:
[0026] The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0027] After forming the first side, the surface of the ion implantation region away from the substrate is subjected to multiple exposures of photoresist and etching, and the critical dimension of the subsequent exposure is larger than the critical dimension of the previous exposure, so as to form at least one step on the second side; each of the steps includes a first surface and a second surface; or,
[0028] The surface of the ion implantation area facing away from the substrate is exposed to photoresist and etched for the first time to form a first step on the second side surface; after the first etching is completed, the photoresist is caused to expand and shrink by temperature, and then etching is performed to form at least one step based on the first step; each step includes a first surface and a second surface.
[0029] Optionally, etching a surface of the ion implantation region away from the substrate to form a first groove includes:
[0030] The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0031] After the first side surface is formed, the surface of the ion implantation region facing away from the substrate is etched by a wet etching method, and the second side surface is undercut during the etching process to form a second groove on the second side surface; the bottom of the second groove extends toward the two-dimensional electron gas, and the second side surface is an arc surface, and the normals at various positions on the arc surface are at different preset angles with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying.
[0032] Obviously, a semiconductor device provided by the present application further improves the side morphology of the groove on the basis of the ion implantation-etching ohmic process, so that the groove near the depth position of the two-dimensional electron gas has a side whose normal is not parallel to the plane where the two-dimensional electron gas is located, and then the ohmic contact electrode fills the improved groove. The contact area between the side wall of the ohmic contact electrode formed under this structure and the ion implantation area is greater than the contact area between the side wall of the ohmic contact electrode perpendicular to the two-dimensional electron gas and the ion implantation area. By increasing the contact area between the side wall of the ohmic contact electrode and the ion implantation area, the contact resistance between the ohmic contact electrode and the ion implantation area can be reduced, thereby reducing the ohmic contact resistance; at the same time, the etching process window can be increased. The present application also provides a method for preparing a semiconductor device, which can prepare the above-mentioned semiconductor device, so it also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0034] Figure 1 A schematic diagram of the structure of a traditional GaN HEMT device;
[0035] Figure 2 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application;
[0036] Figure 3 A schematic structural diagram of a first semiconductor device provided in an embodiment of the present application;
[0037] Figure 4 A schematic diagram of the structure of a second semiconductor device provided in an embodiment of the present application;
[0038] Figure 5 A schematic structural diagram of a third semiconductor device provided in an embodiment of the present application;
[0039] Figure 6 A schematic structural diagram of a fourth semiconductor device provided in an embodiment of the present application.
[0040] The following are the descriptions of the reference numerals:
[0041] 1-substrate; 2-GaN layer; 3-AlGaN layer; 4-two-dimensional electron gas; 5-ion implantation region; 6-ohmic metal; 7-ohmic contact electrode; 8-channel layer; 9-barrier layer; 11-first side; 12-second side; d0-depth of the first groove; d2-preset etching depth range. DETAILED DESCRIPTION
[0042] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0043] Please refer to Figures 3 to 6 , an embodiment of the present application provides a semiconductor device, which may include: an ohmic contact electrode 7, and a substrate 1, a channel layer 8 and a barrier layer 9 sequentially arranged along a thickness direction;
[0044] A two-dimensional electron gas 4 is formed at the interface between the channel layer 8 and the barrier layer 9; an ion implantation region is formed between the barrier layer 9 and at least a portion of the channel layer 8, and the ion implantation region 5 is in contact with the two-dimensional electron gas 4;
[0045] A first groove is formed on the surface of the ion implantation region 5 facing away from the substrate 1; within the preset etching depth range d2, the first groove has a side whose normal is not parallel to the plane where the two-dimensional electron gas 4 is located; the preset etching depth range d2 at least includes the depth position of the two-dimensional electron gas 4; the ohmic contact electrode 7 fills the first groove.
[0046] It should be noted that the channel layer 8 and the barrier layer 9 of this embodiment will form a heterojunction, and a two-dimensional electron gas 4 will be formed at the heterojunction interface through the polarization effect. This embodiment does not limit the specific types of the channel layer 8 and the barrier layer 9, as long as the channel layer 8 and the barrier layer 9 can form a heterojunction, for example, the material of the channel layer 8 can be GaN; the material of the barrier layer 9 can be one or more materials such as AlGaN, AlN, AlScN or InAlGaN.
[0047] It should be noted that the ion implantation region 5 of this embodiment is doped with donor ions, which has a high concentration of electron doping. This embodiment does not limit the specific type of donor ions, as long as it is ensured that high concentration of electrons can be generated in the ion implantation region 5 after being implanted into the ion implantation region 5. For example, the donor ions can be Si ions.
[0048] It should be noted that the depth d0 of the first groove is related to the distribution of the ion implantation area 5. The peak value of the ion implantation area 5 should be close to the two-dimensional electron gas 4. Therefore, the first groove is generally etched to a depth position below the two-dimensional electron gas 4 (i.e., the depth position corresponding to the plane where the two-dimensional electron gas 4 is located) to ensure the overall performance of the device. The preset etching depth range d2 in this embodiment refers to a certain depth interval including multiple depth positions, which is smaller than the depth d0 of the first groove.
[0049] This embodiment does not limit the specific size of the preset etching depth range d2, as long as the preset etching depth range d2 can include the depth position of the two-dimensional electron gas 4. For example, the preset etching depth range d2 can include the preset etching depth position and the bottom of the first groove, and all depth positions between the two positions, wherein the preset etching depth position is higher than the depth position of the two-dimensional electron gas 4 (that is, the preset etching depth position is a certain depth position higher than the depth position of the two-dimensional electron gas 4). Accordingly, the depth d0 of the first groove can be divided into two parts: from the top of the first groove to the preset etching depth position, and from the preset etching depth position to the bottom of the first groove.
[0050] Correspondingly, the first groove of the present embodiment may include a first side surface 11 and a second side surface 12; the first side surface 11 is a side surface within the range from the top of the first groove to a preset etching depth position; the second side surface 12 is a side surface within the range from the preset etching depth position to the bottom of the first groove; the normal of at least part of the position on the second side surface 12 may not be parallel to the plane where the two-dimensional electron gas 4 is located.
[0051] This embodiment does not limit the specific shape of the first side surface 11 , and the first side surface 11 may be, but is not limited to, perpendicular to the plane where the two-dimensional electron gas 4 is located.
[0052] This embodiment does not limit the specific morphology of the second side surface 12 , as long as the normal line of at least part of the second side surface 12 is not parallel to the plane where the two-dimensional electron gas 4 is located. For details, please refer to the following specific embodiments.
[0053] This embodiment does not limit the specific shape of the bottom surface of the first groove. For example, the bottom surface of the first groove may be parallel to the plane where the two-dimensional electron gas 4 is located; the bottom surface of the first groove may also be an arc-shaped bottom surface.
[0054] It should be noted that, in this embodiment, after the ohmic contact electrode 7 fills the first groove, it will form an ohmic contact with the ion implantation area 5. This embodiment does not limit the specific type of the ohmic contact electrode 7, as long as it is ensured that the ohmic contact electrode 7 can form an ohmic contact with the ion implantation area 5, for example, the material of the ohmic contact electrode 7 can be a metal such as TiPtAuTi or TiAuTi.
[0055] Based on the above embodiments, the present application further improves the side morphology of the groove on the basis of the ion implantation-etching ohmic process, so that the groove near the depth position of the two-dimensional electron gas has a side whose normal is not parallel to the plane where the two-dimensional electron gas is located, and then the ohmic contact electrode fills the improved groove. The contact area between the side wall of the ohmic contact electrode formed under this structure and the ion implantation area is greater than the contact area between the side wall of the ohmic contact electrode perpendicular to the two-dimensional electron gas and the ion implantation area. By increasing the contact area between the side wall of the ohmic contact electrode and the ion implantation area, the contact resistance between the ohmic contact electrode and the ion implantation area can be reduced, thereby reducing the ohmic contact resistance; at the same time, the etching process window can be increased.
[0056] Please refer to Figure 2 , Figure 2 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application, the method may include:
[0057] S101: growing a channel layer and a barrier layer in sequence along a thickness direction on a substrate, and forming a two-dimensional electron gas at an interface between the channel layer and the barrier layer.
[0058] It should be noted that, in this embodiment, before the channel layer and the barrier layer are sequentially grown on the substrate along the thickness direction, a supporting substrate needs to be provided in advance.
[0059] This embodiment does not limit the specific types of the channel layer and the barrier layer, and reference may be made to the above semiconductor device embodiments, which will not be described in detail here.
[0060] S102: forming an ion implantation region in the barrier layer and at least a portion of the channel layer by ion implantation; the ion implantation region is in contact with the two-dimensional electron gas.
[0061] This embodiment does not limit the specific type of donor ions, and reference may be made to the above semiconductor device embodiments, which will not be repeated here.
[0062] This embodiment does not limit the specific method of forming the ion implantation region, as long as it is ensured that the ion implantation region can be formed in the barrier layer and at least a portion of the channel layer. For example, the following method may be used:
[0063] forming a mask in a non-implantation region of the barrier layer away from the substrate surface;
[0064] An ion implantation region is formed by an ion implantation method so that an implantation region of the barrier layer away from the substrate surface is formed.
[0065] This embodiment does not limit the specific method of forming the mask, as long as it can cover the non-injection area. For example, a mask can be formed in the non-injection area of the barrier layer away from the substrate surface by coating photoresist or other means.
[0066] S103: etching the surface of the ion implantation region facing away from the substrate to form a first groove, so that within a preset etching depth range, the first groove has a side whose normal is not parallel to the plane where the two-dimensional electron gas is located; the preset etching depth range at least includes the depth position of the two-dimensional electron gas.
[0067] This embodiment does not limit the specific method of forming the first groove, and the specific method of forming the first groove can be determined according to the specific morphology of the side surface of the first groove, for example, the following method can be used:
[0068] Etching the surface of the ion implantation region facing away from the substrate to form a first groove, so that the first groove includes a first side surface and a second side surface;
[0069] The first side surface is a side surface within the range from the top of the first groove to a preset etching depth position; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the normal of at least part of the position on the second side surface is not parallel to the plane where the two-dimensional electron gas is located.
[0070] This embodiment does not limit the specific method of forming the first side surface. The surface of the ion implantation region facing away from the substrate can be etched by dry etching, and part of the barrier layer can be etched to a preset etching depth to form the first side surface. Further, the specific method of forming the first side surface can be determined according to the specific morphology of the first side surface, for example, the following method can be used:
[0071] The surface of the ion implantation region facing away from the substrate is etched in a direction perpendicular to the two-dimensional electron gas by a dry etching method, and part of the barrier layer is etched to a preset etching depth to form a first side surface; the first side surface is perpendicular to the plane where the two-dimensional electron gas is located.
[0072] This embodiment does not limit the specific method of forming the second side surface after forming the first side surface. The specific method of forming the first side surface can be determined according to the specific morphology of the second side surface. For details, please refer to the following specific embodiments.
[0073] S104: depositing an ohmic contact electrode in the first groove, so that the ohmic contact electrode fills the first groove.
[0074] This embodiment does not limit the specific type of the ohmic contact electrode, and reference may be made to the above semiconductor device embodiment, which will not be described in detail here.
[0075] The present embodiment does not limit the specific method of depositing the ohmic contact electrode. In order to fill the first groove well, the ohmic contact electrode may be deposited inside the first groove by a high coverage deposition method such as a sputtering deposition method.
[0076] Based on the above embodiments, the present application can prepare the above semiconductor device, so it also has the above beneficial effects.
[0077] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the first semiconductor device provided in the embodiment of the present application. Different from the first semiconductor device embodiment, this embodiment further specifically defines the morphology of the second side surface 12 on the basis of the first semiconductor device embodiment, and the rest of the contents have been described in detail in the first semiconductor device embodiment and will not be repeated here.
[0078] In this embodiment, the normals at various positions on the second side surface 12 may be at the same preset angle with the plane where the two-dimensional electron gas 4 is located, and the preset angle is an acute angle. It should be noted that the entire side surface of the conventional groove for accommodating the ohmic contact electrode 7 is perpendicular to the plane where the two-dimensional electron gas 4 is located, while in this embodiment, by designing the etching angle, an inclined surface inclined toward the plane where the two-dimensional electron gas 4 is located is formed in the groove near the depth position of the two-dimensional electron gas 4, and the corresponding side wall of the ohmic contact electrode 7 is inclined, so that in this embodiment, the side wall of the ohmic contact electrode 7 and the ion implantation region 5 have a larger contact area than the conventional structure, thereby reducing the contact resistance between the ohmic contact electrode 7 and the ion implantation region 5, and further reducing the ohmic contact resistance.
[0079] Accordingly, the present application also provides a method for preparing Figure 3 The method for preparing the semiconductor device shown in the figure. Different from the first embodiment of the method for preparing the semiconductor device, this embodiment further specifically defines the method for forming the second side surface 12 on the basis of the first embodiment of the semiconductor device. The rest of the contents have been described in detail in the first embodiment of the method for preparing the semiconductor device, and will not be repeated here. In this embodiment, it is possible to:
[0080] The surface of the ion implantation region facing away from the substrate is etched by a dry etching method, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0081] After the first side is formed, the surface of the ion implantation area facing away from the substrate is etched by a dry etching method. During the etching process, the etching morphology of the first groove is controlled by controlling the etching rate and selectivity of the barrier layer and the channel layer to form the second side. The normal line at each position on the second side is at the same preset angle with the plane where the two-dimensional electron gas is located, and the preset angle is an acute angle.
[0082] Please refer to Figure 4 , Figure 4This is a schematic diagram of the structure of the second semiconductor device provided in the embodiment of the present application. Different from the first semiconductor device embodiment, this embodiment further specifically defines the morphology of the second side surface 12 on the basis of the first semiconductor device embodiment, and the rest of the contents have been described in detail in the first semiconductor device embodiment and will not be repeated here.
[0083] In this embodiment, the first groove includes an arc-shaped bottom surface; the arc-shaped bottom surface is formed by being surrounded by two second side surfaces 12 in the width direction of the first groove; the second side surface 12 can be an arc surface, and the normal lines at various positions on the arc surface are at different preset angles with the plane where the two-dimensional electron gas 4 is located, and the different preset angles are gradient-changing. It should be noted that in this embodiment, the left and right arc side surfaces can constitute an arc-shaped bottom as a whole. In this embodiment, by designing the bottom of the groove into an arc shape, an arc surface is formed in the groove near the depth position of the two-dimensional electron gas 4, and the corresponding ohmic contact electrode 7 side wall is also an arc shape, so that in this embodiment, the ohmic contact electrode 7 side wall and the ion implantation area 5 have a larger contact area than the traditional structure, thereby reducing the contact resistance between the ohmic contact electrode 7 and the ion implantation area 5, and further reducing the ohmic contact resistance.
[0084] Accordingly, the present application also provides a method for preparing Figure 4 The method for preparing the semiconductor device shown in the figure. Different from the first embodiment of the method for preparing the semiconductor device, this embodiment further specifically defines the method for forming the second side surface 12 on the basis of the first embodiment of the semiconductor device. The rest of the contents have been described in detail in the first embodiment of the method for preparing the semiconductor device, and will not be repeated here. In this embodiment, it is possible to:
[0085] The surface of the ion implantation region facing away from the substrate is etched by a dry etching method, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0086] After the first side surface is formed, the surface of the ion implantation area facing away from the substrate is etched by a dry etching method. During the etching process, the etching rate and selectivity of the barrier layer and the channel layer are dynamically adjusted to control the etching morphology of the first groove to form an arc-shaped bottom surface; the arc-shaped bottom surface is formed by being surrounded by two second side surfaces in the width direction of the first groove; the second side surface is an arc surface, and the normal at each position on the arc surface is at different preset angles with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-changing.
[0087] Please refer to Figure 5 , Figure 5A schematic diagram of the structure of the third semiconductor device provided in the embodiment of the present application. Different from the first semiconductor device embodiment, this embodiment further specifically defines the morphology of the second side surface 12 on the basis of the first semiconductor device embodiment, and the rest of the contents have been described in detail in the first semiconductor device embodiment and will not be repeated here.
[0088] In this embodiment, the second side surface 12 may be formed with at least one step, and each step includes a first surface and a second surface. In this embodiment, the specific morphology of the first surface and the second surface is not limited, as long as the first surface and the second surface can form a step, for example, the normal of each position on the first surface is at the same first preset angle with the plane where the two-dimensional electron gas 4 is located, and the normal of each position on the second surface is at the same second preset angle with the plane where the two-dimensional electron gas 4 is located. In this embodiment, the specific values of the first preset angle and the second preset angle are not limited, as long as the first preset angle and the second preset angle are different, for example, the first surface can be perpendicular to the plane where the two-dimensional electron gas 4 is located, and the second surface can be parallel to the plane where the two-dimensional electron gas 4 is located. It should be noted that in this embodiment, a step morphology is formed in the groove near the depth position of the two-dimensional electron gas 4 through multiple etchings, and the corresponding side wall of the ohmic contact electrode 7 also has a step morphology, so that the side wall of the ohmic contact electrode 7 in this embodiment has a larger contact area with the ion implantation region 5 than the traditional structure, thereby reducing the contact resistance between the ohmic contact electrode 7 and the ion implantation region 5, and further reducing the ohmic contact resistance.
[0089] Accordingly, the present application also provides two preparation examples. Figure 5 The method for preparing the semiconductor device shown in the figure. Different from the first embodiment of the method for preparing the semiconductor device, this embodiment further specifically defines the method for forming the second side surface 12 on the basis of the first embodiment of the semiconductor device. The rest of the contents have been described in detail in the first embodiment of the method for preparing the semiconductor device, and will not be repeated here. In this embodiment, it is possible to:
[0090] The surface of the ion implantation region facing away from the substrate is etched by a dry etching method, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0091] After the first side surface is formed, the second side surface may be formed in the following two ways.
[0092] The first method of forming the second side provided in this embodiment can be: multiple exposures of the surface of the ion implantation area away from the substrate to photoresist and etching are performed, and the critical dimension of the latter exposure is larger than the critical dimension of the previous exposure, so as to form at least one step on the second side; each step includes a first surface and a second surface.
[0093] This embodiment does not limit the specific etching method, and the specific etching method can be determined according to the specific morphologies of the first surface and the second surface. For example, the following method can be adopted: when the first surface is perpendicular to the plane where the two-dimensional electron gas is located, and the second surface is parallel to the plane where the two-dimensional electron gas is located, the etching method can be etching along the thickness direction; when the first surface and the second surface adopt other morphologies, the etching method can be controlling the etching morphologies of the first surface and the second surface by controlling the etching rate and selectivity of the barrier layer and the channel layer during the etching process.
[0094] It should be noted that this method uses multiple photoresist exposure and etching methods. First, the first photoresist exposure and etching are performed to form the first step; then the next photoresist exposure and etching are performed, and the key dimension of the latter exposure is larger than the key dimension of the previous exposure, forming a second step or more steps.
[0095] The second method of forming the second side provided in this embodiment may be: exposing the surface of the ion implantation area away from the substrate to the photoresist and performing the first etching to form the first step on the second side; after the first etching is completed, the photoresist is expanded and shrunk by temperature, and then etching is performed to form at least one step on the basis of the first step; each step includes a first surface and a second surface, the first surface is perpendicular to the plane where the two-dimensional electron gas is located, and the second surface is parallel to the plane where the two-dimensional electron gas is located. It should be noted that this method adopts a baking and collapsing process. After the first step is formed by the first etching, the photoresist is expanded and shrunk by temperature, and then etching is performed to form a second step or more steps. This embodiment does not limit the specific method of etching, and you can refer to the previous description of etching, which will not be repeated here.
[0096] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of the fourth semiconductor device provided in the embodiment of the present application. Different from the first semiconductor device embodiment, this embodiment further specifically defines the morphology of the second side surface 12 on the basis of the first semiconductor device embodiment, and the rest of the contents have been described in detail in the first semiconductor device embodiment and will not be repeated here.
[0097] In this embodiment, the second side surface 12 may be formed with a second groove, the bottom of the second groove extends toward the two-dimensional electron gas 4, and the second side surface 12 is an arc surface, and the normal lines at various positions on the arc surface are at different preset angles with the plane where the two-dimensional electron gas 4 is located, and the different preset angles are gradient-varying. It should be noted that in this embodiment, by etching the side of the first groove, a protruding groove with an arc shape is formed in the groove near the depth position of the two-dimensional electron gas 4, and the corresponding side wall of the ohmic contact electrode 7 also has a protruding arc shape, so that the side wall of the ohmic contact electrode 7 in this embodiment and the ion implantation area 5 have a larger contact area than the traditional structure, thereby reducing the contact resistance between the ohmic contact electrode 7 and the ion implantation area 5, and further reducing the ohmic contact resistance.
[0098] Accordingly, the present application also provides a method for preparing Figure 6 The method for preparing the semiconductor device shown in the figure. Different from the first embodiment of the method for preparing the semiconductor device, this embodiment further specifically defines the method for forming the second side surface 12 on the basis of the first embodiment of the semiconductor device. The rest of the contents have been described in detail in the first embodiment of the method for preparing the semiconductor device, and will not be repeated here. In this embodiment, it is possible to:
[0099] The surface of the ion implantation region facing away from the substrate is etched by a dry etching method, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove;
[0100] After forming the first side surface, the surface of the ion implantation area facing away from the substrate is etched by a wet etching method, and the second side surface is side-cut during the etching process to form a second groove on the second side surface; the bottom of the second groove extends toward the two-dimensional electron gas, and the second side surface is an arc surface, and the normals at various positions on the arc surface are at different preset angles to the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying. It should be noted that this method can be combined with a high coverage deposition method such as a sputtering deposition method to ensure that the interior of the second groove is well filled.
[0101] Specific examples are used herein to illustrate the principles and implementation methods of the present application, and the embodiments are in a progressive relationship, each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.
[0102] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.
Claims
1. A semiconductor device, characterized in that: include: An ohmic contact electrode, and a substrate, a channel layer and a barrier layer sequentially arranged along a thickness direction; A two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer; The barrier layer and at least a portion of the channel layer are formed with an ion implantation region, and the ion implantation region is in contact with the two-dimensional electron gas; A first groove is formed on the surface of the ion implantation region facing away from the substrate; within a preset etching depth range, the first groove has a side whose normal is not parallel to the plane where the two-dimensional electron gas is located; the preset etching depth range at least includes the depth position of the two-dimensional electron gas; and the ohmic contact electrode fills the first groove.
2. The semiconductor device according to claim 1, wherein: The first groove includes a first side surface and a second side surface; the first side surface is a side surface within a range from the top of the first groove to a preset etching depth position; the second side surface is a side surface within a range from the preset etching depth position to the bottom of the first groove; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; A normal line of at least part of the second side surface is not parallel to the plane where the two-dimensional electron gas is located.
3. The semiconductor device according to claim 2, characterized in that The normal lines at each position on the second side face form a same preset angle with the plane where the two-dimensional electron gas is located, and the preset angle is an acute angle.
4. The semiconductor device according to claim 2, characterized in that The first groove includes an arc-shaped bottom surface; the arc-shaped bottom surface is formed by being surrounded by two second side surfaces in the width direction of the first groove; the second side surface is an arc surface, and the normal line at each position on the arc surface is at a different preset angle with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying.
5. The semiconductor device according to claim 2, wherein: The second side surface is formed with at least one step, and each of the steps includes a first surface and a second surface.
6. The semiconductor device according to claim 2, wherein: A second groove is formed on the second side surface, and the bottom of the second groove extends toward the two-dimensional electron gas. The second side surface is an arc surface, and the normal lines at various positions on the arc surface form different preset angles with the plane where the two-dimensional electron gas is located, and the different preset angles change in a gradient.
7. A method for preparing a semiconductor device, characterized in that: include: Growing a channel layer and a barrier layer in sequence along a thickness direction on a substrate, forming a two-dimensional electron gas at an interface between the channel layer and the barrier layer; forming an ion implantation region in the barrier layer and at least a portion of the channel layer by ion implantation; The ion implantation region is in contact with the two-dimensional electron gas; Etching a surface of the ion implantation region away from the substrate to form a first groove, so that within a preset etching depth range, the first groove has a side whose normal is not parallel to the plane where the two-dimensional electron gas is located; the preset etching depth range at least includes the depth position of the two-dimensional electron gas; The ohmic contact electrode is deposited in the first groove so that the ohmic contact electrode fills the first groove.
8. The method for preparing a semiconductor device according to claim 7, characterized in that: The etching of the surface of the ion implantation region away from the substrate to form a first groove comprises: The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove; After the first side is formed, the surface of the ion implantation area facing away from the substrate is etched by a dry etching method. During the etching process, the etching morphology of the first groove is controlled by controlling the etching rate and the selectivity of the barrier layer and the channel layer to form the second side. The normal of each position on the second side is at the same preset angle with the plane where the two-dimensional electron gas is located, and the angle is an acute angle.
9. The method for preparing a semiconductor device according to claim 7, wherein: The etching of the surface of the ion implantation region away from the substrate to form a first groove comprises: The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove; After the first side surface is formed, the surface of the ion implantation region facing away from the substrate is etched by a dry etching method. During the etching process, the etching morphology of the first groove is controlled by dynamically adjusting the etching rates and the selectivity of the barrier layer and the channel layer to form an arc-shaped bottom surface; the arc-shaped bottom surface is formed by being surrounded by two second side surfaces in the width direction of the first groove; the second side surface is an arc surface, and the normals at various positions on the arc surface are at different preset angles with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying.
10. The method for preparing a semiconductor device according to claim 7, wherein: The etching of the surface of the ion implantation region away from the substrate to form a first groove comprises: The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove; After forming the first side, the surface of the ion implantation region away from the substrate is subjected to multiple exposures of photoresist and etching, and the critical dimension of the subsequent exposure is larger than the critical dimension of the previous exposure, so as to form at least one step on the second side; each of the steps includes a first surface and a second surface; or, The surface of the ion implantation area facing away from the substrate is exposed to photoresist and etched for the first time to form a first step on the second side surface; after the first etching is completed, the photoresist is caused to expand and shrink by temperature, and then etching is performed to form at least one step based on the first step; each step includes a first surface and a second surface.
11. The method for preparing a semiconductor device according to claim 7, characterized in that: The etching of the surface of the ion implantation region away from the substrate to form a first groove comprises: The surface of the ion implantation region facing away from the substrate is etched by dry etching, and part of the barrier layer is etched to a preset etching depth position to form a first side surface; the preset etching depth position is higher than and less than the depth position of the two-dimensional electron gas; the second side surface is a side surface within the range from the preset etching depth position to the bottom of the first groove; After the first side surface is formed, the surface of the ion implantation region facing away from the substrate is etched by a wet etching method, and the second side surface is undercut during the etching process to form a second groove on the second side surface; the bottom of the second groove extends toward the two-dimensional electron gas, and the second side surface is an arc surface, and the normals at various positions on the arc surface are at different preset angles with the plane where the two-dimensional electron gas is located, and the different preset angles are gradient-varying.