High-durability FeFET based on ferroelectric semiconductor channel and anti-ferroelectric gate dielectric and preparation method thereof

Abstract

The invention discloses a high-durability FeFET based on a ferroelectric semiconductor channel and an anti-ferroelectric gate dielectric and a preparation method of the high-durability FeFET. A back gate electrode layer, an anti-ferroelectric gate dielectric layer, a ferroelectric semiconductor channel layer, a top gate high-k gate dielectric layer and a top gate electrode layer are sequentially stacked in a FeFET structure, and the anti-ferroelectric gate dielectric layer serves as a back gate dielectric layer; the top gate high-k gate dielectric layer serves as a top gate dielectric layer, the thickness of the back gate dielectric layer is larger than that of the top gate dielectric layer, and an asymmetric double-gate structure is formed. According to the invention, the hafnium oxide-based anti-ferroelectric thin film is used for replacing a ferroelectric thin film as a gate medium of the FeFET, so that the operation voltage is effectively reduced; no interface layer is arranged between the ferroelectric semiconductor channel and the anti-ferroelectric gate dielectric, so that durability failure caused by charge trapping and defect generation associated with the traditional FeFET and the interface layer is inhibited; the out-of-plane spontaneous polarization continuous, precise and adjustable characteristic of a ferroelectric semiconductor channel and the gate storage mode and the channel storage mode which are switched mutually based on the asymmetric double-gate structure of the FeFET are hopeful to enable the FeFET to show higher durability.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-nanoelectronics, and in particular relates to a high-durability ferroelectric transistor (FeFET) based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric and a preparation method thereof. Background Art

[0002] The emergence of new technologies such as smart chips, the Internet of Things, autonomous driving, and cloud computing indicates that human society has entered the data age. The large-scale data volume has triggered a revolution in data computing and storage. In terms of data computing, the computing and storage of data in the traditional von Neumann architecture are separate, and data needs to be moved back and forth between the central processing unit (CPU) and various levels of storage, which limits the development of computing power and increases power consumption. In terms of data storage, caches represented by static random access memory (SRAM) at a higher storage level have the characteristics of fast data access speed, but their integration density is not high and data is volatile. External storage represented by flash memory (Flash) at a lower storage level has the characteristics of high integration density and non-volatile data, but its data access speed is slow and its durability is low. It can be seen that it is difficult for traditional memory to simultaneously take into account the characteristics of high speed, high durability and non-volatility. In order to cope with the challenges brought by massive data to computing and storage, it is particularly important and urgent to develop new memories and develop a storage-computing integrated architecture based on new memories. Hafnium oxide-based ferroelectric transistor (FeFET) memory has attracted extensive attention from academia and industry due to its advantages such as data non-volatility, fast erase and write speed, low power consumption, and great potential for three-dimensional integration.

[0003] Despite its many advantages, hafnium oxide-based FeFETs also face the key problem of low durability. On the one hand, there is an interface layer between the ferroelectric layer and the channel of conventional silicon channel FeFETs. Due to the low dielectric constant of the interface layer, when applying pulses to the hafnium oxide-based FeFET for erase / write operations, the interface layer is often subjected to a higher electric field, which aggravates the charge capture and defect generation near the interface, resulting in a gradual decrease in the FeFET storage window (MW), and ultimately leading to the failure of the FeFET durability. On the other hand, the coercive field of hafnium oxide-based ferroelectric films is high, which causes the operating voltage of the FeFET to remain high, further aggravating the "short board" effect of the interface layer, which is not conducive to further improving the durability of hafnium oxide-based FeFETs. How to improve durability has become a bottleneck problem restricting the application and development of hafnium oxide-based FeFETs. Summary of the invention

[0004] The purpose of the present invention is to provide a high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric and a preparation method thereof.

[0005] Specifically, the technical solution of the present invention is as follows:

[0006] A high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric, the structure of which mainly includes: an insulating substrate, a back gate electrode layer on the insulating substrate, an antiferroelectric gate dielectric layer on the back gate electrode layer, a ferroelectric semiconductor channel layer on the antiferroelectric gate dielectric layer, source and drain metal electrodes on both sides of the ferroelectric semiconductor channel layer, the source and drain metal electrodes are simultaneously located on the antiferroelectric gate dielectric layer, a top gate high-k gate dielectric layer is on the ferroelectric semiconductor channel layer, and a top gate electrode layer is on the top gate high-k gate dielectric layer, wherein the antiferroelectric gate dielectric layer serves as a back gate dielectric layer, the top gate high-k gate dielectric layer serves as a top gate dielectric layer, the thickness of the back gate dielectric layer is greater than the thickness of the top gate dielectric layer, and the two constitute an asymmetric double-gate structure.

[0007] The above-mentioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric, wherein the insulating substrate can be selected from any substrate with insulating properties such as mica, sapphire, diamond, strontium titanate (STO), silicon oxide (SiO2), etc.

[0008] For the high-durability FeFET based on the ferroelectric semiconductor channel and the antiferroelectric gate dielectric, the back gate electrode material can be selected from common metals such as TiN, Al, Au, Pt, TaN, W, etc., and can also be selected from heavily doped Si or Ge and conductive oxides, including but not limited to LSMO, Nb-STO, RuO2, etc. Any material with excellent conductivity can be used as a candidate material for the back gate electrode.

[0009] The high-durability FeFET based on the ferroelectric semiconductor channel and the antiferroelectric gate dielectric requires the antiferroelectric gate dielectric to have a large dielectric bandgap, low leakage current, and significant double hysteresis characteristics. Hafnium oxide-based antiferroelectric materials can be used, such as Zr-rich doped HfO2, Al-doped HfO2 with a certain concentration, Si-doped HfO2 or ZrO2 with a certain concentration.

[0010] The above-mentioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric requires that the ferroelectric semiconductor channel material has a bandgap width less than 3.5V and has excellent and stable out-of-plane spontaneous polarization. The built-in field introduced by the spontaneous polarization intensity can effectively shift the double hysteresis curve of the antiferroelectric gate dielectric. In addition, the coercive field of the ferroelectric semiconductor channel is more than 2 times larger than the equivalent coercive field of the antiferroelectric gate dielectric to avoid affecting the polarization state of the ferroelectric semiconductor channel when erasing data on the antiferroelectric gate dielectric. Available materials include but are not limited to α-In2Se3, 1T-MoTe2, WTe2, ReS2, InSe and other materials.

[0011] In the above-mentioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric, the source and drain metal electrodes should form good ohmic contact with the ferroelectric semiconductor channel to reduce the contact resistance. The metals that can be used include but are not limited to Al, Ti, Au, Ag, Pt, Pd and other materials.

[0012] For the high-durability FeFET based on the ferroelectric semiconductor channel and the antiferroelectric gate dielectric, the top gate high-k gate dielectric requires a large dielectric bandgap, low leakage current, high dielectric constant, and strong anti-breakdown capability. The top gate high-k gate dielectric material can be selected from materials such as Al2O3, HfO2, and ZrO2. In addition, the thickness of the top gate high-k gate dielectric is also thinner than that of the back gate antiferroelectric gate dielectric to increase the regulation of the top gate electrode on the polarization state of the ferroelectric channel.

[0013] The high-durability FeFET based on the ferroelectric semiconductor channel and the antiferroelectric gate dielectric, the top gate electrode material is required to have excellent conductivity and thermal stability, and the available materials include but are not limited to Pt, TiN, Al, Au, Ag, Pd, TaN, W and other materials.

[0014] For the above-mentioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric, the total thickness of the insulating substrate should be greater than 100μm, and the thickness of the effective insulating layer should be greater than 20nm. The thickness of the back gate electrode material is 30-50nm. The thickness of the antiferroelectric gate dielectric material is 10-20nm. The thickness of the ferroelectric semiconductor channel material is 0.7-40nm, and the lateral size should be greater than 10μm. The thickness of the source and drain metal electrodes on both sides of the ferroelectric semiconductor channel material is between 20 and 80nm. The thickness of the top gate high-k gate dielectric material is 5-10nm. The thickness of the top gate electrode is 30-50nm.

[0015] The present invention also provides a method for preparing the above-mentioned high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric, comprising the following steps:

[0016] (1) First, the size and dimension of the back gate electrode are defined by photolithography on an insulating substrate, and a back gate electrode material with a thickness of 30 to 50 nm is deposited by physical vapor deposition / electron beam evaporation / atomic layer deposition process, and then patterned by etching / stripping process;

[0017] (2) growing an antiferroelectric gate dielectric having a thickness of 10 to 20 nm on the sample obtained in step (1) using an atomic layer deposition (ALD) process;

[0018] (3) A stress layer with a thickness of 5 to 30 nm is grown on the sample obtained in step (2) using an atomic layer deposition (ALD) process / physical vapor deposition (PVD) process, and the sample is subjected to rapid thermal annealing (RTA) in a N2 atmosphere to activate the antiferroelectricity of the antiferroelectric gate dielectric.

[0019] (4) Removing the stress layer by immersion in a corrosive solution / chemical etching method;

[0020] (5) growing a ferroelectric semiconductor channel material having a thickness of 0.7 nm to 40 nm on the sample obtained in step (4) by using a physical vapor transport (PVT) / physical vapor deposition (PVD) / chemical vapor deposition (CVD) process or transferring the material by micromechanical lift-off;

[0021] (6) using electron beam lithography (EBL) to define the source and drain metal positions, and using physical vapor deposition (PVD) / electron beam evaporation (EBE) to deposit source and drain metal materials with a thickness of 20 to 80 nm on the sample obtained in step (5), and then stripping them to make them patterned;

[0022] (7) photolithography defines the position of the top gate high-k gate dielectric and uses a physical vapor deposition (PVD) process to deposit a top gate high-k gate dielectric material with a thickness of 5 to 10 nm on the sample obtained in step (6), and then lifts it off to pattern it;

[0023] (8) Using electron beam lithography (EBL) process to define the position of the top gate electrode, and using physical vapor deposition (PVD) / electron beam evaporation (EBE) process to deposit a top gate electrode material with a thickness of 30 to 50 nm on the sample obtained in step (7), and then peeling it off to make it patterned.

[0024] In the above preparation process, the stress layer selected in step (3) should have a small thermal expansion coefficient and be able to apply sufficient in-plane tensile stress to the antiferroelectric film, so as to activate the antiferroelectricity in the subsequent annealing. The stress layer materials that can be selected include but are not limited to TiN, TaN, W, Ti, and Ru materials; the temperature range of the rapid thermal annealing (RTA) process is 400°C to 700°C, and the annealing time range is 30s to 150s, which needs to be appropriately adjusted according to the selected antiferroelectric gate dielectric material.

[0025] The technical effects of the present invention are as follows:

[0026] 1. Use hafnium oxide-based antiferroelectric film to replace ferroelectric film as the gate dielectric (back gate dielectric and top gate dielectric) of FeFET, reduce the device operating voltage and improve the durability of FeFET.

[0027] The dipoles in adjacent units of hafnium oxide-based antiferroelectric films are arranged in antiparallel, and the material exhibits the characteristics of a double hysteresis loop under the action of an external electric field. One of the sub-hysteresis loops of the double hysteresis loop is very similar to the hysteresis loop of a conventional ferroelectric film, but its equivalent coercive field is lower, and the voltage required for polarization reversal is lower. Therefore, using an antiferroelectric film to replace a ferroelectric film as a gate dielectric can reduce the operating voltage of the device, effectively inhibit charge capture and defect generation, and improve the durability of FeFET.

[0028] 2. The ferroelectric semiconductor channel has an out-of-plane spontaneous polarization, which can apply a continuous, precisely controllable electric field to the antiferroelectric gate medium to achieve non-volatile data storage, and is expected to achieve electrical synergistic optimization of FeFET durability.

[0029] The antiparallel arrangement of dipoles in adjacent unit cells of hafnium oxide-based antiferroelectric thin films results in a zero remanent polarization when the external electric field is removed, which is not conducive to non-volatile data storage. The ferroelectric semiconductor channel has a stable out-of-plane spontaneous polarization. The incompletely shielded depolarization field will cause the double hysteresis loop of the antiferroelectric gate dielectric to shift, resulting in the presence of two stable remanent polarization states in the antiferroelectric gate dielectric when there is no external electric field. Therefore, non-volatile data storage can be achieved by utilizing the hysteresis characteristics of a certain branch of the antiferroelectric gate dielectric. In addition, the offset of the double hysteresis loop of the antiferroelectric gate dielectric can be controlled by the strength of the remanent polarization of the ferroelectric semiconductor channel, which can achieve electrical synergistic optimization of FeFET durability. For example, by using the electrical correlation model of charge capture and defect generation, the electrical bias range corresponding to maintaining the hysteresis polarization reversal of the antiferroelectric gate dielectric but with the weakest charge capture and defect generation effects can be obtained. The erasure electrical bias of the FeFET can be controlled within the optimal range by regulating the ferroelectric channel residual polarization, thereby improving the durability of the FeFET. After a certain number of erasures, when a branch of the hysteresis of the antiferroelectric gate dielectric fails in durability due to fatigue, the ferroelectric channel residual polarization can also be controlled to cause the double hysteresis loop of the antiferroelectric gate dielectric to further shift, thereby using the other branch of the hysteresis to achieve data storage and reading and writing, thereby achieving "double" durability characteristics.

[0030] Third, there is no interface layer between most ferroelectric semiconductor channels and antiferroelectric gate dielectrics, which avoids the durability degradation problems caused by charge trapping and defect generation associated with the interface layer in conventional FeFETs.

[0031] Most ferroelectric semiconductor channel materials are two-dimensional materials. As channel materials, they have the advantages of no dangling bonds, excellent gate control, and sharp atomic-level interfaces. Therefore, there is no low-k interface layer between the two-dimensional ferroelectric semiconductor channel and the antiferroelectric gate dielectric, and there is no charge trapping and defect generation effect associated with the interface layer in conventional Si channel FeFETs. The device is expected to have more superior durability characteristics.

[0032] 4. High-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric can realize mode switching and is expected to achieve better durability.

[0033] The high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric has an asymmetric dual-gate structure and has two working modes. Mode 1 is the gate storage mode, in which the sub-hysteresis used for data storage can be switched. In the gate storage mode, the antiferroelectric gate (back gate) with a larger thickness and a lower equivalent coercive field realizes data storage and erasure, and the top gate high-k gate (top gate) with a smaller thickness is used to regulate the residual polarization size of the coercive field ferroelectric semiconductor channel. When working in this mode, the polarization state of the ferroelectric semiconductor channel must first be placed in a "positive" or "negative" polarization state through the top gate high-k gate. Under the influence of the depolarization field caused by the residual polarization of the ferroelectric semiconductor channel, the double hysteresis loops of the antiferroelectric gate dielectric will shift, and the two polarization states of the sub-hysteresis can be used for non-volatile data storage. Since the thickness of the antiferroelectric gate dielectric is greater than that of the top gate high-k gate dielectric, and its equivalent coercive field is lower than the coercive field of the ferroelectric semiconductor channel, erasing the device in this mode does not affect the polarization state of the ferroelectric channel. In this mode, the switching of the sub-hysteresis of the antiferroelectric gate medium can be achieved by utilizing the continuous adjustability of the ferroelectric semiconductor channel polarization, that is, the sub-hysteresis used for data storage can be any branch of the double hysteresis curve. At the same time, when using different branches of sub-hysteresis to store data, the direction of the combined electric field of the antiferroelectric film is opposite. Therefore, when using sub-hysteresis 2 to store data, the charge trapped in the antiferroelectric gate during the storage of sub-hysteresis 1 can be released, thereby achieving durable recovery. The repeated switching between sub-hysteresis will effectively improve the durability of FeFET. Mode 2 is the channel storage mode. That is, the ferroelectric semiconductor channel with a large coercive field realizes data storage, and the top gate high-k gate realizes data erasure. The switching between the gate storage mode and the channel storage mode, as well as the switching between sub-hysteresis in the gate storage mode can make the FeFET show higher durability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic cross-sectional view of a high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric prepared in an example of the present invention;

[0035] Figure 2 Schematic diagram of the steps of preparing a high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric according to an embodiment of the present invention, wherein:

[0036] (a) is a cross-sectional view of a back gate electrode material deposited on an insulating substrate using a physical vapor deposition (PVD) / electron beam evaporation (EBE) / atomic layer deposition (ALD) process and patterned by photolithography and etching / stripping;

[0037] (b) is a cross-sectional view after the antiferroelectric gate dielectric material with a thickness of 10 to 20 nm is deposited on the entire sheet using the atomic layer deposition (ALD) process based on (a);

[0038] (c) is a cross-sectional view of a stress layer material with a thickness of 5 to 30 nm grown by atomic layer deposition (ALD) / physical vapor deposition (PVD) based on (b), and a subsequent rapid thermal annealing (RTA) process is performed to activate the antiferroelectricity of the antiferroelectric gate dielectric;

[0039] (d) is a cross-sectional view after the stress layer is removed by using the etching solution immersion / chemical etching method based on (c);

[0040] (e) is a cross-sectional view of a ferroelectric semiconductor channel material having a thickness of 0.7 nm to 40 nm after growth by physical vapor transport (PVT) / physical vapor deposition (PVD) / chemical vapor deposition (CVD) process or transfer by micromechanical lift-off process based on (d);

[0041] (f) is a cross-sectional view of the source and drain metal electrode positions defined by electron beam lithography (EBL) based on (e), and then the source and drain metal electrode materials with a thickness of 20 to 80 nm are deposited by physical vapor deposition (PVD) / electron beam evaporation (EBE) process, and then peeled off to make them patterned;

[0042] (g) is a cross-sectional view of the top gate high-k dielectric material after being patterned by using a photolithography process to define the position of the top gate high-k dielectric material and depositing a top gate high-k dielectric material with a thickness of 5 to 10 nm using a physical vapor deposition (PVD) process based on (f);

[0043] (h) is based on (g), using electron beam lithography (EBL) process to define the top gate electrode position, and using physical vapor deposition (PVD) / electron beam evaporation (EBE) process to deposit the top gate electrode material with a thickness of 30 to 50 nm, and then lift it off to make it patterned;

[0044] In the figure:

[0045] 1——Insulating substrate 2——Back gate electrode layer

[0046] 3——Antiferroelectric gate dielectric layer 4——Ferroelectric semiconductor channel layer

[0047] 5——Source and drain metal electrodes 6——Top gate high-k gate dielectric layer

[0048] 7——Top gate electrode layer a——Stress layer DETAILED DESCRIPTION

[0049] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings.

[0050] like Figure 1As shown, the prepared high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric includes an insulating substrate 1, a back gate electrode layer 2, an antiferroelectric gate dielectric layer 3, a ferroelectric semiconductor channel layer 4, source and drain metal electrodes 5, a top gate high-k gate dielectric layer 6 and a top gate electrode layer 7. Among them, the patterned back gate electrode layer 2 is located above the insulating substrate 1, and the antiferroelectric gate dielectric layer 3 is located above the back gate electrode layer 2. On the antiferroelectric gate dielectric layer 3 is the ferroelectric semiconductor channel layer 4, and on both sides of the ferroelectric semiconductor channel layer 4 are the source and drain metal electrodes 5. On the ferroelectric semiconductor channel layer 4 is the top gate high-k gate dielectric layer 6, and on the top gate high-k gate dielectric layer 6 is the top gate electrode layer 7. The entire device presents a dual-gate structure, wherein the antiferroelectric gate dielectric layer serves as a back gate dielectric layer, and the top gate high-k gate dielectric layer serves as a top gate dielectric layer, and the thickness of the back gate dielectric layer is greater than the thickness of the top gate dielectric layer, and the two constitute an asymmetric dual-gate structure.

[0051] The process steps of its preparation method are as follows Figure 2 As shown, specifically including:

[0052] (1) The size and dimensions of the back gate electrode are first defined on the insulating substrate 1 by photolithography, and a back gate electrode material with a thickness of 30 to 50 nm is deposited by physical vapor deposition (PVD) / electron beam evaporation (EBE) / atomic layer deposition (ALD) process, and patterned by acetone ultrasonic stripping, such as Figure 2 As shown in (a); the back gate electrode material can be selected from common metals such as TiN, Al, Au, Pt, TaN, W, etc., and can also be selected from heavily doped Si or Ge and conductive oxides, including but not limited to LSMO, Nb-STO, RuO2, etc. Any material with excellent conductivity can be used as a candidate material for the back gate electrode.

[0053] (2) Using the atomic layer deposition (ALD) process to grow an antiferroelectric gate dielectric material with a thickness of 10 to 20 nm, the antiferroelectric gate dielectric material can be selected from Zr-rich HfO2, Al-doped HfO2 with a certain concentration, Si-doped HfO2 with a certain concentration, or ZrO 2， like Figure 2 (b)

[0054] (3) A stress layer a with a thickness of 5 to 30 nm is grown on the whole wafer by using an atomic layer deposition (ALD) process / physical vapor deposition (PVD) process, and the sample is subjected to rapid thermal annealing (RTA) in a N2 atmosphere to activate the antiferroelectricity of the antiferroelectric gate dielectric, such as Figure 2 (c) is shown. The annealing temperature range is 400℃~700℃, and the annealing time range is 30s~150s. The annealing conditions should be adjusted appropriately according to the type of antiferroelectric gate dielectric;

[0055] (4) Remove the stress layer a by using a corrosive solution immersion / chemical etching method, such as Figure 2(d) As shown. When removing the stress layer, a process with excellent etching selectivity should be selected to avoid damaging the antiferroelectric layer while removing the stress layer. For example, if the stress layer is TiN, a mixture of H2O2 and NH3·H2O (H2O2: NH3·H2O: H2O = 1:1:5) can be selected to remove TiN;

[0056] (5) Using physical vapor transport (PVT) / physical vapor deposition (PVD) / chemical vapor deposition (CVD) processes to grow or using micromechanical lift-off processes to transfer ferroelectric semiconductor channel materials with a thickness of 0.7 nm to 40 nm, such as Figure 2 (e) As shown. The ferroelectric semiconductor channel material must have a suitable spontaneous polarization strength, a bandgap width of less than 3.5V, excellent and stable out-of-plane spontaneous polarization, and ensure that the introduced built-in field can effectively shift the double hysteresis curve of the antiferroelectric gate medium. At the same time, its coercive field should also be at least twice greater than the equivalent coercive field of the antiferroelectric gate medium. Available materials include but are not limited to α-In2Se3, 1T-MoTe2, WTe2, ReS2, InSe, etc.;

[0057] (6) Use electron beam lithography (EBL) to define the source and drain metal electrode positions, and then use physical vapor deposition (PVD) / electron beam evaporation (EBE) to deposit source and drain metal electrode materials with a thickness of 20 to 80 nm, and then use acetone stripping to pattern them, such as Figure 2 (f) As shown; the source and drain metal electrodes should form good ohmic contact with the ferroelectric semiconductor channel to reduce the contact resistance. Metal materials such as Al, Ti, Au, Ag, Pt, and Pd can be used. Low temperature annealing (100℃~200℃) can improve the contact resistance;

[0058] (7) Use photolithography to define the position of the top gate high-k gate dielectric, and then use physical vapor deposition (PVD) to deposit a top gate high-k gate dielectric material with a thickness of 5 to 10 nm, and then use acetone stripping to pattern it, such as Figure 2 (g) As shown. The top gate high-k gate dielectric requires a large dielectric bandgap, low leakage current, high dielectric constant, and strong anti-breakdown capability. Materials such as Al2O3, HfO2, and ZrO2 can be selected;

[0059] (8) Using electron beam lithography (EBL) process to define the top gate electrode position, and using physical vapor deposition (PVD) / electron beam evaporation (EBE) process to deposit the top gate electrode material with a thickness of 30 to 50 nm, and then lift it off to make it patterned, such as Figure 2 The top gate electrode material is required to have excellent electrical conductivity and thermal stability, and the available materials include but are not limited to Pt, TiN, Al, Au, Ag, Pd, TaN, W and other materials.

[0060] At this point, the high-durability FeFET based on the ferroelectric semiconductor channel and the antiferroelectric gate dielectric can be obtained.

[0061] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A high-durability FeFET device based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric, comprising an insulating substrate, characterized in that: A back gate electrode layer is formed on the insulating substrate, an antiferroelectric gate dielectric layer is formed on the back gate electrode layer, a ferroelectric semiconductor channel layer is formed on the antiferroelectric gate dielectric layer, source and drain metal electrodes are formed on both sides of the ferroelectric semiconductor channel layer, the source and drain metal electrodes are simultaneously located on the antiferroelectric gate dielectric layer, a top gate high-k gate dielectric layer is formed on the ferroelectric semiconductor channel layer, and a top gate electrode layer is formed on the top gate high-k gate dielectric layer, wherein the antiferroelectric gate dielectric layer serves as the back gate dielectric layer, the top gate high-k gate dielectric layer serves as the top gate dielectric layer, the thickness of the back gate dielectric layer is greater than the thickness of the top gate dielectric layer, and the two constitute an asymmetric double-gate structure.

2. The FeFET device according to claim 1, characterized in that The insulating substrate material is mica, sapphire, diamond, strontium titanate STO, silicon oxide SiO2; the total thickness of the insulating substrate should be greater than 100 μm, and the thickness of the effective insulating layer should be greater than 20 nm.

3. The FeFET device according to claim 1, characterized in that The back gate electrode material is TiN, Al, Au, Pt, TaN, W, or heavily doped Si or Ge, and conductive oxides: LSMO, Nb-STO, RuO2; the thickness of the back gate electrode material is 30 to 50 nm.

4. The FeFET device according to claim 1, characterized in that The antiferroelectric gate dielectric material adopts hafnium oxide-based antiferroelectric material: Zr-rich HfO2, Al-doped HfO2 with a certain concentration, Si-doped HfO2 or ZrO2 with a certain concentration; the thickness of the antiferroelectric gate dielectric material is 10-20nm.

5. The FeFET device according to claim 1, characterized in that The ferroelectric semiconductor channel material is α-In2Se3, 1T-MoTe2, WTe2, ReS2 or InSe; the thickness of the ferroelectric semiconductor channel material is 0.7-40nm, and the lateral size is greater than 10μm.

6. The FeFET device according to claim 1, characterized in that The source and drain metal electrodes are made of Al, Ti, Au, Ag, Pt or Pd; the thickness of the source and drain metal electrodes is between 20 and 80 nm.

7. The FeFET device according to claim 1, characterized in that The top gate high-k gate dielectric material is Al2O3, HfO2 or ZrO2, and the thickness of the top gate high-k gate dielectric material is 5-10nm.

8. The FeFET device according to claim 1, characterized in that The top gate electrode material is Pt, TiN, Al, Au, Ag, Pd, TaN or W, and the thickness of the top gate electrode is 30-50 nm.

9. A method for preparing a FeFET device as claimed in claim 1, characterized in that: The following steps are involved: (1) First, the size and dimension of the back gate electrode are defined by photolithography on an insulating substrate, and a back gate electrode material with a thickness of 30 to 50 nm is deposited by physical vapor deposition / electron beam evaporation / atomic layer deposition process, and then patterned by etching / stripping process; (2) growing an antiferroelectric gate dielectric with a thickness of 10 to 20 nm on the sample obtained in step (1) using an atomic layer deposition process; (3) growing a stress layer with a thickness of 5 to 30 nm on the sample obtained in step (2) by using an atomic layer deposition process / physical vapor deposition process, and performing rapid thermal annealing on the sample in a N2 atmosphere to activate the antiferroelectricity of the antiferroelectric gate dielectric; (4) Removing the stress layer by immersion in a corrosive solution / chemical etching method; (5) growing a ferroelectric semiconductor channel material having a thickness of 0.7 nm to 40 nm on the sample obtained in step (4) by using a physical vapor transport / physical vapor deposition / chemical vapor deposition process or transferring the material by micromechanical stripping; (6) using electron beam lithography to define the positions of source and drain metal electrodes, and using physical vapor deposition / electron beam evaporation to deposit source and drain metal electrode materials with a thickness of 20 to 80 nm on the sample obtained in step (5), and then peeling them off to make them patterned; (7) photolithography to define the position of the top gate high-k gate dielectric, and using a physical vapor deposition process to deposit a top gate high-k gate dielectric material with a thickness of 5 to 10 nm on the sample obtained in step (6), and then stripping it to make it patterned; (8) Using electron beam lithography to define the position of the top gate electrode, and using physical vapor deposition / electron beam evaporation to deposit a top gate electrode material with a thickness of 30 to 50 nm on the sample obtained in step (7), and then peeling it off to make it patterned.

10. The method for preparing a FeFET device according to claim 9, characterized in that: The material of the stress layer is TiN, TaN, W, Ti or Ru, the temperature range of the rapid thermal annealing RTA process is 400° C. to 700° C., and the annealing time range is 30s to 150s.

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