Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, and the array substrate comprises a substrate, at least one first transistor located at one side of the substrate; the first shielding structure is located between the first transistor and the substrate; the at least one second transistor is located on one side of the substrate, and the first transistor and the second transistor are located on the same side of the substrate; the second shielding structure is located between the second transistor and the substrate; the first shielding structure and the second shielding structure are different in potential. By applying different potentials to the first shielding structure and the second shielding structure, respectively, compensation can be made for output characteristics of the first transistor and the second transistor, respectively. Therefore, according to the technical scheme provided by the invention, the problem of non-uniform display caused by output characteristic drift of the thin film transistor can be solved, the stability of the output characteristic of the thin film transistor is improved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Thin Film Transistor (TFT) is one of the core components in the display panel, responsible for controlling the on / off state of each pixel, thereby accurately adjusting the arrangement of liquid crystal molecules to achieve image display. With the continuous development of display technology, thin film transistors have been widely used in fields such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). However, in the integrated circuit of the display panel, due to the electric field effect, the output characteristics of the thin film transistor show instability, resulting in inaccurate pixel control of the display panel, which in turn affects the overall display quality, manifested as uneven brightness, color distortion or image retention.

[0003] Therefore, the prior art has the problem that the output characteristics of the thin film transistor drift, resulting in uneven display. Summary of the invention

[0004] In view of this, the embodiments of the present application are directed to providing an array substrate and a display panel to solve the problem of uneven display caused by drift of output characteristics of thin film transistors.

[0005] In a first aspect, the present application provides an array substrate, comprising: a substrate; at least one first transistor, located on one side of the substrate; a first shielding structure, the first shielding structure is located between the first transistor and the substrate; at least one second transistor, located on one side of the substrate, and the first transistor and the second transistor are located on the same side of the substrate; and a second shielding structure, the second shielding structure is located between the second transistor and the substrate; wherein the first shielding structure and the second shielding structure have different potentials.

[0006] In one embodiment, the first shielding structure includes multiple first shielding units, and the multiple first shielding units are of the same potential; preferably, at least one first transistor includes multiple first transistors, and the first shielding units correspond to the first transistors one by one; preferably, the first shielding structure also includes a first bridge wire, and the multiple first shielding units are interconnected through the first bridge wire, and the first bridge wire and the first shielding unit are arranged in different layers; preferably, the second shielding structure includes multiple second shielding units, and the multiple second shielding units are of the same potential; preferably, at least one second transistor includes multiple second transistors, and the second shielding units correspond to the second transistors one by one; preferably, the second shielding structure also includes a second bridge wire, and the multiple second shielding units are interconnected through the second bridge wire, and the second bridge wire and the second shielding unit are arranged in different layers.

[0007] In one embodiment, at least part of the first shielding unit and the second shielding unit are disposed on the same layer.

[0008] In one embodiment, the orthographic projection of the first transistor on the substrate is located within the orthographic projection range of the first shielding unit corresponding to the first transistor on the substrate; the orthographic projection of the second transistor on the substrate is located within the orthographic projection range of the second shielding unit corresponding to the second transistor on the substrate.

[0009] In one embodiment, the materials of the first transistor and the second transistor are different; and / or the functions of the first transistor and the second transistor are different; preferably, the first transistor is a switch tube and the second transistor is a driver tube; preferably, the first transistor includes at least one of a low-temperature polysilicon switch tube, a low-temperature polysilicon driver tube, an indium gallium zinc oxide switch tube, and an indium gallium zinc oxide driver tube; preferably, the second transistor includes at least one of a low-temperature polysilicon switch tube, a low-temperature polysilicon driver tube, an indium gallium zinc oxide switch tube, and an indium gallium zinc oxide driver tube.

[0010] In one embodiment, the array substrate further includes a first signal line connected to the first shielding structure; and a second signal line connected to the second shielding structure.

[0011] The second aspect of the present application provides an array substrate, comprising: a base substrate; a plurality of first transistors located on one side of the base substrate; and a first shielding structure located between the first transistors and the base substrate; wherein the potential of the first shielding structure is adjustable.

[0012] In one embodiment, the array substrate also includes multiple selection modules and multiple first signal lines, the first shielding structure includes multiple first shielding units, the selection modules correspond one-to-one to the first shielding units, and the selection modules are configured to selectively turn on a first signal line and a first shielding unit corresponding to the selection module based on the acquired control signal.

[0013] In one embodiment, the selection module includes multiple switch tubes, the switch tubes correspond to the first signal line one by one, and the switch tubes are coupled between the first signal line and the first shielding unit; preferably, the number of switch tubes is 2 or 3; preferably, the number of switch tubes in different selection modules is the same.

[0014] A third aspect of the present application provides a display panel, comprising: an array substrate as mentioned in the above embodiment.

[0015] The array substrate provided by the present application can apply different potentials to the first shielding structure and the second shielding structure respectively by setting the first shielding structure and the second shielding structure corresponding to the first transistor and the second transistor respectively. Under the action of the electric field generated by the first shielding structure and the second shielding structure, the output characteristics of the first transistor and the second transistor are shifted differently. Therefore, by applying different potentials to the first shielding structure and the second shielding structure respectively, compensation can be made for the output characteristics of the first transistor and the second transistor respectively, so that the first transistor and the second transistor can be restored to a working state that is not affected by the electric field of the first shielding structure and the second shielding structure. Therefore, the technical solution provided by the present application can solve the problem of uneven display caused by the drift of the output characteristics of the thin film transistor, improve the stability of the output characteristics of the thin film transistor, and enhance the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a structural schematic diagram of an array substrate in the related art.

[0017] Figure 2 Shown is a structural schematic diagram of another array substrate in the related art.

[0018] Figure 3 FIG. 1 is a schematic diagram of the structure of an array substrate provided in one embodiment of the present application.

[0019] Figure 4 Shown is a schematic structural diagram of an array substrate provided in another embodiment of the present application.

[0020] Figure 5 Shown is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0021] Figure 6 Shown is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0022] Figure 7 Shown is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0023] Figure 8 Shown is a schematic structural diagram of an array substrate provided in yet another embodiment of the present application.

[0024] Fig. 9 The figure shows a circuit diagram of a selection module, a first signal line and a shielding unit connected according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] Figure 1 FIG. 1 is a schematic diagram of the structure of an array substrate in the related art. Figure 1 The conventional array substrate includes a substrate 101 and a pixel circuit located on one side of the substrate 101, and the pixel circuit includes multiple film layers, and the multiple film layers include a first flexible layer PI1, a first barrier layer BL1, a second flexible layer PI2, a second barrier layer BL2, a first inorganic layer 102, a second inorganic layer 103, a first channel layer 104, a first gate insulating layer GI1, a first metal layer M1, a first capacitor insulating layer CI1, a second metal layer M2, a first dielectric layer ILD1, a third metal layer M3, a first planar layer PIN1, a fourth metal layer M4, a second planar layer PIN2, a first electrode Anode1, a first pixel definition layer PDL1 and a first support layer SPC1.

[0027] Figure 2 FIG. 1 is a schematic diagram of another structure of an array substrate in the related art, see Figure 2 , the array substrate also includes a first shielding layer BSM, which is located between the substrate 101 and the first channel layer 104. In the manufacturing process of the display panel or the array substrate, the first shielding layer BSM is often used for light shielding layer or fingerprint recognition. In the flexible display panel, the first shielding layer BSM is also used to eliminate the influence of mobile charges on the flexible substrate side. The inventors have found that the first shielding layer BSM is not connected to the circuit in the array substrate, resulting in uncontrollable electric field strength of the additional electric field formed. When the additional electric field acts on the first channel layer 104, it may cause the abnormal phenomenon that the output characteristic curve of the thin film transistor in the pixel circuit is warped in the saturation region, making the output current of the pixel circuit abnormal, resulting in uneven display.

[0028] Based on this, the present application provides an array substrate and a display panel to solve the problem of uneven display caused by output characteristic drift of thin film transistors.

[0029] Figure 3 FIG. 1 is a schematic diagram of the structure of an array substrate provided in an embodiment of the present application. Figure 3The array substrate includes a substrate substrate 200, at least one first transistor 201, which is located on one side of the substrate substrate 200; a first shielding structure 202, which is located between the first transistor 201 and the substrate substrate 200; at least one second transistor 203, which is located on one side of the substrate substrate 200, and the first transistor 201 and the second transistor 203 are located on the same side of the substrate substrate 200; and a second shielding structure 204, which is located between the second transistor 203 and the substrate substrate 200; wherein the first shielding structure 202 and the second shielding structure 204 have different potentials.

[0030] Specifically, the base substrate 200 is used to carry the first transistor 201 and the second transistor 203. The types of the base substrate 200 include but are not limited to a glass substrate or a polymer substrate.

[0031] The array substrate includes at least one first transistor 201 and at least one second transistor 203, which correspond to a first shielding structure 202 and a second shielding structure 204, respectively. Each shielding structure is located between the transistor corresponding to the shielding structure and the base substrate 200, and is used for light shielding or fingerprint recognition. The material of the first shielding structure 202 and the second shielding structure 204 includes a metal material, and the first shielding structure 202 and the second shielding structure 204 are insulated. The present application does not specifically limit the relative position relationship between the first shielding structure 202 and the second shielding structure 204. The first shielding structure 202 and the second shielding structure 204 can be set in the same layer or in different layers.

[0032] The electric fields generated by the first shielding structure 202 and the second shielding structure 204 act on the channel layers of the first transistor 201 and the second transistor 203, respectively, which may cause the output characteristics of the first transistor 201 and the second transistor 203 to shift. In order to eliminate the characteristic drift phenomenon of the first transistor 201 and the second transistor 203, different potentials are applied to the first shielding structure 202 and the second shielding structure 204.

[0033] In the array substrate, the first shielding structure 202 and the second shielding structure 204 are insulated from each other. Under the action of the electric field generated by the first shielding structure 202 and the second shielding structure 204, the output characteristics of the first transistor 201 and the second transistor 203 are offset differently. Therefore, by applying different potentials to the first shielding structure 202 and the second shielding structure 204, the output characteristic offsets of the first transistor 201 and the second transistor 203 can be compensated respectively.

[0034] The array substrate provided in the embodiment of the present application can apply different potentials to the first shielding structure 202 and the second shielding structure 204 respectively by setting the first shielding structure 202 and the second shielding structure 204 corresponding to the first transistor 201 and the second transistor 203 respectively. Under the action of the electric field generated by the first shielding structure 202 and the second shielding structure 204, the output characteristics of the first transistor 201 and the second transistor 203 are offset differently. Therefore, by applying different potentials to the first shielding structure 202 and the second shielding structure 204 respectively, compensation can be made for the output characteristics of the first transistor 201 and the second transistor 203 respectively, so that the first transistor 201 and the second transistor 203 are restored to the working state not affected by the electric field of the first shielding structure 202 and the second shielding structure 204. Therefore, the technical solution provided in the embodiment of the present application can solve the problem of uneven display caused by the drift of the output characteristics of the thin film transistor, improve the stability of the output characteristics of the thin film transistor, and enhance the display effect of the display panel.

[0035] Figure 4 FIG. 1 is a schematic diagram of the structure of an array substrate provided by another embodiment of the present application. Figure 4 The first shielding structure 202 includes a plurality of first shielding units 2021, and the plurality of first shielding units 2021 are of equal potential; preferably, at least one first transistor 201 includes a plurality of first transistors 201, and the first shielding units 2021 correspond to the first transistors 201 one by one; preferably, the first shielding structure 202 also includes a first bridge wire, and the plurality of first shielding units 2021 are interconnected through the first bridge wire, and the first bridge wire and the first shielding unit 2021 are arranged in different layers; preferably, the second shielding structure 204 includes a plurality of second shielding units 2041, and the plurality of second shielding units 2041 are of equal potential; preferably, at least one second transistor 203 includes a plurality of second transistors 203, and the second shielding units 2041 correspond to the second transistors 203 one by one; preferably, the second shielding structure 204 also includes a second bridge wire, and the plurality of second shielding units 2041 are interconnected through the second bridge wire, and the second bridge wire and the second shielding unit 2041 are arranged in different layers.

[0036] Specifically, in the array substrate, the first shielding structure 202 includes a plurality of first shielding units 2021, and the second shielding structure 204 includes a plurality of second shielding units 2041. The number of the first shielding units 2021 is related to the number of the first transistors 201, and the number of the second shielding units 2041 is related to the number of the second transistors 203. In a preferred case, the first shielding units 2021 correspond to the first transistors 201 one-to-one, and the second shielding units 2041 correspond to the second transistors 203 one-to-one. For example, when the working states of the plurality of first transistors 201 are consistent during operation, the drift of the output characteristics thereof after being acted upon by the electric field is also consistent. By applying the same potential to the plurality of first shielding units 2021 corresponding to the plurality of first transistors 201, the output characteristics of the plurality of first transistors 201 can be compensated. For another example, when the working states of the plurality of second transistors 203 are consistent during operation, the drift of the output characteristics thereof after being acted upon by the electric field is also consistent. By applying the same potential to the plurality of second shielding units 2041 corresponding to the plurality of second transistors 203, the output characteristics of the plurality of second transistors 203 can be compensated. The first shielding structure 202 and the second shielding structure 204 are respectively provided with a first bridge wire and a second bridge wire. The first bridge wire is used to connect multiple first shielding units 2021, and the second bridge wire is used to connect multiple second shielding units 2041. For the convenience of routing, these bridge wires and shielding units are arranged in different layers.

[0037] In this embodiment, by respectively providing a plurality of first shielding units 2021 and a second shielding unit 2041 in the first shielding structure 202 and the second shielding structure 204, the plurality of first transistors 201 and the second transistors 203 are respectively corresponded. By applying the same potential to the plurality of first shielding units 2021 (or the second shielding units 2041), the output characteristics of the plurality of first transistors 201 (or the second transistors 203) can be compensated. By applying different potentials to the first shielding unit 2021 and the second shielding unit 2041, the output characteristics of the first transistor 201 and the second transistor 203 can be further compensated respectively, which is beneficial to improving the stability of the output characteristics of the transistors and the display effect of the display panel.

[0038] In one embodiment, at least part of the first shielding unit 2021 and the second shielding unit 2041 are disposed on the same layer.

[0039] Specifically, disposing at least a portion of the first shielding unit 2021 and the second shielding unit 2041 on the same layer is beneficial to improving the compactness of the device, making the manufacturing process simple and easy to implement.

[0040] In one embodiment, the orthographic projection of the first transistor 201 on the substrate 200 is located within the orthographic projection range of the first shielding unit 2021 corresponding to the first transistor 201 on the substrate 200; the orthographic projection of the second transistor 203 on the substrate 200 is located within the orthographic projection range of the second shielding unit 2041 corresponding to the second transistor 203 on the substrate 200.

[0041] Specifically, Figure 5 FIG. 1 is a schematic diagram of the structure of an array substrate provided in another embodiment of the present application. Figure 5 The array substrate includes a plurality of film layers, which include a third flexible layer PI3, a third barrier layer BL3, a fourth flexible layer PI4, a fourth barrier layer BL4, a third inorganic layer 211, a fourth inorganic layer 212, a second channel layer 213, a second gate insulating layer GI2, a fifth metal layer M5, a second capacitor insulating layer CI2, a sixth metal layer M6, a second dielectric layer ILD2, a seventh metal layer M7, a third planar layer PIN3, an eighth metal layer M8, a fourth planar layer PIN4, a second electrode Anode2, a second pixel definition layer PDL2, a second support layer SPC2, and a first shielding unit 20212021. The second channel layer 213, the second gate insulating layer GI2, the fifth metal layer M5, the seventh metal layer M7, and the eighth metal layer M8 together constitute a first transistor 201 and a second transistor 203. The orthographic projection of the first transistor 201 on the substrate 200 is located within the orthographic projection range of the first shielding unit 2021 on the substrate 200 corresponding to the first transistor 201 , and the orthographic projection of the second transistor 203 on the substrate 200 is located within the orthographic projection range of the second shielding unit 2041 on the substrate 200 corresponding to the second transistor 203 .

[0042] Exemplarily, the material of the third flexible layer PI3 and the fourth flexible layer PI4 may include polyimide (PI), which is an excellent flexible material. The materials of the third barrier layer BL3, the fourth barrier layer BL4, the third inorganic layer 211, the fourth inorganic layer 212, the second gate insulating layer GI2, the second capacitor insulating layer CI2 and the second dielectric layer ILD2 may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON) and their stacks, which may be achieved by a chemical vapor deposition (CVD) process. The materials forming the first shielding unit 2021 and the second shielding unit 2041 include, but are not limited to, metals or metal alloys, such as molybdenum, aluminum or molybdenum-tungsten alloys.

[0043] In this embodiment, by limiting the orthographic projection of the transistor on the base substrate 200 to be within the orthographic projection range of the shielding unit corresponding to the transistor on the base substrate 200 , the light shielding effect of the shielding unit on the transistor is further improved.

[0044] In one embodiment, the materials of the first transistor 201 and the second transistor 203 are different; and / or, the functions of the first transistor 201 and the second transistor 203 are different; preferably, the first transistor 201 is a switch tube, and the second transistor 203 is a driver tube; preferably, the first transistor 201 includes at least one of a low-temperature polysilicon switch tube, a low-temperature polysilicon driver tube, an indium gallium zinc oxide switch tube, and an indium gallium zinc oxide driver tube; preferably, the second transistor 203 includes at least one of a low-temperature polysilicon switch tube, a low-temperature polysilicon driver tube, an indium gallium zinc oxide switch tube, and an indium gallium zinc oxide driver tube.

[0045] Specifically, the first transistor 201 and the second transistor 203 are of different types, that is, the materials of the channel layers in the first transistor 201 and the second transistor 203 are different, and / or the functions of the first transistor 201 and the second transistor 203 in the array substrate are different. For example, the channel layer material of the first transistor 201 is a low-temperature polycrystalline silicon semiconductor, which is used as a switching transistor in the array substrate; for another example, the channel layer material of the first transistor 201 is a low-temperature polycrystalline silicon semiconductor, which is used as a driving transistor in the array substrate; for another example, the channel layer material of the first transistor 201 is an indium gallium zinc oxide semiconductor, which is used as a switching transistor in the array substrate; for another example, the channel layer material of the first transistor 201 is an indium gallium zinc oxide semiconductor, which is used as a driving transistor in the array substrate. Usually, the array substrate includes both a switching transistor and a driving transistor. The indium gallium zinc oxide transistor has good uniformity and can further improve the performance of the thin film transistor. Low-temperature polysilicon thin film has a regular atomic arrangement, high carrier mobility, and high driving current. It can speed up the reaction time of liquid crystal molecules, reduce the volume of thin-film transistors, increase the transmission area in pixel units, and make the display device have higher brightness and resolution. Low-temperature polysilicon oxide (LTPO) substrate technology is an emerging technology in recent years, that is, the array substrate contains both oxide thin-film transistors and low-temperature polysilicon thin-film transistors. This setting can save power for the display screen, thereby reducing the power consumption of the display screen.

[0046] It should be noted that the embodiment of the present application does not specifically limit the channel layer materials of the first transistor 201 and the second transistor 203 included in the array substrate. The materials forming the channel layer include but are not limited to the low-temperature polysilicon, indium gallium zinc oxide semiconductor and other materials mentioned in the above embodiments.

[0047] In this embodiment, the transistors in the array substrate are divided into a first transistor 201 and a second transistor 203 according to the materials and functions of the transistors, which correspond to the first shielding structure 202 and the second shielding structure 204 respectively. By applying different potentials to the first shielding structure 202 and the second shielding structure 204, it is possible to further compensate for the output characteristics of the first transistor 201 and the second transistor 203 respectively, which is beneficial to improving the stability of the output characteristics of the transistors and the display effect of the display panel.

[0048] Figure 6 FIG. 2 is a schematic diagram of the structure of an array substrate provided by another embodiment of the present application. Figure 6 As shown, the array substrate further includes a first signal line 205 connected to the first shielding structure 202 ; and a second signal line 206 connected to the second shielding structure 204 .

[0049] Specifically, when the first signal line 205 is connected to the first shielding structure 202, the potential of the first signal line 205 is applied to the first shielding structure 202 to compensate for the output characteristic deviation of the first transistor 201 corresponding to the first shielding structure 202. When the second signal line 206 is connected to the second shielding structure 204, the potential of the second signal line 206 is applied to the second shielding structure 204 to compensate for the output characteristic deviation of the second transistor 203 corresponding to the second shielding structure 204.

[0050] In this embodiment, by providing the first signal line 205 and the second signal line 206 corresponding to the first shielding structure 202 and the second shielding structure 204 respectively in the array substrate, the potentials of the first signal line 205 and the second signal line 206 can be respectively applied to the first shielding structure 202 and the second shielding structure 204, thereby compensating for the output characteristic deviations of the first transistor 201 and the second transistor 203 respectively, which is beneficial to improving the stability of the output characteristics of the transistors and improving the display effect of the display panel.

[0051] Figure 7 FIG. 2 is a schematic diagram of the structure of an array substrate provided by another embodiment of the present application. Figure 7 As shown, the array substrate includes: a base substrate 200; a plurality of first transistors 201 located on one side of the base substrate 200; and a first shielding structure 202 located between the first transistors 201 and the base substrate 200; wherein the potential of the first shielding structure 202 is adjustable.

[0052] Specifically, in the array substrate, multiple first transistors 201 correspond to the same first shielding structure 202, and the first shielding structure 202 generates a first electric field. When the working states of the multiple first transistors 201 are consistent, the first electric field has the same effect on the multiple first transistors 201. Therefore, by applying a single corresponding potential on the first shielding structure 202, the output characteristic deviation of the multiple first transistors 201 can be compensated. When the working states of the multiple first transistors 201 are inconsistent, the effects of the first electric field on the multiple first transistors 201 are inconsistent. Therefore, by applying corresponding multiple potentials on the first shielding structure 202, the output characteristic deviation of the multiple first transistors 201 can be compensated. Therefore, the potential of the first shielding structure 202 is adjustable in this embodiment, and the advantage is that the output characteristics of the first transistor 201 can be compensated according to the different working states of the first transistor 201.

[0053] Figure 8 FIG. 1 is a schematic diagram of the structure of an array substrate provided in another embodiment of the present application. Figure 8 The first shielding structure 202 includes a plurality of first shielding units 2021, the selection module 207 corresponds to the first shielding unit 2021 one by one, and the selection module 207 is configured to selectively conduct a first signal line 205 and the first shielding unit 2021 corresponding to the selection module based on the acquired control signal.

[0054] Specifically, the potentials of the plurality of first signal lines 205 are different. The control signal acquired by the selection module 207 includes the on-off state between the first shielding unit 2021 corresponding to the selection module 207 and the plurality of first signal lines 205. Exemplarily, the working principle of the selection module 207 is as follows: when the selection module 207 acquires the control signal, the corresponding first signal line 205 is selected to be connected with the first shielding unit 2021 corresponding to the selection module 207 according to the control signal, and the potential of the first signal line 205 is applied to the first shielding unit 2021 corresponding to the selection module 207. The working state of each transistor in the array substrate includes at least one of a cut-off state, an amplified state and a saturated state. Exemplarily, the working state of the driving transistor includes a saturated state, and the working state of the switching transistor includes a cut-off state and an amplified state. When the first transistor 201 is in different working states, the selection module 207 corresponding to the first shielding unit 2021 corresponding to the first transistor 201 turns on different first signal lines 205 and the first shielding unit 2021, so that different potentials are applied to the first shielding unit 2021, thereby compensating for the output characteristic deviation of the first transistor 201 in different working states.

[0055] In this embodiment, by setting the selection module 207 and the first signal line 205, the selection module 207 corresponds to the first shielding unit 2021, and the first signal line 205 and the first shielding unit 2021 are selectively turned on according to the control signal, so that the potential of the first shielding unit 2021 can be dynamically adjusted according to the actual working state of the first transistor 201, and further compensation can be made for the output characteristic deviation of the first transistor 201 under different working states, which is beneficial to improving the stability of the output characteristics of the transistor and the display effect of the display panel.

[0056] Fig. 9 FIG. 1 is a schematic diagram of a circuit for connecting a selection module, a first signal line, and a first shielding unit provided by an embodiment of the present application. Fig. 9 Optionally, the selection module 207 includes multiple switch tubes 2071, the switch tubes 2071 correspond to the first signal line 205 one by one, and the switch tubes 2071 are coupled between the first signal line 205 and the first shielding unit 2021; preferably, the number of switch tubes 2071 is 2 or 3; preferably, the number of switch tubes 2071 in different selection modules 207 is the same.

[0057] Specifically, the on-off state of the switch tube 2071 is controlled by the control signal obtained by the selection module 207. Exemplarily, after the selection module 207 obtains the control signal, the switch tube 2071 coupled between the first signal line 205 and the first shielding unit 2021 corresponding to the selection module 207 is turned on according to the control signal, and the corresponding first signal line 205 is turned on with the first shielding unit 2021 corresponding to the selection module 207, and the potential of the first signal line 205 is applied to the first shielding unit 2021 corresponding to the selection module 207.

[0058] The number of switch tubes 2071 is related to the working state of the first transistor 201201. Exemplarily, setting the number of switch tubes 2071 to 2 can achieve compensation for the cut-off state and the amplified state of the first transistor 201201. Setting the number of switch tubes 2071 to 3 can achieve compensation for the cut-off state, the amplified state, and the saturated state of the first transistor 201201. The embodiment of the present application does not specifically limit the number of switch tubes 2071. In one embodiment, the number of switch tubes 2071 in different selection modules 207 is the same.

[0059] In this embodiment, a switch tube 2071 coupled between the first signal line 205 and the first shielding unit 2021 is provided in the selection module 207, and whether the first signal line 205 and the first shielding unit 2021 are connected is controlled by controlling the on-off state of the switch tube 2071. This arrangement makes the structure of the selection module 207 simple and easy to implement, which is further conducive to improving the stability of the output characteristics of the transistor and the display effect of the display panel.

[0060] The embodiment of the present application further provides a display panel, which includes the array substrate mentioned in the above embodiment. The technical principles and effects produced are similar and will not be described in detail here.

[0061] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: substrate substrate; At least one first transistor, located on one side of the substrate; a first shielding structure, the first shielding structure being located between the first transistor and the substrate; at least one second transistor, located on one side of the substrate, and the first transistor and the second transistor are located on the same side of the substrate; as well as a second shielding structure, the second shielding structure being located between the second transistor and the substrate; The first shielding structure and the second shielding structure have different potentials.

2. The array substrate according to claim 1, characterized in that: The first shielding structure comprises a plurality of first shielding units, and the plurality of first shielding units have the same potential; Preferably, at least one of the first transistors includes a plurality of the first transistors, and the first shielding units correspond to the first transistors one by one; Preferably, the first shielding structure further comprises a first bridge wire, the plurality of first shielding units are connected to each other via the first bridge wire, and the first bridge wire and the first shielding unit are arranged in different layers; Preferably, the second shielding structure comprises a plurality of second shielding units, and the plurality of second shielding units are of equal potential; Preferably, at least one of the second transistors includes a plurality of the second transistors, and the second shielding units correspond to the second transistors one by one; Preferably, the second shielding structure further includes a second bridging wire, the plurality of second shielding units are interconnected via the second bridging wire, and the second bridging wire and the second shielding units are arranged in different layers.

3. The array substrate according to claim 2, characterized in that: At least part of the first shielding unit and the second shielding unit are arranged on the same layer.

4. The array substrate according to claim 2, characterized in that: The orthographic projection of the first transistor on the substrate is located within the orthographic projection range of the first shielding unit corresponding to the first transistor on the substrate; the orthographic projection of the second transistor on the substrate is located within the orthographic projection range of the second shielding unit corresponding to the second transistor on the substrate.

5. The array substrate according to claim 1, characterized in that: The first transistor and the second transistor are made of different materials; and / or, the first transistor and the second transistor have different functions; Preferably, the first transistor is a switch transistor, and the second transistor is a drive transistor; Preferably, the first transistor includes at least one of a low-temperature polysilicon switch tube, a low-temperature polysilicon drive tube, an indium gallium zinc oxide switch tube, and an indium gallium zinc oxide drive tube; Preferably, the second transistor includes at least one of a low-temperature polysilicon switch tube, a low-temperature polysilicon drive tube, an indium gallium zinc oxide switch tube, and an indium gallium zinc oxide drive tube.

6. The array substrate according to claim 1, characterized in that: Also includes: A first signal line connected to the first shielding structure; The second signal line is connected to the second shielding structure.

7. An array substrate, characterized in that: include: substrate substrate; A plurality of first transistors are located on one side of the substrate; as well as A first shielding structure is located between the first transistor and the substrate; Wherein, the potential of the first shielding structure is adjustable.

8. The array substrate according to claim 7, characterized in that: It also includes multiple selection modules and multiple first signal lines, the first shielding structure includes multiple first shielding units, the selection modules correspond one-to-one to the first shielding units, and the selection modules are configured to selectively turn on the first signal line and the first shielding unit corresponding to the selection module based on the acquired control signal.

9. The array substrate according to claim 8, characterized in that: The selection module includes a plurality of switch tubes, the switch tubes correspond to the first signal lines one by one, and the switch tubes are coupled between the first signal line and the first shielding unit; Preferably, the number of the switch tubes is 2 or 3; Preferably, the number of the switch tubes in different selection modules is the same.

10. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 9.

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