Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a first capacitor dielectric layer which is located on a first electrode layer; the second electrode layer is located on the first capacitor dielectric layer of the first capacitor region; the one or more capacitor lamination layers are positioned on the second electrode layer of the first capacitor region; each capacitor lamination layer comprises a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; projection overlapping areas are arranged between the third electrode layers and the second electrode layers and between the adjacent third electrode layers; wherein the one or more second capacitor dielectric layers are also located on the first capacitor dielectric layer of the second capacitor region; the third electrode layer located in the top capacitor lamination layer is used as a top electrode layer, the top electrode layer is further located on one or more second capacitor dielectric layers of the second capacitor area, and a projection overlapping area exists between the top electrode layer and the first electrode layer. According to the embodiment of the invention, the performance of the semiconductor structure is optimized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design in the IC industry have produced successive generations of integrated circuits. Each generation has smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and similar advances in IC processing and manufacturing are required to achieve these advances. Over the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component that can be made using a manufacturing process) has decreased.

[0003] One type of capacitor is a Metal Insulator Metal (MIM) capacitor, which is commonly used in mixed-signal devices and logic devices (such as embedded memory and RF devices). MIM capacitors are commonly used to store charge in various semiconductor devices. In order to meet the performance requirements of the device, the capacitance density of MIM capacitors is also gradually increasing.

[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first capacitor region and a second capacitor region; a plurality of first electrode layers, respectively located on the substrate of the first capacitor region and the second capacitor region; a first capacitor dielectric layer, located on the first electrode layer; a second electrode layer, located on the first capacitor dielectric layer in the first capacitor region; one or more capacitor stacks, located on the second electrode layer in the first capacitor region; each capacitor stack includes a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; wherein one or more second capacitor dielectric layers are also located on the first capacitor dielectric layer in the second capacitor region; the third electrode layer in the capacitor stack located on the top layer is used as a top electrode layer, and the top electrode layer is also located on one or more second capacitor dielectric layers in the second capacitor region, and there is a projected overlapping area with the first electrode layer.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first capacitor region and a second capacitor region; forming multiple first electrode layers on the substrate, respectively located on the first capacitor region and the second capacitor region; forming a first capacitor dielectric layer on the first electrode layer; forming a second electrode layer on the first capacitor dielectric layer in the first capacitor region; after forming the second electrode layer, forming one or more capacitor stacks on the first capacitor region, each capacitor stack comprising a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; wherein, in the step of forming the second capacitor dielectric layer, one or more second capacitor dielectric layers are also formed on the first capacitor dielectric layer in the second capacitor region; the third electrode layer in the capacitor stack located on the top layer is used as a top electrode layer, and the top electrode layer is also formed on one or more second capacitor dielectric layers in the second capacitor region, and there is a projected overlapping area with the first electrode layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The semiconductor structure provided by the embodiment of the present invention further comprises one or more capacitor stacks, which are located on the second electrode layer of the first capacitor region; each capacitor stack comprises a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; wherein one or more second capacitor dielectric layers are also located on the first capacitor dielectric layer of the second capacitor region; the third electrode layer in the capacitor stack located on the top layer is used as the top electrode layer, and the top electrode layer is also located on one or more second capacitor dielectric layers of the second capacitor region, and there is a projected overlapping area with the first electrode layer; therefore, in the first capacitor region, one or more capacitor stacks are also arranged on the second electrode layer, which is beneficial to Capacitors can be formed between two adjacent electrode layers (between the first electrode layer and the second electrode layer, between the second electrode layer and the third electrode layer, and between adjacent third electrode layers), which is beneficial to improving the capacitance density of the first capacitance region; in the second capacitance region, a capacitor is formed between the first electrode layer and the top electrode layer, and a first capacitor dielectric layer and one or more second capacitor dielectric layers are provided between the first electrode layer and the top electrode layer, thereby increasing the thickness of the capacitor dielectric layer between the first electrode layer and the top electrode layer, and further improving the withstand voltage performance of the capacitor in the second capacitance region; further, the embodiment of the present invention can form both a capacitor with good withstand voltage performance and a capacitor with high capacitance density, thereby meeting the demand for providing capacitors of different types and performance parameters on a substrate.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the second electrode layer, one or more capacitor stacks are further formed on the first capacitor region, each capacitor stack comprising a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; wherein, in the step of forming the second capacitor dielectric layer, one or more second capacitor dielectric layers are further formed on the first capacitor dielectric layer in the second capacitor region; the third electrode layer in the capacitor stack located at the top layer is used as the top electrode layer, and the top electrode layer is further formed on one or more second capacitor dielectric layers in the second capacitor region, and there is a projected overlapping area with the first electrode layer; therefore, in the first capacitor region, one or more capacitor stacks are further formed on the second electrode layer. The multi-layer capacitor stack is conducive to forming capacitors between two adjacent electrode layers (between the first electrode layer and the second electrode layer, between the second electrode layer and the third electrode layer, and between adjacent third electrode layers), which is conducive to improving the capacitance density of the first capacitor area; in the second capacitor area, a capacitor is formed between the first electrode layer and the top electrode layer, and a first capacitor dielectric layer and one or more second capacitor dielectric layers are formed between the first electrode layer and the top electrode layer, thereby increasing the thickness of the capacitor dielectric layer between the first electrode layer and the top electrode layer, thereby improving the withstand voltage performance of the capacitor in the second capacitor area; further, the embodiment of the present invention can form a capacitor with good withstand voltage performance and a capacitor with high capacitance density, meeting the needs of forming capacitors of different types and performance parameters on a substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0012] Figures 2 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, the performance of current semiconductor structures needs to be improved.

[0014] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, wherein one or more layers of capacitor stacks are also provided, which are located on the second electrode layer of the first capacitor region; each layer of the capacitor stack includes a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; wherein one or more layers of the second capacitor dielectric layer are also located on the first capacitor dielectric layer of the second capacitor region; the third electrode layer in the capacitor stack located on the top layer is used as a top electrode layer, and the top electrode layer is also located on one or more layers of the second capacitor dielectric layer of the second capacitor region, and has a projected overlapping area with the first electrode layer; therefore, in the first capacitor region, one or more layers of the capacitor stack are also provided on the second electrode layer. The layer is conducive to making the electrode layers of two adjacent layers (between the first electrode layer and the second electrode layer, between the second electrode layer and the third electrode layer, and between the adjacent third electrode layers) form capacitors, which is conducive to improving the capacitance density of the first capacitance area; in the second capacitance area, a capacitor is formed between the first electrode layer and the top electrode layer, and a first capacitor dielectric layer and one or more second capacitor dielectric layers are arranged between the first electrode layer and the top electrode layer, thereby increasing the thickness of the capacitor dielectric layer between the first electrode layer and the top electrode layer, and then improving the withstand voltage performance of the capacitor in the second capacitance area; further, the embodiment of the present invention can form a capacitor with good withstand voltage performance and a capacitor with high capacitance density, which meets the demand for providing capacitors of different types and performance parameters on a substrate.

[0015] In order to solve the technical problem, an embodiment of the present invention also provides a method for forming a semiconductor structure, after forming the second electrode layer, one or more capacitor stacks are formed on the first capacitor region, each capacitor stack includes a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; wherein, in the step of forming the second capacitor dielectric layer, one or more second capacitor dielectric layers are also formed on the first capacitor dielectric layer in the second capacitor region; the third electrode layer in the capacitor stack located at the top layer is used as the top electrode layer, and the top electrode layer is also formed on one or more second capacitor dielectric layers in the second capacitor region, and has a projected overlapping area with the first electrode layer; therefore, in the first capacitor region, a projected overlapping area is also formed on the second electrode layer A capacitor stack having one or more layers is formed, so that capacitors can be formed between two adjacent electrode layers (between the first electrode layer and the second electrode layer, between the second electrode layer and the third electrode layer, and between adjacent third electrode layers), which is beneficial to improving the capacitance density of the first capacitor region; in the second capacitor region, a capacitor is formed between the first electrode layer and the top electrode layer, and a first capacitor dielectric layer and one or more second capacitor dielectric layers are formed between the first electrode layer and the top electrode layer, thereby increasing the thickness of the capacitor dielectric layer between the first electrode layer and the top electrode layer, thereby improving the withstand voltage performance of the capacitor in the second capacitor region; further, the embodiment of the present invention can form a capacitor with good withstand voltage performance and a capacitor with high capacitance density, meeting the demand for forming capacitors of different types and performance parameters on a substrate.

[0016] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0017] refer to Figure 1 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0018] like Figure 1As shown, in this embodiment, the semiconductor structure includes: a substrate 100, including a first capacitor region 100a and a second capacitor region 100b; a plurality of first electrode layers 110, respectively located on the substrates of the first capacitor region 100a and the second capacitor region 100b; a first capacitor dielectric layer 115, located on the first electrode layer 110; a second electrode layer 120, located on the first capacitor dielectric layer 115 of the first capacitor region 100a; one or more capacitor stacks 200, located on the second electrode layer 120 of the first capacitor region 100a; each capacitor stack 200 includes a second capacitor dielectric layer 125 and a second capacitor dielectric layer 125 located on the second capacitor dielectric layer 120; The third electrode layer 130 on the dielectric layer 125; there is a projected overlapping area D between the third electrode layer 130 and the second electrode layer 120, and between adjacent third electrode layers 130; wherein one or more layers of the second capacitor dielectric layer 125 are also located on the first capacitor dielectric layer 115 of the second capacitor area 100b; the third electrode layer 130 in the capacitor stack 200 located on the top layer is used as the top electrode layer 130a, and the top electrode layer 130a is also located on one or more layers of the second capacitor dielectric layer 125 in the second capacitor area 100b, and has a projected overlapping area E with the first electrode layer 110.

[0019] The substrate 100 is used to provide a process platform for forming a MIM capacitor.

[0020] In this embodiment, the substrate 100 includes a device structure layer (not shown) and a back-end interconnection layer (not shown) located on the device structure layer and electrically connected to the device structure layer, the back-end interconnection layer includes a bottom dielectric layer 101 and one or more metal layers located in the bottom dielectric layer, and the multiple metal layers located on the top layer are used as a top metal layer 105.

[0021] The device structure layer is formed by a front-end device manufacturing process. In a specific implementation, the device structure layer may include a substrate and a device structure located on the substrate. The device structure may include a MOS transistor, for example, an NMOS transistor, a PMOS transistor.

[0022] As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0023] The back-end interconnect layer is formed by a back-end interconnect process.

[0024] In this embodiment, the back-end interconnection layer includes a bottom dielectric layer 101 and one or more metal layers located in the bottom dielectric layer 101 , and the multiple metal layers located at the top layer are used as the top metal layer 105 .

[0025] The bottom dielectric layer 101 is used to achieve isolation between metal layers. Specifically, the bottom dielectric layer 101 is an intermetallic dielectric layer (Inter Metal Dielectric, IMD).

[0026] The material of the bottom dielectric layer 101 is a dielectric material. As an example, the material of the bottom dielectric layer 101 is silicon oxide.

[0027] In this embodiment, adjacent metal layers are electrically connected to each other so that the electrical properties of the device structure in the device structure layer are led out through one or more metal layers. Specifically, two adjacent metal layers are electrically connected through a via interconnection structure located between the two layers; the electrical properties of the device structure in the device structure layer are led out through the top metal layer 105.

[0028] The material of the metal layer is a conductive material. In this embodiment, the material of the metal layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0029] The first capacitance region 100a and the second capacitance region 100b are used to form capacitors, respectively. Specifically, in this embodiment, capacitors of different types and performance parameters are formed in the first capacitance region 100a and the second capacitance region 100b, respectively.

[0030] In this embodiment, the substrate 100 further includes: an etch stop layer 102 located on the bottom dielectric layer 101 and covering the top metal layer 105 ; and a top dielectric layer 103 located on the etch stop layer 102 .

[0031] The etch stop layer 102 is used to define the etching stop position in the steps of forming the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, so as to reduce the probability of damaging the top metal layer 105, and is also beneficial to improve the bottom height consistency of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug.

[0032] As an example, the material of the etch stop layer 102 is silicon nitride. In other embodiments, the etch stop layer can also be other materials with high etching selectivity to the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride and NDC (nitride doped carbon).

[0033] The top dielectric layer 103 is used to achieve isolation between the top metal layer 105 and the first electrode layer 110 .

[0034] The material of the top dielectric layer 103 is a dielectric material. As an example, the material of the top dielectric layer 103 is silicon oxide.

[0035] The first electrode layer 110 is used as an electrode plate of the MIM capacitor.

[0036] In this embodiment, the second electrode layer 120 exposes a portion of the top of the first electrode layer 110; in the first capacitor region 100a, the portion of the top of the first electrode layer 110 exposed by the second electrode layer 120 is used as a first connection region I; in the second capacitor region 100b, the top electrode layer 130a exposes a portion of the top of the first electrode layer 110, and the portion of the top of the first electrode layer 110 exposed by the top electrode layer 130a is used as a third connection region III.

[0037] In this embodiment, in the first capacitor region 100a, the first connection region I is used to form a first conductive plug so as to achieve electrical connection between the first conductive plug and the first electrode layer 110, or between the first conductive plug and the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layer.

[0038] In this embodiment, in the second capacitor region 100 b , the third connection region III is used to form a third conductive plug, so that the third conductive plug is electrically connected to the first electrode layer 110 .

[0039] The material of the first electrode layer 110 is a conductive material. As an example, the material of the first electrode layer 110 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0040] The first capacitor dielectric layer 115 is used as an insulating layer in forming the MIM capacitor. The first capacitor dielectric layer 115 located in the first capacitor region 100a is used to isolate the first electrode layer 110 and the second electrode layer 120. The first capacitor dielectric layer 115 located in the second capacitor region 100b is used to achieve isolation between the first electrode layer 110 and the top electrode layer 130a together with the second capacitor dielectric layer 125. Specifically, the first capacitor dielectric layer 115 conformally covers the first electrode layer 110 and the substrate 100.

[0041] The material of the first capacitor dielectric layer 115 is an insulating dielectric material. In this embodiment, the material of the first capacitor dielectric layer 115 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor and correspondingly increase the capacitance density.

[0042] As an example, the material of the first capacitor dielectric layer 115 includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0043] The second electrode layer 120 is used as an electrode plate of the MIM capacitor.

[0044] In this embodiment, the second electrode layer 120 is also located on the substrate 100 at the side of the first electrode layer 110 , and a portion of the second electrode layer 120 on the substrate 100 at the side of the first electrode layer 110 is used as a second connection region II.

[0045] In this embodiment, in the first capacitor region 100a, the second connection region II is used to form a second conductive plug so as to achieve electrical connection between the second conductive plug and the second electrode layer 120, or between the second electrode layer 120 and the third electrode layer 130 of an even numbered layer.

[0046] The material of the second electrode layer 120 is a conductive material. As an example, the material of the second electrode layer 120 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0047] One or more layers of capacitor stacks 200 are located on the second electrode layer 120 of the first capacitor region 100a; each layer of the capacitor stack 200 includes a second capacitor dielectric layer 125 and a third electrode layer 130 located on the second capacitor dielectric layer 125; there is a projected overlapping area D between the third electrode layer 130 and the second electrode layer 120, as well as between adjacent third electrode layers 130, so that in the first capacitor region 100a, capacitors can be formed between two adjacent electrode layers (between the first electrode layer 110 and the second electrode layer 120, between the second electrode layer 120 and the third electrode layer 130, and between adjacent third electrode layers 130), which is beneficial to improving the capacitance density of the first capacitor region 100a.

[0048] Moreover, in the present embodiment, one or more layers of the second capacitor dielectric layer 125 are also located on the first capacitor dielectric layer 115 of the second capacitor region 100b; the third electrode layer 130 in the capacitor stack 200 located at the top layer is used as the top electrode layer 130a, and the top electrode layer 130a is also located on one or more layers of the second capacitor dielectric layer 125 of the second capacitor region 100b, and has a projected overlapping area E with the first electrode layer 110; therefore, in the second capacitor region 100b, a capacitor is formed between the first electrode layer 110 and the top electrode layer 130a, and the first capacitor dielectric layer 115 and one or more layers of the second capacitor dielectric layer 125 are arranged between the first electrode layer 110 and the top electrode layer 130a, thereby increasing the thickness of the capacitor dielectric layer between the first electrode layer 110 and the top electrode layer 130a, and further improving the withstand voltage performance of the capacitor in the second capacitor region 100b.

[0049] Furthermore, in this embodiment, it is possible to form a capacitor with good withstand voltage performance and a capacitor with high capacitance density, thereby meeting the demand for providing capacitors of different types and performance parameters on a substrate.

[0050] In this embodiment, for the convenience of illustration and description, the number of the capacitor stack 200 is one as an example for description.

[0051] In other embodiments, the number of capacitor stacks may be more than one. The more the number of capacitor stacks, the higher the capacitance density of the first capacitor region, and the more the number of second capacitor dielectric layers in the second capacitor region, the greater the thickness of the capacitor dielectric layer between the first electrode layer and the top electrode layer in the second capacitor region, and the higher the withstand voltage of the capacitor in the second capacitor region.

[0052] In each capacitor stack 200, the second capacitor dielectric layer 125 is used to form an insulating layer in the MIM capacitor. Specifically, the second capacitor dielectric layer 125 located in the first capacitor region 100a is used to isolate the second electrode layer 120 and the third electrode layer 130 and to isolate the adjacent third electrode layer, and the second capacitor dielectric layer 125 located in the second capacitor region 100b is used to achieve isolation between the first electrode layer 110 and the top electrode layer 130a together with the first capacitor dielectric layer 115.

[0053] The material of the second capacitor dielectric layer 125 is an insulating dielectric material. In this embodiment, the material of the second capacitor dielectric layer 125 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor and correspondingly increase the capacitance density.

[0054] As an example, the material of the second capacitor dielectric layer 125 includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0055] In this embodiment, the second capacitor dielectric layer 125 is made of the same material as the first capacitor dielectric layer 115. In other embodiments, the second capacitor dielectric layer and the first capacitor dielectric layer may also be made of different materials.

[0056] In this embodiment, the number of capacitor stacks 200 is one as an example for description, and accordingly, the number of second capacitor dielectric layers 125 is also one. In other embodiments, when the number of capacitor stacks is other, the number of second capacitor dielectric layers is also other.

[0057] The third electrode layer 130 is used as an electrode plate of the MIM capacitor.

[0058] In this embodiment, there is a projected overlapping area D between the third electrode layer 130 and the second electrode layer 120 , and between adjacent third electrode layers 130 , so that capacitors can be formed between the third electrode layer 130 and the second electrode layer 120 , and between adjacent third electrode layers 130 .

[0059] In this embodiment, there is a projected overlapping area D between the third electrode layer 130 and the second electrode layer 120, as well as between adjacent third electrode layers 130, which means that on a projection plane parallel to the surface of the substrate 100, there is an overlapping area between the third electrode layer 130 and the second electrode layer 120, as well as between adjacent third electrode layers 130.

[0060] In this embodiment, a projected overlapping area E is provided between the top electrode layer 130 a and the first electrode layer 110 , so that a capacitor can be formed between the top electrode layer 130 a and the first electrode layer 110 .

[0061] In this embodiment, the projection overlap region E between the top electrode layer 130 a and the first electrode layer 110 means that the top electrode layer 130 a and the first electrode layer 110 have an overlap region on a projection plane parallel to the surface of the substrate 100 .

[0062] The material of the third electrode layer 130 is a conductive material. As an example, the material of the third electrode layer 130 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0063] Along the direction of the surface normal of the substrate 100, the direction from the first electrode layer 110 to the second electrode layer 120 is the vertical direction. Along the vertical direction, the third electrode layer 130 in one or more layers of the capacitor stack 200 includes: the third electrode layer 130 of the odd-numbered layers and the third electrode layer 130 of the even-numbered layers.

[0064] In this embodiment, the third electrode layer 130 of the odd-numbered layers exposes the second connection area II and is also located on the first connection area I, so that the third electrode layer 130 of the even-numbered layers can cover the second connection area II, thereby facilitating the arrangement of a second conductive plug on the second connection area II that is electrically connected to the second electrode layer 120, or to the second electrode layer 120 and the third electrode layer 130 of the even-numbered layers.

[0065] In the present embodiment, when there are multiple capacitor stacks 200, the third electrode layer 130 of the even-numbered layers covers the second connection area II and also exposes the first connection area I, so that the third electrode layers 130 of the odd-numbered layers can all be located in the first connection area I, so that a first conductive plug electrically connected to the first electrode layer 110 and the third electrode layers 130 of the odd-numbered layers is arranged on the first connection area I.

[0066] In this embodiment, the top electrode layer 130a exposes the third connection region III so as to expose the first electrode layer 110 located in the third connection region III, thereby facilitating the provision of a third conductive plug electrically connected to the first electrode layer 110 on the third connection region II.

[0067] In this embodiment, the top electrode layer 130a is also located on the substrate 100 on the side of the first electrode layer 110, and a portion of the top electrode layer 130a on the substrate 100 on the side of the first electrode layer 110 is used as a fourth connection area IV, so that a fourth conductive plug electrically connected to the top electrode layer 130 is arranged on the fourth connection area IV.

[0068] In this embodiment, the semiconductor structure also includes: a first conductive plug 210, located in the first capacitor region 100a and electrically connected to the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layers; a second conductive plug 220, located in the first capacitor region 100a and electrically connected to the second electrode layer 120, or electrically connected to the second electrode layer 120 and the third electrode layer 130 of the even-numbered layers.

[0069] The first conductive plug 210 is used to realize electrical connection between the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layers, and between the first electrode layer 110 and the external circuit, so that the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layers can be connected to the same potential.

[0070] In the present embodiment, in the first capacitor region 100a, the first conductive plug 210 is located on the first connection region I, the first conductive plug 210 penetrates the third electrode layer 130 of the odd-numbered layers and contacts the first electrode layer 110, and the side wall of the first conductive plug 210 contacts the third electrode layer 130 of the odd-numbered layers, thereby realizing electrical connection between the first conductive plug 210 and the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layers.

[0071] In this embodiment, in the first capacitor region 100a, the first conductive plug 210 also penetrates the first electrode layer 110 and contacts the top metal layer 105 of the first connection region I, thereby achieving electrical connection between the top metal layer 105 and the first electrode layer 110 and the third electrode layer 130 of the odd layer.

[0072] In the present embodiment, in the first capacitor region 100a, the first conductive plug 210 also penetrates the top dielectric layer 103 and the etch stop layer 102 on top of the top metal layer 105 of the first connection region I, wherein the etch stop layer 102 can define the etching stop position during the formation of the first conductive plug 210, thereby reducing the probability of the process of forming the first conductive plug 210 causing damage to the top metal layer 105 and improving the depth consistency of the bottom of the first conductive plug 210.

[0073] The second conductive plug 220 is used to realize the electrical connection between the second electrode layer 120 and the external circuit, or, when the number of the capacitor stack 200 is multiple, the second conductive plug 220 is used to realize the electrical connection between the second electrode layer 120 and the third electrode layer 130 of the even-numbered layer, and between the second electrode layer 120 and the external circuit, so that the second electrode layer 120 and the third electrode layer 130 of the even-numbered layer can be connected to the same potential.

[0074] Correspondingly, the first electrode layer 110 and the second electrode layer 120 are connected to different potentials, the second electrode layer 120 and the third electrode layer 130 adjacent to the second electrode layer 120 are connected to different potentials, and when the number of the third electrode layers 130 is multiple, the third electrode layers 130 of two adjacent layers are also connected to different potentials, so that in the first capacitance area 100a, capacitors can be formed between the first electrode layer 110 and the second electrode layer 120, between the second electrode layer 120 and the third electrode layer 130 adjacent to the second electrode layer 120, and between the third electrode layers 130 of two adjacent layers.

[0075] In this embodiment, in the first capacitor region 100a, the second conductive plug 220 is located on the second connection region 100b, and the second conductive plug 220 is in contact with the second electrode layer 120, thereby realizing electrical connection between the second conductive plug 220 and the second electrode layer 120; or, the second conductive plug 220 penetrates the third electrode layer 130 of the even-numbered layer and is in contact with the second electrode layer 120, and the side wall of the second conductive plug 220 is in contact with the third electrode layer 130 of the even-numbered layer, thereby realizing electrical connection between the second conductive plug 220 and the second electrode layer 120 and the third electrode layer 130 of the even-numbered layer.

[0076] In this embodiment, in the first capacitor region 100a, the second conductive plug 220 also penetrates the second electrode layer 120 and contacts the top metal layer 105 of the second connection region II, thereby achieving electrical connection between the second conductive plug 220 and the second electrode layer 120 and the top metal layer 105.

[0077] More specifically, in the present embodiment, the second conductive plug 220 penetrates the etch stop layer 102 and the top dielectric layer 103 on the top of the top metal layer 105 of the second connection region II, wherein the etch stop layer 102 can define the etching stop position during the formation of the second conductive plug 220, thereby reducing the probability of damaging the top metal layer 105 during the formation of the second conductive plug 220 and improving the bottom depth consistency of the second conductive plug 220.

[0078] The first conductive plug 210 and the second conductive plug 220 are made of conductive materials. In this embodiment, the materials of the first conductive plug 210 and the second conductive plug 220 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0079] In this embodiment, the semiconductor structure further includes: a third conductive plug 230 located in the second capacitor region 100b and electrically connected to the first electrode layer 110; and a fourth conductive plug 240 located in the second capacitor region 100b and electrically connected to the top electrode layer 130a.

[0080] The third conductive plug 230 is used to realize electrical connection between the first electrode layer 110 of the second capacitor region 100 b and an external circuit.

[0081] In this embodiment, in the second capacitor region 100 b , the third conductive plug 230 is located on the third connection region III and contacts the first electrode layer 110 , thereby achieving electrical connection between the third conductive plug 230 and the first electrode layer 110 .

[0082] In this embodiment, in the second capacitor region 100b, the third conductive plug 230 also penetrates the first electrode layer 110 and contacts the top metal layer 105 of the third connection region III, thereby achieving electrical connection between the third conductive plug 230 and the top metal layer 105 of the third connection region III.

[0083] More specifically, in the present embodiment, in the second capacitor region 100 b, the third conductive plug 230 penetrates the etch stop layer 102 and the top dielectric layer 103 on the top of the top metal layer 105 of the third connection region III, wherein the etch stop layer 102 can define the position where the etching stops during the formation of the third conductive plug 230, so as to reduce the probability of the top metal layer 105 being damaged during the formation of the third conductive plug 230, and improve the bottom depth consistency of the third conductive plug 230.

[0084] The fourth conductive plug 240 is used to realize electrical connection between the top electrode layer 130a of the second capacitor region 100b and an external circuit.

[0085] In this embodiment, the fourth conductive plug 240 and the third conductive plug 230 are connected to different potentials, so that the first electrode layer 110 and the top electrode layer 130a of the second capacitor region 100b are connected to different potentials.

[0086] In this embodiment, in the second capacitor region 100b, the fourth conductive plug 240 is located on the fourth connection region IV and contacts the top electrode layer 130a, thereby achieving electrical connection between the fourth conductive plug 240 and the top electrode layer 130a.

[0087] In this embodiment, in the second capacitor region 100b, the fourth conductive plug 240 also penetrates the top electrode layer 130a and contacts the top metal layer 105 of the fourth connection region IV, thereby realizing electrical connection between the fourth conductive plug 240 and the top electrode layer 130a of the second capacitor region 100b and the top metal layer 105 of the fourth connection region IV.

[0088] More specifically, in the present embodiment, in the second capacitor region 100 b, the fourth conductive plug 240 also penetrates the etch stop layer 102 and the top dielectric layer 103 on the top of the top metal layer 105 of the fourth connection region IV, wherein the etch stop layer 102 can define the etching stop position during the formation of the fourth conductive plug 240, so as to reduce the probability of damaging the top metal layer 105 during the formation of the fourth conductive plug 240, and improve the bottom depth consistency of the fourth conductive plug 240.

[0089] The third conductive plug 230 and the fourth conductive plug 240 are made of conductive materials. In this embodiment, the materials of the third conductive plug 230 and the fourth conductive plug 240 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0090] In this embodiment, the semiconductor structure further includes: a covering dielectric layer 250 , a second capacitor dielectric layer 125 and a top electrode layer 130 a located on the substrate 100 and covering the capacitor stack 200 and the second capacitor region 100 b .

[0091] The covering dielectric layer 250 is used to cover the capacitor stack 200 and the second capacitor dielectric layer 125 and the top electrode layer 130a of the second capacitor region 100b, and is also used to provide a process basis for the formation of the first conductive plug 210, the second conductive plug 220, the third conductive plug 230 and the fourth conductive plug 240, and to achieve electrical isolation between the first conductive plug 210, the second conductive plug 220, the third conductive plug 230 and the fourth conductive plug 240.

[0092] Accordingly, in this embodiment, the first conductive plug 210 , the second conductive plug 220 , the third conductive plug 230 and the fourth conductive plug 240 are located in the covering dielectric layer 250 .

[0093] The material covering the dielectric layer 250 is a dielectric material. As an example, the material covering the dielectric layer 250 is silicon oxide.

[0094] The semiconductor structure may be formed by the method for forming a semiconductor structure provided by the embodiment of the present invention, or may be formed by other methods.

[0095] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 2 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0096] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0097] refer to Figure 2 , providing a substrate, including a first capacitor region 100a and a second capacitor region 100b.

[0098] The substrate 100 is used to provide a process platform for forming a MIM capacitor.

[0099] In this embodiment, the substrate 100 includes a device structure layer (not shown) and a back-end interconnection layer (not shown) located on the device structure layer and electrically connected to the device structure layer. The back-end interconnection layer includes a bottom dielectric layer 101 and one or more metal layers located in the bottom dielectric layer 101. The multiple metal layers located on the top layer are used as a top metal layer 105.

[0100] The device structure layer is formed by a front-end device manufacturing process. In a specific implementation, the device structure layer may include a substrate and a device structure located on the substrate. The device structure may include a MOS transistor, for example, an NMOS transistor, a PMOS transistor.

[0101] As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0102] The back-end interconnect layer is formed by a back-end interconnect process.

[0103] In this embodiment, the back-end interconnection layer includes a bottom dielectric layer 101 and one or more metal layers located in the bottom dielectric layer 101 , and the multiple metal layers located at the top layer are used as the top metal layer 105 .

[0104] The bottom dielectric layer 101 is used to achieve isolation between metal layers. Specifically, the bottom dielectric layer 101 is an intermetallic dielectric layer (Inter Metal Dielectric, IMD).

[0105] The material of the bottom dielectric layer 101 is a dielectric material. As an example, the material of the bottom dielectric layer 101 is silicon oxide.

[0106] In this embodiment, adjacent metal layers are electrically connected to each other so that the electrical properties of the device structure in the device structure layer are led out through one or more metal layers. Specifically, two adjacent metal layers are electrically connected through a via interconnection structure located between the two layers; the electrical properties of the device structure in the device structure layer are led out through the top metal layer 105.

[0107] The material of the metal layer is a conductive material. In this embodiment, the material of the metal layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0108] The first capacitance region 100a and the second capacitance region 100b are used to form capacitors, respectively. Specifically, in this embodiment, capacitors of different types and performance parameters are formed in the first capacitance region 100a and the second capacitance region 100b, respectively.

[0109] In this embodiment, the substrate 100 further includes: an etch stop layer 102 located on the bottom dielectric layer 101 and covering the top metal layer 105 ; and a top dielectric layer 103 located on the etch stop layer 102 .

[0110] The etch stop layer 102 is used to define the etching stop position in the steps of forming the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, so as to reduce the probability of damaging the top metal layer 105, and is also beneficial to improve the bottom height consistency of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug.

[0111] As an example, the material of the etch stop layer 102 is silicon nitride. In other embodiments, the etch stop layer can also be other materials with high etching selectivity to the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride and NDC (nitride doped carbon).

[0112] The top dielectric layer 103 is used to achieve isolation between the top metal layer 105 and the first electrode layer 110 .

[0113] The material of the top dielectric layer 103 is a dielectric material. As an example, the material of the top dielectric layer 103 is silicon oxide.

[0114] refer to Figure 3 , a plurality of first electrode layers 110 are formed on the substrate 100 , and are respectively located on the first capacitor region 100 a and the second capacitor region 100 b .

[0115] The first electrode layer 110 is used as an electrode plate of the MIM capacitor.

[0116] The material of the first electrode layer 110 is a conductive material. As an example, the material of the first electrode layer 110 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0117] In this embodiment, the step of forming the first electrode layer 110 includes: covering the substrate 100 with a first electrode material layer (not shown); and patterning the first electrode material layer, retaining a portion of the first electrode material layer located on the first capacitor region 100a and the second capacitor region 100b for use as the first electrode layer 110.

[0118] In this embodiment, the process of forming the first electrode material layer includes any one of a physical vapor deposition process and a chemical vapor deposition process.

[0119] In this embodiment, an anisotropic dry etching process is used to pattern the first electrode material layer.

[0120] refer to Figure 4 , a first capacitor dielectric layer 115 is formed on the first electrode layer 110 .

[0121] The first capacitor dielectric layer 115 is used as an insulating layer in forming a MIM capacitor. The first capacitor dielectric layer 115 located in the first capacitor area 100a is used to isolate the first electrode layer 110 and the subsequent second electrode layer. The first capacitor dielectric layer 115 located in the second capacitor area 100b is used to achieve isolation between the first electrode layer 110 and the top electrode layer together with the subsequent second capacitor dielectric layer.

[0122] Specifically, the first capacitor dielectric layer 115 conformally covers the first electrode layer 110 and the substrate 100 .

[0123] The material of the first capacitor dielectric layer 115 is an insulating dielectric material.

[0124] In this embodiment, the material of the first capacitor dielectric layer 115 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of high-k dielectric materials is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0125] As an example, the material of the first capacitor dielectric layer 115 includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0126] In this embodiment, the process of forming the first capacitor dielectric layer 115 includes a chemical vapor deposition process or an atomic layer deposition process.

[0127] Continue to refer Figure 4 A second electrode layer 120 is formed on the first capacitor dielectric layer 115 in the first capacitor region 100a.

[0128] The second electrode layer 120 is used as an electrode plate of the MIM capacitor.

[0129] In this embodiment, the second electrode layer 120 exposes a portion of the top of the first electrode layer 110 ; in the first capacitor region 100 a , the portion of the top of the first electrode layer 110 exposed by the second electrode layer 120 is used as the first connection region I.

[0130] In this embodiment, in the first capacitor region 100a, the first connection region I is used to form a first conductive plug so as to achieve electrical connection between the first conductive plug and the first electrode layer 110, or between the first conductive plug and the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layer.

[0131] In this embodiment, in the first capacitor region 100a, the second electrode layer 120 is also located on the substrate 100 at the side of the first electrode layer 110, and a portion of the second electrode layer 120 on the substrate 100 at the side of the first electrode layer 110 is used as a second connection region II.

[0132] In this embodiment, in the first capacitor region 100a, the second connection region II is used to form a second conductive plug so as to achieve electrical connection between the second conductive plug and the second electrode layer, or between the second electrode layer and the third electrode layer of an even number layer.

[0133] The material of the second electrode layer 120 is a conductive material. As an example, the material of the second electrode layer 120 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0134] In this embodiment, the steps of forming the second electrode layer 120 include: covering the first capacitor dielectric layer 115 with a second electrode material layer (not shown); patterning the second electrode material layer, and retaining a portion of the second electrode material layer located on the first capacitor region 100a for use as the second electrode layer 120.

[0135] In this embodiment, the process of forming the second electrode material layer includes any one of a physical vapor deposition process and a chemical vapor deposition process.

[0136] In this embodiment, an anisotropic dry etching process is used to pattern the second electrode material layer.

[0137] refer to Figure 5 After forming the second electrode layer 120, one or more capacitor stacks 200 are formed on the first capacitor region 100a, each capacitor stack 200 includes a second capacitor dielectric layer 125 and a third electrode layer 130 located on the second capacitor dielectric layer 125; there is a projected overlapping area between the third electrode layer 130 and the second electrode layer 120, and between adjacent third electrode layers 130.

[0138] One or more layers of capacitor stacks 200 are located on the second electrode layer 120 of the first capacitor region 100a; each layer of the capacitor stack 200 includes a second capacitor dielectric layer 125 and a third electrode layer 130 located on the second capacitor dielectric layer 125; there is a projected overlapping area D between the third electrode layer 130 and the second electrode layer 120, as well as between adjacent third electrode layers 130, so that in the first capacitor region 100a, capacitors can be formed between two adjacent electrode layers (between the first electrode layer 110 and the second electrode layer 120, between the second electrode layer 120 and the third electrode layer 130, and between adjacent third electrode layers 130), which is beneficial to improving the capacitance density of the first capacitor region 100a.

[0139] Moreover, in the present embodiment, in the step of forming the second capacitor dielectric layer 125, one or more layers of the second capacitor dielectric layer 125 are also formed on the first capacitor dielectric layer 115 of the second capacitor region 100b; the third electrode layer 130 in the capacitor stack 200 located at the top layer is used as the top electrode layer 130a, and the top electrode layer 130a is also formed on one or more layers of the second capacitor dielectric layer 125 of the second capacitor region 100b, and has a projected overlapping area E with the first electrode layer 110; therefore, in the second capacitor region 100b, a capacitor is formed between the first electrode layer 110 and the top electrode layer 130a, and the first capacitor dielectric layer 115 and one or more layers of the second capacitor dielectric layer 125 are arranged between the first electrode layer 110 and the top electrode layer 130a, thereby increasing the thickness of the capacitor dielectric layer between the first electrode layer 110 and the top electrode layer 130a, and further improving the withstand voltage performance of the capacitor in the second capacitor region 100b.

[0140] Furthermore, in this embodiment, it is possible to form a capacitor with good withstand voltage performance and a capacitor with high capacitance density, thereby satisfying the need to provide capacitors of different types and performance parameters on the substrate 100 .

[0141] In each capacitor stack 200, the second capacitor dielectric layer 125 is used to form an insulating layer in the MIM capacitor. Specifically, the second capacitor dielectric layer 125 located in the first capacitor region 100a is used to isolate the second electrode layer 120 and the third electrode layer 130 and to isolate the adjacent third electrode layer 130, and the second capacitor dielectric layer 125 located in the second capacitor region 100b is used to achieve isolation between the first electrode layer 110 and the top electrode layer 130a together with the first capacitor dielectric layer 115.

[0142] The material of the second capacitor dielectric layer 125 is an insulating dielectric material.

[0143] In this embodiment, the material of the second capacitor dielectric layer 125 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. The use of high-k dielectric materials is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0144] As an example, the material of the second capacitor dielectric layer 125 includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0145] In this embodiment, the second capacitor dielectric layer 125 is made of the same material as the first capacitor dielectric layer 115. In other embodiments, the second capacitor dielectric layer and the first capacitor dielectric layer may also be made of different materials.

[0146] In this embodiment, the number of capacitor stacks 200 is one as an example for description, and accordingly, the number of second capacitor dielectric layers 125 is also one. In other embodiments, when the number of capacitor stacks is other, the number of second capacitor dielectric layers is also other.

[0147] The third electrode layer 130 is used as an electrode plate of the MIM capacitor.

[0148] In this embodiment, there is a projected overlapping area D between the third electrode layer 130 and the second electrode layer 120 , and between adjacent third electrode layers 130 , so that capacitors can be formed between the third electrode layer 130 and the second electrode layer 120 , and between adjacent third electrode layers 130 .

[0149] In this embodiment, there is a projected overlapping area D between the third electrode layer 130 and the second electrode layer 120, as well as between adjacent third electrode layers 130, which means that on a projection plane parallel to the surface of the substrate 100, there is an overlapping area between the third electrode layer 130 and the second electrode layer 120, as well as between adjacent third electrode layers 130.

[0150] In this embodiment, a projected overlapping area E is provided between the top electrode layer 130 a and the first electrode layer 110 , so that a capacitor can be formed between the top electrode layer 130 a and the first electrode layer 110 .

[0151] In this embodiment, the projection overlap region E between the top electrode layer 130 a and the first electrode layer 110 means that the top electrode layer 130 a and the first electrode layer 110 have an overlap region on a projection plane parallel to the surface of the substrate 100 .

[0152] The material of the third electrode layer 130 is a conductive material. As an example, the material of the third electrode layer 130 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0153] In this embodiment, along the direction of the surface normal of the substrate 100, the direction from the first electrode layer 110 to the second electrode layer 120 is a vertical direction. Along the vertical direction, the third electrode layer 130 in one or more layers of the capacitor stack 200 includes: third electrode layers 130 of odd-numbered layers and third electrode layers 130 of even-numbered layers.

[0154] In this embodiment, the third electrode layer 130 of the odd-numbered layers exposes the second connection area II and is also located on the first connection area I, so that the third electrode layer 130 of the even-numbered layers can cover the second connection area II, thereby facilitating the arrangement of a second conductive plug on the second connection area II that is electrically connected to the second electrode layer 120, or to the second electrode layer 120 and the third electrode layer 130 of the even-numbered layers.

[0155] In the present embodiment, when there are multiple capacitor stacks 200, the third electrode layer 130 of the even-numbered layers covers the second connection area II and also exposes the first connection area I, so that the third electrode layers 130 of the odd-numbered layers can all be located in the first connection area I, so that a first conductive plug electrically connected to the first electrode layer 110 and the third electrode layers 130 of the odd-numbered layers is arranged on the first connection area I.

[0156] In this embodiment, the top electrode layer 130a exposes the third connection region III so as to expose the first electrode layer 110 located in the third connection region III, thereby facilitating the provision of a third conductive plug electrically connected to the first electrode layer 110 on the third connection region II.

[0157] In this embodiment, the top electrode layer 130a is also located on the substrate 100 on the side of the first electrode layer 110, and a portion of the top electrode layer 130a on the substrate 100 on the side of the first electrode layer 110 is used as a fourth connection area IV, so that a fourth conductive plug electrically connected to the top electrode layer 130 is arranged on the fourth connection area IV.

[0158] In this embodiment, the steps of forming the capacitor stack 200 include: conformally covering the second capacitor dielectric layer 125 on the substrate 100; covering the third electrode material layer (not shown) on the second capacitor dielectric layer 125; and patterning the third electrode material layer to remove the third electrode material layer located in the second capacitor region 100b, and retaining a portion of the third electrode material layer located in the first capacitor region 100a for use as the third electrode layer 130.

[0159] In this embodiment, the process of forming the second capacitor dielectric layer 125 includes a chemical vapor deposition process or an atomic layer deposition process.

[0160] In this embodiment, the process of forming the third electrode material layer includes any one of a physical vapor deposition process and a chemical vapor deposition process.

[0161] In this embodiment, an anisotropic dry etching process is used to pattern the third electrode material layer.

[0162] refer to Figure 6 In this embodiment, the method for forming a semiconductor structure further includes: after forming one or more layers of capacitor stack 200 , forming a covering dielectric layer 250 on the substrate 100 .

[0163] The covering dielectric layer 250 is used to cover the capacitor stack 200 and the second capacitor dielectric layer 125 and the top electrode layer 130a of the second capacitor region 100b, and is also used to provide a process basis for the formation of the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug, and to achieve electrical isolation between the first conductive plug, the second conductive plug, the third conductive plug and the fourth conductive plug.

[0164] The material covering the dielectric layer 250 is a dielectric material. As an example, the material covering the dielectric layer 250 is silicon oxide.

[0165] As an example, the cover dielectric layer 250 is formed by using a chemical vapor deposition process.

[0166] refer to Figure 7The method for forming a semiconductor structure also includes: after forming one or more layers of capacitor stack 200, forming a first conductive plug 210 in the first capacitor region 100a, electrically connecting the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layer; forming a second conductive plug 220 in the first capacitor region 100a, the second conductive plug 220 electrically connecting the second electrode layer 120; or, the second conductive plug 220 electrically connecting the second electrode layer 120 and the third electrode layer 130 of the even-numbered layer.

[0167] Specifically, in this embodiment, after forming the covering dielectric layer 250 , the first conductive plug 210 and the second conductive plug 220 are formed. The first conductive plug 210 and the second conductive plug 220 are formed in the covering dielectric layer 250 , respectively.

[0168] The first conductive plug 210 is used to realize electrical connection between the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layers, and between the first electrode layer 110 and the external circuit, so that the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layers can be connected to the same potential.

[0169] In this embodiment, the step of forming the first conductive plug 210 includes: forming the first conductive plug 210 on the first connection area I in the first capacitor area 100a, the first conductive plug 210 penetrates the third electrode layer 130 of the odd layer and contacts the first electrode layer 110, and the side wall of the first conductive plug 210 contacts the third electrode layer 130 of the odd layer, thereby realizing electrical connection between the first conductive plug 210 and the first electrode layer 110 and the third electrode layer 130 of the odd layer.

[0170] In the present embodiment, in the step of forming the first conductive plug 210, in the first capacitor region 100a, the first conductive plug 210 also penetrates the first electrode layer 110 and contacts the top metal layer 105 of the first connection region I, thereby realizing electrical connection between the top metal layer 105 and the first electrode layer 110 and the third electrode layer 130 of the odd-numbered layer.

[0171] In the present embodiment, in the first capacitor region 100a, the first conductive plug 210 also penetrates the top dielectric layer 103 and the etch stop layer 102 on top of the top metal layer 105 of the first connection region I, wherein the etch stop layer 102 can define the etching stop position during the formation of the first conductive plug 210, thereby reducing the probability of the process of forming the first conductive plug 210 causing damage to the top metal layer 105 and improving the depth consistency of the bottom of the first conductive plug 210.

[0172] The second conductive plug 220 is used to realize the electrical connection between the second electrode layer 120 and the external circuit, or, when the number of the capacitor stack 200 is multiple, the second conductive plug 220 is used to realize the electrical connection between the second electrode layer 120 and the third electrode layer 130 of the even-numbered layer, and between the second electrode layer 120 and the external circuit, so that the second electrode layer 120 and the third electrode layer 130 of the even-numbered layer can be connected to the same potential.

[0173] Correspondingly, the first electrode layer 110 and the second electrode layer 120 are connected to different potentials, the second electrode layer 120 and the third electrode layer 130 adjacent to the second electrode layer 120 are connected to different potentials, and when the number of the third electrode layers 130 is multiple, the third electrode layers 130 of two adjacent layers are also connected to different potentials, so that in the first capacitance area 100a, capacitors can be formed between the first electrode layer 110 and the second electrode layer 120, between the second electrode layer 120 and the third electrode layer 130 adjacent to the second electrode layer 120, and between the third electrode layers 130 of two adjacent layers.

[0174] In this embodiment, the step of forming the second conductive plug 220 includes: forming the second conductive plug 220 on the first capacitor region 100a and the second connection region 100b, the second conductive plug 220 contacts the second electrode layer 120, thereby realizing electrical connection between the second conductive plug 220 and the second electrode layer 120; or, the second conductive plug 220 penetrates the third electrode layer 130 of the even-numbered layer and contacts the second electrode layer 120, the side wall of the second conductive plug 220 contacts the third electrode layer 130 of the even-numbered layer, thereby realizing electrical connection between the second conductive plug 220 and the second electrode layer 120 and the third electrode layer 130 of the even-numbered layer.

[0175] In this embodiment, in the step of forming the second conductive plug 220, in the first capacitor region 100a, the second conductive plug 220 also penetrates the second electrode layer 120 and contacts the top metal layer 105 of the second connection region II, thereby realizing electrical connection between the second conductive plug 220 and the second electrode layer 120 and the top metal layer 105.

[0176] More specifically, in the present embodiment, the second conductive plug 220 penetrates the etch stop layer 102 and the top dielectric layer 103 on the top of the top metal layer 105 of the second connection region II, wherein the etch stop layer 102 can define the etching stop position during the formation of the second conductive plug 220, thereby reducing the probability of damaging the top metal layer 105 during the formation of the second conductive plug 220 and improving the bottom depth consistency of the second conductive plug 220.

[0177] The first conductive plug 210 and the second conductive plug 220 are made of conductive materials. In this embodiment, the materials of the first conductive plug 210 and the second conductive plug 220 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0178] refer to Figure 7 The method for forming a semiconductor structure also includes: after forming one or more layers of capacitor stack 200, forming a third conductive plug 230 in the second capacitor region 100b, electrically connected to the first electrode layer 110; forming a fourth conductive plug 240 in the second capacitor region 100b, electrically connected to the top electrode layer 130a.

[0179] In this embodiment, the first conductive plug 210 , the second conductive plug 220 , the third conductive plug 230 and the fourth conductive plug 240 are located in the covering dielectric layer 250 .

[0180] The third conductive plug 230 is used to realize electrical connection between the first electrode layer 110 of the second capacitor region 100 b and an external circuit.

[0181] In this embodiment, the step of forming the third conductive plug 230 includes: forming the third conductive plug 230 in contact with the first electrode layer 110 on the third connection region III in the second capacitor region 100 b, thereby achieving electrical connection between the third conductive plug 230 and the first electrode layer 110 .

[0182] In this embodiment, in the step of forming the third conductive plug 230, in the second capacitor region 100b, the third conductive plug 230 also penetrates the first electrode layer 110 and contacts the top metal layer 105 of the third connection region III, thereby realizing electrical connection between the third conductive plug 230 and the top metal layer 105 of the third connection region III.

[0183] More specifically, in the present embodiment, in the second capacitor region 100 b, the third conductive plug 230 penetrates the etch stop layer 102 and the top dielectric layer 103 on the top of the top metal layer 105 of the third connection region III, wherein the etch stop layer 102 can define the position where the etching stops during the formation of the third conductive plug 230, so as to reduce the probability of the top metal layer 105 being damaged during the formation of the third conductive plug 230, and improve the bottom depth consistency of the third conductive plug 230.

[0184] The fourth conductive plug 240 is used to realize electrical connection between the top electrode layer 130a of the second capacitor region 100b and an external circuit.

[0185] In this embodiment, the fourth conductive plug 240 and the third conductive plug 230 are connected to different potentials, so that the first electrode layer 110 and the top electrode layer 130a of the second capacitor region 100b are connected to different potentials.

[0186] In this embodiment, the step of forming the fourth conductive plug 240 includes: forming a fourth conductive plug 240 in contact with the top electrode layer 130a on the fourth connection region IV in the second capacitor region 100b, thereby achieving electrical connection between the fourth conductive plug 240 and the top electrode layer 130a.

[0187] In the present embodiment, in the step of forming the fourth conductive plug 240, in the second capacitor region 100b, the fourth conductive plug 240 also penetrates the top electrode layer 130a and contacts the top metal layer 105 of the fourth connection region IV, thereby realizing electrical connection between the fourth conductive plug 240 and the top electrode layer 130a of the second capacitor region 100b and the top metal layer 105 of the fourth connection region IV.

[0188] More specifically, in the present embodiment, in the second capacitor region 100 b, the fourth conductive plug 240 also penetrates the etch stop layer 102 and the top dielectric layer 103 on the top of the top metal layer 105 of the fourth connection region IV, wherein the etch stop layer 102 can define the etching stop position during the formation of the fourth conductive plug 240, so as to reduce the probability of damaging the top metal layer 105 during the formation of the fourth conductive plug 240, and improve the bottom depth consistency of the fourth conductive plug 240.

[0189] The third conductive plug 230 and the fourth conductive plug 240 are made of conductive materials. In this embodiment, the materials of the third conductive plug 230 and the fourth conductive plug 240 include one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0190] Specifically, as an example, forming the first conductive plug 210 , the second conductive plug 220 , the third conductive plug 230 and the fourth conductive plug 240 in the same step is beneficial to simplifying the process and improving the process manufacturing efficiency.

[0191] As an example, the steps of forming the first conductive plug 210, the second conductive plug 220, the third conductive plug 230 and the fourth conductive plug 240 include:

[0192] A first contact hole (not shown), a second contact hole (not shown), a third contact hole (not shown) and a fourth contact hole (not shown) are formed in the first connection region I, the second connection region II, the third connection region III and the fourth connection region IV, respectively. The first contact hole penetrates the etch stop layer 102, the top dielectric layer 103, the first electrode layer 110 and the capacitor stack 200 and the covering dielectric layer 250 on the top of the top metal layer 105 in the first connection region I, and the second contact hole penetrates the etch stop layer 102, the top dielectric layer 103, the second electrode layer 120 on the top of the top metal layer 105 in the second connection region II, or the second contact hole penetrates the second dielectric layer 103, the second electrode layer 120 on the top of the top metal layer 105 in the second connection region II. The etch stop layer 102, the top dielectric layer 103, the second electrode layer 120, the capacitor stack 200 and the cover dielectric layer 250 on the top of the top metal layer 105, the third contact hole penetrates the etch stop layer 102, the top dielectric layer 103, the first electrode layer 110, the first capacitor dielectric layer 115, the second capacitor dielectric layer 125 and the cover dielectric layer 250 on the top metal layer 105 located in the third connection area III, and the fourth contact hole penetrates the etch stop layer 102, the top dielectric layer 103, the first capacitor dielectric layer 115, the second capacitor dielectric layer 125, the top dielectric layer 130a and the cover dielectric layer 250 on the top metal layer 105 located in the fourth connection area IV;

[0193] Conductive materials are filled in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole to form a first conductive plug 210, a second conductive plug 220, a third conductive plug 230 and a fourth conductive plug 240 respectively.

[0194] In this embodiment, in the steps of forming the first contact hole, the second contact hole, the third contact hole and the fourth contact hole, the etch stop layer 102 can be used to temporarily define the position where the etching stops, thereby reducing the probability of the process of forming the first contact hole, the second contact hole, the third contact hole and the fourth contact hole causing damage to the top metal layer 105, and improving the depth consistency of the bottom of the first contact hole, the second contact hole, the third contact hole and the fourth contact hole.

[0195] In this embodiment, an anisotropic dry etching process is used to form the first contact hole, the second contact hole, the third contact hole and the fourth contact hole to improve the ability to control the profiles of the first contact hole, the second contact hole, the third contact hole and the fourth contact hole.

[0196] In a specific implementation, the steps of filling the first contact hole, the second contact hole, the third contact hole and the fourth contact hole with conductive material to form the first conductive plug 210, the second conductive plug 220, the third conductive plug 230 and the fourth conductive plug 240 respectively include: filling the first contact hole, the second contact hole, the third contact hole and the fourth contact hole with a conductive material layer, the conductive material layer also covering the covering dielectric layer 250; removing the conductive material layer located on the covering dielectric layer 250, and the remaining conductive material layers located in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole are used as the first conductive plug 210, the second conductive plug 220, the third conductive plug 230 and the fourth conductive plug 240 respectively.

[0197] In this embodiment, the process of filling the conductive material layer in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole includes one or more of a chemical vapor deposition process, a physical vapor deposition process and an electrochemical plating process.

[0198] In this embodiment, removing the conductive material layer on the cover dielectric layer 250 may include a chemical mechanical polishing process.

[0199] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate including a first capacitor region and a second capacitor region; A plurality of first electrode layers, respectively located on the substrate of the first capacitor region and the second capacitor region; A first capacitor dielectric layer, located on the first electrode layer; A second electrode layer, located on the first capacitor dielectric layer of the first capacitor region; One or more capacitor stacks are located on the second electrode layer of the first capacitor region; each of the capacitor stacks includes a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; Among them, the one or more layers of the second capacitor dielectric layer are also located on the first capacitor dielectric layer of the second capacitor region; the third electrode layer in the capacitor stack located at the top layer is used as the top electrode layer, and the top electrode layer is also located on the one or more layers of the second capacitor dielectric layer of the second capacitor region, and has a projected overlapping area with the first electrode layer.

2. The semiconductor structure according to claim 1, wherein: The number of the capacitor stack is one.

3. The semiconductor structure according to claim 1, wherein: Along the direction of the normal line of the substrate surface, the direction from the first electrode layer to the second electrode layer is a vertical direction, and along the vertical direction, the third electrode layer in the one or more layers of the capacitor stack includes: a third electrode layer of an odd-numbered layer and a third electrode layer of an even-numbered layer; The semiconductor structure further includes: a first conductive plug located in the first capacitor region and electrically connected to the first electrode layer and the third electrode layer of the odd-numbered layers; The second conductive plug is located in the first capacitor region and electrically connected to the second electrode layer, or electrically connected to the second electrode layer and the third electrode layer of the even-numbered layer.

4. The semiconductor structure according to claim 3, characterized in that The second electrode layer exposes a portion of the top of the first electrode layer, and the portion of the top of the first electrode layer exposed by the second electrode layer is used as a first connection area; the second electrode layer is also located on the substrate at the side of the first electrode layer, and the portion of the second electrode layer located on the substrate at the side of the first electrode layer is used as a second connection area; The third electrode layer of the odd-numbered layers exposes the second connection area and is also located on the first connection area; the third electrode layer of the even-numbered layers covers the second connection area and also exposes the first connection area; In the first capacitor region, the first conductive plug is located on the first connection region, the first conductive plug penetrates the third electrode layer of the odd-numbered layers and contacts the first electrode layer, and a side wall of the first conductive plug contacts the third electrode layer of the odd-numbered layers; In the first capacitor region, the second conductive plug is located on the second connection region, and the second conductive plug is in contact with the second electrode layer; Alternatively, the second conductive plug penetrates the third electrode layer of the even-numbered layers and contacts the second electrode layer, and a side wall of the second conductive plug contacts the third electrode layer of the even-numbered layers.

5. The semiconductor structure according to claim 4, characterized in that The substrate comprises a device structure layer and a back-end interconnection layer located on the device structure layer and electrically connected to the device structure layer, the back-end interconnection layer comprises a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, and the multiple metal layers located on the top layer are used as top metal layers; In the first capacitor region, the first conductive plug also penetrates the first electrode layer and contacts the top metal layer of the first connection region; In the first capacitor region, the second conductive plug also penetrates the second electrode layer and contacts the top metal layer in the second connection region.

6. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a third conductive plug located in the second capacitor region and electrically connected to the first electrode layer; and a fourth conductive plug located in the second capacitor region and electrically connected to the top electrode layer.

7. The semiconductor structure according to claim 6, wherein: In the second capacitor region, the top electrode layer exposes a portion of the top of the first electrode layer, and the portion of the top of the first electrode layer exposed by the top electrode layer is used as a third connection region; the top electrode layer is also located on the substrate at the side of the first electrode layer, and a portion of the top electrode layer located on the substrate at the side of the first electrode layer is used as a fourth connection region; In the second capacitor region, a third conductive plug is located on the third connection region and contacts the first electrode layer; In the second capacitor region, a fourth conductive plug is located on the fourth connection region and contacts the top electrode layer.

8. The semiconductor structure according to claim 7, wherein: The substrate comprises a device structure layer and a back-end interconnection layer located on the device structure layer and electrically connected to the device structure layer, the back-end interconnection layer comprises a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, and the multiple metal layers located on the top layer are used as top metal layers; In the second capacitor region, the third conductive plug also penetrates the first electrode layer and contacts the top metal layer of the third connection region; In the second capacitor region, the fourth conductive plug also penetrates the top electrode layer and contacts the top metal layer of the fourth connection region.

9. The semiconductor structure according to claim 1, wherein: The material of the first capacitor dielectric layer includes hafnium oxide, aluminum oxide or zirconium oxide; the material of the second capacitor dielectric layer includes hafnium oxide, aluminum oxide or zirconium oxide.

10. The semiconductor structure according to claim 1, wherein: The second capacitor dielectric layer and the first capacitor dielectric layer are made of the same material.

11. The semiconductor structure according to claim 1, wherein: The material of the first electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; The material of the second electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; The material of the third electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a first capacitor region and a second capacitor region; forming a plurality of first electrode layers on the substrate, respectively located on the first capacitor region and the second capacitor region; forming a first capacitor dielectric layer on the first electrode layer; forming a second electrode layer on the first capacitor dielectric layer in the first capacitor region; After forming the second electrode layer, forming one or more capacitor stacks on the first capacitor region, each capacitor stack comprising a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer; there is a projected overlapping area between the third electrode layer and the second electrode layer, and between adjacent third electrode layers; In the step of forming the second capacitor dielectric layer, one or more layers of the second capacitor dielectric layer are also formed on the first capacitor dielectric layer of the second capacitor region; the third electrode layer in the capacitor stack located at the top layer is used as the top electrode layer, and the top electrode layer is also formed on one or more layers of the second capacitor dielectric layer of the second capacitor region, and has a projected overlapping area with the first electrode layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The number of the capacitor stack is one.

14. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming one or more capacitor stacks on the first capacitor region, along the direction of the normal line of the substrate surface, the direction from the first electrode layer to the second electrode layer is a vertical direction, and along the vertical direction, the third electrode layers in the one or more capacitor stacks include: third electrode layers of odd-numbered layers and third electrode layers of even-numbered layers; The method for forming the semiconductor structure further comprises: after forming one or more capacitor stacks, forming a first conductive plug in the first capacitor region to electrically connect the first electrode layer and the third electrode layer of the odd-numbered layer; A second conductive plug is formed in the first capacitor region, and the second conductive plug is electrically connected to the second electrode layer; or the second conductive plug is electrically connected to the second electrode layer and the third electrode layer of an even-numbered layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming the second electrode layer, the second electrode layer exposes a portion of the top of the first electrode layer, and the portion of the top of the first electrode layer exposed by the second electrode layer is used as a first connection area; the second electrode layer is also located on the substrate at the side of the first electrode layer, and the portion of the second electrode layer located on the substrate at the side of the first electrode layer is used as a second connection area; In the step of forming one or more capacitor stacks, in the first capacitor region, the third electrode layer of the odd-numbered layers exposes the second connection region and is also located on the first connection region; the third electrode layer of the even-numbered layers covers the second connection region and also exposes the first connection region; The step of forming the first conductive plug includes: forming a first conductive plug on the first connection area in the first capacitor area, the first conductive plug penetrating the third electrode layer of the odd-numbered layer and contacting the first electrode layer, and the sidewall of the first conductive plug contacting the third electrode layer of the odd-numbered layer; The step of forming the second conductive plug includes: forming a second conductive plug on the second connection area in the first capacitor area, and the second conductive plug is in contact with the second electrode layer; or, the second conductive plug passes through the third electrode layer of the even-numbered layer and is in contact with the second electrode layer, and the side wall of the second conductive plug is in contact with the third electrode layer of the even-numbered layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of providing a substrate, the substrate includes a device structure layer and a back-end interconnection layer located on the device structure layer and electrically connected to the device structure layer, the back-end interconnection layer includes a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, and the multiple metal layers located on the top layer are used as top metal layers; In the step of forming the first conductive plug, in the first capacitor region, the first conductive plug also penetrates the first electrode layer and contacts the top metal layer of the first connection region; In the step of forming the second conductive plug, in the first capacitor region, the second conductive plug also penetrates the second electrode layer and contacts the top metal layer of the second connection region.

17. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the semiconductor structure also includes: after forming one or more layers of capacitor stacks, forming a third conductive plug in the second capacitor region, electrically connected to the first electrode layer; and forming a fourth conductive plug in the second capacitor region, electrically connected to the top electrode layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: In the step of forming the top electrode layer, the top electrode layer exposes a portion of the top of the first electrode layer, and the portion of the top of the first electrode layer exposed by the top electrode layer is used as a third connection area; the top electrode layer is also located on the substrate at the side of the first electrode layer, and a portion of the top electrode layer located on the substrate at the side of the first electrode layer is used as a fourth connection area; The step of forming the third conductive plug includes: forming a third conductive plug in contact with the first electrode layer on the third connection area in the second capacitor area; The step of forming the fourth conductive plug includes: forming a fourth conductive plug in contact with the top electrode layer on the fourth connection region in the second capacitor region.

19. The method for forming a semiconductor structure according to claim 18, wherein: In the step of providing a substrate, the substrate includes a device structure layer and a back-end interconnection layer located on the device structure layer and electrically connected to the device structure layer, the back-end interconnection layer includes a bottom dielectric layer and one or more metal layers located in the bottom dielectric layer, and the multiple metal layers located on the top layer are used as top metal layers; In the step of forming the third conductive plug, in the second capacitor region, the third conductive plug also penetrates the first electrode layer and contacts the top metal layer of the third connection region; In the step of forming the fourth conductive plug, in the second capacitor region, the fourth conductive plug also penetrates the second electrode layer and contacts the top metal layer of the fourth connection region.

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