Protection device hardware-in-the-loop test method and system

Abstract

The invention discloses a protection device hardware-in-the-loop test method and system, and relates to the technical field of in-the-loop tests, and the method comprises the steps: constructing a simulation scene in a hardware-in-the-loop simulation test system; according to the installation position of the to-be-verified protection device in the simulation scene, minimum sampling signals needed by normal work of the to-be-verified protection device are determined, and a current transformer model capable of restoring a transient saturation scene is established; electrifying the to-be-verified protection device, and enabling the hardware-in-the-loop simulation test system to output an electrical signal; when a correct sampling reading is obtained on the protection device, a fault scene is simulated in a simulation scene, and whether an action result meets a constant value and action logic or not is determined through logic judgment of a current signal which is calculated by a model and contains transient saturation characteristics and the protection device. According to the protection device hardware-in-the-loop test method provided by the invention, the truth value current in a non-ideal fault state is restored, and the working characteristics of the relay protection device of the power station are deeply tested.

Description

Technical Field

[0001] The present invention relates to the technical field of in-the-loop testing, and in particular to a method and system for in-the-loop testing of hardware of a protection device. Background Art

[0002] In the verification test of the protection device of the power station, the method of checking the flow and pressure of the steady-state protection device based on the effective value has been relatively mature. However, when a system fault occurs, the behavior of the protection device will still cause false operation or refusal to operate due to insufficient setting margin and insufficient device logic testing. The reason is that the effective value of the added simulation action is not enough to reflect the actual system situation. Due to the inrush current problem of the transformer core and the transient saturation problem of the current transformer, the nonlinear transient characteristics caused by the conventional relay protection device added verification are difficult to stimulate the real fault scene in the action logic of the protection device, resulting in unreliable verification results. Increasing the setting threshold of the relay protection setting can eliminate this problem to a certain extent, but excessive unbalanced margin value will make the sensitivity worse. Therefore, a device test system using hardware in the loop is developed, and the nonlinear characteristics of transient saturation are considered. It can deeply test the related work of the protection device action logic and setting verification, and effectively ensure the safety and reliability of the power station protection system.

[0003] Hardware-in-the-loop simulation test is a new type of test technology. Through the CPU+FPGA hardware architecture, it realizes the restoration of the refined system change process at the us level or even the ns level. Through the peripheral interface device, it can be connected to the sampling part of the protection device, and the whole process of fault triggering, maintenance and fault removal can be simulated according to the set program. This architecture provides a good test platform, but the system modeling in the computer also needs to be accurate enough to reflect the characteristics of the real fault transient state before it can be simulated. Among the general fault types of power plants, motor models are accepted by a large number of software, but components such as transformers generally use ideal transformers. Accurate characterization of transformer transmission characteristics can facilitate the true effectiveness of the test. JA (Jiles-Atherton) theory is a classical ferromagnetic theory. It is used to describe the magnetization characteristics of ferromagnetic materials. It has a very good phenomenon explanation and is easy to calculate. It can be used in the transient saturation modeling of current transformers. Summary of the invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by the present invention is: to achieve the functional measurement and in-depth verification tasks of the relay protection device and ensure the safe and stable operation of the power system.

[0006] The existing flow and pressure verification method of steady-state protection devices based on effective values ​​cannot reflect the actual system fault state, resulting in false operation or refusal of the protection device to operate. It also solves the problem of how to accurately restore the transient saturation characteristics and optimize the action logic of the test protection device through simulation.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: a protection device hardware-in-the-loop test method, comprising:

[0008] Construct simulation scenarios in the hardware-in-the-loop simulation test system;

[0009] According to the installation position of the protection device to be verified in the simulation scenario, the minimum sampling signal required for the normal operation of the protection device to be verified is determined, and a current transformer model that can restore the transient saturation scenario is established;

[0010] Perform power-on operation on the protection device to be verified, and make the hardware-in-the-loop simulation test system output electrical signals;

[0011] After the correct sampling indication is obtained on the protection device, a fault scenario is simulated in the simulation scenario. The current signal with transient saturation characteristics calculated by the model is judged by the protection device logic to determine whether its action result meets the set value and action logic.

[0012] As a preferred solution of the protection device hardware-in-the-loop test method described in the present invention, wherein: the current transformer model includes a TP-level current transformer and a P-level current transformer.

[0013] As a preferred solution of the hardware-in-the-loop test method for the protection device described in the present invention, the saturation characteristics of the TP-level current transformer are not taken into account.

[0014] As a preferred solution of the hardware-in-the-loop test method for the protection device described in the present invention, wherein: a JA transient saturation model is established for the P current level transformer.

[0015] As a preferred solution of the protection device hardware-in-the-loop test method of the present invention, wherein: the establishment of the JA transient saturation model includes initializing the model and setting the P-level current transformer parameters;

[0016] Calculate the differential formula of magnetic susceptibility, an important parameter of transient saturation JA model;

[0017] Calculate the differential equation of the excitation current;

[0018] The output current of the P-class transformer with saturation characteristics on the secondary side is updated in real time according to the changed primary current.

[0019] As a preferred scheme of the hardware-in-the-loop test method for the protection device described in the present invention, the parameters of the P-level current transformer include transformation ratio turns, equivalent cross-section of the iron core, magnetic permeability under vacuum state, equivalent flux linkage length of the iron core, resistance and leakage reactance of the secondary circuit of the current transformer, initial excitation current value and initial magnetization intensity.

[0020] As a preferred solution of the protection device hardware-in-the-loop test method of the present invention, the method includes connecting the current and voltage sampling channels of the protection device to be verified with the hardware of the hardware-in-the-loop simulation test system, and matching the analog AO level level of the hardware physical interface board of the hardware-in-the-loop simulation test system;

[0021] The current signal calculated by the mutual inductor model in the hardware-in-the-loop simulation test system is connected to the current sampling port of the protection device after being output and amplified;

[0022] The voltage signal calculated by the ideal voltage transformer model in the hardware-in-the-loop simulation test system is connected to the voltage sampling port of the protection device through signal output and amplification;

[0023] Connect the tripping output signal of the protection device to be verified back to the digital DI channel of the physical interface board of the hardware-in-the-loop simulation test system.

[0024] Another object of the present invention is to provide a hardware-in-the-loop test system for a protection device, which can solve the problem of inaccurate simulation of the nonlinear transient characteristics caused by the transformer core inrush current and the transient saturation characteristics of the current transformer during the existing protection device verification process by constructing a hardware-in-the-loop simulation test system based on the JA transient saturation theory, and deeply test the working characteristics of the protection device under complex fault scenarios.

[0025] In order to solve the above technical problems, the present invention provides the following technical solutions: a protection device hardware-in-the-loop test system, comprising: a CPU+multi-FPGA simulation test host, a host computer, a power amplifier, a protection device to be tested, a signal cable, a control cable and an Ethernet cable; the CPU+multi-FPGA simulation test host is used to generate current and voltage signals under simulation scenarios, and calculate fault scenarios through simulation algorithms; the host computer is connected to the CPU+multi-FPGA simulation test host through an Ethernet cable, and is used to set fault scenarios and monitor simulation results; the power amplifier amplifies the analog signal output by the simulation host to drive the input channel of the protection device to be tested; the signal cable connects the power amplifier and the protection device to be tested, and is used to transmit current and voltage signals; the control cable connects the protection device to be tested and the simulation test host, and is used to transmit input and output signals and monitor the action logic of the protection device; the fault scenario is adjusted in real time by the host computer, and the simulation host outputs a signal that meets the requirements to the protection device through the power amplifier for verification.

[0026] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned protection device hardware-in-the-loop test method when executing the computer program.

[0027] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the protection device hardware-in-the-loop test method as described above.

[0028] Beneficial effects of the present invention: The protection device hardware-in-the-loop test method provided by the present invention uses the real simulation of the current transformer JA saturation model to restore the true current under non-ideal fault conditions, and deeply tests the working characteristics of the power station relay protection device. At the same time, the method of the present invention is convenient to wire and has a reliable principle, which is suitable for the requirements of relay protection device verification based on the principle of electrical quantity protection. The semi-physical test technology has high versatility and safety, and is easy to promote and use on site. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0030] Figure 1 A structural layout diagram of a hardware-in-the-loop simulation test system in a hardware-in-the-loop test method for a protection device provided by an embodiment of the present invention.

[0031] Figure 2 A schematic diagram of a simulation scenario to be verified in a hardware-in-the-loop test method for a protection device provided by an embodiment of the present invention.

[0032] Figure 3 A three-phase fault current recording diagram on both sides of a transformer in a hardware-in-the-loop test method for a protection device provided by an embodiment of the present invention.

[0033] Figure 4 A three-phase differential current calculation value and a trip signal recording curve diagram when the "second harmonic braking coefficient" is 0.30 in a protection device hardware-in-the-loop test method provided by an embodiment of the present invention.

[0034] Figure 5 A three-phase differential current calculation value and a trip signal recording curve diagram when the "second harmonic braking coefficient" is 0.65 in a protection device hardware-in-the-loop test method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0036] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0037] Example 1

[0038] Reference Figure 1 , as an embodiment of the present invention, provides a protection device hardware-in-the-loop test method, comprising:

[0039] Step 1: Build a simulation system in the hardware-in-the-loop simulation test system, which is the simulation scenario to be verified. The components included are generators, transformers, infinite systems, transmission lines, load impedances, mutual inductors, etc.

[0040] Step 2: According to the installation position of the protection device to be verified in the simulation scenario to be verified, determine the minimum sampling signal required for the normal operation of the protection device to be verified, and establish a current transformer model that can restore the transient saturation scenario. For TP-level current transformers, saturation characteristics are not considered. For P-level current transformers, according to the transformation ratio, core cross-sectional area, core size and other parameters, establish the JA transient saturation model of all P-level transformers in the simulation scenario to be verified;

[0041] Step 3: Connect the peripheral interfaces of the protection device to be verified, such as the current and voltage sampling channels, to the hardware of the simulated primary system, where the current signal comes from the calculated value of the current transformer model in step 2), and the voltage signal can use an ideal voltage transformer. Match the analog AIO, digital DIO and other interface devices and level levels;

[0042] Step 4: Power on the protection device to be verified, and make the simulation system output a continuous and stable electrical signal, and the correct sampling indication can be seen on the protection device. Then simulate a fault scenario in the simulation scenario to be verified, and judge the current signal with transient saturation characteristics calculated by the model and the protection device logic, observe whether its action result meets the set value and action logic, record the relevant process, and then change the fault scenario in the simulation scenario to be verified, repeat step 4, otherwise end the test.

[0043] The simulation system of step 1 has the following characteristics: it adopts the hardware architecture of CPU + multiple FPGAs. Each FPGA simulation board is equipped with synchronous analog input AI and output AO channels. The maximum sampling rate is not less than 1MS / s and the voltage range supports ±10V; it is equipped with high-speed digital input DI and output DO channels. The maximum update frequency of a single channel is not less than 10MHz, and the TTL interface standard is adopted. The basic modules can be used to build and verify the algorithm model of FPGA at will, and can be deployed and run. The basic modules include: addition, subtraction, multiplication, division, integration module, differentiation module, logic comparison module, coordinate transformation module, PID module, PLL phase lock module and other modules. In real-time simulation, the circuit parameters are adjusted online in real time, and the number of parameters and the number of modifications are not limited; power amplifiers may be used. The structural diagram of the simulation system is as follows: Figure 1 The simulation scenario to be verified is a pure software model, which has certain human-computer interaction interfaces during operation, and can trigger faults, observe model operation and other basic functions.

[0044] In step 2, the TP-level current transformer arranged in the simulation scene to be verified is converted into an ideal transformer according to the transformation ratio, that is, the primary current divided by the secondary current is the model output current. For the P-level current transformer, the calculation is performed according to the following steps:

[0045] (1) Initialize the model and set the parameters of the P-class current transformer, including the number of turns N, the equivalent cross-section A of the core, the magnetic permeability μ0 in vacuum state, μ0 = 4π×10-7T·m / A, the equivalent flux length l of the core, the resistance R2 and the leakage reactance L2 of the secondary circuit of the current transformer. Set the initial excitation current value im(k-1) and the initial magnetization intensity M(k-1). For the purpose of general algorithm flow description, the k-1th moment is recorded as the initial state mark.

[0046] (2) Calculation of the differential formula of the important parameter magnetic susceptibility of the transient saturation JA model

[0047] Calculate magnetic field strength

[0048] H(k)=i m (k-1)·N / l (1)

[0049] Calculation of JA theoretical parameters - effective magnetic field strength

[0050] H e (k) = H (k) + αM (k-1) (2)

[0051] Calculation of JA theoretical parameters - hysteresis-free magnetization

[0052]

[0053] Calculation of JA theoretical parameters - hysteresis-free magnetic permeability

[0054]

[0055] Calculation of JA theoretical parameters - magnetic permeability

[0056]

[0057] Where M s , c, K, α, and a are the five key parameters of the JA model, among which M s is the saturation magnetization of the core material; c is the energy loss coefficient; K is the pinning effect constant; a is the shape parameter; α is the domain wall coupling coefficient, which can be easily obtained from the factory magnetization curve of the ferromagnetic material; M an It is the magnetization intensity assuming that the ferromagnetic material has no hysteresis effect; the calculation of the direction parameter δ is shown in the following formula:

[0058]

[0059] (3) Calculate the differential formula of the excitation current:

[0060]

[0061] (4) Then, the output current of the P-class transformer with saturation characteristics on the secondary side is updated in real time according to the changing primary current.

[0062] i2(k)=i1(k) / Ni m (k)(8)

[0063] The step 3 connects the current and voltage sampling channels of the protection device to be verified with the hardware of the simulation system, and matches the analog AO level of the physical interface board of the hardware of the simulation system. The current signal calculated by the transformer model in the simulation system is connected to the current sampling port of the protection device through the signal output and amplification; the voltage signal calculated by the ideal voltage transformer model in the simulation system is connected to the voltage sampling port of the protection device through the signal output and amplification; the tripping output signal of the protection device to be verified is connected back to the digital DI channel of the physical interface board of the simulation system to observe and judge the correctness of the tripping action logic.

[0064] In step 4, the protection device to be verified is debugged and run with the simulation system. After the signal is observed to be stable, a fault scenario is designed according to the test item and the fault is triggered to observe whether the protection device to be verified operates correctly, whether the action time meets the protection logic, and whether the action value is consistent with the set value.

[0065] Then, according to actual needs, multiple tests can be performed in other set scenarios.

[0066] Example 2

[0067] Reference Figure 1 , as an embodiment of the present invention, provides a hardware-in-the-loop simulation test system, comprising:

[0068] CPU+multi-FPGA simulation test host, host computer, power amplifier, protection devices to be tested, signal cables and control cables.

[0069] The system adopts the hardware architecture of CPU+multi-FPGA. Each FPGA simulation board is equipped with synchronous analog input AI and output AO channels. The maximum sampling rate is not less than 1MS / s and the voltage range supports ±10V; it is equipped with high-speed digital input DI and output DO channels. The maximum update frequency of a single channel is not less than 10MHz, and the TTL interface is standard. The basic modules can be used to build and verify the algorithm model of FPGA at will, and can be deployed and run. The basic modules include: addition, subtraction, multiplication, division, integration module, differential module, logic comparison module, coordinate transformation module, PID module, PLL phase lock module, etc. In real-time simulation, the circuit parameters are adjusted online in real time, and the number of parameters and the number of modifications are not limited; power amplifiers may be used.

[0070] The structure diagram of system 1 is as follows Figure 1 As shown, Figure 1 In the figure, 1 is the CPU+multi-FPGA simulation test host; 2 is the host computer; 3 is the power amplifier; 4 is the protection device to be tested; 5 is the signal cable; 6 is the control cable; and 7 is the Ethernet cable.

[0071] During runtime, it has a certain human-computer interaction interface that can trigger faults, observe model operation and other basic functions.

[0072] Example 3

[0073] An embodiment of the present invention is different from the first two embodiments in that:

[0074] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0075] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0076] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0077] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0078] Example 3

[0079] Reference Figure 1-Figure 5 , which is an embodiment of the present invention, provides a hardware-in-the-loop test method for a protection device. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0080] The present invention discloses a protection device hardware-in-the-loop test method and system based on JA transient saturation theory. First, a simulated primary simulation system is built in a hardware-in-the-loop simulation test system (referred to as the simulated primary system in this document), that is, a simulation scenario to be verified (referred to as the simulated scenario to be verified in this document). The components included may include generators, transformers, infinite systems, transmission lines, load impedances, mutual inductors, etc. The hardware components of the simulated primary system are as follows: Figure 1 The simulated primary system is as follows Figure 2 shown.

[0081] Then, according to the installation position of the protection device to be verified in the simulation scenario to be verified, the minimum sampling signal required for the normal operation of the protection device to be verified is determined, and a current transformer model that can be used to restore the transient saturation scenario is established. For the P-class current transformer, the P-class transformer JA transient saturation model is established according to parameters such as transformation ratio, core cross-sectional area, and core size. For the TP-class current transformer, it is simulated according to the ideal transformer. The calculation steps of the P-class current transformer JA transient saturation model are:

[0082] (1) Initialize the model and set the parameters of the P-class current transformer, including the number of turns N, the equivalent cross-section A of the core, the magnetic permeability μ0 in vacuum state, μ0 = 4π×10-7T·m / A, the equivalent flux length l of the core, the resistance R2 and the leakage reactance L2 of the secondary circuit of the current transformer. Set the initial excitation current value im(k-1) and the initial magnetization intensity M(k-1). For the purpose of general algorithm flow description, the k-1th moment is recorded as the initial state mark.

[0083] (2) Calculation of the differential formula of the important parameter magnetic susceptibility of the transient saturation JA model

[0084] Calculate magnetic field strength

[0085] H(k)=i m (k-1)·N / l (1)

[0086] Calculation of JA theoretical parameters - effective magnetic field strength

[0087] H e (k) = H (k) + αM (k-1) (2)

[0088] Calculation of JA theoretical parameters - hysteresis-free magnetization

[0089]

[0090] Calculation of JA theoretical parameters - hysteresis-free magnetic permeability

[0091]

[0092] Calculation of JA theoretical parameters - magnetic permeability

[0093]

[0094] In the formula, Ms, c, K, α, and a are the five key parameters of the JA model, among which Ms is the saturation magnetization of the core material; c is the energy loss coefficient; K is the pinning effect constant; a is the shape parameter; α is the domain wall coupling coefficient, which can be easily obtained from the factory magnetization curve of the ferromagnetic material; Man is the magnetization intensity assuming that the ferromagnetic material has no hysteresis effect; the calculation of the direction parameter δ is shown in the following formula:

[0095]

[0096] (3) Calculate the differential formula of the excitation current:

[0097]

[0098] (4) Then, the output current of the P-class transformer with saturation characteristics on the secondary side is updated in real time according to the changing primary current.

[0099] i2(k)=i1(k) / Ni m (k) (8)

[0100] Then connect the peripheral interfaces of the protection device to be verified, such as the current and voltage sampling channels, to the hardware of the simulation primary system, where the current signal comes from the calculated value of the transformer model, and the voltage signal can use an ideal voltage transformer. The power amplifier in the simulation primary system can be used to match the analog AIO signal calculated by the software with the voltage and current levels of the interface of the protection device to be verified. For example, the 0-5V line voltage signal output by the simulation system is converted to 0-100V through the power amplifier, and the 0-5V phase current signal output by the simulation system is converted to 0-1A through the power amplifier. If the digital DIO signal is different from the level signal of the actual device, it also needs to be matched by the power amplifier before being connected to the actual protection device to be verified.

[0101] After completing the level matching and wiring, power on the protection device to be verified, and make the simulation system output continuous and stable electrical signals, and correct sampling can be seen on the protection device. Then simulate a fault scenario in the simulation scenario to be verified, and send the current signal with transient saturation characteristics calculated by the model to the protection device to be verified for logical judgment, observe whether its action result meets the set value and action logic, record the relevant process, and then change the fault scenario in the simulation scenario to be verified, repeat step 4), otherwise end the test.

[0102] This example simulates a 330 / 110kV, 240MVA double-winding three-phase transformer for a hardware-in-the-loop simulation test of the transformer protection device. After consulting the factory data, the transformer protection device contains a second harmonic braking criterion to avoid transformer saturation, transformer excitation inrush current and other unbalanced currents, and now it is subjected to a deep in-the-loop test. Input the transformer ratio turns, voltage level, capacity and current transformer ratio in the simulation system into the actual protection device, and configure the corresponding constants. The P-class transformer on the 330kV side is established as 600 / 1, and the secondary load is set to 7Ω. The P-class current transformer on the 110kV side is 1200 / 1, and the secondary load is also set to 7Ω. According to the actual core cross-sectional area and equivalent flux length of the two transformers, combined with the JA parameters describing the nonlinear characteristics of the core, the corresponding current transformer JA transient saturation model is established. Among them, the key parameters of the JA model are set as: Ms = 1.8 × 106, c = 0.1, k = 300, α = 2.5 × 10-5, a = 100. The key settings in the transformer protection device are: "differential start setting" is set to 0.3, "differential ratio braking maximum slope" is set to 0.8, "inrush current blocking function selection" is set to 0 (indicating second harmonic braking), and "second harmonic braking coefficient" is selected as 0.30 and 0.65 respectively for control testing.

[0103] In order to illustrate the benefits of the present invention for the setting verification and functional testing of the protection device, a fault outside the transformer area is simulated here to illustrate the advancement of this method. In the simulation scene to be verified, a three-phase short-circuit grounding fault is set near the 330kV side outside the transformer area, with a fault time of 0.7s and a duration of 0.05s. The tripping output signal and three-phase current signal of the protection device are recorded by an oscilloscope. The power supply impedance parameters of the simulation scene to be verified are set to cause the P-class current transformer to be transiently saturated under the fault current, verify the adaptability of the protection device and its setting to the transient saturation signal, and observe whether the action signal of the protection device responds correctly.

[0104] Figure 3 The three-phase current waveform calculated by the JA transient saturation model in this simulation system is shown. In the figure, IA, IB, and IC are the current transformer model calculation signals on the 330kV side, and Ia, Ib, and Ic are the current transformer model calculation signals on the 110kV side.

[0105] Figure 4 The three-phase differential current calculation results and trip signal recording curves are shown when the "second harmonic braking coefficient" in the transformer protection device is selected as 0.30. Under this setting, although the current transformer is severely distorted and the differential current is obvious, the locking logic of the protection device is correctly locked and reliably does not operate in the out-of-zone fault scenario.

[0106] Figure 5 The three-phase differential current calculation results and trip signal recording curves are shown when the "second harmonic braking coefficient" in the transformer protection device is selected as 0.65. Under this setting, the same transient saturation and the same differential current have already caused a false trip at 0.7339s.

[0107] The results show that the model, test method and system described in the present invention can perform hardware-in-the-loop semi-physical simulation testing on transformer protection devices. Compared with the verification of protection devices by conventional methods, this method can deeply test fault scenarios that are difficult to restore by conventional means, and verify the correctness and reliability of the protection device functions and their settings.

[0108] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A protection device hardware-in-the-loop test method, characterized in that: include: Construct simulation scenarios in the hardware-in-the-loop simulation test system; According to the installation position of the protection device to be verified in the simulation scenario, the minimum sampling signal required for the normal operation of the protection device to be verified is determined, and a current transformer model that can restore the transient saturation scenario is established; Perform power-on operation on the protection device to be verified, and make the hardware-in-the-loop simulation test system output electrical signals; After the correct sampling indication is obtained on the protection device, a fault scenario is simulated in the simulation scenario. The current signal with transient saturation characteristics calculated by the model is judged by the protection device logic to determine whether its action result meets the set value and action logic.

2. The protection device hardware-in-the-loop test method according to claim 1, characterized in that: The current transformer model includes a TP-level current transformer and a P-level current transformer.

3. The protection device hardware-in-the-loop test method according to claim 2, characterized in that: The saturation characteristics of the TP-level current transformer are not considered.

4. The protection device hardware-in-the-loop test method according to claim 3, characterized in that: A JA transient saturation model is established for the P current level transformer.

5. The protection device hardware-in-the-loop test method according to claim 4, characterized in that: The establishment of the JA transient saturation model includes initializing the model and setting the P-level current transformer parameters; Calculate the differential formula of magnetic susceptibility, an important parameter of transient saturation JA model; Calculate the differential equation of the excitation current; The output current of the P-class transformer with saturation characteristics on the secondary side is updated in real time according to the changed primary current.

6. The protection device hardware-in-the-loop test method according to claim 5, characterized in that: The P-class current transformer parameters include transformation ratio turns, equivalent cross-section of the core, magnetic permeability in a vacuum state, equivalent flux length of the core, resistance and leakage reactance of the secondary circuit of the current transformer, initial excitation current value and initial magnetization intensity.

7. The protection device hardware-in-the-loop test method according to claim 6, characterized in that: The method includes connecting the current and voltage sampling channels of the protection device to be verified with the hardware of the hardware-in-the-loop simulation test system, and matching the analog AO level level of the hardware physical interface board of the hardware-in-the-loop simulation test system; The current signal calculated by the mutual inductor model in the hardware-in-the-loop simulation test system is connected to the current sampling port of the protection device after being output and amplified; The voltage signal calculated by the ideal voltage transformer model in the hardware-in-the-loop simulation test system is connected to the voltage sampling port of the protection device through signal output and amplification; Connect the tripping output signal of the protection device to be verified back to the digital DI channel of the physical interface board of the hardware-in-the-loop simulation test system.

8. A hardware-in-the-loop simulation test system, characterized in that: include: CPU+multi-FPGA simulation test host, host computer, power amplifier, protection device to be tested, signal cable, control cable and Ethernet cable; The CPU+multi-FPGA simulation test host is used to generate current and voltage signals under simulation scenarios and calculate fault scenarios through simulation algorithms; The host computer is connected to the CPU+multi-FPGA simulation test host via an Ethernet cable to set fault scenarios and monitor simulation results; The power amplifier amplifies the analog signal output by the simulation host to drive the input channel of the protection device to be verified; The signal cable connects the power amplifier and the protection device to be checked, and is used to transmit current and voltage signals; The control cable connects the protection device to be verified with the simulation test host, and is used to transmit input and output signals and monitor the action logic of the protection device; The fault scenario is adjusted in real time by the host computer, and the simulation host outputs a signal that meets the requirements through the power amplifier to the protection device for verification.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the protection device hardware-in-the-loop test method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the protection device hardware-in-the-loop test method according to any one of claims 1 to 7 are implemented.

Images