System-on-chip control method and device, equipment and medium

Abstract

The invention discloses a system-on-chip control method, device, equipment and medium, and the system-on-chip control method is applied to a microcontroller, and comprises the steps: sending a control signal to a target system-on-chip in response to the detection that the target system-on-chip meets a control condition; a control result is determined according to whether a corresponding response signal is detected in a first duration, and the first duration is determined based on a historical control duration; and executing an associated control action based on the control result. And the control efficiency and success rate of the target system on chip are improved, so that the stability and reliability of the system are improved.

Description

Technical Field

[0001] The present application relates to the technical field of system-on-chip control, and in particular to a method, device, equipment and medium for controlling a system-on-chip. Background Art

[0002] At present, most smart cockpit systems use a microcontroller (MCU) + system on chip (SOC) solution, in which the MCU usually undertakes the basic control tasks of the system, such as vehicle power management, bus communication, sensor data reading, etc. The characteristics of MCU are low power consumption and fast response, which are suitable for executing tasks with high real-time requirements. SOC is mainly used to handle complex multimedia, navigation, infotainment, instrument display and other tasks in smart cockpits. It has powerful computing power and usually runs on operating systems such as Linux or Android to provide a rich user experience. SOC has high power consumption and is suitable for processing high-bandwidth, multi-tasking workloads.

[0003] Furthermore, the MCU is also responsible for controlling the power-on and power-off processes of the SOC, and determines whether the SOC has completed startup or shutdown normally by setting a fixed timeout. However, this strategy of determining whether the SOC has completed startup or shutdown normally by setting a fixed timeout has many problems and shortcomings in actual applications: when the SOC is first started after flashing the machine at the factory, additional initialization tasks are often required, so the startup time is long. In order to ensure that the SOC completes these initial startup tasks, the MCU usually sets a longer timeout, such as 2 minutes. However, in subsequent daily use, the startup time of the SOC is greatly shortened, and the startup time and shutdown time of the SOC are not fixed. Each cabin system on the vehicle may fluctuate due to load, system status, environmental factors, software version, hardware, etc. The setting of a fixed timeout cannot cope with such dynamic changes. If the timeout is set too long, the MCU will wait too long after the fault occurs and will not be able to restart or shut down the SOC in time, causing the system to stagnate for a long time, affecting the overall reliability of the system. If the timeout period is set too short, the SOC may be mistakenly considered abnormal before it has completed normal startup, thereby triggering unnecessary restart or shutdown operations and affecting system stability.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0006] The present application provides a control method, device, equipment and medium for a system on chip, which improves the control efficiency and success rate of a target system on chip, thereby improving the system stability and reliability.

[0007] In a first aspect, the present invention provides a control method for a system on chip, which is applied to a microcontroller, and comprises the following steps:

[0008] In response to detecting that the target system-on-chip satisfies the control condition, sending a control signal to the target system-on-chip;

[0009] Determining a control result according to whether a corresponding response signal is detected within a first duration, wherein the first duration is determined based on a historical control duration;

[0010] An associated control action is performed based on the control result.

[0011] Furthermore, before sending the control signal to the target system on chip, the method further includes:

[0012] Determining the first duration based on historical control durations;

[0013] Alternatively, a target duration is read and the target duration is determined as the first duration, wherein the target duration is predetermined based on a historical control duration.

[0014] Further, the determining the first duration based on the historical control duration includes:

[0015] Determine the reference duration based on the historical control duration;

[0016] The smaller one of a reference duration and an initial timeout time set for the target system-on-chip is determined as the first duration.

[0017] Further, determining the reference duration based on the historical control duration includes:

[0018] The reference duration is determined based on one or more of a historical control duration, a confidence coefficient of a normal distribution curve, and a dynamic adjustment function based on a sample size of the historical control duration.

[0019] Further, the determining of the reference duration based on one or more of the historical control duration, the confidence coefficient of the normal distribution curve, and the dynamic adjustment function based on the number of historical control duration samples includes:

[0020] The reference duration is determined based on the following calculation formula:

[0021] T F =μ n +Z α ×σ n +T redundancy ×f(n)

[0022] Among them, T F represents the reference duration, μ n represents the mean of the historical control duration samples, σ n represents the variance of the historical control time sample, Z α Represents the confidence coefficient of the normal distribution curve, T redundancy represents the preset redundancy time, f(n) represents the dynamic adjustment function based on the number of historical control duration samples, and n represents the number of historical control duration samples.

[0023] Furthermore, the dynamic adjustment function f(n) based on the number of historical control duration samples is:

[0024]

[0025] Among them, N represents the preset threshold, n represents the number of samples of historical control duration, and f max represents the maximum value of the redundancy coefficient, f min represents the minimum value of the redundancy coefficient, k represents the decreasing coefficient, k = (f max -f min ) / (N-1).

[0026] Further, the determining of the control result according to whether a corresponding response signal is detected within the first time period includes:

[0027] In response to not detecting a corresponding response signal within a first time period, determining that the control result is a failure;

[0028] In response to detecting a corresponding response signal within the first time period, it is determined that the control result is successful.

[0029] Further, the control signal includes a power-on signal, and correspondingly, the historical control duration includes a historical power-on duration; and the associated control action is performed based on the control result, including:

[0030] In response to the control result being a power-on failure, controlling the power of the target system-on-chip to be turned off, and resending a power-on signal to the target system-on-chip after waiting for a preset time;

[0031] Adjusting the first duration to obtain a new first duration;

[0032] The control result is determined according to whether the corresponding response signal is detected within the new first time period.

[0033] Furthermore, the adjusting the first duration to obtain a new first duration includes:

[0034] The new first duration is determined based on the following first formula:

[0035] T timeout =min(T timeout_previous +ΔT,T initial )

[0036] Among them, T timeout Indicates the new first duration, T timeout_previous Indicates the first duration of the previous adjacent time, ΔT indicates the set delay value, T initial Indicates the initial timeout period.

[0037] Further, sending a control signal to the target system on chip includes:

[0038] Send a power-on signal to the power status pin of the target system-on-chip.

[0039] Further, the determining of the control result according to whether a corresponding response signal is detected within the first time period includes:

[0040] In response to not detecting a startup completion flag signal within a first time period, determining that the control result is a power-on failure;

[0041] In response to detecting the startup completion flag signal within the first time period, determining the control result as a power-on success.

[0042] Furthermore, after sending the control signal to the target system-on-chip and before determining the control result according to whether the corresponding response signal is detected within the first time period, the method further includes:

[0043] In response to detecting a response signal fed back by the power state pin of the target system-on-chip within a set time period, continuing to perform the operation of determining a control result according to whether a corresponding response signal is detected within a first time period;

[0044] In response to not detecting a response signal fed back by a power state pin of the target system-on-chip within a set time period, it is determined that power-on failure has occurred.

[0045] Furthermore, it also includes:

[0046] In response to the number of consecutive power-on failures reaching a threshold, a fault alarm is issued.

[0047] Further, the control signal includes a power-off signal or a system suspend-to-memory signal, and the associated control action is performed based on the control result, including:

[0048] In response to the control result being a power-off failure or a system suspend to memory failure, the state information of the target system-on-chip at that time is recorded, and the power of the target system-on-chip is forcibly turned off.

[0049] In a second aspect, the present invention further provides a control device for a system on chip, comprising:

[0050] a sending module, configured to send a control signal to the target system-on-chip in response to detecting that the target system-on-chip satisfies the control condition;

[0051] A determination module, configured to determine a control result according to whether a corresponding response signal is detected within a first duration, wherein the first duration is determined based on a historical control duration;

[0052] A control module is used to execute an associated control action based on the control result.

[0053] In a third aspect, the present invention further provides an electronic device, the electronic device comprising:

[0054] one or more processors;

[0055] A storage device for storing one or more programs;

[0056] When the one or more programs are executed by the one or more processors, the one or more processors implement the control method of the system on chip as described above.

[0057] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the control method of the system on chip as described above.

[0058] The control method of the system on chip disclosed in the present invention dynamically determines the current control duration (i.e., the first duration) based on the historical control duration, so that the value of the first duration is more appropriate, and the normal control process will not be considered abnormal due to the first duration being too short, thereby triggering unnecessary repeated control processes and affecting the stability of the system, and the failure of the system to be handled in time due to the first duration being too long, affecting the reliability of the system. By determining the control result according to whether the corresponding response signal is detected within the first duration, and executing the associated control action based on the control result, the control efficiency and success rate of the target system on chip are improved, thereby improving the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0060] Figure 1 A schematic diagram of a control method for a system on chip provided by an embodiment of the present invention Figure 1 ;

[0061] Figure 2 A schematic diagram of a control method for a system on chip provided by an embodiment of the present invention Figure 2 ;

[0062] Figure 3 A schematic diagram of a control method for a system on chip provided by an embodiment of the present invention Figure 3 ;

[0063] Figure 4 A schematic diagram of a control method for a system on chip provided by an embodiment of the present invention Figure 4 ;

[0064] Figure 5 A schematic diagram of a control method for a system on chip provided by an embodiment of the present invention Figure 5 ;

[0065] Figure 6 A schematic diagram of the structure of a control device of a system on chip provided by an embodiment of the present invention;

[0066] Figure 7 FIG. 4 is a schematic diagram of the structure of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0067] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0068] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0069] The control method of the system on chip proposed in this application is applicable to the application scenario where a microcontroller MCU is used to control the system on chip SOC. Typically, it can be applied to the microcontroller in the smart cockpit system.

[0070] At present, most smart cockpit systems use a microcontroller MCU + system-on-chip SOC solution, in which the MCU usually undertakes the basic control tasks of the system, such as vehicle power management, bus communication, sensor data reading, etc. The characteristics of MCU are low power consumption and fast response, which are suitable for executing tasks with high real-time requirements. SOC is mainly used to handle complex multimedia, navigation, infotainment, instrument display and other tasks in smart cockpits. It has powerful computing power and usually runs on operating systems such as Linux or Android to provide a rich user experience. SOC has high power consumption and is suitable for processing high-bandwidth, multi-tasking workloads.

[0071] Furthermore, the MCU is also responsible for controlling the power-on and power-off processes of the SOC, and determines whether the SOC has completed startup or shutdown normally by setting a fixed timeout. However, this strategy of determining whether the SOC has completed startup or shutdown normally by setting a fixed timeout has many problems and shortcomings in actual applications: when the SOC is first started after flashing the machine at the factory, additional initialization tasks are often required, so the startup time is long. In order to ensure that the SOC completes these initial startup tasks, the MCU usually sets a longer timeout, such as 2 minutes. However, in subsequent daily use, the startup time of the SOC is greatly shortened, and the startup time and shutdown time of the SOC are not fixed. Each cabin system on the vehicle may fluctuate due to load, system status, environmental factors, software version, hardware, etc. The setting of a fixed timeout cannot cope with such dynamic changes. If the timeout is set too long, the MCU will wait too long after the fault occurs and will not be able to restart or shut down the SOC in time, causing the system to stagnate for a long time, affecting the overall reliability of the system. If the timeout period is set too short, the SOC may be mistakenly considered abnormal before it has completed normal startup, thereby triggering unnecessary restart or shutdown operations and affecting system stability.

[0072] In view of the above problems, the present application proposes a solution. Specifically, a mechanism for dynamically adjusting the timeout time is proposed. The mechanism sets the timeout time based on the statistical data of the most recent startup time to ensure the reliability of the startup process. Under normal startup conditions, the timeout time is calculated by normal distribution to ensure that the timeout time is sufficient to cover the time required for normal startup. And a timeout processing strategy for startup failure is proposed: when the startup fails, the timeout time is gradually increased to avoid frequent restarts. And a timeout setting adapted to small sample conditions is proposed: when the number of startups is small, resulting in a small number of samples of the most recent startup time, an initial timeout time setting is provided to ensure stability during the startup process. If the number of samples is not enough to calculate the standard deviation, the preset initial timeout time Tinitial is used as the initial setting, and the timeout time is gradually adjusted until the sample size is sufficient for more accurate adjustment. The MCU controls the power-on and power-off timing of the SOC. When the SOC is started or powered off abnormally, the MCU can process it quickly to avoid long waiting times, thereby improving the system response efficiency, and can locate the cause of the abnormality through abnormal storage information.

[0073] For example, Figure 1 A flow chart of a control method of a system on chip proposed in this application is shown in FIG. Figure 1 As shown, the control method of the system on chip includes the following steps:

[0074] S110 . In response to detecting that the target system-on-chip satisfies a control condition, sending a control signal to the target system-on-chip.

[0075] In the smart cockpit system, the microcontroller receives messages through the bus (FlexRay or CAN). When the INH pin of the FlexRay or CAN transceiver is pulled high, the MCU is awakened, and the MCU determines whether the target on-chip system meets the control conditions based on the bus signal.

[0076] Exemplarily, the control condition includes a power-on condition, a power-off condition, or a system suspend to memory condition, and the corresponding control signal includes a power-on signal, a power-off signal, or a system suspend to memory signal. That is, when it is determined that the power-on condition is met, a power-on signal is sent to the target system-on-chip; when it is determined that the power-off condition is met, a power-off signal is sent to the target system-on-chip; when it is determined that the system suspend to memory condition is met, a system suspend to memory signal is sent to the target system-on-chip.

[0077] The sending of a power-on signal to the target system-on-chip includes: sending a power-on signal to a power state pin PG of the target system-on-chip.

[0078] S120. Determine a control result according to whether a corresponding response signal is detected within a first time period, wherein the first time period is determined based on a historical control time period.

[0079] Exemplarily, in response to not detecting a corresponding response signal within a first time period, the control result is determined to be a failure; in response to detecting a corresponding response signal within the first time period, the control result is determined to be a success.

[0080] For example, taking the power-on control of the target system-on-chip as an example, in response to detecting that the target system-on-chip meets the power-on conditions, a power-on signal is sent to the target system-on-chip; in response to not detecting a startup completion mark signal (such as an SD_ACK signal) within a first time period, the control result is determined to be a power-on failure; in response to detecting a startup completion mark signal within the first time period, the control result is determined to be a power-on success.

[0081] For another example, taking the power-off control of the target system on chip as an example, in response to detecting that the target system on chip meets the power-off conditions, a power-off signal is sent to the target system on chip, in response to not detecting a normal power-off completion signal (for example, SD_ACK pull-down signal) within a first time period, that is, SD_ACK is still in a high-level state, it means that the target system on chip SOC has not been powered off successfully, and the control result is determined to be a power-off failure; in response to detecting a normal power-off completion signal within the first time period, it is determined that the control result is a power-off success.

[0082] By dynamically determining the current control duration (i.e., the first duration) based on the historical control duration, the value of the first duration is made more appropriate. It will not cause the normal control process to be deemed abnormal before it is completed due to the first duration being too short, thereby triggering unnecessary repeated control processes and affecting the stability of the system. It will not cause the failure of the system to be handled in time when a failure occurs due to the first duration being too long, thereby affecting the reliability of the system.

[0083] S130: Execute an associated control action based on the control result.

[0084] In some implementations, the control signal includes a power-on signal, and correspondingly, the historical control duration includes a historical power-on duration; and performing an associated control action based on the control result includes:

[0085] In response to the control result being a power-on failure, the power of the target system-on-chip is controlled to be turned off, and a power-on signal is resent to the target system-on-chip after waiting for a preset time; the first time is adjusted to obtain a new first time; and the control result is determined according to whether a corresponding response signal is detected within the new first time. The adjusting of the first time to obtain a new first time includes:

[0086] The new first duration is determined based on the following first formula:

[0087] T timeout =min(T timeout_previous +ΔT,T initial)

[0088] Among them, T timeout Indicates the new first duration, T timeout_previous Indicates the first duration of the previous adjacent time, ΔT indicates the set delay value, T initial Indicates the initial timeout period.

[0089] If a startup fails, it may be affected by many factors, such as environment, temperature, hardware status, etc. Therefore, within the three startup times, increasing the timeout time can allow the system to have enough time to complete the startup the next time it restarts, but it will not exceed the initial timeout time T set by the MCU in the end. initial (e.g. 120s).

[0090] That is, a timeout handling strategy for startup failure is proposed: gradually increase the timeout time T when startup fails. timeout , avoiding frequent restarts, thereby improving system stability. In addition, when a startup fails, restarting the system can improve the success rate and efficiency of the system startup, which is beneficial to improving system stability.

[0091] Furthermore, it also includes: in response to the number of consecutive power-on failures reaching a threshold, a fault alarm is issued. By setting a threshold for the number of consecutive power-on failures, a fault alarm is issued when the number of consecutive power-on failures reaches the threshold, the accuracy of the fault alarm can be improved, false alarms can be avoided, and when a fault occurs, the fault can be handled in a timely manner, which is conducive to improving the reliability of the system.

[0092] In some other implementations, the control signal includes a power-off signal or a system suspend-to-memory signal, and the performing of the associated control action based on the control result includes:

[0093] In response to the control result being a power-off failure or a system suspend to memory failure, the state information of the target system-on-chip at that time is recorded, and the power of the target system-on-chip is forcibly turned off.

[0094] Furthermore, in some implementations, before sending the control signal to the target system on chip, the method further includes:

[0095] The first duration is determined based on the historical control duration; or, the target duration is read and the target duration is determined as the first duration, wherein the target duration is predetermined based on the historical control duration. That is, the first duration can be calculated in real time, or can be calculated in advance and stored, and can be directly read when used.

[0096] The determining the first duration based on the historical control duration includes:

[0097] Determine a reference duration based on the historical control duration; determine the smaller of the reference duration and the initial timeout time set for the target system-on-chip as the first duration. It is understandable that in order to ensure the stability of the startup process, the stability of the power-off process, or the stability of the system suspending to the memory, the initial timeout time is usually set to be longer. However, in subsequent daily use, the specific startup time, shutdown time, or the time required for the system to suspend to the memory will fluctuate. Therefore, the present application proposes a solution for dynamically determining the current control duration based on the historical control duration. In particular, a timeout setting adapted to the small sample situation is proposed: when the number of samples of the historical control duration is small due to the small number of startup times, power-off times, or system suspending times to the memory, an initial timeout time setting is provided to ensure system stability. If the number of samples is not enough to calculate the standard deviation, the preset initial timeout time Tinitial is used as the initial setting, and the timeout time is gradually adjusted until the sample size is sufficient for more accurate adjustment.

[0098] Further, determining the reference duration based on the historical control duration includes:

[0099] The reference duration is determined based on one or more of a historical control duration, a confidence coefficient of a normal distribution curve, and a dynamic adjustment function based on a sample size of the historical control duration.

[0100] Optionally, the reference duration is determined based on the following calculation formula:

[0101] T F =μ n +Z α ×σ n +T redundancy ×f(n)

[0102] Among them, T F represents the reference duration, μ n represents the mean of the historical control duration samples, σ n represents the variance of the historical control time sample, Z α It represents the confidence coefficient of the normal distribution curve. For example, when Z=5, the probability under the normal distribution curve is close to 99.99994%, and the probability that the data falls within the range of the mean μ plus or minus 5σ is very close to 99.99994%. By calculating the reference duration in combination with the normal distribution method, it can be ensured that the timeout time is sufficient to cover the time required for normal control, thereby ensuring that the value of the first duration is more appropriate, more objective, and closer to the actual situation.

[0103] T redundancy Indicates the preset redundancy time (can be 5s or 10s). By setting the preset redundancy time T redundancy, the range of the timeout period can be further extended, and the fault tolerance can be further extended. f(n) represents a dynamic adjustment function based on the number of historical control duration samples. When the number of samples is small, the value of f(n) is high. As the number of samples increases, the value of f(n) gradually decreases to improve the response speed and stability of the system. n represents the number of historical control duration samples, that is, the number of normal power-on, normal power-off, or normal entry into STR (Suspend To RAM, system suspend to memory) mode.

[0104] Exemplarily, the dynamic adjustment function f(n) based on the number of historical control duration samples is:

[0105]

[0106] Where N represents the preset threshold (for example, 30), n represents the number of samples of historical control duration, and f max represents the maximum value of the redundancy coefficient (for example, 1), f min represents the minimum value of the redundancy coefficient (for example, 0.3), k represents the decreasing coefficient, k = (f max -f min ) / (N-1).

[0107] In particular, the dynamic adjustment function f(n) based on the number of historical control duration samples can also be in other function forms, as long as it satisfies the rule that when n is small, the value of f(n) is large, and as n increases, the value of f(n) gradually decreases.

[0108] For example, suppose there are 30 samples of normal startup time, and you want to set a timeout to ensure that the probability of successful system startup is close to 100%, corresponding to Z α =5, N=30, the first duration can be calculated by the above calculation method.

[0109] Sample data: Assume that the samples of the most recent 30 startup times are as follows (in seconds): 18, 19, 20, 21, 22, 20, 19, 18, 23, 21, 22, 20, 19, 24, 23, 21, 22, 23, 19, 20, 22, 23, 24, 25, 20, 21, 22, 19, 20, 21.

[0110] Calculate the mean μ of the above sample data n :μ n =(18+19+20+21+22+20+19+18+23+21+22+20+19+24+23+21+22+23+19+20+22+23+24+25+20+21+22+19+20+21) / 30=21.17s.

[0111] Calculate the variance σ of the above sample data n :σ n =1.6s. α =5, T redundancy =10, f max is the maximum value of the redundancy factor, for example 1. min is the minimum value of the redundancy coefficient, for example 0.3. The reference duration T is finally calculated. F =21.17+8+0.3*10=32.17. In this example, based on the samples of the last 30 startup times (i.e., historical control duration), Z α =5 confidence level and 5 seconds redundancy time, the timeout time (i.e., the first duration) is set to 32.17s, which can almost ensure that the probability of successful system startup is close to 100%. If the startup fails within 34.17s, it can be basically determined that the SOC startup is abnormal, and the SOC will not be successfully started even if the MCU waits for a longer period of time. Therefore, the MCU can directly perform exception processing after the timeout time expires, and execute the operation of restarting the SOC to achieve rapid processing of the exception.

[0112] Optionally, the reference duration may also be determined based on the following calculation formula:

[0113] T F =μ n +Z α ×σ n

[0114] Among them, T F represents the reference duration, μ n represents the mean of the historical control duration samples, σ n represents the variance of the historical control time sample, Z α Represents the confidence coefficient of the normal distribution curve.

[0115] In summary, the first duration is determined based on the historical control duration, that is, each time the control ends, the actual control duration of the time needs to be recorded as the basis for calculating the next control duration. Taking the power-on and power-off control as an example, the recording method of the actual power-off time of the SOC is described. After the MCU is powered on, an OS ISR interrupt can be generated every 1ms. A variable can be used to record the MCU system time. For example, the power-off time starts from notifying the SOC to power off, and the current timestamp A1 is obtained. When the SOC is powered off successfully or after a timeout, the current timestamp A2 is recorded. A2-A1 is the actual power-off time (if the SOC is powered off for a timeout, then the value of A2-A1 is the first duration obtained by calculation before the control). The time of A2-A1 can be recorded each time, and the actual control duration of the last time is read as a basis for the next control. The first duration of this control is calculated, and the dynamic determination of the first duration is realized, so that the value of the first duration is more reasonable and objective, neither too long nor too short, which is conducive to improving control efficiency and system stability and reliability.

[0116] In some implementations, taking controlling the power-on of a target system-on-chip as an example, the control method flow of the system-on-chip is described. Figure 2 As shown, the following steps are included:

[0117] S210 . In response to detecting that the target system on chip meets a power-on condition, sending a power-on signal to the target system on chip.

[0118] Optionally, the MCU notifies the SOC to power on through the general purpose input and output port GPIO. At this time, the GPIO of the MCU serves as an output, the GPIO of the SOC receives the output signal of the MCU GPIO, and then the SOC performs a power-on operation.

[0119] S220, determining whether a response signal fed back from the power state pin of the target system-on-chip is detected within a set time period, if yes, executing S230, otherwise executing S240a.

[0120] The MCU detects whether the Power Good (PG) pin of the SOC feeds back a response signal within the set time. If the PG pin of the SOC feeds back a response signal within the set time, it indicates that the SOC power supply is in normal working condition. At this time, the SOC is the signal output terminal, and the MCU reads the output signal of the SOC as an input. The main function of the Power Good (PG) pin signal is to indicate whether the SOC power supply is in normal working condition. If the Power Good signal is not received within the set time, the SOC power supply is abnormal and the SOC needs to be restarted. First turn off the SOC power supply, wait for an appropriate time, and wait for the SOC power to be released (the waiting time depends on the hardware design, such as 1s), and then restart the SOC. When the Power Good (PG) detection is started for three consecutive times without a response within the timeout period, it is determined that the SOC power supply is abnormal, and the hardware needs to be checked (DDR chip problem, or it may be power supply, welding and other problems). Each time the SOC fails to start successfully, the MCU side can record the abnormal log as needed and store it (including the time, power status, Power Good and other statuses) to facilitate further positioning of the abnormality. If Power Good responds normally within the timeout period, the MCU will further detect the SOC startup completion flag signal SD_ACK after obtaining it. This signal is output by the SOC and read by the MCU. When the SD_ACK detection fails to respond within the timeout period for three consecutive startups, it means that the system or hardware has failed. The abnormal log is also recorded and stored for further investigation. If SD_ACK responds normally within the specified time, it means that the SOC has successfully started. The above three consecutive startup failures are extreme cases, which basically only occur in the factory offline or development stage (hardware problem). In most cases, the startup can be completed normally. In rare cases, the startup may time out once, and the next startup will be successful.

[0121] S230, determining whether a startup completion flag signal is detected within the first time period, if detected, determining that the SOC is powered on successfully, if not detected, executing S240b.

[0122] S240a, record the number of SOC startup failures in this power-on cycle, and execute S250a.

[0123] S240b, record the number of SOC startup failures in this power-on cycle, and execute S250b.

[0124] S250a, determine whether the number of startup failures is less than a threshold, if so, execute S260, otherwise execute S270.

[0125] S250b, determine whether the number of startup failures is less than a threshold, if so, execute S260, otherwise execute S280.

[0126] S260 , controlling the target system-on-chip to power off, and returning to S210 after waiting for a preset time, to resend a power-on signal to the target system-on-chip.

[0127] S270, maintain the scene, hardware PG failure, trigger fault alarm.

[0128] S280, maintain the scene, SOC failure, trigger fault alarm.

[0129] In some implementations, taking controlling the target SoC to power off or enter STR as an example, the control method flow of the SoC is described. Figure 3 As shown, the following steps are included:

[0130] S310 . In response to detecting that the target system-on-chip meets a power-off condition or an STR-entering condition, sending a power-off signal or an STR-entering signal to the target system-on-chip.

[0131] S320, determining whether a normal power-off signal or a normal STR entry signal is detected within the first time period, if detected, executing S330, otherwise, executing S340.

[0132] S330, SOC shutdown is normal or STR is normal, turn off the SOC related power supply.

[0133] S340, record the abnormal information, and the MCU forcibly shuts down the SOC related power supply.

[0134] In some implementations, one MCU can control two SOCs at the same time. For example, in a vehicle intelligent cockpit system, the MCU controls the master SOC and the slave SOC at the same time, where the master SOC mainly controls instrument-related functions and applications, and the slave SOC mainly controls central control system-related functions and applications. When the MCU controls the master SOC and the slave SOC at the same time, it is required that both the master SOC and the slave SOC are powered on, powered off, or enter STR normally to determine that a control is completed normally. Figure 4 As shown in the figure, the process of MCU controlling the power-down of the main SOC and the slave SOC at the same time includes the following steps:

[0135] S410 . When the MCU power state meets the shutdown condition, set the master SOC power-off timeout T5 and the slave SOC power-off timeout T6 .

[0136] The specific values ​​of T5 and T6 are calculated according to the aforementioned method of determining the first duration.

[0137] S420 , sending power-off signals to the master SOC and the slave SOC respectively.

[0138] S430, detecting whether the main SOC feeds back a power-off success signal within T5, and whether the slave SOC feeds back a power-off success signal within T6. If both feed back a power-off success signal within the specified time, executing S440; if either does not feed back a power-off success signal within the specified time, executing S450.

[0139] S440 , the master SOC and the slave SOC are shut down normally, the power supply related to the master SOC is turned off, and the power supply related to the slave SOC is turned off.

[0140] S450 , recording abnormal information, and forcibly shutting down the power supply related to the master SOC and the power supply related to the slave SOC.

[0141] like Figure 5 As shown, the process of MCU controlling the main SOC and the slave SOC to enter STR at the same time includes the following steps:

[0142] S510. When the MCU power state meets the STR entry condition, set the master SOC to enter STR timeout time T7, and the slave SOC to enter STR timeout time T8.

[0143] The specific values ​​of T7 and T8 are calculated according to the aforementioned method of determining the first duration.

[0144] S520 , sending STR signals to the master SOC and the slave SOC respectively.

[0145] S530, check whether the main SOC feeds back the STR success signal within T7, and whether the slave SOC feeds back the STR success signal within T8. If both feed back the STR success signal within the specified time, execute S540. If either does not feed back the STR success signal within the specified time, execute S550.

[0146] S540, the master SOC and the slave SOC enter STR normally, turn off the power supply related to the master SOC, and turn off the power supply related to the slave SOC.

[0147] S550 , recording abnormal information, and forcibly shutting down the power supply related to the master SOC and the power supply related to the slave SOC.

[0148] In summary, when the power state meets the conditions for shutdown or entering STR (the choice of entering STR and shutdown depends on bus signals, such as battery power, temperature, vehicle mode, etc.), set the main SOC power-off timeout (timeout) T5, the slave SOC power-off timeout T6, if entering STR, then set the main SOC to enter STR timeout T7, the slave SOC to enter STR timeout T8. Power-off and entering STR are 2-choose-1 based on the signal state, and the process is basically the same. The following is described by controlling SOC power-off. GPIO is used to notify the main SOC and the slave SOC to power off, and then detect whether the SD_ACK of the main SOC responds within T5 time, and detect whether the SD_ACK of the slave SOC responds within T6 time. If SD_ACK is normally pulled low within the specified time, it means that the SOC power-off is completed normally, so that the SOC related power can be turned off. If SD_ACK is still in a high level state within the specified time, it means that the SOC has not been powered off successfully, and the abnormal information is recorded. The MCU forces the SOC power to be turned off, and then the MCU goes through the power-off sleep process. In particular, as a special treatment, sometimes when the SOC is powered off or entering the STR process, the user needs to use the car again. In this case, the MCU side can restart the SOC directly without waiting for the power-off process, and then quickly respond to the car demand and light up the screen.

[0149] The control method of the system on chip disclosed in the embodiment of the present invention can improve the success rate of the startup process by dynamically adjusting the timeout time based on historical control data, ensuring that the system can adapt when facing fluctuations in the startup time. It can reduce system restarts: when the startup is abnormal, the frequent restarts are reduced by gradually increasing the timeout time, thereby improving the stability and reliability of the system. Optimize the timeout setting: The present invention optimizes the timeout setting by comprehensively considering the normal startup time and the processing strategy after the startup failure, so that it can avoid excessive waiting time while ensuring the startup success rate.

[0150] Figure 6 FIG. 1 is a schematic diagram of a control device of a system on a chip provided by an embodiment of the present invention, which can be integrated into a microcontroller of a vehicle. Figure 6 As shown, the device includes: a sending module 610, a determining module 620 and a controlling module 630.

[0151] Among them, the sending module 610 is used to send a control signal to the target system-on-chip in response to detecting that the target system-on-chip meets the control condition; the determination module 620 is used to determine the control result according to whether the corresponding response signal is detected within a first time period, wherein the first time period is determined based on the historical control time period; the control module 630 is used to perform associated control actions based on the control result.

[0152] The control device of the system on chip provided in the embodiment of the present disclosure can execute the steps of the control method of the system on chip provided in the method embodiment of the present disclosure, and the execution steps and beneficial effects are no longer repeated here.

[0153] Figure 7 Schematic diagram of the structure of an electronic device in the embodiment of the present disclosure. Figure 7 , which shows a structural schematic diagram of an electronic device 500 suitable for implementing the embodiments of the present disclosure. Figure 7 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0154] like Figure 7 As shown, the electronic device 500 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) or a program loaded from a storage device 508 into a random access memory (RAM) to implement the method of the embodiment described in the present disclosure. In RAM503, various programs and data required for the operation of the electronic device 500 are also stored. The processing device 501, ROM 502, and RAM503 are connected to each other via a bus 504. An I / O interface 505 is also connected to the bus 504. An input device 506, an output device 507, a storage device 508, and a communication device 509 are all connected to the I / O interface 505.

[0155] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart, thereby implementing the control method of the system on chip as described above. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 509, or installed from the storage device 508, or installed from the ROM 502. When the computer program is executed by the processing device 501, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0156] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0157] The computer-readable medium may be included in the electronic device, or may exist independently without being installed in the electronic device. The computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device executes the method steps in the present application.

[0158] Optionally, when the above one or more programs are executed by the electronic device, the electronic device may also execute other steps described in the above embodiments.

[0159] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0160] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0161] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and its core ideas of this application. The above is only the preferred implementation method of this application. It should be pointed out that due to the limitations of textual expression and the objective existence of infinite specific structures, ordinary technicians in this technical field can make several improvements, modifications or changes without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the inventive concept and technical solution to other occasions without improvement, should be regarded as the scope of protection of this application.

Claims

1. A control method of a system on chip, applied to a microcontroller, characterized in that: include: In response to detecting that the target system-on-chip satisfies the control condition, sending a control signal to the target system-on-chip; Determining a control result according to whether a corresponding response signal is detected within a first duration, wherein the first duration is determined based on a historical control duration; An associated control action is performed based on the control result.

2. The control method of the system on chip according to claim 1, characterized in that: Before sending the control signal to the target system on chip, the method further includes: Determining the first duration based on historical control durations; Alternatively, a target duration is read and the target duration is determined as the first duration, wherein the target duration is predetermined based on a historical control duration.

3. The control method of the system on chip according to claim 2, characterized in that: The determining the first duration based on the historical control duration includes: Determine the reference duration based on the historical control duration; The smaller one of a reference duration and an initial timeout time set for the target system-on-chip is determined as the first duration.

4. The control method of the system on chip according to claim 3, characterized in that: The determining of the reference duration based on the historical control duration includes: The reference duration is determined based on one or more of a historical control duration, a confidence coefficient of a normal distribution curve, and a dynamic adjustment function based on a sample size of the historical control duration.

5. The control method of the system on chip according to claim 4, characterized in that: The determining of the reference duration based on one or more of the historical control duration, the confidence coefficient of the normal distribution curve, and the dynamic adjustment function based on the number of historical control duration samples includes: The reference duration is determined based on the following calculation formula: T F =μ n +Z α ×σ n +T redundancy ×f(n) Among them, T F represents the reference duration, μ n represents the mean of the historical control duration samples, σ n represents the variance of the historical control time sample, Z α Represents the confidence coefficient of the normal distribution curve, T redundancy represents the preset redundancy time, f(n) represents the dynamic adjustment function based on the number of historical control duration samples, and n represents the number of historical control duration samples.

6. The control method of the system on chip according to claim 5, characterized in that: The dynamic adjustment function f(n) based on the number of historical control duration samples is: Among them, N represents the preset threshold, n represents the number of samples of historical control duration, and f max represents the maximum value of the redundancy coefficient, f min represents the minimum value of the redundancy coefficient, k represents the decreasing coefficient, k = (f max -f min ) / (N-1).

7. The method for controlling a system on chip according to claim 1, characterized in that: The determining of the control result according to whether the corresponding response signal is detected within the first time period includes: In response to not detecting a corresponding response signal within a first time period, determining that the control result is a failure; In response to detecting a corresponding response signal within the first time period, it is determined that the control result is successful.

8. The method for controlling a system on chip according to claim 1, characterized in that: The control signal includes a power-on signal, and correspondingly, the historical control duration includes the historical power-on duration; and the associated control action performed based on the control result includes: In response to the control result being a power-on failure, controlling the power of the target system-on-chip to be turned off, and resending a power-on signal to the target system-on-chip after waiting for a preset time; Adjusting the first duration to obtain a new first duration; The control result is determined according to whether the corresponding response signal is detected within the new first time period.

9. The control method of the system on chip according to claim 8, characterized in that: The adjusting the first duration to obtain a new first duration includes: The new first duration is determined based on the following first formula: T timeout =min(T timeout_previous +ΔT,T initial ) Among them, T timeout Indicates the new first duration, T timeout_previous Indicates the first duration of the previous adjacent time, ΔT indicates the set delay value, T initial Indicates the initial timeout period.

10. The method for controlling a system on chip according to claim 8, characterized in that: The sending of a control signal to the target system-on-chip comprises: Send a power-on signal to the power status pin of the target system-on-chip.

11. The method for controlling a system on chip according to claim 8, characterized in that: The determining of the control result according to whether the corresponding response signal is detected within the first time period includes: In response to not detecting a startup completion flag signal within a first time period, determining that the control result is a power-on failure; In response to detecting the startup completion flag signal within the first time period, determining the control result as a power-on success.

12. The method for controlling a system on chip according to claim 8, characterized in that: After sending the control signal to the target system-on-chip and before determining the control result according to whether the corresponding response signal is detected within the first time period, the method further includes: In response to detecting a response signal fed back by the power state pin of the target system-on-chip within a set time period, continuing to perform the operation of determining a control result according to whether a corresponding response signal is detected within a first time period; In response to not detecting a response signal fed back by a power state pin of the target system-on-chip within a set time period, it is determined that power-on failure has occurred.

13. The control method of the system on chip according to claim 8, characterized in that: Also includes: In response to the number of consecutive power-on failures reaching a threshold, a fault alarm is issued.

14. The method for controlling a system on chip according to claim 1, characterized in that: The control signal includes a power-off signal or a system suspend-to-memory signal, and the associated control action is performed based on the control result, including: In response to the control result being a power-off failure or a system suspend to memory failure, the state information of the target system-on-chip at that time is recorded, and the power of the target system-on-chip is forcibly turned off.

15. A control device for a system on chip, characterized in that: include: a sending module, configured to send a control signal to the target system-on-chip in response to detecting that the target system-on-chip satisfies the control condition; A determination module, configured to determine a control result according to whether a corresponding response signal is detected within a first duration, wherein the first duration is determined based on a historical control duration; A control module is used to execute an associated control action based on the control result.

16. An electronic device, characterized in that: The electronic device comprises: one or more processors; A storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the control method of the system on chip according to any one of claims 1 to 14.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the control method of the system on chip according to any one of claims 1 to 14 is implemented.

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