Fixed-point and floating-point hybrid processing circuit

Abstract

The invention provides a fixed-point and floating-point hybrid processing circuit, which comprises a multiplication and addition auxiliary calculation module, a floating-point addition and subtraction shift preprocessing module, a fixed-point multiplication module, a fixed-point addition and subtraction and logical operation module, a lookup table module, a reciprocal interpolation module, an index compensation module, a fine granularity regularization module and a coarse granularity regularization module, the multiplication and addition auxiliary calculation module comprises a * / + ACU1 module for processing index correlation operation and a * / + ACU2 module for processing significant bit correlation operation of source operands, the * / + ACU1 module is connected with the preprocessing module for floating point addition and subtraction shifting, and the * / + ACU2 module is connected with the index compensation module; the coarse granularity regularization module shifts the mantissa of the calculation result into a redundant space according to the significant bit estimation of the index compensation module; wherein the source operand is stored in an MFP data format. According to the invention, hardware resources are multiplexed by configuring the data stream and the module connection mode, so that the consumption of the hardware resources is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuit design, and in particular to a fixed-floating point mixed processing circuit. Background Art

[0002] Neural network reasoning requires enormous computing power. Currently, when neural networks are deployed on end-side devices, fixed-point data is mainly used to perform neural network reasoning. However, fixed-point operations only show good properties in convolution operations, and the implementation of other operators still requires floating-point operations to improve accuracy. Therefore, how to implement a mixed-precision computing framework that can combine the characteristics of large dynamic range of floating-point operations and no need for online quantization, as well as the characteristics of low energy consumption and high speed of fixed-point operations, is a research hotspot in the current industry. Summary of the invention

[0003] The purpose of the present invention is to provide a data structure MFP compatible with fixed-point and floating-point, simplifying common arithmetic operations through redundant carry; and based on the data structure, propose hardware implementation methods of various corresponding operations; and a complete vector processor micro-architecture. The hardware resource overhead and computing energy consumption of the micro-architecture based on MFP proposed by the present invention are superior to the traditional fixed-point and floating-point separation processing architecture design.

[0004] To achieve the above-mentioned object of the invention, the present invention discloses a fixed-point and floating-point mixed processing circuit, comprising:

[0005] Multiplication and addition auxiliary calculation module, floating-point addition and subtraction shift preprocessing module, fixed-point multiplication module, fixed-point addition and subtraction and logic operation module, lookup table module, reciprocal interpolation module, exponential compensation module, fine-grained regularization module and coarse-grained regularization module, among which,

[0006] The multiplication and addition auxiliary calculation module includes an * / +ACU1 module for processing exponential related operations and an * / +ACU2 module for processing effective bit related operations of source operands, the * / +ACU1 module is connected to the floating point addition and subtraction shift preprocessing module, and the * / +ACU2 module is connected to the exponential compensation module;

[0007] The floating-point addition and subtraction shift preprocessing module is connected to the fixed-point addition and subtraction and logic operation module and the lookup table module, and is used to move the mantissa of the operand with the smaller exponent in the addition and subtraction mode so that the exponents of the two source operands are the same;

[0008] The fixed-point multiplication module is connected to the fine-grained regularization module and the coarse-grained regularization module, and is used to perform multiplication operations on source operands;

[0009] The fixed-point addition and subtraction and logic operation module is connected to the fine-grained regularization module and the coarse-grained regularization module, and is used to perform logic operations and fixed-point addition and subtraction;

[0010] The lookup table module is connected to the reciprocal interpolation module to realize the collaborative multiplexing lookup table of positive and negative numbers;

[0011] The reciprocal interpolation module combines the reciprocal values ​​of two adjacent points output by the lookup table and interpolates according to the weights of the input values ​​close to the two points, thereby obtaining the precise value of the reciprocal operation;

[0012] The exponential compensation module is connected to the fine-grained normalization module and the coarse-grained normalization module, and is used to compensate the exponential part of the floating point number;

[0013] The fine-grained normalization module is used to convert floating-point numbers into a specified format;

[0014] The coarse-grained normalization module shifts the mantissa of the calculation result into the redundant space according to the effective bit estimation of the exponential compensation module;

[0015] The source operand is stored in the MFP data format.

[0016] The original intention of the present invention is to reduce hardware resource consumption and power consumption by sacrificing a small amount of calculation accuracy. The present invention finally achieves the purpose of reducing hardware resource consumption by configuring data flow and module connection mode to reuse hardware resources; and reduces power consumption by using the coarse-grained normalization "cg_norm" module to reduce normalization shift operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the structure of a fixed-point and floating-point mixed processing circuit provided in one embodiment of the present invention;

[0018] Figure 2 is a periodic arrangement diagram of a fixed-floating point hybrid processing circuit provided in one embodiment of the present disclosure;

[0019] Figure 3 is a diagram of an MFP data representation format provided in one embodiment of the present disclosure;

[0020] Figure 4 is a circuit diagram of a * / +ACU1 module provided in one embodiment of the present disclosure;

[0021] Figure 5 is a circuit diagram of a * / +ACU2 module provided in one embodiment of the present disclosure;

[0022] Figure 6 is a circuit diagram of a floating-point addition and subtraction shift preprocessing module provided in one embodiment of the present disclosure;

[0023] Figure 7 is a circuit diagram of a fixed-point multiplication module provided in one embodiment of the present disclosure;

[0024] Figure 8 is a circuit diagram of a valid bit detection module provided in one embodiment of the present disclosure;

[0025] Fig. 9 It is a circuit diagram of a fixed-point addition and subtraction and logic operation module provided in one embodiment of the present disclosure;

[0026] Fig.10 is a circuit diagram of a valid digit estimation module specific to addition and subtraction provided in one embodiment of the present disclosure;

[0027] Fig.11 It is a circuit diagram of a significant digit estimation module common to addition, subtraction and multiplication provided in one embodiment of the present disclosure;

[0028] Fig.12 is an additional circuit diagram required for power saving provided in one embodiment of the present disclosure;

[0029] Fig.13 is a lookup table tail number arrangement diagram provided in one embodiment of the present disclosure;

[0030] Fig.14 It is a circuit diagram of an exponential compensation module dedicated to the LUT mode provided in one embodiment of the present disclosure;

[0031] Fig.15 is a coarse-grained regularized direct-through bypass circuit diagram provided in one embodiment of the present disclosure;

[0032] Fig.16 is a circuit diagram of a coarse-grained regularization module provided in one embodiment of the present disclosure;

[0033] Fig.17 is an application diagram of a fixed-floating point mixed processing circuit provided in an embodiment of the present disclosure in a vector processor;

[0034] Fig.18 It is a pipeline diagram of a vector processor provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The following is combined with Figures 1 to 18 The embodiments of the present invention are described in detail. It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Those skilled in the art should know that the following specific embodiments or specific implementations are a series of optimized settings listed by the present invention to further explain the specific content of the invention, and these settings can be combined or used in association with each other, unless the present invention clearly states that some or a specific embodiment or implementation cannot be associated or used together with other embodiments or implementations. At the same time, the following specific embodiments or implementations are only used as the most optimized settings, and are not to be understood as limiting the scope of protection of the present invention.

[0037] See also Figure 1 In one embodiment, the present invention discloses a fixed-floating point mixed processing circuit, including a multiplication and addition auxiliary calculation module, a floating point addition and subtraction shift preprocessing module, a fixed point multiplication module, a fixed point addition and subtraction and logic operation module, a lookup table module, a reciprocal interpolation module, an exponential compensation module, a fine-grained regularization module and a coarse-grained regularization module, characterized in that,

[0038] The multiplication and addition auxiliary calculation module includes an * / +ACU1 module for processing exponential related operations and an * / +ACU2 module for processing effective bit related operations of source operands, the * / +ACU1 module is connected to the floating point addition and subtraction shift preprocessing module, and the * / +ACU2 module is connected to the exponential compensation module;

[0039] The floating-point addition and subtraction shift preprocessing module is connected to the fixed-point addition and subtraction and logic operation module and the lookup table module, and is used to move the mantissa of the operand with the smaller exponent in the addition and subtraction mode so that the exponents of the two source operands are the same;

[0040] The fixed-point multiplication module is connected to the fine-grained regularization module and the coarse-grained regularization module, and is used to perform multiplication operations on source operands;

[0041] The fixed-point addition and subtraction and logic operation module is connected to the fine-grained regularization module and the coarse-grained regularization module, and is used to perform logic operations and fixed-point addition and subtraction;

[0042] The lookup table module is connected to the reciprocal interpolation module to realize the collaborative multiplexing lookup table of positive and negative numbers;

[0043] The reciprocal interpolation module combines the reciprocal values ​​of two adjacent points output by the lookup table and interpolates according to the weights of the input values ​​close to the two points, thereby obtaining the precise value of the reciprocal operation;

[0044] The exponential compensation module is connected to the fine-grained normalization module and the coarse-grained normalization module, and is used to compensate the exponential part of the floating point number;

[0045] The fine-grained normalization module is used to convert floating-point numbers into a specified format;

[0046] The coarse-grained normalization module shifts the mantissa of the calculation result into the redundant space according to the effective bit estimation of the exponential compensation module;

[0047] The source operand is stored in the MFP data format.

[0048] In this embodiment, the cycle arrangement of the fixed-point and floating-point mixed processing circuit is as follows: Figure 2 As shown, the right horizontal axis is the time axis T, which is divided into three cycle clock periods by dotted lines. The modules and operations used in the circuit are arranged on the time axis, as shown in Figure 2 As shown, the horizontal length of a module represents the time required for the module to operate.

[0049] In order to use the above circuit to realize operations of different precisions (such as fixed point, floating point) and different types (such as addition, subtraction, multiplication and division logic operations), we will control the switches of different modules and the combination and connection between modules through configuration parameters and control signals during the operation. In this way, the data flow is guided through different modules to be compatible with various types of operation requirements. Table 1 shows the symbol conventions for the control signals and input and output data flows involved.

[0050] symbol Number of bits Meaning and Description <![CDATA[X1,X2]]> 32 The mantissa bits of the two source operands <![CDATA[E1,E2]]> 8 The exponent bits of the two source operands <![CDATA[X o ]]> 32 Output the mantissa of the result <![CDATA[E o ]]> 8 Output the exponential part of the result fp_en 1 Floating point precision enable (0: fixed point operation; 1: floating point operation) <![CDATA[S + / * ]]> 1 Addition and multiplication control signal (0: addition and subtraction; 1: multiplication) <![CDATA[S + / - ]]> 1 Addition and subtraction control signals (0: addition; 1: subtraction) lut_sel 1 Lookup table control signal (0: other operations; 1: lookup table) lg_crtl 3 Logic selection and control signals

[0051] Table 1

[0052] The first 4 rows in the table are input and output data flows, and the last 5 rows are control flows. If a control flow signal appears in a submodule, its value will directly determine the function and role of the module.

[0053] The decimal part of the MFP format involved in this technical solution includes an 8-bit integer and a 24-bit decimal. The position of the decimal point can be changed to obtain better performance for a specific data set, and the length of the decimal part (such as 16 bits, 24 bits) can be changed to obtain a balance between calculation accuracy and resource consumption. This technical solution is applied to the implementation of arithmetic circuits of very large-scale integrated circuits.

[0054] The fixed-point and floating-point mixed processing circuit also includes a clz high-bit detection module, which is a general module used to detect the most significant bit of the data. Figure 1 The "clz_src" symbol indicates the highest bit of the source operand to be detected.

[0055] In another embodiment, the data in the MFP data format is represented as x={S, I, D; E}, wherein S is a sign bit, I is an integer bit, D is a decimal bit, and E is an exponent bit.

[0056] In this embodiment, the complement operation means: if {S, X} is used to represent a binary signed number x, where S is the sign bit and X is the remaining value bits. The conversion between the original code and the complement code requires the complement operation. The complement operation is expressed in the following form:

[0057]

[0058] Use (X) C Indicates the complement operation of X. If S = 1, the number is negative. When complementing, the numerical part X needs to be bitwise inverted and added by 1. ~X indicates the bitwise inversion operation. If S = 0, X is complemented and the result is still X.

[0059] Therefore, if x = {S, X} is a signed number represented by a fixed-point complement, then its value can be recorded as: x = (-1) S (X) C .

[0060] For standard floating-point data formats such as FP32, 32 bits are used to store a data, including 1-bit sign bit, 8-bit exponent bit and 23-bit mantissa bit. When the floating-point number is a regular number, 1 is added to the front of the highest bit of the mantissa; when the floating-point number is an irregular number, 0 is added to the front of the highest bit of the mantissa to form the decimal part of the floating-point number. All 24 bits of the decimal part are valid bits, which makes full use of every bit of storage space to improve accuracy. However, when calculating with this standard data format, the calculation results need to be normalized multiple times to ensure that the results do not overflow and occupy the full mantissa precision, thereby meeting the standards of regular numbers.

[0061] However, the normalization part of floating-point operations consumes a lot of energy and area, and lengthens the computing pipeline. The standard data format of other related floating-points is the same as FP32. The mantissa needs to be fully valid during calculation, and multiple normalization operations are required. It can be considered that the standard floating-point data format is a data format with high storage density but not conducive to calculation.

[0062] In order to reduce the normalization operation as much as possible, thereby reducing the power consumption and area overhead of the computing unit, this solution proposes a new data expression format, called the MFP format. Its definition and idea is that during calculation, a certain number of additional redundant bits are given to each data, which is called the redundant space of the data. As long as the most significant bit of the data falls within the redundant space, the data is considered to be legal for calculation and can be stored on-chip and participate in subsequent calculations. Only when a calculation result is the final result output or needs to be stored in the memory, it is then normalized and converted into a standard floating-point data format.

[0063] In this way, using the MFP format for calculations can avoid a lot of meaningless normalization operations in the calculation. In addition, this format uses the complement code to represent the mantissa, which is compatible with fixed-point operations.

[0064] MFP format: In this solution, the standard FP32 is improved, and the fixed-point and floating-point data are expressed in a unified data format, such as Figure 3 As shown. The data mantissa is X = {S, I, D}, and the data x can be expressed as x = {S, I, D; E} or x = {X; E}. Among them, the mantissa X is stored uniformly, occupying 32 bits. In the mantissa X, S (sign) is the sign bit, 1 bit occupies the 31st bit; I (integer) is the integer bit, 7 bits occupy [30:24]; D (decimal) is the decimal bit, 24 bits occupy [23:0]. The exponent bit E (expoent) is 8 bits in total and is stored separately.

[0065] The mantissa part X = {S, I, D} is a two's complement representation, which specifies that the decimal point is fixed between 23 and 24. The representation range is: from -2 31-24 to (2 31 -1)·2 -24 , with a precision of 2 -24 The independently stored E is an 8-bit shift code, which needs to be shifted downward by 127 numbers when used, that is, [0, 255] is used to represent [-127, 128], and 127 represents the exponent 0.

[0066] Therefore, the value of data x can be recorded as:

[0067] x=(-1) S (I, D) C 2 E-127-24

[0068] If x is specified as floating-point data, the numerical representation of x is the above formula. If x is specified as fixed-point signed data, the exponent bits are fixed to E = 151. So the representation of the signed integer can be the above formula:

[0069] x=(-1) s (I, D) C

[0070] Its representation range is: [-2 31 , 2 31 -1].

[0071] If x is specified as an unsigned integer, the sign bit is included in the count and the value of x can be expressed as:

[0072] x=(S,I,D)

[0073] Its representation range is: [0, 2 32 -1].

[0074] In another embodiment, the integer bit I is a redundant carry space. As long as the most significant bit of the data falls within the range of the redundant carry space, the data is stored on-chip and participates in subsequent calculations. Only when a calculation result is output as the final result or needs to be stored in the memory, it is normalized.

[0075] In this embodiment, the integer part I is the number of redundant bits compared to the FP32 format, and I or X[30:24] is called the redundant carry space. As long as the most significant bit of the data falls within the range of the redundant space, the data is legal. If it is estimated that the most significant bit of the calculation result still falls within this range, the regularization operation can be directly omitted. When I is equal to 1 or -1, the data is called a fully normalized number.

[0076] In another embodiment, the * / +ACU1 module includes a Max module, a + / - module and a multiplexer mux, wherein the Max module is used to compare the sizes of the two inputs and output the larger term number, the term with the larger exponent and the term with the smaller exponent; the + / - module is an 8-bit adder, used to add or subtract the two inputs and then output; the multiplexer mux selects the reference exponent E b And output.

[0077] In this embodiment, * / +ACU has a special structure, and when the processor performs multiplication, addition and table lookup operations, it will perform different calculations and assume different functions. Figure 1 As shown, * / +ACU will be instantiated into two modules, * / +ACU1 and * / +ACU2, which will be slightly different.

[0078] * / +ACU module mainly processes exponential related operations. According to the design principle of this device, when calculating multiplication, the subsequent modules will use the multiplication base exponent E b =E1+E2. When calculating addition and subtraction, the addition and subtraction base index E b =E max =max{E1, E2}, no exponential addition calculation is required. However, compared with multiplication, the subsequent modules of addition and subtraction will use the absolute value of the exponential difference |E1-E2| to shift the mantissa. In response to the above requirements, a collaborative reuse design of the multiplication and addition auxiliary calculation module is carried out. Its circuit implementation is as follows Figure 4 The inputs are: the exponent bits E1 and E2 of the two 8-bit source operands; the addition and multiplication control signal S + / * The outputs are: the larger index item number max_index; the ACU calculation item ACU_out1; the base index Eb .

[0079] Figure 4 In , the "max" module can compare the size of two inputs and output the larger item number (max_index), the exponentially larger item (E max ), the smaller exponent (E min ). The "+ / -" module is an 8-bit adder that can add or subtract two inputs and then output them. The addition and multiplication control signal S + / * It is used to indicate whether the operation unit is performing addition, subtraction or multiplication. In addition and subtraction mode, S + / * = 0, control "+ / -" to do subtraction, the calculated output is: ACU_out1 = |E1-E2|; in multiplication mode, S + / * =1, control "+ / -" to do addition, and the calculated output is: ACU_out1 = E1 + E2. Note that since the exponent is calculated using shift code, the addition here should meet the shift code operation rules. At the end of the circuit, a multiplexer mux is used to select the reference exponent E b And output.

[0080] In another embodiment, the * / +ACU2 module includes a Max module, a + / - module and a multiplexer mux, and the input of the * / +ACU2 module is the valid bit values ​​C1 and C2 of two 5-bit source operands and the addition and multiplication control signal S + / * ; The output of the * / +ACU2 module is the reference valid bit C and the ACU calculation item ACU_out2.

[0081] In this embodiment, the * / +ACU2 module mainly processes the effective bit related operations of the source operands. In the design of the computing unit of this device, the result effective bit estimation technology is adopted, and it is necessary to perform relevant auxiliary calculations on the effective bits C1 and C2 of the two source operands. The relevant effective bit estimation technology will be introduced in detail in the exponential compensation module (compensation_E). According to the design principle of this device, when calculating multiplication, the subsequent modules will use the value of the multiplication base effective bit C=C1+C2. When calculating addition and subtraction, the addition and subtraction base effective bit C=C max =max{C1, C2}, no significant bit addition calculation is required. However, compared with multiplication, the subsequent modules of addition and subtraction will use the absolute value of the significant bit |C1-C2| for coarse-grained regularization discussion. In response to the above requirements, a collaborative reuse design of the multiplication and addition auxiliary calculation module is carried out. Its circuit implementation is as follows Figure 5 The inputs are: two 5-bit source operands with valid bits C1 and C2, which are generated by the pre-module; the addition and multiplication control signal S + / * The outputs are: reference valid bit C; ACU calculation item ACU_out2.

[0082] and Figure 4 resemblance, Figure 5 In the example, the "max" module can compare the magnitudes of two inputs and output the item with the larger significant digit (C max ), the term with smaller significant digits (C min ). Here, the "+ / -" module is a 5-bit adder that can add or subtract two inputs and then output them. The addition and multiplication control signal S + / * It is used to indicate whether the operation unit is performing addition, subtraction or multiplication. In addition and subtraction mode, S + / * = 0, control "+ / -" to do subtraction, the calculated output is: ACU_out2 = |C1-C2|; in multiplication mode, S + / * =1, control "+ / -" to do addition, and the calculated output is: ACU_out2 = C1 + C2. At the end of the circuit, a multiplexer mux is used to select the reference index C and output it.

[0083] In another embodiment, the floating-point addition and subtraction shift preprocessing module comprises a Shift_r module and a multiplexer mux, wherein the Shift_r module is used to shift the input right by a specified number of bits, and the multiplexer mux selects a certain input signal as output according to a sel selection signal 0 / 1; the input of the floating-point addition and subtraction shift preprocessing module is the mantissa part X1 and X2 of the source operand, the output ACU_out1 of the * / +ACU1 module, the source operand number max_index with a larger exponent, the selection signal lut_sel of the lookup table module; the valid bit C1 of the source operand 1; the output of the floating-point addition and subtraction shift preprocessing module is the preprocessed mantissa X1 of the two source operands 1_s and X 2_s .

[0084] For this embodiment, this module is only in S + / * = 0. It is mainly used to move the mantissa of the operand with the smaller exponent in addition and subtraction mode so that the exponents of the two source operands are the same. In addition, in lut mode (lut_sel = 1), the number to be looked up needs to be shifted and normalized before the table is looked up. Therefore, in lut mode, a little configuration can be made to reuse the module to complete the preprocessing of the number to be looked up. It should be noted that in the control logic of the operation unit, when lut_sel = 1, S must be configured. + / * =0.

[0085] The specific circuit implementation of this module Figure 6As shown. The inputs are: the mantissas of the source operands X1 and X2; the ACU1 calculation term ACU_out1, which must be |E1-E2| here; the source operand number max_index with a larger exponent; the lookup table module selection signal lut_sel; the valid bit C1 of source operand 1. The output is: the preprocessed mantissa X of the two source operands 1_s and X 2_s .

[0086] In addition, the "shift_r" module shifts the input right by a specified number of bits. When lut_sel=0 in non-lut mode, the shift number is |E1-E2|; when lut_sel=1 in lut mode, the shift number is C1[2:0], which will shift the most significant bit of X1 to the 23rd bit;

[0087] Figure 6 The functions implemented by the combination of the three "mux" and "shift_r" in the upper middle part are: select the source operand with the smaller exponent from X1 and X2, and send it to shift_r for shifting. 1_s , X 2_s They correspond to the processing outputs of X1 and X2 respectively. The output mux logic is that if the exponent of the source operand is small, the shifted data is selected for output. If the exponent of the source operand is large, the source operand is directly selected for output.

[0088] In lut mode, use this module to preprocess the data in the lookup table. At this time, the number in the lookup table is used as the first source operand, and its mantissa and exponent are used as X1 and E1 inputs respectively. Configure E2 to the maximum value, lut_sel = 1. In this way, the module will select the mantissa X1 with a smaller exponent data to shift right, and the number of right shifts is selected by lut_sel as C1[2:0]. The most significant bit of X1 will be moved to the 23rd bit. Therefore, the lookup table module can reuse this module to complete the normalization of the number to be looked up. Figure 6 In the figure, "mux" is a multiplexer, which selects a certain input signal as output according to the sel selection signal 0 / 1. Some mux modules in the figure have input 0 / 1 marks. In this article, the unmarked mux modules default to the upper input signal marked as 0 and the lower input signal marked as 1.

[0089] In another embodiment, the fixed-point multiplication module is as follows Figure 7 As shown, the high 16 bits of X1 and X2 are taken and multiplied respectively. 16-bit standard fixed-point multiplier, supporting both signed and unsigned multiplication, the output result is 32 bits. Finally, use the addition and multiplication selection signal S + / - To select the base digit X of the result bThe last mux is the same as the last mux in the "+logic" module. Here we assume that we can directly get the base mantissa X b . Clz_src is a high-bit detection module, such as Figure 8 As shown, it is used to detect the number of effective bits of the two source operands. When the measured number is positive, the number of 0s is detected from the highest bit; when the measured number is negative, the number of 1s is detected from the highest bit. Sat is a data saturation test. When the calculation result exceeds the maximum value, it is assigned the maximum value; when the data result is less than the minimum value, it is assigned the minimum value. fg_norm is a fine-grained normalization module, which is the same as the normalization module of the standard floating point.

[0090] In another embodiment, the fixed-point addition and subtraction and logic operation module includes an integrated logic operation module logic, a fixed-point adder and a multiplexer mux, and the input of the fixed-point addition and subtraction and logic operation module is the pre-processed mantissa X of the two source operands. 1_s and X 2_s And the addition and subtraction control signal S + / - , add and multiply control signal S + / * , and logic control signal lg_crtl; the output of the fixed-point addition and subtraction and logic operation module is the reference mantissa X b .

[0091] In this embodiment, the input of the fixed-point addition and subtraction and logic operation module is: the mantissa of the two processed 32-bit source operands X 1_s and X 2_s ; Addition and subtraction control signal S + / - ; Addition and multiplication control signal S + / * ;Logic control signal lg_crtl. Output: 32-bit mantissa processing result X b The specific circuit implementation of this module Fig. 9 As shown. "logic" is an integrated logic operation unit that can perform logic operations such as "and", "or", "xor", and "shift". "+ / -" is a 32-bit fixed-point adder with a 32-bit output result. Use lg_ctrl to select the output of the logic operation or addition and subtraction. Finally, use the addition and multiplication selection signal S + / * To select the base digit X of the result b The last mux is the same as the last mux in the "*" module. Here we assume that we can directly get the base mantissa X. b .

[0092] In another embodiment, in this design, the lut table lookup module is tightly coupled with the inplt interpolation module, and a special formulation is made for the table lookup function that is an even function or an odd function, which can significantly compress the number of items in the lookup table. In this example, it can be used to perform the reciprocal operation of the inverse proportional function to assist in completing the division operation.

[0093] In another embodiment, the inverse interpolation module (Intplt) combines the inverse values ​​of two adjacent points output by the lookup table and interpolates according to the weights of the input values ​​close to the two points, thereby obtaining the precise value of the inverse operation.

[0094] In another embodiment, the exponential compensation module includes a significant digit estimation module SBE common to addition, subtraction and multiplication, a significant digit estimation module +SBE specific to addition and subtraction, and an exponential compensation module lut_E dedicated to the lut mode.

[0095] In this embodiment, the exponential compensation module is divided into three parts, namely, the significant bit estimation module "SBE" (Significant bit estimation) common to addition, subtraction and multiplication; the significant bit estimation module "+SBE" unique to addition and subtraction; and the exponential compensation module "lut_E" dedicated to the lut mode. Before the floating-point operation, the significant bit estimation technology can be used to make a coarse-grained estimate of the significant bit number of the operation result. In this way, based on the estimation of the significant bit of the result, we can enable the operation unit to compensate for the exponential part of the floating point without completing the decimal operation of the data.

[0096] In this way, the calculation of the decimal part of the data and the compensation of the exponential part can be performed at the same time. In addition, we can choose whether to further perform precise regularization, coarse-grained regularization, or directly skip the regularization step on the calculation result according to the exponential compensation. This can not only reduce the number of pipeline cycles of the computing unit, but also reduce power consumption by conditionally shutting down the regularization module. Fig.10 The control flow required for the coarse-grained regularization of the sub-classification table is generated. Among them, "==1?" and "==0?" indicate whether the input is equal to 1 or 0.

[0097] When judging the coarse-grained normalization, there are many situations that can satisfy multiple coarse-grained normalization options. For example, if the estimated result is definitely 25, no matter whether the mantissa is selected to be straight-through or shifted left by 4 bits, the result will fall within the redundant range and will not go wrong. The above detailed table is designed to increase the straight-through option as much as possible. Adding the straight-through option can directly turn off the subsequent cg_norm module to reduce power consumption. If power consumption is not considered, in order to simplify the circuit, it can be simplified to the following coarse classification table 2.

[0098] C Direct Left 4 Left 8 Right 4 [18：21] 0 0 1 0 [22：25] 0 1 0 0 [26：30] 1 0 0 0 31 0 0 0 1

[0099] Table 2

[0100] The premise of using Table 2 is fg_sel=0. The effective bit estimation circuit designed according to Table 2 is implemented as follows: Fig.11 shown.

[0101] If you need to save power, you need to use Fig.10 The output results and add additional circuitry. Fig.11 Additional circuit design such as Fig.12 This additional power saving design enables the original regularization of c1, c2, c3, C 25 Update c1′, c2′, c3′, c4′ to enable more direct routes to be selected after the update regularization.

[0102] lut_E principle derivation and implementation: The exponent in lut mode also needs to be compensated. The output of the lut module is lut_out, which has 10 bits, the highest bit is the sign bit, and the effective bit is 9 bits. From lut_out to output X o The settings are:

[0103] X o ={(7){S}, lut_out[8:0], (16){0}}

[0104] Arrange the most significant bit of the LUT output at bit 24, such as Fig.13 As shown. The resulting exponent shift changes are: pre-normalization right shift C1[2:0] bits, the most significant bit of the mantissa moves to the 23rd bit. After the table lookup, the mantissa significant bit is reduced by 1 bit, and the most significant bit is the 22nd bit. Now the most significant bit of the result needs to be placed at the 24th bit, and the mantissa is shifted left by 2 bits, so the exponent needs to be reduced by 2 bits.

[0105] Correspondingly, the calculation formula for the index output of the LUT mode is:

[0106] E o =- s (E min +C1[2:0])-2

[0107] =127-(E min +C1[2:0]-127)-2

[0108] =252-E min -C1[2:0]

[0109] In the formula, - s The Lut_E module performs the above calculation result fixedly, which can be realized by using an adder with a fixed offset. The specific circuit implementation of the module is Fig.14shown.

[0110] In another embodiment, the input of the coarse-grained normalization module is the coarse-grained selection signals c1, c2, c3, c4, the reference index E b and the base mantissa X b The output of the coarse-grained normalization module is the index E of the final operation result. o and the last digit X o .

[0111] In this embodiment, the mantissa of the calculation result is shifted to the redundant space according to the effective bit estimation of the pre-module compensation_E. The inputs of the coarse-grained normalization module are: coarse-grained selection signals c1, c2, c3, c4, reference index E b ; Benchmark Index X b The outputs are: the exponent and mantissa E of the final calculation result o and X o .

[0112] like Fig.15 As shown, when the coarse-grained direct selection signal c3 is high, this module is closed and the reference mantissa X b and the benchmark index E b Directly as the final output result.

[0113] cg_norm internally performs a three-choice execution expression, and each execution unit completes the fixed shift of the mantissa and the addition of the fixed value of the exponent. Fig.16 shown.

[0114] In another embodiment, the circuit switches between different operation modes by configuring different control signals.

[0115] In this embodiment, if Figure 2 The fixed-floating point mixed processing circuit shown can be compatible with fixed-floating point addition and subtraction, fixed-floating point multiplication, division, reciprocal, and logical operations. This embodiment introduces a method for collaborative use between modules that are compatible with completing these operations.

[0116] This fixed-point and floating-point mixed processing circuit switches different operation modes by configuring different control signals. There are five control signals in total, and their signal names and explanations are detailed in Table 1. In different operation modes, the values ​​of these signals that need to be configured are shown in Table 3 below.

[0117] Operation Type fp_en <![CDATA[S + / * ]]> <![CDATA[S + / - ]]> lut_sel lg_ctrl Floating point addition 1 0 0 0 000 Floating point subtraction 1 0 1 0 000 Floating-point multiplication 1 1 d 0 d Reciprocal Lookup Table 1 0 d 1 000 fixed point addition 0 0 0 0 000 Fixed-point subtraction 0 0 1 0 000 Fixed-point multiplication 0 1 d 0 d Logical operations 0 0 d 0 001～111

[0118] Table 3

[0119] In Table 3, the signal value d indicates that in this mode, the enable of the module controlled by the signal has been turned off. At this time, the control signal has no control effect and the signal value can be any value. In the logic operation mode, S + / * =0 and lg_ctrl≠0, lg_ctrl can be configured to implement 7 logical operations.

[0120] In different operation modes, each module in the fixed-floating point mixed processing circuit also has different states. The following lists all the sub-modules included in the fixed-floating point mixed processing circuit, and the enable configuration of each sub-module and their open states in different operation modes are shown in Table 4.

[0121] Module Name Each module enables Fixed point + / - Fixed-point multiplication logic Floating point + / - Floating-point multiplication Lookup Table + / *ACU1 fp_en √ √ √ +pre_shift <![CDATA[fp_en&(~S + / * )]]> √ √ +logic <![CDATA[~(S + / * ||lut_sel)]]> √ √ √ clz_src fp_en √ √ √ * <![CDATA[S + / * ]]> √ √ + / *ACU2 fp_en&(~lut_sel) √ √ SEB fp_en&(~lut_sel) √ √ +SEB <![CDATA[fp en &~(s + / * ||lut sel )]]> √ lut_E lut_sel √ lut lutsel √ intplt lutsel √ cg_norm <![CDATA[~(fg_sel||c3)]]> √(？) √(？) fg_norm fg_sel √(？) sat ~(lut_sel||(|lg_ctrl)) √ √ √ √

[0122] Table 4

[0123] The first column in Table 4 shows all submodules involved in the fixed-floating point mixed processing circuit. SAT is generally configured in the write-back phase of the processor. Figure 2 It is not reflected in the schematic diagram of the operation stage. The second column of the table is the enable configuration corresponding to the sub-module. Except for the two normalization modules fg_norm and cg_norm, all enables are only related to the control signal. The remaining columns in the table are the operation modes that the device can execute. In Table 4, the "√" symbol indicates that the module will be used in this mode. The two normalization modules involved in "√(?)" are both placed in the third cycle of the operation. Only when the operation is executed to the second cycle, its enable signal is generated, and only then can it be determined whether it is turned on, so it indicates that its on state is band (?).

[0124] In another embodiment, a fixed-point and floating-point mixed processing circuit is applied in a vector processor.

[0125] The vector coprocessor has the following characteristics: 1. The control flow is implemented in the scalar processor, so the vector processor does not make jump judgments, and all instructions are executed sequentially. 2. The data processing bit width is 16 elements, and the data bit width represented by the instruction is 64 elements, so each instruction requires 4 cycles to complete the calculation, so that every two instructions are separated by 4 clock cycles, which can achieve step-by-step pipeline.

[0126] According to the characteristics of the above-mentioned vector processor, the application of fixed-point and floating-point mixed processing circuits in vector processors is as follows: Fig.17As shown. In the vector processor, the fixed-floating point mixed processing circuit, as the computing unit of the entire processor, can be compatible with fixed-floating point addition, subtraction, multiplication, division, logical operation, inverse table lookup and other operations. After entering the "instruction queue" of the vector processor, the vector instruction waits for wake-up. The "scoreboard" is used to control the wake-up of the vector instructions in the vector queue. If the awakened instruction is a read load or store store instruction, the "read and store vector instruction" module below will configure the corresponding control flow to complete the read or store operation. Among them, when receiving the read instruction load, the "on-chip memory" will pass the specified data to the "vector register file VRF" through the "data format conversion" module. When receiving the store instruction store, the "vector register file VRF" will pass the specified data to the "on-chip memory" through the "data format conversion" module.

[0127] We use Figure 3 The data in the vector "register file" is a special data format shown in FIG. Figure 3 The data format shown is stored. The "on-chip memory" stores data in a universal standard format that can interact with the outside world, so when data is transmitted between the on-chip memory and the vector register file, a "data format conversion" module needs to be added in the middle. If the command to read the register is awakened, the "vector register file" will be directly controlled to send data to the "fixed-point and floating-point mixed processing circuit." This part of the instructions involves the application of this fixed-point and floating-point mixed processing circuit. The data sent is a pair of source operands, and the data includes the mantissas X1 and X2 of the two source operands; the exponents E1 and E2 of the two source operands. The result of the operation is returned as the exponent and mantissa E of the calculation result. o and X o At the same time, the "instruction parsing and parameter configuration" module will configure the parameters required for the "fixed-point and floating-point mixed processing circuit". The parameters to be configured follow the pipeline flow, and the required parameters include: the addition and multiplication control signal S + / * ; Addition and subtraction control signal S + / - ; Lookup table control signal lut_sel; Logic operation control signal lg_ctrl. The data and control signal explanation of the fixed-point and floating-point processing devices are shown in Table 1.

[0128] Vector processor pipeline description: The vector processor contains 16 sets of parallel fixed-point and floating-point mixed processing circuits. The usage of each set of fixed-point and floating-point mixed processing circuits in the vector processor is as follows Fig.17 As shown, only one pair of data can be processed. A vector instruction contains 64 data to be processed, represented by Item[63:0]. Therefore, the device needs to be input 4 times to complete the calculation of a vector instruction. The pipeline design of the vector processor is shown in Fig.18As shown. The vertical axis is the time direction, and the length of each small box in the vertical direction represents a cycle. The same color represents the same instruction. As shown in the figure, enter Item[15:0] in cycle1. Enter Item[31:16] in cycle2. At this time, enter Item[15:0] in cycle1 to enter the second cycle of calculation. In the description of fixed-point and floating-point computing devices, all types of calculations are arranged to be completed within 3 cycles, such as Figure 2 . When applied in a vector processor, a fourth cycle is added as a write-back cycle, so each calculation has to go through a pipeline with a depth of 4 cycles. In cycle 4, the last end of the first instruction Item[63:48] is input, and at the same time, Item[15:0] input in cycle 1 has been calculated and entered the write-back stage. The advantage of designing the pipeline in this way is: if there is a dependency between instructions, such as a dependency between Item0[15:0] and Item1[15:0]. When Item1[15:0] is input, Item0[15:0] has completed the calculation, and the dependency problem has been solved. In other words, even if there is a dependency between the corresponding element positions between instructions, they can still be calculated back to back, reducing bubbles between instructions at runtime and improving the efficiency of calculations.

[0129] In another embodiment, a fixed-point and floating-point mixed processing circuit is used to implement a specific embodiment of multiple operations. The following calculation steps are all based on Fig.17 For reference, the step definition rules are as follows: the first two bits in S100 indicate that Step 1 is the first step; the last two bits 00 indicate the specific operations in the current step, and these operations can be executed in parallel if they have no dependencies.

[0130] First, use the fixed-point and floating-point mixed processing circuit to implement floating-point addition and subtraction operations. The steps are as follows:

[0131] S100: Instruction parsing and preparation stage. Read source operands and configure control signals. The configuration method of control signals is shown in Table 3. The input of control signals will not be mentioned again in subsequent steps.

[0132] S200: Cycle1 stage. At the beginning of cycle1, modules "+ / *ACU1" and "clz_src" start working. In the middle of cycle1, modules "+ / *ACU1" and "clz_src" complete the calculation. Modules "+pre_shift" and "+ / *ACU2" start working. At the end of cycle1, modules "+pre_shift" and "+ / *ACU2" complete the calculation.

[0133] S201: At the beginning of cycle 1, indexes E1 and E2 are input into the "+ / *ACU1" module. Half a cycle later, in the middle of cycle 1, the output max_index, E b , ACU_out1.

[0134] S202: At the beginning of cycle 1, the mantissas X1 and X2 are input into the "clz_src" module. Half a cycle later, in the middle of cycle 1, the outputs C1 and C2 are obtained.

[0135] S203: In the middle of cycle1, the mantissa X1, X2, S201 result max_index, ACU_out1, and S202 result C1 are input into the "+pre_shift" module. Half a cycle later, at the end of cycle1, the output X is obtained. 1_s , X 2_s .

[0136] S204: In the middle of cycle1, the results C1 and C2 of S202 are input into the "+ / *ACU2" module. When cycle1 ends half a cycle later, the output C and ACU_out2 are obtained.

[0137] S300: Cycle2 stage. At the beginning of cycle2, modules "+logic", "SEB" and "+SEB" start working. In the middle of cycle2, module "SEB" completes calculation. At the end of cycle2, modules "+logic" and "+SEB" complete calculation.

[0138] S301: At the beginning of cycle 2, the result C of S204 is input into module "SEB". In the middle of cycle 2, outputs c1, c2, c3, c4 are obtained.

[0139] S302: When cycle 2 starts, S203 result X 1_s , X 2_s Input module "+logic". At the end of cycle 2, the output is X b .

[0140] S303: At the beginning of cycle2, the sign bits S1, S2, and S204 result ACU_out2 are input to the module "+SEB". In the middle of cycle2, the output fg_sel, c, a is obtained. If the power saving circuit design is realized, in the middle of cycle2, the results c1, c2, c3, c4 of S301 are input to the "+SEB" module additional circuit ( Fig.12 Circuit), at the end of cycle2, the modified coarse-grained selection outputs c1′, c2′, c3′, c4′ are obtained.

[0141] S400: cycle3 stage. Use the results of S303 fg_sel, c3 (c3′) to calculate the enable signals of modules “fg_norm” and “cg_norm” in Table 4. If fg_en=1, execute S401; if cg_en=1, execute S402; otherwise, skip cycle3 stage and directly output the result of S302 X b and S201 Result E b The final result is X o , E o .

[0142] S401: Perform standard fine-grained regularization operations. At the beginning of cycle 3, the result of S301 is X b and S201 Result E b Enter the "fg_norm" module. At the end of cycle 3, the final result X is obtained. o , E o .

[0143] S402: Execute the coarse-grained normalization operation. At the beginning of cycle 3, the S303 result c1, c2, c3, c4 or its modified result (c1′, c2′, c3′, c4′), S301 result X b 、S201 Result E b Input the "cg_norm" module. At the end of cycle 3, the final result X is obtained. o , E o .

[0144] S500: Final Result X o , E o Do sat saturation check and write back.

[0145] Second, use the fixed-floating point mixed processing circuit to implement floating-point multiplication operations. The steps are as follows:

[0146] S100: Instruction parsing and preparation stage. Read source operands and configure control signals. The configuration method of control signals is shown in Table 3. The input of control signals will not be mentioned again in subsequent steps.

[0147] S200: Cycle1 stage. At the beginning of cycle1, modules "+ / *ACU1", "*" and "clz_src" start working. In the middle of cycle1, modules "+ / *ACU1" and "clZ_src" complete the calculation. Module "+ / *ACU2" starts working. At the end of cycle1, module "+ / *ACU2" completes the calculation. At the end of cycle2, module "*" completes the calculation.

[0148] S201: At the beginning of cycle 1, indexes E1 and E2 are input into the "+ / *ACU1" module. Half a cycle later, in the middle of cycle 1, output E is obtained. b .

[0149] S202: At the beginning of cycle 1, the mantissas X1 and X2 are input into the "clz_src" module. Half a cycle later, in the middle of cycle 1, the outputs C1 and C2 are obtained.

[0150] S203: At the beginning of cycle 1, the mantissas X1 and X2 are input into the “*” module. Two cycles later, at the end of cycle 2, the output X is obtained. b .

[0151] S204: In the middle of cycle1, the results C1 and C2 of S202 are input into the "+ / *ACU2" module. When cycle1 ends half a cycle later, the output C is obtained.

[0152] S300: Cycle 2 stage. At the beginning of cycle 2, the result C of S204 is input into module "SEB". In the middle of cycle 2, "SEB" completes the calculation and obtains outputs c1, c2, c3, c4.

[0153] S400: Cycle 3 stage. Determine the enable signal of module "cg_norm" according to S300 result c3 and Table 4. If cg_en=1, execute S401; otherwise, skip cycle 3 stage and directly output S203 result X b and S201 Result E b The final result is X o , E o .

[0154] S401: Execute the coarse-grained normalization operation. At the beginning of cycle 3, the results of S301 are c1, c2, c3, c4, and the results of S203 are X b 、S201 Result E b Input the "cg_norm" module. At the end of cycle 3, the final result X is obtained. o , E o .

[0155] S500: Final Result X o , E o Do sat saturation check and write back.

[0156] Third, use the fixed-floating point mixed processing circuit to implement the reciprocal lookup table. The steps are as follows:

[0157] S100: Instruction parsing and preparation stage. Configure the table number to be searched as operand 1, and configure the index of operand 2 as E2 = {(8){1′b1}} maximum value. The configuration method of the control signal is shown in Table 3. The input of the control signal will not be mentioned again in the following steps.

[0158] S200: Cycle1 stage. At the beginning of cycle1, modules "+ / *ACU1" and "clz_src" start working. In the middle of cycle1, modules "+ / *ACU1" and "clz_src" complete the calculation. Module "+pre_shift" starts working. At the end of cycle1, module "+pre_shift" completes the calculation.

[0159] S201: At the beginning of cycle 1, indexes E1 and E2 are input into the "+ / *ACU1" module. Half a cycle later, in the middle of cycle 1, outputs max_index and ACU_out1 are obtained.

[0160] S202: At the beginning of cycle 1, the mantissa X1 is input into the "clz_src" module. Half a cycle later, in the middle of cycle 1, the output C1 is obtained.

[0161] S203: In the middle of cycle1, the mantissa X1, S201 result max_index, ACU_out1, and S202 result C1 are input into the "+pre_shift" module. At the end of cycle1 after half a cycle, the output X is obtained. 1_s .

[0162] S300: Cycle2 stage. At the beginning of cycle2, modules "LUT" and "lut_E" start working. At the end of cycle2, modules "LUT" and "lut_E" complete the calculation.

[0163] S301: At the beginning of cycle 2, index E1 is input into module "lut_E". At the end of cycle 2, the final index result E is obtained. o .

[0164] S302: At the beginning of cycle 2, the sign bit is S1, and the result of S203 is X 1_s [23:16] Input module "LUT". At the end of cycle 2, outputs A and B are obtained.

[0165] S400: Cycle 3 stage. At the beginning of cycle 3, the sign bit S1 and S203 result X 1_s[15:14], S303 results A and B are input into module "intplt". When cycle 3 ends, output LUT_out is obtained.

[0166] S500: Write back stage, S400 result LUT_out according to Fig.13 The final result is X. o , and S301 result E o are output together as the final result.

[0167] Fourth, use fixed-point and floating-point mixed processing circuits to implement division and other operations. Division needs to be split into two instructions: first, find the reciprocal of the divisor, and then find the floating-point multiplication of the reciprocal result and the dividend. The steps are as follows:

[0168] S100: using a fixed-point and floating-point mixed processing circuit to calculate the reciprocal of the divisor, using the third step method to calculate the reciprocal.

[0169] S200: using a fixed-floating point mixed processing circuit to calculate the floating-point multiplication of the reciprocal of the divisor and the dividend, and the floating-point multiplication is calculated using the second step method.

[0170] For other operations, such as fixed-point + / -, logical operations, etc., you only need to enable the corresponding arithmetic module and will not be expanded in detail.

[0171] Although the embodiments of the present invention are described above in conjunction with the accompanying drawings, the present invention is not limited to the above specific embodiments and application fields, and the above specific embodiments are only illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present invention, all of which belong to the protection of the present invention.

Claims

1. A fixed-point and floating-point mixed processing circuit, comprising: Multiplication and addition auxiliary calculation module, floating-point addition and subtraction shift preprocessing module, fixed-point multiplication module, fixed-point addition and subtraction and logic operation module, lookup table module, reciprocal interpolation module, exponential compensation module, fine-grained regularization module and coarse-grained regularization module, among which, The multiplication and addition auxiliary calculation module includes an * / +ACU1 module for processing exponential related operations and an * / +ACU2 module for processing effective bit related operations of source operands, the * / +ACU1 module is connected to the floating point addition and subtraction shift preprocessing module, and the * / +ACU2 module is connected to the exponential compensation module; The floating-point addition and subtraction shift preprocessing module is connected to the fixed-point addition and subtraction and logic operation module and the lookup table module, and is used to move the mantissa of the operand with the smaller exponent in the addition and subtraction mode so that the exponents of the two source operands are the same; The fixed-point multiplication module is connected to the fine-grained regularization module and the coarse-grained regularization module, and is used to perform multiplication operations on source operands; The fixed-point addition and subtraction and logic operation module is connected to the fine-grained regularization module and the coarse-grained regularization module, and is used to perform logic operations and fixed-point addition and subtraction; The lookup table module is connected to the reciprocal interpolation module to realize the collaborative multiplexing lookup table of positive and negative numbers; The reciprocal interpolation module combines the reciprocal values ​​of two adjacent points output by the lookup table and interpolates according to the weights of the input values ​​close to the two points, thereby obtaining the precise value of the reciprocal operation; The exponential compensation module is connected to the fine-grained normalization module and the coarse-grained normalization module, and is used to compensate the exponential part of the floating point number; The fine-grained normalization module is used to convert floating-point numbers into a specified format; The coarse-grained normalization module shifts the mantissa of the calculation result into the redundant space according to the effective bit estimation of the exponential compensation module; The source operand is stored in the MFP data format.

2. The circuit according to claim 1, wherein Preferably, the data in the MFP data format is represented as ,in, is the sign bit, is an integer, is the decimal place, is the exponent bit.

3. The circuit according to claim 2, wherein: The integer digit It is a redundant carry space. As long as the most significant bit of the data falls within the range of the redundant carry space, the data will be stored on-chip and participate in subsequent calculations. Only when a calculation result is the final output or needs to be stored in the memory, it will be normalized.

4. The circuit according to claim 1, wherein: The * / +ACU1 module includes a Max module, a + / - module and a multiplexer mux, wherein the Max module is used to compare the sizes of the two inputs and output the larger term number, the term with the larger exponent and the term with the smaller exponent; the + / - module is an 8-bit adder, used to add or subtract the two inputs and then output; the multiplexer mux selects the reference exponent. And output.

5. The circuit according to claim 1, wherein: The * / +ACU2 module includes a Max module, a + / - module and a multiplexer mux. The input of the * / +ACU2 module is the valid bit value of two 5-bit source operands. and , and the addition and multiplication control signals ; The output of the * / +ACU2 module is the reference valid bit And the ACU calculation item ACU_out2.

6. The circuit according to claim 1, wherein: The floating point addition and subtraction shift preprocessing module includes a Shift_r module and a multiplexer mux. The Shift_r module is used to shift the input right by a specified number of bits. The multiplexer mux is used to shift the input right by a specified number of bits. The selection signal 0 / 1 selects a certain input signal as output; the input of the floating point addition and subtraction shift preprocessing module is the mantissa part of the source operand and , the output ACU_out1 of the * / +ACU1 module has the source operand number with the larger exponent , the selection signal of the lookup table module ; The effective bit of source operand 1 The output of the floating point addition and subtraction shift preprocessing module is the preprocessed mantissa of the two source operands. and .

7. The circuit according to claim 1, wherein: The fixed-point addition and subtraction and logic operation module includes an integrated logic operation module logic, a fixed-point adder and a multiplexer mux. The input of the fixed-point addition and subtraction and logic operation module is the pre-processed mantissa of the two source operands. and And plus or minus control signals , addition and multiplication control signal , and logic control signals The output of the fixed-point addition and subtraction and logic operation module is the reference mantissa .

8. The circuit according to claim 1, wherein the exponential compensation module comprises an effective digit estimation module SBE common to addition, subtraction and multiplication, an effective digit estimation module +SBE specific to addition and subtraction, and an exponential compensation module lut_E dedicated to the lut mode.

9. The circuit according to claim 1, wherein: The input of the coarse-grained regularization module is the coarse-grained selection signal , benchmark index and the base mantissa The output of the coarse-grained normalization module is the index of the final operation result. and tail number .

10. The circuit of claim 1, wherein: The circuit switches between different operation modes by configuring different control signals.

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