Programmable logic gate array apparatus, control method thereof, and storage medium

Abstract

The invention discloses a programmable logic gate array device, a control method thereof and a storage medium, in the programmable logic gate array device, each read-write cache module is connected with a corresponding data reading channel or data writing channel; the single multiplexing arbitration module is used for performing data interaction with the at least two read-write cache modules so as to cache data corresponding to the at least two read-write cache modules, and the first bit width is smaller than the second bit width; the bit width of the multiplexing arbitration module is the same as that of the read-write state control module, and the read-write state control module is used for performing data interaction with the at least two multiplexing arbitration modules respectively; the bit width of the read-write state control module is the same as that of the memory device control module, the read-write state control module is used for performing data interaction with the memory device control module, and the number of resource blocks needing to be consumed when the programmable logic gate array device performs data interaction with the memory device can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of data interaction, a programmable logic gate array device, a control method thereof and a storage medium. Background Art

[0002] In the prior art, data interaction can be achieved by writing or reading data to a connected storage device (such as DDR3 SDRAM) through a programmable logic gate array device (such as FPGA, Field Programmable Gate Array).

[0003] The defect of the prior art is that when the programmable logic gate array device reads and writes the storage device through the corresponding FIFO (First Input First Output) cache module, the read-write state control module (such as the read-write state controller), and the storage device control module (such as the DDR3 controller), the bit width of the FIFO cache module needs to be equal to the bit width of the corresponding storage device, and each data read and write channel needs to be configured with a corresponding FIFO cache module, so that the programmable logic gate array device needs to consume a large number of resource blocks when exchanging data with the storage device. Summary of the invention

[0004] The main technical problem solved by the present application is how to reduce the number of resource blocks consumed when a programmable logic gate array device interacts with a storage device for data.

[0005] In order to solve the above technical problems, the first technical solution adopted in the present application is: a programmable logic gate array device, including: multiple read-write cache modules, each read-write cache module is connected to a corresponding data reading channel or a data writing channel, and the bit width of the read-write cache module is a first bit width; at least one multiplexing arbitration module, a single multiplexing arbitration module is used to interact with at least two read-write cache modules to cache data corresponding to at least two read-write cache modules, the bit width of the multiplexing arbitration module is a second bit width, and the first bit width is smaller than the second bit width; a read-write state control module, the bit width of the multiplexing arbitration module is the same as the bit width of the read-write state control module, and the read-write state control module is used to interact with at least two multiplexing arbitration modules respectively; a storage device control module, the bit width of the read-write state control module is the same as the bit width of the storage device control module, and the read-write state control module is used to interact with the storage device control module.

[0006] Among them, the multiple read-write cache modules include multiple read cache modules and multiple write cache modules, and the write arbitration module is a multiplexing arbitration module whose connected read-write cache modules are all write cache modules; the write arbitration module is used to: poll all corresponding write cache modules to store the data sent by each write cache module into the corresponding cache area of ​​the write arbitration module respectively; write the data stored in the cache area into the storage device through the read-write status control module and the storage device control module.

[0007] Among them, the read arbitration module is a multiplexing arbitration module whose connected read and write cache modules are all read cache modules; the read arbitration module is used to: poll all corresponding read cache modules, so as to store the data to be read by each read cache module into the corresponding cache area in the read arbitration module through the read-write status control module and the storage device control module; and output the data stored in the cache area from the corresponding data read channel through the corresponding read cache module.

[0008] Wherein, the first cache area is any cache area among all cache areas of the target write arbitration module; the data stored in the cache area is written into the storage device through the read-write status control module and the storage device control module, including: in response to the cached amount in the first cache area being not less than a preset ratio of the maximum cache amount of the first cache area, the data in the first cache area is written into the storage device through the read-write status control module and the storage device control module.

[0009] Among them, the second cache area is any cache area among all the cache areas of the target read arbitration module; the data stored in the cache area is output from the corresponding data read channel through the corresponding read cache module, including: in response to the cached amount in the second cache area being not less than a preset ratio of the maximum cache amount of the second cache area, the data stored in the second cache area is output from the corresponding data read channel through the corresponding read cache module.

[0010] Among them, the preset ratio is 50%.

[0011] The read / write status control module is used to poll all multiplexing arbitration modules to write the data to be written by each multiplexing arbitration module into the storage device through the storage device control module, or to obtain the data to be read by each multiplexing arbitration module from the storage device through the storage device control module.

[0012] In order to solve the above technical problems, the second technical solution adopted in the present application is: a control method of a programmable logic gate array device, applied to the programmable logic gate array device, the programmable logic gate array device includes multiple read-write cache modules, at least one multiplexing arbitration module, a read-write state control module and a storage device control module; each read-write cache module is connected to a corresponding data reading channel or a data writing channel, and the bit width of the read-write cache module is the first bit width; the bit width of the multiplexing arbitration module is the same as the bit width of the read-write state control module; the bit width of the read-write state control module is the same as the bit width of the storage device control module; the control method includes: controlling the multiplexing arbitration module to exchange data with at least two read-write cache modules to cache data corresponding to the at least two read-write cache modules, the bit width of the multiplexing arbitration module is the second bit width, and the first bit width is smaller than the second bit width; controlling the read-write state control module to exchange data with at least two multiplexing arbitration modules respectively, and the read-write state control module is used to exchange data with the storage device control module; controlling the storage device control module to write data to or read data from the storage device.

[0013] In order to solve the above technical problems, the third technical solution adopted in this application is: a programmable logic gate array device, including: a memory and a processor; the memory is used to store program instructions, and the processor is used to execute program instructions to implement the above method.

[0014] In order to solve the above technical problems, the fourth technical solution adopted in the present application is: a computer-readable storage medium, which stores program instructions, and the above method is implemented when the program instructions are executed by a processor.

[0015] The beneficial effect of the present application is that, different from the prior art, in the technical solution of the present application, at least one multiplexing arbitration module having a bit width equal to the bit width of the read-write state control module and the bit width of the storage device control module is provided, and each multiplexing arbitration module can perform data interaction on at least two data read / write channels having a bit width smaller than the bit width of the multiplexing arbitration module, so that the number of modules for data interaction directly connected to the read-write state control module is less than the number of all data read / write channels, and the bit width of the read-write cache module can be smaller than the bit width of the storage device or the read-write state control module. Therefore, based on the above method, by constructing a multiplexing arbitration module to cooperate with the read-write cache module and the read-write state control module to read data from the storage device, the number of resource blocks required to be consumed by all the constructed modules when the programmable logic gate array device and the storage device perform data interaction can be reduced, that is, the number of resource blocks required to be consumed when the programmable logic gate array device and the storage device perform data interaction is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a structural schematic diagram of an embodiment of the programmable logic gate array device of the present application;

[0018] Figure 2 It is a flowchart of an embodiment of a control method of a programmable logic gate array device of the present application;

[0019] Figure 3 It is a structural schematic diagram of an embodiment of the programmable logic gate array device of the present application;

[0020] Figure 4 It is a structural diagram of an embodiment of the computer-readable storage medium of the present application. DETAILED DESCRIPTION

[0021] The present application is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application, but are not intended to limit the scope of the present application. Similarly, the following examples are only some embodiments of the present application rather than all embodiments, and all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0022] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] In the description of this application, it is necessary to explain that, unless otherwise clearly specified and limited, the terms "install", "set", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or connected through an intermediate medium. For ordinary technicians in this field, the above-mentioned specific meanings belonging to this application can be connected according to specific circumstances.

[0024] The present application proposes a programmable logic gate array device, see Figure 1 , Figure 1is a schematic diagram of the structure of an embodiment of the programmable logic gate array device of the present application, such as Figure 1 As shown, the programmable logic gate array device includes a plurality of read-write cache modules 11 , at least one multiplexing arbitration module 12 , a read-write state control module 13 and a storage device control module 14 .

[0025] Among them, the storage device control module 14 can be connected to the corresponding storage device 15, and the storage device 15 can be specifically used to write and read video stream data. The data transmitted at a single time by each read-write cache module 11 can be the data of a pixel in a frame in a video file. The storage device 15 can also be used to write and read other types of files, which is not limited here.

[0026] The storage device 15 may specifically be a DDR3 SDRAM (Synchronous Dynamic Random Access Memory), or may be other devices with storage functions, which are not limited here.

[0027] Each read-write cache module 11 is connected to a corresponding data reading channel or a data writing channel, and the bit width of the read-write cache module 11 is the first bit width.

[0028] Among them, the read-write cache module 11 can be a FIFO (First Input First Output) cache module, and the data transmission channel connected to each read-write cache module 11 can be a data reading channel or a data writing channel, that is, the read-write cache module 11 can be used to write data into the storage device 15, and can also be used to read data from the storage device 15 to output from the corresponding data transmission channel.

[0029] When the data stored in the storage device 15 is video stream data, the bit width of the read-write cache module 11 can be the data length of one pixel in a frame of the video stream data, that is, the read-write cache module 11 can transmit one pixel of data each time. For example, the first bit width of the read-write cache module 11 can be 32 bits, and the data length of one pixel in a frame of the video stream data is 32 bits.

[0030] Under the premise that other conditions are the same, the smaller the bit width of a single read-write cache module 11 is, the fewer the number of resource blocks of the programmable logic gate array device occupied by all the read-write cache modules 11 is.

[0031] A plurality of devices with storage functions can be spliced ​​together to form a storage device 15 having a bit width greater than that of a single device with storage function, so that the bit width of the storage device 15 is greater than the bit width of a single read-write cache module 11, thereby enabling a single multiplexing arbitration module 12 to simultaneously connect to at least two read-write cache modules 11.

[0032] A single multiplexing arbitration module 12 is used to exchange data with at least two read-write cache modules 11 to cache data corresponding to the at least two read-write cache modules 11. The bit width of the multiplexing arbitration module 12 is the second bit width, and the first bit width is smaller than the second bit width.

[0033] Among them, the multiplexing arbitration module 12 can be specifically used to poll all the read-write cache modules 11 connected to it, and ask each read-write cache module 11 connected to it in turn whether it has received a corresponding read data request or write data request, and when receiving the corresponding request, read or write data through the corresponding read-write cache module 11 and the data reading channel or data writing channel.

[0034] The second bit width of a single multiplexing arbitration module 12 is greater than the first bit width of a single read-write cache module 11, and the second bit width can be more than twice the first bit width, so that the single multiplexing arbitration module 12 can multiplex at least two read-write cache modules 11, that is, perform the above-mentioned polling processing, so that multiple read-write cache modules 11 with lower bit widths can write or read data to the storage device 15 through the single multiplexing arbitration module 12 with higher bit width, so that the bit width of each read-write cache module 11 does not need to be equal to the bit width of the storage device 15.

[0035] When the first bit width of the read / write cache module 11 can be 32 bits, the second bit width of the multiplexing arbitration module 12 can be 512 bits, and the number of read / write cache modules 11 connected to a single multiplexing arbitration module 12 can be 2, 5, 6 or other numbers, which is not limited here.

[0036] The bit width of the multiplexing arbitration module 12 is the same as the bit width of the read / write state control module 13 . The read / write state control module 13 is used to perform data exchange with at least two multiplexing arbitration modules 12 .

[0037] The bit width of each input / output terminal of the read / write state control module 13 is respectively equal to that of the storage device 15 , or respectively equal to that of the multiplexing arbitration module 12 , and specifically may be 512 bits.

[0038] The storage device control module 14 , the bit width of the read / write state control module 13 is the same as the bit width of the storage device control module 14 , and the read / write state control module 13 is used to perform data exchange with the storage device control module 14 .

[0039] The bit width of the storage device control module 14 is equal to that of the storage device 15 , and may be 512 bits.

[0040] For example, when the storage device 15 is a device based on multiple DDR3 SDRAM chips, the conventional programmable logic gate array device without the multiplexing arbitration module 12 has the following calculation formula for the amount of resources consumed when performing the above data interaction:

[0041] X={[[(bandwidth of the read / write cache module 11*the number of all read / write cache modules 11) / bandwidth of a single-chip DDR3 SDRAM]*bit width of a single-chip DDR3 SDRAM x8] / bit width of the read / write cache module 11}*the number of all read / write cache modules 11.

[0042] X is a programmable logic gate array device in a traditional solution that is not provided with a multiplexing arbitration module 12. The amount of resources that need to be consumed when performing the above data interaction, and the bandwidth is the bit width multiplied by the operating frequency of the corresponding device.

[0043] The programmable logic gate array device provided with the multiplexing arbitration module 12 proposed in the present application solution calculates the amount of resources consumed when performing the above data interaction as follows:

[0044] Y={[[(bandwidth of read-write cache module 11*number of all read-write cache modules 11) / bandwidth of single-chip DDR3 SDRAM]*bit width of single-chip DDR3 SDRAM x 8] / bit width of read-write cache module 11}*(number of all read-write cache modules 11 / number of read-write cache modules 11 connected to a single multiplexing arbitration module 12)+bit width of read-write cache module 11*number of all read-write cache modules 11.

[0045] Y is the amount of resources that the programmable logic gate array device provided with the multiplexing arbitration module 12 proposed in the present application needs to consume when performing the above-mentioned data interaction, and the bandwidth is the bit width multiplied by the operating frequency of the corresponding device.

[0046] Assume that all read-write cache modules 11 include 10 read-write cache modules 11 for data writing and 10 read-write cache modules 11 for data reading, the bit width of the storage device 15 is 512 bits, and the bit width of the read-write cache module 11 is 32 bits, then:

[0047] When the number of read-write cache modules 11 connected to a single multiplexing arbitration module 12 is 2, the number of resource blocks consumed by the programmable logic gate array device in the present application is 120, which is 40 less than that of the programmable logic gate array device in the traditional solution, and the resource saving efficiency is about 25%.

[0048] When the number of read-write cache modules 11 connected to a single multiplexing arbitration module 12 is 3, the number of resource blocks consumed by the programmable logic gate array device in the present application is 96, which is 64 less than that of the programmable logic gate array device in the traditional solution, and the resource saving efficiency is about 40%.

[0049] When the number of read-write cache modules 11 connected to a single multiplexing arbitration module 12 is 4, the number of resource blocks consumed by the programmable logic gate array device in the present application is 88, which is 72 less than that of the programmable logic gate array device in the traditional solution, and the resource saving efficiency is about 45%.

[0050] When the number of read-write cache modules 11 connected to a single multiplexing arbitration module 12 is 5, the number of resource blocks consumed by the programmable logic gate array device in the present application is 80, which is 80 less than that of the programmable logic gate array device in the traditional solution, and the resource saving efficiency is about 50%.

[0051] When the number of read-write cache modules 11 connected to a single multiplexing arbitration module 12 is 6, the number of resource blocks consumed by the programmable logic gate array device in the present application is 80, which is 80 less than that of the programmable logic gate array device in the traditional solution, and the resource saving efficiency is about 50%.

[0052] When the number of read-write cache modules 11 connected to a single multiplexing arbitration module 12 is 7, the number of resource blocks consumed by the programmable logic gate array device in the present application is 64, which is 96 less than that of the programmable logic gate array device in the traditional solution, and the resource saving efficiency is about 60%.

[0053] It can be seen from the above that, based on the configuration of the multiplexing arbitration module 12 , compared with the programmable logic gate array device in the traditional solution, the number of resource blocks required to be consumed during data interaction of the storage device 15 can be effectively reduced.

[0054] Different from the prior art, in the technical solution of the present application, at least one multiplexing arbitration module having a bit width equal to the bit width of the read-write state control module and the bit width of the storage device control module is provided. Each multiplexing arbitration module can perform data interaction on at least two data read / write channels having a bit width smaller than the bit width of the multiplexing arbitration module, so that the number of modules for data interaction directly connected to the read-write state control module is less than the number of all data read / write channels, and the bit width of the read-write cache module can be smaller than the bit width of the storage device or the read-write state control module. Therefore, based on the above method, by constructing a multiplexing arbitration module to cooperate with the read-write cache module and the read-write state control module to read data from the storage device, the number of resource blocks required to be consumed by all the constructed modules when the programmable logic gate array device interacts with the storage device can be reduced, that is, the number of resource blocks required to be consumed when the programmable logic gate array device interacts with the storage device is reduced.

[0055] In one embodiment, the multiple read-write cache modules 11 include multiple read cache modules and multiple write cache modules, and the write arbitration module is a multiplexing arbitration module 12 whose connected read-write cache modules 11 are all write cache modules.

[0056] Write arbitration module for:

[0057] Polling is performed on all corresponding write cache modules to store the data sent by each write cache module into the corresponding cache area of ​​the write arbitration module.

[0058] The data stored in the cache area is written into the storage device 15 through the read-write state control module 13 and the storage device control module 14 .

[0059] Specifically, Figure 1 As shown, all read-write cache modules 11 connected to the write arbitration module A are write cache modules, that is, all read-write cache modules 11 connected to the write arbitration module A are used to receive data and write the data into the storage device 15 through the corresponding module.

[0060] The total cache area of ​​the write arbitration module A can be divided into cache areas corresponding to the connected read-write cache modules 11. When the write arbitration module A polls each read-write cache module 11, it writes the data received by each read-write cache module 11 into its corresponding cache area in turn.

[0061] For example, the bit width of the write arbitration module A is 512 bits. If the number of read-write cache modules 11 connected to the write arbitration module A is 4, a 512-bit register can be defined in the write arbitration module A, and the storage space (i.e., cache area) of the register can be divided into 4 parts, corresponding to different read-write cache modules 11. After the storage spaces corresponding to each read-write cache module 11 are respectively stored with corresponding data, the data obtained by the write arbitration module A can be written into the storage device 15 through the corresponding module. By making different storage spaces correspond to different read-write cache modules 11 connected to the write arbitration module A, the synchronization of the four read-write cache modules 11 can be improved, and the possibility of data mixing and confusion between different read-write cache modules 11 can be reduced.

[0062] Based on the above method, the accuracy of writing data into the programmable logic gate array device can be effectively improved.

[0063] Optionally, the first cache area is any cache area among all cache areas of the target write arbitration module.

[0064] Writing the data stored in the cache area into the storage device 15 through the read-write state control module 13 and the storage device control module 14 includes:

[0065] In response to the cached amount in the first cache area being not less than a preset ratio of the maximum cache amount in the first cache area, the data in the first cache area is written into the storage device 15 through the read / write state control module 13 and the storage device control module 14 .

[0066] Specifically, the preset ratio may be greater than 0% and less than 100%.

[0067] By setting the preset ratio, the data in the cache area can be written accordingly while ensuring that the cache area is not fully filled, thereby avoiding data loss due to the cache area being filled up, thereby improving the reliability of the programmable logic gate array device.

[0068] For example, the target write arbitration module can cyclically detect whether there is a write request for each read-write cache module 11 connected to it. If there is a write request, the loop is stopped and the corresponding data is written to the corresponding cache area in the target write arbitration module through the corresponding read-write cache module 11. If there is no write request, after waiting for a preset period of time or when the corresponding cache area is filled, the detection continues in a cyclic manner to determine whether the next read-write cache module 11 has the above-mentioned write request.

[0069] It should be noted that after the data in the cache area has been written into the storage device 15, the written data in the cache area can be regarded as no longer existing, that is, the space occupied by the written data in the cache area is regarded as free space, which can be overwritten by new data to be written.

[0070] Optionally, the read arbitration module is a multiplexing arbitration module 12 to which all the connected read and write cache modules 11 are read cache modules.

[0071] The read arbitration module is used to:

[0072] Polling is performed on all corresponding read cache modules, so that the data to be read by each read cache module is stored in the corresponding cache area in the read arbitration module through the read-write state control module 13 and the storage device control module 14 .

[0073] The data stored in the cache area is output from the corresponding data reading channel through the corresponding read cache module.

[0074] Specifically, Figure 1 As shown, all read-write cache modules 11 connected to the read arbitration module B are read cache modules, that is, all read-write cache modules 11 connected to the read arbitration module B are used to receive data and read data from the storage device 15 through the corresponding module.

[0075] The total cache area of ​​the read arbitration module B can be divided into cache areas corresponding to the connected read-write cache modules 11. When the read arbitration module B polls each read-write cache module 11, it writes the data to be read from the storage device 15 by each read-write cache module 11 into its corresponding cache area in turn.

[0076] For example, the bit width of the read arbitration module B is 512 bits. If the number of read-write cache modules 11 connected to the read arbitration module B is 4, a 512-bit register can be defined in the read arbitration module B, and the storage space (i.e., cache area) of the register can be divided into 4 parts, corresponding to different read-write cache modules 11. After the storage space corresponding to each read-write cache module 11 is used to store corresponding data, the data obtained by the read arbitration module B can be output from the corresponding read-write cache module 11 through the corresponding module. By making different storage spaces correspond to different read-write cache modules 11 connected to the read arbitration module B, the synchronization of the four read-write cache modules 11 can be improved, and the possibility of data mixing and confusion between different read-write cache modules 11 can be reduced.

[0077] Based on the above method, the accuracy of the programmable logic gate array device when reading data can be effectively improved.

[0078] Further, the second cache area is any cache area among all cache areas of the target read arbitration module.

[0079] The data stored in the cache area is output from the corresponding data reading channel through the corresponding read cache module, including:

[0080] In response to the cached amount in the second cache area being not less than a preset ratio of the maximum cache amount in the second cache area, the data stored in the second cache area is output from the corresponding data read channel through the corresponding read cache module.

[0081] Specifically, the preset ratio may be greater than 0% and less than 100%.

[0082] By setting the preset ratio, the data in the cache area can be read accordingly while ensuring that the cache area is not fully filled, thereby avoiding data loss due to the cache area being filled, thereby improving the reliability of the programmable logic gate array device.

[0083] For example, the target read arbitration module can loop and detect in turn whether there is a read request for each read-write cache module 11 connected to it. If there is a read request, the loop is stopped and the corresponding data is read from the corresponding cache area in the target read arbitration module through the corresponding read-write cache module 11. If there is no read request, the loop continues to detect in turn after waiting for a preset period of time or when the corresponding cache area is empty to determine whether the next read-write cache module 11 has the above-mentioned read request.

[0084] It should be noted that if the data in the cache area has been read by the corresponding read-write cache module 11, the read data in the cache area can be regarded as no longer existing, that is, the space occupied by the read data in the cache area is regarded as free space, and the new data to be read can overwrite it.

[0085] The preset ratio mentioned in the above embodiment can be 50%, that is, when the data in the cache area reaches half of the maximum cache capacity of the cache area, the data in the cache area can be written or read accordingly, thereby avoiding the loss of data in the cache area due to lack of free cache space, thereby further improving the reliability of the programmable logic gate array device.

[0086] In one embodiment, the read / write state control module 13 is used to:

[0087] All multiplexing arbitration modules 12 are polled to write the data to be written by each multiplexing arbitration module 12 into the storage device 15 through the storage device control module 14 , or obtain the data to be read by each multiplexing arbitration module 12 from the storage device 15 through the storage device control module 14 .

[0088] Specifically, each multiplexing arbitration module 12 can be polled through the read-write status control module 13 to inquire whether each multiplexing arbitration module 12 has a request to write or read data. If there is a request, the cache data corresponding to the corresponding read-write cache module 11 in the corresponding multiplexing arbitration module 12 is written to the storage device 15 to complete the operation of writing data to the storage device 15, or the data in the storage device 15 is stored in the cache area corresponding to the corresponding read-write cache module 11 to complete the operation of reading data from the storage device 15.

[0089] For example, when the cache data of a read-write cache module 11 in the multiplexing arbitration module 12 is obtained through the read-write status control module 13, the mark number of the read-write cache module 11 in all the read-write cache modules 11 can be recorded, and the length of the obtained cache data can be recorded, so that the storage device 15 can distinguish the data source of the written data according to the content of the above record, and then realize the integration of the data written by different read-write cache modules 11 to complete the data storage.

[0090] Based on the above method, when obtaining the cache data of a certain read-write cache module 11, due to the delay of signal transmission, the read-write status control module 13 usually inquires the next multiplexing arbitration module 12 before the cache data is completely written into the storage device 15. Therefore, each segment of data written into the storage device 15 needs to record the corresponding data length and tag number to determine its source, so as to avoid the storage device 15 from damaging the data when integrating the data provided by different channels, and being unable to restore the original data, such as being unable to restore the video stream data that originally needed to be written, thereby causing confusion in the content of the video corresponding to the written video stream data, thereby improving the reliability of the programmable logic gate array device when storing data.

[0091] The present application also proposes a control method for a programmable logic gate array device, which is applied to the programmable logic gate array device described in any of the above embodiments, such as Figure 1 As shown, the programmable logic gate array device includes a plurality of read-write cache modules 11 , at least one multiplexing arbitration module 12 , a read-write state control module 13 and a storage device control module 14 .

[0092] Each read / write cache module 11 is connected to a corresponding data read channel or a data write channel, and the bit width of the read / write cache module 11 is the first bit width. The bit width of the multiplexing arbitration module 12 is the same as the bit width of the read / write state control module 13. The bit width of the read / write state control module 13 is the same as the bit width of the storage device control module 14.

[0093] See also Figure 2 , Figure 2FIG. 1 is a flow chart of an embodiment of a control method of a programmable logic gate array device of the present application. Figure 2 As shown, the control method includes:

[0094] Step S21 : controlling the multiplexing arbitration module 12 to perform data interaction with at least two read-write cache modules 11 , so as to cache data corresponding to the at least two read-write cache modules 11 .

[0095] The bit width of the read / write cache module 11 is the first bit width, the bit width of the multiplexing arbitration module 12 is the second bit width, and the first bit width is smaller than the second bit width.

[0096] Step S22 : controlling the read / write state control module 13 to perform data exchange with at least two multiplexing arbitration modules 12 respectively, and the read / write state control module 13 is used to perform data exchange with the storage device control module 14 .

[0097] Step S23 : controlling the storage device control module 14 to write data into the storage device 15 or read data from the storage device 15 .

[0098] Different from the prior art, in the technical solution of the present application, at least one multiplexing arbitration module having a bit width equal to the bit width of the read-write state control module and the bit width of the storage device control module is provided. Each multiplexing arbitration module can perform data interaction on at least two data read / write channels having a bit width smaller than the bit width of the multiplexing arbitration module, so that the number of modules for data interaction directly connected to the read-write state control module is less than the number of all data read / write channels, and the bit width of the read-write cache module can be smaller than the bit width of the storage device or the read-write state control module. Therefore, based on the above method, by constructing a multiplexing arbitration module to cooperate with the read-write cache module and the read-write state control module to read data from the storage device, the number of resource blocks required to be consumed by all the constructed modules when the programmable logic gate array device interacts with the storage device can be reduced, that is, the number of resource blocks required to be consumed when the programmable logic gate array device interacts with the storage device is reduced.

[0099] The present application also proposes a programmable logic gate array device, see Figure 3 , Figure 3 is a schematic diagram of the structure of an embodiment of the programmable logic gate array device of the present application, such as Figure 3 As shown, the programmable logic gate array device 30 includes a processor 31 , a memory 32 and a bus 33 .

[0100] The processor 31 and the memory 32 are connected to the bus 33 respectively. The memory 32 stores program instructions. The processor 31 is used to execute the program instructions to implement the control method of the programmable logic gate array device in the above embodiment.

[0101] In this embodiment, the processor 31 may also be referred to as a CPU (Central Processing Unit). The processor 31 may be an integrated circuit chip having signal processing capabilities. The processor 31 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. A general-purpose processor may be a microprocessor or the processor 31 may also be any conventional processor, etc.

[0102] Different from the prior art, in the technical solution of the present application, at least one multiplexing arbitration module having a bit width equal to the bit width of the read-write state control module and the bit width of the storage device control module is provided. Each multiplexing arbitration module can perform data interaction on at least two data read / write channels having a bit width smaller than the bit width of the multiplexing arbitration module, so that the number of modules for data interaction directly connected to the read-write state control module is less than the number of all data read / write channels, and the bit width of the read-write cache module can be smaller than the bit width of the storage device or the read-write state control module. Therefore, based on the above method, by constructing a multiplexing arbitration module to cooperate with the read-write cache module and the read-write state control module to read data from the storage device, the number of resource blocks required to be consumed by all the constructed modules when the programmable logic gate array device interacts with the storage device can be reduced, that is, the number of resource blocks required to be consumed when the programmable logic gate array device interacts with the storage device is reduced.

[0103] The present application also proposes a computer-readable storage medium, such as Figure 4 As shown, Figure 4 is a schematic diagram of the structure of an embodiment of the computer-readable storage medium of the present application. Figure 4 As shown, a computer-readable storage medium 40 stores program instructions 41 thereon, and when the program instructions 41 are executed by a processor (not shown), the control method of the programmable logic gate array device in the above embodiment is implemented.

[0104] The computer-readable storage medium 40 of this embodiment can be, but is not limited to, a USB flash drive, an SD card, a PD optical drive, a mobile hard disk, a large-capacity floppy drive, a flash memory, a multimedia memory card, a server, a storage unit in an FPGA or an ASIC, etc.

[0105] Different from the prior art, in the technical solution of the present application, at least one multiplexing arbitration module having a bit width equal to the bit width of the read-write state control module and the bit width of the storage device control module is provided. Each multiplexing arbitration module can perform data interaction on at least two data read / write channels having a bit width smaller than the bit width of the multiplexing arbitration module, so that the number of modules for data interaction directly connected to the read-write state control module is less than the number of all data read / write channels, and the bit width of the read-write cache module can be smaller than the bit width of the storage device or the read-write state control module. Therefore, based on the above method, by constructing a multiplexing arbitration module to cooperate with the read-write cache module and the read-write state control module to read data from the storage device, the number of resource blocks required to be consumed by all the constructed modules when the programmable logic gate array device interacts with the storage device can be reduced, that is, the number of resource blocks required to be consumed when the programmable logic gate array device interacts with the storage device is reduced.

[0106] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0107] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0108] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0109] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (which can be a personal computer, server, network device or other system that can fetch instructions from the instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0110] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A programmable logic gate array device, characterized in that: include: A plurality of read-write cache modules, each of which is connected to a corresponding data reading channel or a data writing channel, and the bit width of the read-write cache module is the first bit width; at least one multiplexing arbitration module, a single multiplexing arbitration module is used to perform data interaction with at least two of the read-write cache modules to cache data corresponding to the at least two of the read-write cache modules, the bit width of the multiplexing arbitration module is the second bit width, and the first bit width is smaller than the second bit width; A read / write state control module, the bit width of the multiplexing arbitration module is the same as the bit width of the read / write state control module, and the read / write state control module is used to perform data exchange with at least two of the multiplexing arbitration modules respectively; A storage device control module, the bit width of the read-write state control module is the same as the bit width of the storage device control module, and the read-write state control module is used to perform data exchange with the storage device control module.

2. The programmable logic gate array device according to claim 1, characterized in that: The multiple read-write cache modules include multiple read cache modules and multiple write cache modules, and the write arbitration module is the multiplexing arbitration module whose connected read-write cache modules are all the write cache modules; The write arbitration module is used for: Performing polling processing on all the corresponding write cache modules to store the data sent by each write cache module into the corresponding cache area of ​​the write arbitration module respectively; The data stored in the cache area is written into the storage device through the read-write state control module and the storage device control module.

3. The programmable logic gate array device according to claim 2, characterized in that: The first cache area is any cache area among all the cache areas of the target write arbitration module; The step of writing the data stored in the cache area into the storage device through the read / write state control module and the storage device control module comprises: In response to the cached amount in the first cache area being not less than a preset ratio of the maximum cache amount in the first cache area, the data in the first cache area is written into the storage device through the read-write state control module and the storage device control module.

4. The programmable logic gate array device according to claim 2, characterized in that: The read arbitration module is the multiplexing arbitration module to which the connected read and write cache modules are all the read cache modules; The read arbitration module is used for: Polling all the corresponding read cache modules, so as to store the data to be read by each read cache module into the corresponding cache area in the read arbitration module through the read-write state control module and the storage device control module; The data stored in the cache area is output from the corresponding data reading channel through the corresponding read cache module.

5. The programmable logic gate array device according to claim 4, characterized in that: The second cache area is any cache area among all the cache areas of the target read arbitration module; The step of outputting the data stored in the cache area from the corresponding data reading channel through the corresponding read cache module includes: In response to the cached amount in the second cache area being not less than a preset ratio of the maximum cache amount in the second cache area, the data stored in the second cache area is output from the corresponding data read channel through the corresponding read cache module.

6. The programmable logic gate array device according to claim 3 or 5, characterized in that: The preset ratio is 50%.

7. The programmable logic gate array device according to any one of claims 1 to 5, characterized in that: The read-write status control module is used for: Polling is performed on all the multiplexing arbitration modules to write the data to be written by each multiplexing arbitration module into the storage device through the storage device control module, or to obtain the data to be read by each multiplexing arbitration module from the storage device through the storage device control module.

8. A control method for a programmable logic gate array device, characterized in that: Applied to a programmable logic gate array device, the programmable logic gate array device includes a plurality of read-write cache modules, at least one multiplexing arbitration module, a read-write state control module and a storage device control module; each of the read-write cache modules is connected to a corresponding data reading channel or a data writing channel, and the bit width of the read-write cache module is the first bit width; the bit width of the multiplexing arbitration module is the same as the bit width of the read-write state control module; The bit width of the read / write state control module is the same as the bit width of the storage device control module; The control method comprises: Control the multiplexing arbitration module to perform data interaction with at least two of the read-write cache modules to cache data corresponding to the at least two of the read-write cache modules, the bit width of the multiplexing arbitration module being the second bit width, and the first bit width being smaller than the second bit width; Controlling the read / write state control module to perform data interaction with at least two of the multiplexing arbitration modules respectively, and the read / write state control module is used to perform data interaction with the storage device control module; The memory device control module is controlled to write data to or read data from the memory device.

9. A programmable logic gate array device, characterized in that: include: Memory and processor; The memory is used to store program instructions, and the processor is used to execute the program instructions to implement the method according to claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program instructions, and when the program instructions are executed by a processor, the method according to claim 8 is implemented.

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