Scan chain constraint correction method and device in integrated circuit, equipment and storage medium

Abstract

The invention provides a scan chain constraint correction method and device in an integrated circuit, equipment and a storage medium, and the method comprises the steps: obtaining an initial constraint file of the integrated circuit, the initial constraint file comprises initial function constraint information of each end pin, and the initial function constraint information at least comprises relaxation constraint information; determining at least one target pin according to the relaxation constraint information of each pin in the initial constraint file, and determining target function constraint information of the target pin and a boundary register and a target register of a target scan chain corresponding to the target pin according to the connection information and the relaxation constraint information of the target pin, and performing time sequence correction on the boundary register and the target register according to the target function constraint information of the target pin. According to the method and the device, the subsequent test time is not influenced while the physical design is not increased, and the efficiency of the DFT design is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a scan chain constraint correction method, device, equipment and storage medium in an integrated circuit. Background Art

[0002] DFT (Design for test) improves the efficiency and reliability of testing by considering test requirements and functions in the design phase and introducing test hardware in the physical layout and circuit design of the chip. Commonly used DFT methods in the physical design phase include scan chain-based testing methods and built-in self-test circuits. Among them, the scan chain-based testing methods include the scan chain of the chip's internal registers and the scan chain of the chip's I / O ports.

[0003] There are currently two chip design methods for inserting scan chains. The first is to impose high-frequency constraints on all scan chains. After a large amount of timing convergence time, the paths that cannot meet the timing are relaxed through DFT design. The second is to impose low-frequency constraints on the registers of the boundary scan chain so that the boundary scan chain registers meet the low-frequency timing and reduce the difficulty of physical design.

[0004] However, the first method imposes high-frequency constraints on all scan chain registers without distinction, which increases the difficulty of physical design, causes design redundancy, and further increases power consumption. The second method imposes low-frequency constraints on the registers of the boundary scan chain, which reduces design performance and increases test time. Summary of the invention

[0005] The purpose of the present application is to provide a scan chain constraint correction method, device, equipment and storage medium in an integrated circuit in order to address the deficiencies in the above-mentioned prior art, so as to solve the problem in the prior art that the physical design needs to be added in the scan chain timing constraint process, resulting in design redundancy, and reducing design performance and increasing test time.

[0006] To achieve the above objectives, the technical solutions adopted in this application are as follows:

[0007] In a first aspect, the present application provides a method for correcting scan chain constraints in an integrated circuit, the method comprising:

[0008] Acquire an initial constraint file of the integrated circuit, wherein the initial constraint file includes initial function constraint information of each terminal pin, and the initial function constraint information at least includes: relaxation constraint information;

[0009] Determine at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file;

[0010] According to the connection information and the relaxed constraint information of the target pin, determine the target function constraint information of the target pin and the boundary register and the target register of the target scan chain corresponding to the target pin, wherein the target register includes a head register or a tail register, the head register is the first register on the target scan chain, and the tail register is the last register on the target scan chain;

[0011] According to the target function constraint information of the target pin, timing correction is performed on the boundary register and the target register.

[0012] As a possible implementation manner, the relaxed constraint information is used to indicate whether the initial functional constraint information of the terminal pin is a timing relaxed constraint;

[0013] The step of determining at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file comprises:

[0014] If the relaxed constraint information indicates that the pin is a timing relaxed constraint, the pin is taken as a target pin.

[0015] As a possible implementation manner, the constraint relaxation information is used to indicate the number of clock cycles for which the constraint of the target pin is relaxed;

[0016] The step of determining target function constraint information of the target pin and a boundary register and a target register of a target scan chain corresponding to the target pin according to the connection information and the relaxed constraint information of the target pin comprises:

[0017] If the clock cycle of the relaxed constraint information is greater than a preset value, the initial function constraint information of the target pin is modified to obtain the target function constraint information of the target pin;

[0018] Based on the connection information of the target pin, a boundary register and a target register of the target scan chain are determined.

[0019] As a possible implementation manner, the initial function constraint information of the target end pin is modified to obtain the target function constraint information of the target end pin, including:

[0020] Determine constraint modification information of the hold time according to the setup time and the hold time in the initial function constraint information;

[0021] The constraint correction information of the hold time is added to the initial function constraint information to obtain the target function constraint information of the target pin.

[0022] As a possible implementation manner, determining the boundary register and the target register of the target scan chain based on the connection information of the target pin includes:

[0023] Taking the target pin as a starting point, determining a target data selector based on connection information of the target pin;

[0024] The connection line of the target data selector is determined based on the connection relationship of the target data selector, and the devices on the connection line of the target data selector are traversed to determine the boundary register and the target register of the target pin.

[0025] As a possible implementation manner, determining the target data selector based on the connection information of the target terminal pin includes:

[0026] Based on the connection information of the target pin, the devices on the target pin connection line are traversed. If the currently traversed device is a data selector and the device name contains preset characters, the currently traversed data selector is used as the target data selector.

[0027] As a possible implementation, the target terminal pin is an input terminal pin, and the target register is a tail register;

[0028] The traversing of the devices on the target data selector connection line to determine the boundary register and the target register of the target terminal pin includes:

[0029] Starting from the data input terminal of the target data selector, traverse in the first direction of the connection line until the current traversal object is a register, and taking the current traversal register as the boundary register of the target input terminal pin;

[0030] Starting from the data output terminal of the target data selector, traverse in the second direction of the connection line until the current traversal object is a register, and the current traversal register is used as the tail end register of the target input terminal pin.

[0031] As a possible implementation, the target terminal pin is an output terminal pin, and the target register is a head-end register;

[0032] The traversing of the devices on the target data selector connection line to determine the boundary register and the target register of the target terminal pin includes:

[0033] Taking the data input terminal of the target data selector as the end point, traverse in the third direction of the connection line until the current traversal object is a register, and taking the current traversal register as the boundary register of the target output terminal pin;

[0034] Taking the data output end of the target data selector as a starting point, traverse in a fourth direction of the connection line until the current traversal object is a register, and use the current traversal register as the head end register of the target output end pin.

[0035] As a possible implementation, the step of performing timing correction on the boundary register and the target register according to the target function constraint information of the target pin includes:

[0036] The timing constraint information of the boundary register and the target register is modified into the target function constraint information of the target pin.

[0037] In a second aspect, the present application provides a scan chain constraint correction device in an integrated circuit, the device comprising:

[0038] A constraint acquisition module, used to acquire an initial constraint file of the integrated circuit, wherein the initial constraint file includes initial functional constraint information of each terminal pin, and the initial functional constraint information at least includes: relaxed constraint information;

[0039] A first determination module, configured to determine at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file;

[0040] A second determination module is used to determine the target function constraint information of the target pin and the boundary register and the target register of the target scan chain corresponding to the target pin according to the connection information and the relaxation constraint information of the target pin, wherein the target register includes a head register or a tail register, the head register is the first register on the target scan chain, and the tail register is the last register on the target scan chain;

[0041] The timing correction module is used to perform timing correction on the boundary register and the target register according to the target function constraint information of the target pin.

[0042] As a possible implementation manner, the relaxed constraint information is used to indicate whether the initial functional constraint information of the terminal pin is a timing relaxed constraint;

[0043] The first determining module is specifically used for:

[0044] If the relaxed constraint information indicates that the pin is a timing relaxed constraint, the pin is taken as a target pin.

[0045] As a possible implementation manner, the constraint relaxation information is used to indicate the number of clock cycles for which the constraint of the target pin is relaxed;

[0046] The second determining module is specifically used for:

[0047] If the clock cycle of the relaxed constraint information is greater than a preset value, the initial function constraint information of the target pin is modified to obtain the target function constraint information of the target pin;

[0048] Based on the connection information of the target pin, a boundary register and a target register of the target scan chain are determined.

[0049] As a possible implementation manner, the second determining module is specifically configured to:

[0050] Determine constraint modification information of the hold time according to the setup time and the hold time in the initial function constraint information;

[0051] The constraint correction information of the hold time is added to the initial function constraint information to obtain the target function constraint information of the target pin.

[0052] As a possible implementation manner, the second determining module is specifically configured to:

[0053] Taking the target pin as a starting point, determining a target data selector based on connection information of the target pin;

[0054] The connection line of the target data selector is determined based on the connection relationship of the target data selector, and the devices on the connection line of the target data selector are traversed to determine the boundary register and the target register of the target pin.

[0055] As a possible implementation manner, the second determining module is specifically configured to:

[0056] Based on the connection information of the target pin, the devices on the target pin connection line are traversed. If the currently traversed device is a data selector and the device name contains preset characters, the currently traversed data selector is used as the target data selector.

[0057] As a possible implementation manner, the target terminal pin is an input terminal pin, the target register is a tail register, and the second determining module is specifically configured to:

[0058] Starting from the data input terminal of the target data selector, traverse in the first direction of the connection line until the current traversal object is a register, and taking the current traversal register as the boundary register of the target input terminal pin;

[0059] Starting from the data output terminal of the target data selector, traverse in the second direction of the connection line until the current traversal object is a register, and the current traversal register is used as the tail end register of the target input terminal pin.

[0060] As a possible implementation manner, the target terminal pin is an output terminal pin, and the target register is a head-end register; and the second determining module is specifically used for:

[0061] Starting from the data output terminal of the target data selector, traverse in the third direction of the connection line until the current traversal object is a register, and taking the current traversal register as the boundary register of the target output terminal pin;

[0062] Starting from the data input end of the target data selector, traverse in the fourth direction of the connection line until the current traversal object is a register, and the current traversal register is used as the head end register of the target output end pin.

[0063] As a possible implementation, the timing correction module is specifically used for:

[0064] The timing constraint information of the boundary register and the target register is modified into the target function constraint information of the target pin.

[0065] In a third aspect, an embodiment of the present application further provides a chip structure, which at least includes: a scan chain after timing correction, and the scan chain after timing correction is determined based on the steps of the scan chain constraint correction method in the integrated circuit described in the first aspect.

[0066] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of the scan chain constraint correction method in an integrated circuit as described in any one of the first aspects.

[0067] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the scan chain constraint correction method in an integrated circuit as described in any one of the first aspects are executed.

[0068] The beneficial effect of the present application is that after the high-frequency constraint is applied to the scan chain, the functional constraint information of the terminal pin is corrected according to the relaxed constraint information, and the boundary register and the target register corresponding to the target terminal pin are determined. Thus, the constraint correction of the boundary register and the target register can be performed according to the target functional constraint information of the terminal pin obtained after the correction. The constraint correction of the boundary register of the boundary circuit detection is realized according to the functional timing constraint, so that the key signal still maintains the high-frequency check, but the non-key signal in the boundary register is appropriately relaxed, so that the physical design is not increased, and the subsequent test time is not affected, thereby improving the efficiency of DFT design.

[0069] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0071] Figure 1 A flow chart of a scan chain constraint correction method in an integrated circuit provided by an embodiment of the present application is shown;

[0072] Figure 2 A schematic diagram of a timing path provided by an embodiment of the present application is shown;

[0073] Figure 3 A schematic diagram of a timing path after inserting a scan chain provided by an embodiment of the present application is shown;

[0074] Figure 4 A flowchart of obtaining target function constraint information and determining boundary registers and target registers provided by an embodiment of the present application is shown;

[0075] Figure 5 A flowchart of determining target function constraint information provided by an embodiment of the present application is shown;

[0076] Figure 6 A flow chart for determining a boundary register and a target register provided by an embodiment of the present application is shown;

[0077] Figure 7 A flow chart for determining a boundary register and a tail register provided in an embodiment of the present application is shown;

[0078] Figure 8A flow chart for determining a boundary register and a head-end register provided in an embodiment of the present application is shown;

[0079] Fig. 9 A schematic diagram of the structure of a scan chain constraint correction device in an integrated circuit provided by an embodiment of the present application is shown;

[0080] Fig.10 A schematic structural diagram of an electronic device 100 provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0081] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0082] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0083] In order to improve the controllability and observability of circuits in chips, it is currently possible to add scan chains to the chip structure and perform DFT design based on the scan chains to detect manufacturing defects inside the chip structure and at the system circuit board level in advance.

[0084] In the prior art, there are two DFT design methods based on scan chains. The first method is to impose the same high-frequency constraints as the functional clock on all scan chains, perform static timing analysis after the physical design layout and routing is completed, perform timing convergence on all timing paths in the DFT mode, and after a large amount of timing convergence time, relax the paths that cannot meet the timing through DFT design.

[0085] However, this approach requires indiscriminate high-frequency constraints on all scan chain registers and timing convergence on all timing paths in the DFT mode, which will increase the difficulty of physical design, cause design redundancy, and further increase power consumption.

[0086] The second method is to create a low-frequency clock for the registers of the boundary scan chain so that the boundary scan chain registers meet the low-frequency timing, thereby reducing the difficulty of physical design.

[0087] However, this method of low-frequency constraint on all boundary scan chain registers will reduce design performance and lead to insufficient signal inspection that requires high-frequency inspection, so problems are prone to occur during testing, which in turn leads to an increase in test time.

[0088] Therefore, how to reduce the time required for subsequent testing without increasing the physical design has become an urgent problem to be solved in scan chain-based DFT design.

[0089] Based on this, the present application proposes a scan chain constraint correction method in an integrated circuit. Before using the gate-level netlist after the chaining for layout and routing, the registers inserted by the DFT for boundary circuit detection are corrected accordingly based on the original functional logic intent. By correcting the timing constraints of the added DFT logic, redundant timing convergence can be achieved without increasing the physical design, and will not affect the subsequent test time.

[0090] After inserting the scan chain into the gate-level netlist, the on-chip controller can be placed and the clock tree can be constructed based on the current gate-level netlist. After high-frequency constraints are performed on all scan chain registers, timing corrections are performed on some boundary scan chain registers based on the solution of the present application. After the timing correction is completed, DFT testing is performed.

[0091] Among them, each clock corresponds to a group of on-chip controllers. In order to ensure that the timing deviation before and after adding the on-chip controllers is small, the positions of the on-chip controllers need to be placed separately. The placement process of the on-chip controllers can be as follows.

[0092] S11, extract the logic unit of the on-chip controller, trace back to find the location of the clock input pin based on the logic, and use the location as the anchor point of the logic unit;

[0093] S12, pre-place all on-chip controller logic units at their corresponding anchor points, and set a "position movable" attribute for all logic units;

[0094] S13, placing standard units, while allowing small-range movement of logic units with the attribute of "position movable", so that the logic units pre-placed at the same anchor point coordinates in S2 do not overlap and are not too far apart. The small-range movement distance can be within 20um, for example.

[0095] After completing the placement of the on-chip controller, the steps of clock tree synthesis can be performed. The specific process can be as follows:

[0096] S21, subdividing the pre-placed on-chip controller logic into a clock transmission part and a logic control part. The clock transmission part is a part of the clock tree trunk composed of data selectors, buffers, gate control units, etc.; while the logic control part is a part of the clock tree leaf node composed of registers, triggers, etc.;

[0097] S22. Add a buffer named Buf1 at the front end of the logic control part. At the end of the clock transmission part, insert a second buffer named Buf2 at the rest of the logic front end except Buf1. Create a sub-clock tree at the output end of Buf1 and Buf2 respectively, and divide them into separate clock tree groups. Do not balance according to the same clock tree.

[0098] S23. Perform clock tree synthesis based on the relationship between clock trees in S22. The relationship between clock trees is as follows: the sub-clock trees at the output ends of Buf1 and Buf2, and the isolation between the input ends of Buf1 and Buf2 and the source clock tree.

[0099] After clock tree synthesis, the registers in the scan chain can be corrected for timing based on the scan chain constraint correction method in the integrated circuit of this application. It should be noted that the integrated circuit is divided into functional mode and test mode. The input frequency in the functional mode is very high. Therefore, if each device in the functional mode can meet the timing requirements, the timing requirements of the device in the test mode can also be met. Based on this, this application proposes that the registers inserted in the DFT test can be constrained and corrected according to the timing constraints in the functional mode, so that the registers where the critical signals are located still maintain high-frequency checks, and the registers where the non-critical signals are located are appropriately relaxed, so as not to increase the physical design while not affecting the subsequent test time and improving the DFT design efficiency.

[0100] The following is a further description of the method of the present application. The execution subject of the method may be an electronic device, such as Figure 1 As shown, the scan chain constraint correction method in the integrated circuit of the present application specifically includes:

[0101] S101, obtaining an initial constraint file of an integrated circuit, wherein the initial constraint file includes initial functional constraint information of each pin, and the initial functional constraint information includes at least relaxed constraint information.

[0102] Before starting the test, you can first make high-frequency constraints for all scan chains and obtain the initial constraint file in the functional mode. Among them, the pins include input pins and output pins. The initial constraint file stores the constraint information of all devices in the functional mode, including the initial functional constraint information of the input pins and the output pins. The initial functional constraint information is the timing constraint information of the pins in the functional mode, including the creation of clocks, the relationship between clocks, and the relaxation of constraint information.

[0103] Creating a clock includes defining information of the clock, such as clock source point, clock period, clock duty cycle, clock naming, clock delay, etc. The relationship between clocks can be synchronous clock, asynchronous clock, and non-extended clock.

[0104] Timing constraints are key factors in ensuring that a circuit completes a specific operation within a specified time. Timing constraints can specifically limit parameters such as signal setup time, hold time, and clock-to-data delay. Relaxation of timing constraints means appropriately relaxing these already restricted parameters to meet specific design requirements or solve certain problems in the design. Accordingly, the above-mentioned relaxed constraint information can indicate whether the parameters of the terminal pins need to be relaxed and the scope of relaxation.

[0105] S102. Determine at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file.

[0106] Since the relaxation constraint information can indicate whether the parameters of the terminal pins need to be relaxed, based on the relaxation constraint information of each terminal pin, it is possible to know which terminal pins need to have their parameters relaxed. In the following embodiments of the present application, the terminal pins that need to have their parameters relaxed are referred to as timing relaxed terminal pins.

[0107] The register connected to the pin with relaxed timing can be corrected to be the same as the maximum timing limit of the pin. Therefore, the pin with relaxed timing can be used as the target pin, and the register to be corrected for timing can be determined based on the target pin, thereby modifying the high-frequency constraints of the register to be corrected for timing to be the same as the functional logic intention.

[0108] The initial constraint file may include initial functional constraint information of multiple devices. After screening the initial constraint information related to the pins in the initial constraint file, the initial functional constraint information of the pins can be obtained. According to the relaxed constraint information in the initial functional constraint information of each pin, the pin with relaxed timing can be determined as the target pin. The number of target pins can be multiple, including input pins and / or output pins.

[0109] S103. Determine the target function constraint information of the target pin and the boundary register and target register of the target scan chain corresponding to the target pin according to the connection information of the target pin and the relaxed constraint information. The target register includes a head register or a tail register. The head register is the first register on the target scan chain, and the tail register is the last register on the target scan chain.

[0110] The connection information of the target pin may indicate the devices included in the timing path of the target pin and the connection order of each device. The target function constraint information may be obtained by modifying the initial function constraint information based on the relaxed constraint information.

[0111] It should be noted that the initial functional constraint information of the target pin is the timing constraint under the functional mode. According to the relaxed constraint information, the timing of the initial functional constraint information can be moderately relaxed to obtain the target functional constraint information, thereby improving the stability of the clock and data during the test process.

[0112] The target scan chain corresponding to the target pin may be a scan chain inserted on the timing path where the target pin is located. The target register may be the last register (tail register) on the target scan chain or the first register (head register) on the target scan chain. The boundary register may be a boundary scan chain register between the pin and the target register, including a boundary register between the pin and the head register and a boundary register between the pin and the tail register.

[0113] S104. Perform timing correction on the boundary register and the target register according to the target function constraint information of the target pin.

[0114] As a possible implementation method, the above steps S102-S103 can be performed on all target pins to obtain a target constraint file, which includes target function constraint information of all target pins. Next, the target constraint file is rewritten, and the field value of the target pin in the target constraint file is replaced with the corresponding boundary register to the target register, and the modified target constraint file is used as the constraint file of the boundary register.

[0115] As another possible implementation method, the above steps S102-S103 can be performed on each target pin in sequence to obtain the target function constraint information of each target pin, and the function constraint information of the target pin can be used as the timing constraint information between its corresponding boundary register and the target register.

[0116] Next, combine Figure 2 and Figure 3 The relationship between the pins, boundary registers, and target registers is explained. Figure 2 It is a timing path diagram before inserting the scan chain. Figure 3 This is a schematic diagram of the timing path after the scan chain is inserted. Figure 2 and Figure 3 , input is the terminal pin, FF1 is the target register on the scan chain. After inserting the scan chain, it is equivalent to inserting a Figure 3 The boundary register FF0 shown in the figure will Figure 2 The one timing path shown is broken into two. At this time, the timing requirement between the boundary register FF0 and the target register FF1 is the same as the timing requirement from the pin input to the target register FF1.

[0117] For example, assuming that the relaxation constraint information of the terminal pin input indicates that the terminal pin input is a timing relaxation constraint, the timing formed by the terminal pin input to the target register FF1 can be relaxed to n beats. Figure 3 After the boundary register shown, the timing constraint from the boundary register FF0 to the target register FF1 after high-frequency constraint is one beat, then the timing constraint between the boundary register FF0 and the target register FF1 can be corrected to n beats, relaxed to the same as the timing from the terminal input to the target register FF1.

[0118] In an embodiment of the present application, an initial constraint file of an integrated circuit is obtained, the initial constraint file including initial functional constraint information of each pin, the initial functional constraint information including at least: relaxed constraint information, at least one target pin is determined based on the relaxed constraint information of each pin in the initial constraint file, target functional constraint information of the target pin and boundary registers and target registers of a target scan chain corresponding to the target pin are determined based on connection information of the target pin and the relaxed constraint information, and timing correction is performed on the boundary registers and the target registers based on the target functional constraint information of the target pin.

[0119] After high-frequency constraints are applied to the scan chain, the functional constraint information of the terminal pin is modified according to the relaxed constraint information, and the boundary register and target register corresponding to the target terminal pin are determined. Therefore, the boundary register and target register can be constrained and modified according to the target functional constraint information of the terminal pin obtained after the correction. The boundary register of the boundary circuit detection is constrained and modified according to the functional timing constraints, so that the key signals are still checked at high frequency, but the non-critical signals in the boundary register are appropriately relaxed, so that the physical design is not increased and the subsequent test time is not affected, thereby improving the efficiency of DFT design.

[0120] Optionally, the relaxed constraint information is used to indicate whether the initial functional constraint information of the pin is a timing relaxed constraint. The process of determining at least one target pin according to the relaxed constraint information of each pin in the initial constraint file includes:

[0121] If the relaxation constraint information indicates that the pin is a constraint for timing relaxation, the pin is taken as a target pin.

[0122] Optionally, if the initial functional constraint information of the pin is a timing-relaxed constraint, it indicates that the pin is the aforementioned timing-relaxed pin.

[0123] Among them, when the terminal pin is a terminal pin with relaxed timing, the initial functional constraint information of the terminal pin meets at least one of the following requirements: the initial functional constraint information is a constraint relaxed to multiple beats, for example, the setup time check of the terminal pin is a multiple cycle check and the hold time check is postponed to the cycle check; or the initial functional constraint information does not check the timing of the terminal pin, for example, a false_path (cross-domain clock constraint) is set for the timing of the terminal pin; or the initial functional constraint information sets a maximum constraint, and a constraint greater than one cycle check is imposed on the timing of the original one-cycle check.

[0124] Optionally, the constraint relaxation information is used to indicate the number of clock cycles for which the constraint of the target pin is relaxed.

[0125] The above process of determining the target function constraint information of the target pin and the boundary register and target register of the target scan chain corresponding to the target pin according to the connection information of the target pin and the relaxation constraint information is as follows: Figure 4 As shown, including:

[0126] S401. If the clock cycle of the relaxed constraint information is greater than a preset value, the initial function constraint information of the target pin is modified to obtain the target function constraint information of the target pin.

[0127] The preset value may be 2 or other integer values. The relaxed constraint information may indicate whether the timing constraint of the pin is a constraint of multiple clock cycles. If the timing constraint is a timing relaxed constraint and is a constraint of multiple clock cycles, the initial functional constraint information of the target pin may be modified.

[0128] When the initial function constraint information is modified, the initial function constraint information of all the end pins can be extracted into the intermediate constraint file, and the above step S401 is performed on each end pin in the intermediate constraint file to complete the modification of the initial function constraint information of all the end pins.

[0129] If the timing constraint is a timing relaxation constraint, but the clock period of the relaxed constraint information is less than or equal to the preset value, there is no need to modify the initial functional constraint information, and the initial functional constraint information can be used as the target functional constraint information.

[0130] S402 : Determine the boundary register and the target register of the target scan chain based on the connection information of the target pin.

[0131] The connection information of the target pin may indicate the device connected to the timing path of the target pin, so by searching based on the connection information of the target pin, the boundary register and the target register on the timing path of the target pin may be determined.

[0132] Reference Figure 3The connection information of the target pin can indicate the data selector mux_d connected to the target pin input, the register FF1 connected to the data selector mux_d, and the register FF0, thereby determining the boundary register FF0 of the target pin input and the target register FF1.

[0133] Furthermore, in the above S401, the initial function constraint information of the target end pin is corrected to obtain the target function constraint information of the target end pin, such as Figure 5 As shown, including:

[0134] S501: Determine constraint modification information of the retention time according to the setup time and retention time in the initial function constraint information.

[0135] As a possible implementation, the check period of the setup time and the check period of the hold time can be determined, and when the check period of the setup time and the check period of the hold time do not meet the conventional timing constraints, the check period of the hold time can be corrected. The conventional timing constraints can be that the setup time is checked in the next cycle and the hold time is checked in the current cycle.

[0136] The hold time constraint correction information may be a constraint on the hold time that needs to be increased at the target end.

[0137] For example, assume that the relaxed constraint in the initial functional constraint information is three beats, that is, the check period for the establishment time is three beats, and after the timing check it is determined that the check period for the hold time is two beats. At this time, it is necessary to correct the hold time and add the hold time constraint to the initial functional constraint information.

[0138] S502: Add the constraint correction information of the hold time to the initial function constraint information to obtain the target function constraint information of the target terminal pin.

[0139] After determining the hold time constraint correction information, the hold time constraint correction information may be added to the initial function constraint information of the target pin, for example, the hold time constraint correction information may be added to the hold time constraint information in the initial function constraint information.

[0140] The above process of determining the boundary register and the target register of the target scan chain based on the connection information of the target pin is as follows: Figure 6 As shown, including:

[0141] S601. Determine a target data selector based on connection information of a target terminal pin.

[0142] The scanning method of the scan chain test is to add a data selector to each trigger so that it has two modes. The first is the normal mode. In the normal mode, all registers work as usual. The other is the scan test mode, which is essentially to connect the triggers into multiple shift registers, called scan registers. In the test mode, the scan clock controls the scan registers, and the output signal is captured and then compared with the data to detect whether the registers are working properly, thereby determining the test results.

[0143] The target data selector may be a data selector added when inserting the scan chain. When determining the boundary scan chain and the tail scan chain corresponding to the target pin, the data selector connected to the target pin may be searched to determine whether the data selector connected to the target pin is the data selector inserted when inserting the scan chain.

[0144] In the first implementation, the target pin may be an input pin, and in this case the target pin may be used as a starting point to determine the target data selector based on connection information of the target pin.

[0145] In the second implementation, the target pin may be an output pin, in which case the target pin may be used as the end point, and the target data selector is determined based on connection information of the target pin.

[0146] S602, determining a connection line of the target data selector based on the connection relationship of the target data selector, and traversing the devices on the connection line of the target data selector to determine a boundary register and a target register of the target pin.

[0147] After the target data selector is determined, the target data selector may be used as a starting point or an end point, and the boundary register and the target register connected on the connection path of the target data selector may be determined based on the connection relationship of the target data selector.

[0148] The connection line of the target data selector may be a timing path where the target data selector is located.

[0149] Furthermore, the process of determining the target data selector based on the connection information of the target terminal pin in the above S601 includes:

[0150] Based on the connection information of the target pin, the devices on the target pin connection line are traversed. If the currently traversed device is a data selector and the device name contains preset characters, the currently traversed data selector is used as the target data selector.

[0151] When the target pin is an input pin, the target data selector can be determined by traversing the downstream devices connected to the target pin based on the connection information of the target pin, starting from the target pin.

[0152] When the target pin is an output pin, the target data selector can be determined by traversing the previous devices connected to the target pin based on the connection information of the target pin and starting from the target pin.

[0153] by Figure 3 For example, the connection information of the target pin input indicates the devices on the timing path where the target pin is located and the connection order of each device. Based on the connection information, traverse to find the first data selector mux_d connected to the target pin input, and determine that the device name of the currently traversed data selector includes preset characters, then the data selector mux_d can be used as the target data selector.

[0154] In another example, referring to Figure 3 , traverse the target pin clk_func, determine that the data selector mux_c connected to it is a two-input data selector, and the device name includes preset characters, then the data selector mux_c can also be used as a target data selector.

[0155] Optionally, the target data selector may be a two-input data selector. The preset character may be an identifier added to the name of the inserted data selector when the data selector is inserted into the scan chain, and is used to indicate that the data selector is a DFT test unit.

[0156] It should be noted that when inserting a scan chain, preset characters can be added to the name of the inserted data selector. Therefore, when traversing based on the connection information of the target pin, as long as the name of the currently traversed data selector includes the preset characters, it can be said that the currently traversed data selector is the data selector inserted in the process of inserting the scan chain, that is, a test unit of the DFT. It should be understood that this application only uses the inclusion of preset characters in the name as a possible implementation method for identifying a data selector as a DFT test unit. In actual execution, the target data selector can also be determined by other methods, and this application does not limit this.

[0157] After the target data selector is determined, the devices on the target data selector connection line can be further traversed to determine the boundary register and the target register of the target pin.

[0158] In the first implementation, the target pin is an input pin. In this case, the target register can be a tail register, that is, the last register on the target scan chain. Figure 7 As shown, the above step S602 includes:

[0159] S701, starting from the data input terminal of the target data selector, traverse in the first direction of the connection line until the current traversal object is a register, and use the current traversal register as the boundary register of the target input terminal pin.

[0160] The first direction may be the front of the connection line starting from the data input terminal, that is, the opposite direction of the signal flow. Taking a two-input data selector as an example, the data input terminal of the target data selector may be another input terminal that is not connected to the input terminal pin input.

[0161] Continue to refer to Figure 3 , starting from the data input end of the target data selector mux_d, traverse in the opposite direction of the signal flow in the connection line until the current traversal object is a register, and use the currently traversed register FF0 as the boundary register corresponding to the target terminal input.

[0162] S702, starting from the data output terminal of the target data selector, traverse in the second direction of the connection line until the current traversal object is a register, and use the current traversal register as the tail end register of the target input terminal pin.

[0163] The second direction may be the rear of the connection line starting from the data output end, that is, the same direction as the signal flow direction.

[0164] Reference Figure 3 , starting from the data output end of the target data selector mux_d, traverse in the same direction of the connection line signal flow until the current traversal object is a register, and use the currently traversed register FF1 as the tail register corresponding to the target terminal input.

[0165] In the second implementation, the target pin can be an output pin, and the target register can be a head register, that is, the first register on the target scan chain. Figure 8 As shown, the above step S602 includes:

[0166] S801, starting from the data output terminal of the target data selector, traverse in the third direction of the connection line until the current traversal object is a register, and use the current traversal register as the boundary register of the target output terminal pin.

[0167] The third direction may be the rear of the connection line, specifically the same direction as the signal flow starting from the data output end.

[0168] Reference Figure 3 , starting from the data output end of the target data selector mux_c, traverse in the same direction of the signal flow in the connection line until the current traversal object is a register, and use the currently traversed register FF0 as the boundary register corresponding to the target end pin.

[0169] S802, starting from the data input terminal of the target data selector, traverse in the fourth direction of the connection line until the current traversal object is a register, and use the current traversal register as the head end register of the target output terminal pin.

[0170] The fourth direction may be the front of the connection line, specifically, the opposite direction of the signal flow starting from the data input terminal.

[0171] Continue to refer to Figure 3 , starting from the data input end of the target data selector mux_c, traverse in the opposite direction of the signal flow in the connection line until the current traversal object is a register, and the currently traversed register FFs is used as the head end register corresponding to the target end pin.

[0172] After determining the boundary register and the target register, the timing of the boundary register and the target register can be corrected according to the target function constraint information of the target pin, including:

[0173] Modify the timing constraint information of the boundary register and the target register to the target function constraint information of the target pin.

[0174] by Figure 3 Taking this as an example, the timing constraint information between the boundary register FF0 and the target register FF1 can be rewritten into the target function constraint information of the target pin input, thereby completing the timing constraint correction of the boundary register FF0.

[0175] After completing the timing constraint correction of all boundary registers in the chip structure, the scan clock can be used to control the scan register in the test mode, and the output signal can be captured and then compared with the data to detect whether the register is working properly, thereby determining the test result.

[0176] Based on the same inventive concept, an embodiment of the present application also provides a scan chain constraint correction device in an integrated circuit corresponding to the scan chain constraint correction method in an integrated circuit. Since the principle of solving the problem by the device in the embodiment of the present application is similar to the scan chain constraint correction method in the integrated circuit in the embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0177] Fig. 9 The structure diagram of a scan chain constraint correction device in an integrated circuit provided by an embodiment of the present application is shown. Fig. 9 The scan chain constraint correction device in the integrated circuit includes a constraint acquisition module 901, a first determination module 902, a second determination module 903 and a timing correction module 904.

[0178] The constraint acquisition module 901 is used to acquire an initial constraint file of the integrated circuit, wherein the initial constraint file includes initial functional constraint information of each terminal pin, and the initial functional constraint information at least includes: relaxed constraint information;

[0179] A first determination module 902 is used to determine at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file;

[0180] The second determination module 903 is used to determine the target function constraint information of the target pin and the boundary register and the target register of the target scan chain corresponding to the target pin according to the connection information of the target pin and the relaxation constraint information, wherein the target register includes a head register or a tail register, the head register is the first register on the target scan chain, and the tail register is the last register on the target scan chain;

[0181] The timing correction module 904 is used to perform timing correction on the boundary register and the target register according to the target function constraint information of the target pin.

[0182] As a possible implementation method, the relaxed constraint information is used to indicate whether the initial functional constraint information of the terminal pin is a timing relaxed constraint;

[0183] The first determining module 902 is specifically used for:

[0184] If the relaxation constraint information indicates that the pin is a constraint for timing relaxation, the pin is taken as a target pin.

[0185] As a possible implementation method, the constraint relaxation information is used to indicate the number of clock cycles for which the constraint of the target pin is relaxed;

[0186] The second determining module 903 is specifically used for:

[0187] If the clock cycle of the relaxed constraint information is greater than a preset value, the initial function constraint information of the target pin is modified to obtain the target function constraint information of the target pin;

[0188] Based on the connection information of the target pin, the boundary register and the target register of the target scan chain are determined.

[0189] As a possible implementation manner, the second determining module 903 is specifically configured to:

[0190] Determine constraint correction information of the hold time according to the setup time and the hold time in the initial function constraint information;

[0191] The constraint correction information of the hold time is added to the initial function constraint information to obtain the target function constraint information of the target pin.

[0192] As a possible implementation manner, the second determining module 903 is specifically configured to:

[0193] Taking the target end pin as a starting point, determining the target data selector based on the connection information of the target end pin;

[0194] The connection line of the target data selector is determined based on the connection relationship of the target data selector, and the devices on the connection line of the target data selector are traversed to determine the boundary register and the target register of the target pin.

[0195] As a possible implementation manner, the second determining module 903 is specifically configured to:

[0196] Based on the connection information of the target pin, the devices on the target pin connection line are traversed. If the currently traversed device is a data selector and the device name contains preset characters, the currently traversed data selector is used as the target data selector.

[0197] As a possible implementation manner, the target terminal pin is an input terminal pin, the target register is a tail register, and the second determination module 903 is specifically used for:

[0198] Starting from the data input terminal of the target data selector, traverse in the first direction of the connection line until the current traversal object is a register, and taking the current traversal register as the boundary register of the target input terminal pin;

[0199] Starting from the data output terminal of the target data selector, traverse in the second direction of the connection line until the current traversal object is a register, and the current traversal register is used as the target register of the target input terminal pin.

[0200] As a possible implementation manner, the target terminal pin is an output terminal pin, the target register is a head-end register, and the second determination module 903 is specifically used for:

[0201] Starting from the data output terminal of the target data selector, traverse in the third direction of the connection line until the current traversal object is a register, and the current traversal register is used as the boundary register of the target output terminal pin;

[0202] Starting from the data input end of the target data selector, traverse in the fourth direction of the connection line until the current traversal object is a register, and the current traversal register is used as the head end register of the target output end pin.

[0203] As a possible implementation, the timing correction module 904 is specifically used for:

[0204] Modify the timing constraint information of the boundary register and the target register to the target function constraint information of the target pin.

[0205] After the scan chain is subjected to high-frequency constraints, the embodiment of the present application modifies the functional constraint information of the terminal pin according to the relaxed constraint information, and determines the boundary register and target register corresponding to the target terminal pin. Thus, the boundary register and the target register can be constrained and modified according to the target functional constraint information of the terminal pin obtained after the correction. The boundary register of the boundary circuit detection is constrained and modified according to the functional timing constraint, so that the key signal still maintains the high-frequency inspection, but the non-key signal in the boundary register is appropriately relaxed, so that the physical design is not increased, and the subsequent test time is not affected, thereby improving the efficiency of DFT design.

[0206] An embodiment of the present application further provides a chip structure, which at least includes: a scan chain after timing correction, wherein the scan chain after timing correction is determined based on the steps of the scan chain constraint correction method in the above integrated circuit.

[0207] Fig.10 A structural schematic diagram of an electronic device provided in an embodiment of the present application is shown, comprising: a processor 1001, a storage medium 1002 and a bus 1003, wherein the storage medium 1002 stores machine-readable instructions executable by the processor 1001, and when the electronic device runs a scan chain constraint correction method in an integrated circuit as in the embodiment, the processor 1001 communicates with the storage medium 1002 via the bus 1003, and the processor 1001 executes the machine-readable instructions, and the processor 1001 executes the preamble of the method item to execute the steps of the scan chain constraint correction method in the integrated circuit in the above method embodiment.

[0208] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. The computer program is executed when a processor is running, and the processor executes the steps of the scan chain constraint correction method in an integrated circuit in the above method embodiment.

[0209] In the embodiment of the present application, the computer program can also execute other machine-readable instructions when run by the processor to execute other methods described in the embodiment. For the specific execution method steps and principles, please refer to the description of the embodiment, which will not be repeated here.

[0210] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0211] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0212] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0213] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0214] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0215] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A scan chain constraint correction method in an integrated circuit, characterized in that: include: Acquire an initial constraint file of the integrated circuit, wherein the initial constraint file includes initial function constraint information of each terminal pin, and the initial function constraint information at least includes: relaxation constraint information; Determine at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file; According to the connection information and the relaxed constraint information of the target pin, determine the target function constraint information of the target pin and the boundary register and the target register of the target scan chain corresponding to the target pin, wherein the target register includes a head register or a tail register, the head register is the first register on the target scan chain, and the tail register is the last register on the target scan chain; According to the target function constraint information of the target pin, timing correction is performed on the boundary register and the target register.

2. The method according to claim 1, characterized in that: The relaxed constraint information is used to indicate whether the initial functional constraint information of the terminal pin is a timing relaxed constraint; The step of determining at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file comprises: If the relaxed constraint information indicates that the pin is a timing relaxed constraint, the pin is taken as a target pin.

3. The method according to claim 1, characterized in that The relaxation constraint information is used to indicate the number of clock cycles of the relaxation constraint of the target pin; The step of determining target function constraint information of the target pin and a boundary register and a target register of a target scan chain corresponding to the target pin according to the connection information and the relaxed constraint information of the target pin comprises: If the clock cycle of the relaxed constraint information is greater than a preset value, the initial function constraint information of the target pin is modified to obtain the target function constraint information of the target pin; Based on the connection information of the target pin, a boundary register and a target register of the target scan chain are determined.

4. The method according to claim 3, characterized in that The step of correcting the initial function constraint information of the target end pin to obtain the target function constraint information of the target end pin includes: Determine constraint modification information of the hold time according to the setup time and the hold time in the initial function constraint information; The constraint correction information of the hold time is added to the initial function constraint information to obtain the target function constraint information of the target pin.

5. The method according to claim 3, characterized in that: The step of determining the boundary register and the target register of the target scan chain based on the connection information of the target pin includes: Determine a target data selector based on the connection information of the target pin; The connection line of the target data selector is determined based on the connection relationship of the target data selector, and the devices on the connection line of the target data selector are traversed to determine the boundary register and the target register of the target pin.

6. The method according to claim 5, characterized in that The step of determining a target data selector based on the connection information of the target terminal pin comprises: Based on the connection information of the target pin, the devices on the target pin connection line are traversed. If the currently traversed device is a data selector and the device name contains preset characters, the currently traversed data selector is used as the target data selector.

7. The method according to claim 5, characterized in that The target terminal pin is an input terminal pin, and the target register is a tail terminal register; The traversing of the devices on the target data selector connection line to determine the boundary register and the target register of the target terminal pin includes: Starting from the data input terminal of the target data selector, traverse in the first direction of the connection line until the current traversal object is a register, and taking the current traversal register as the boundary register of the target input terminal pin; Starting from the data output terminal of the target data selector, traverse in the second direction of the connection line until the current traversal object is a register, and the current traversal register is used as the tail end register of the target input terminal pin.

8. The method according to claim 5, characterized in that The target terminal pin is an output terminal pin, and the target register is a head-end register; The traversing of the devices on the target data selector connection line to determine the boundary register and the target register of the target terminal pin includes: Starting from the data output terminal of the target data selector, traverse in the third direction of the connection line until the current traversal object is a register, and taking the current traversal register as the boundary register of the target output terminal pin; Starting from the data input end of the target data selector, traverse in the fourth direction of the connection line until the current traversal object is a register, and the current traversal register is used as the head end register of the target output end pin.

9. The method according to claim 1, characterized in that: The step of performing timing correction on the boundary register and the target register according to the target function constraint information of the target pin includes: The timing constraint information of the boundary register and the target register is modified into the target function constraint information of the target pin.

10. A scan chain constraint correction device in an integrated circuit, characterized in that: include: A constraint acquisition module, used to acquire an initial constraint file of the integrated circuit, wherein the initial constraint file includes initial functional constraint information of each terminal pin, and the initial functional constraint information at least includes: relaxed constraint information; A first determination module, configured to determine at least one target end pin according to the relaxed constraint information of each end pin in the initial constraint file; A second determination module is used to determine the target function constraint information of the target pin and the boundary register and the target register of the target scan chain corresponding to the target pin according to the connection information and the relaxation constraint information of the target pin, wherein the target register includes a head register or a tail register, the head register is the first register on the target scan chain, and the tail register is the last register on the target scan chain; The timing correction module is used to perform timing correction on the boundary register and the target register according to the target function constraint information of the target pin.

11. A chip structure, characterized in that: The chip structure at least includes: a scan chain after timing correction, wherein the scan chain after timing correction is determined based on the steps of the scan chain constraint correction method in an integrated circuit according to any one of claims 1 to 9.

12. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the scan chain constraint correction method in an integrated circuit as described in any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the scan chain constraint correction method in an integrated circuit as claimed in any one of claims 1 to 9 are executed.

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