Image edge detection processing system based on FPGA

Abstract

The invention discloses an image edge detection processing system based on an FPGA, and relates to the technical field of edge detection, and the system comprises an image collection module which is used for obtaining a processing image to be subjected to edge detection; the image storage module is used for storing the processed image acquired by the image acquisition module; the image processing module is used for preprocessing the processed image stored in the image storage module and is also used for carrying out edge detection on the preprocessed processed image; the image display module is used for displaying the processed image subjected to edge detection; the system clock module is used for synchronizing reference clock signals operated by all the modules; the problems that in an existing FPGA-based edge detection algorithm, an algorithm based on convolution operation is low in operation speed and not beneficial to real-time processing, and meanwhile the speed and efficiency of edge detection are further improved on the premise that the power consumption of a system is reduced to guarantee the edge detection effect are solved.

Description

Technical Field

[0001] The present invention relates to the field of edge detection technology, and more specifically, to an image edge detection processing system based on FPGA. Background Art

[0002] In practical applications, the current image edge detection requires the edge detection system to process images in real time and to perform edge detection at different resolutions. Therefore, how to further improve the speed and efficiency of edge detection while ensuring the edge detection effect is one of the current shortcomings; secondly, image edge detection based on FPGA also needs to work hard on algorithm optimization. At present, the edge detection algorithms based on FPGA mainly include algorithms based on convolution operations and algorithms based on integral images. Among them, algorithms based on convolution operations have been widely used. However, due to its slow operation speed, it is not conducive to real-time processing. Therefore, one of the shortcomings is how to further improve the efficiency and speed of edge detection by optimizing the algorithm while reducing the power consumption of the system. Summary of the invention

[0003] The purpose of the present invention is to provide an image edge detection processing system based on FPGA to solve the problems existing in the above-mentioned background technology.

[0004] The above technical objectives of the present invention are achieved through the following technical solutions:

[0005] In a first aspect, the present application provides an image edge detection processing system based on FPGA, comprising:

[0006] An image acquisition module, used to obtain a processed image to be edge detected;

[0007] An image storage module, used for storing processed images acquired by the image acquisition module;

[0008] An image processing module, used for preprocessing the processed image stored in the image storage module, and for performing edge detection on the processed image after preprocessing;

[0009] An image display module, used for displaying the processed image after edge detection;

[0010] The system clock module is used to synchronize the reference clock signal of each module operation.

[0011] Based on the above technical solution, the present invention can also be improved as follows.

[0012] Furthermore, the above-mentioned image acquisition module is a camera of model OV7670.

[0013] Furthermore, the type of the above-mentioned image storage module is SDRAM.

[0014] Furthermore, the above-mentioned image display module is a VGA display module.

[0015] Furthermore, the above preprocessing includes denoising, smoothing and enhancement.

[0016] Furthermore, the above edge detection is specifically as follows:

[0017] Convert the preprocessed processed image into a grayscale image in YCbCr format;

[0018] The image pixels of each pixel point in the grayscale image are obtained through a sliding window of a preset size, and the gradient amplitude of each pixel point in the grayscale image is calculated using the image pixels of each pixel point and a convolution factor template preset in multiple directions;

[0019] The non-maximum suppression process is performed on the gradient amplitude of each pixel in the grayscale image, and the grayscale image after the non-maximum suppression process is determined as the processing result of edge detection.

[0020] Furthermore, the above method also includes:

[0021] The gradient value of each pixel in each direction is calculated by using the image pixels of each pixel and the preset convolution factor template based on multiple directions;

[0022] The gradient value of each pixel in each direction is used to calculate the gradient amplitude of each pixel.

[0023] Furthermore, the gradient amplitude of each pixel is specifically:

[0024]

[0025] Where G represents the gradient amplitude of one pixel, G1 represents the gradient value of the pixel in one direction, and n represents the number of directions for calculating the gradient value of the pixel.

[0026] Furthermore, the above non-maximum suppression process is specifically as follows:

[0027] The gradient amplitude of each pixel point is compared with the gradient amplitudes of multiple adjacent points of the pixel point in the gradient direction. If the gradient amplitude of the pixel point is greater than the gradient amplitudes of the adjacent points, the pixel of the pixel point is retained, otherwise the pixel of the pixel point is adjusted to 0.

[0028] In a second aspect, the present application provides an application of an FPGA-based image edge detection processing system as described in any one of the first aspects in image edge detection.

[0029] Compared with the prior art, the present invention has at least the following beneficial effects:

[0030] In the present application, an image acquisition module, an image storage module, an image processing module, an image display module and a system clock module that are connected to each other are used. When edge detection is performed on an image, first, a processed image to be edge detected is acquired through the image acquisition module, and the acquired processed image is stored in the image storage module; secondly, the image processing module performs preprocessing and edge detection processing on the processed image in turn, and obtains the result of edge detection; finally, the processed image after edge detection is displayed using the image display module; in FPGA, a stable external clock source is often required as the system clock; this external clock source can be provided by a crystal oscillator, and its frequency is called the system clock frequency; in FPGA design, the setting of the system clock plays a vital role in the performance and function of the entire system; the system clock refers to a reference clock signal used to synchronize the operations of each module. Reasonable setting of the system clock can ensure the correct timing relationship between the modules and avoid clock conflicts and data errors.

[0031] In the present application, a common practice for setting the clock of each module is to use a clock divider for frequency division, which can simplify clock wiring and reduce the complexity of the clock network; since each module may have different requirements for different operations and processing speeds, in order to simplify the clock design and meet the needs of each module, the system clock frequency can be divided into a module clock frequency of 25MHz. In this way, each module can perform operations and process data according to the clock frequency of 25MHz, thereby better adapting to the functions and performance requirements of each module.

[0032] In this application, the performance and power consumption of the FPGA design are further optimized, and the accuracy and robustness of the edge detection algorithm are improved. For the optimization of the FPGA design, higher-level synthesis and layout tools are used to achieve a faster and more efficient design process. At the same time, different FPGA devices and architectures are used to further improve the performance and power efficiency of the design. In addition, a parallel design method is adopted to utilize the parallel computing capabilities of the FPGA to further improve the speed and efficiency of edge detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0034] Figure 1 Schematic diagram of the connection of the image edge detection processing system in the embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0038] In the description of the embodiments of the present invention, it should be noted that if the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when used. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0039] In the description of the embodiments of the present invention, "plurality" means at least 2.

[0040] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] Embodiment 1: In order to solve the problem that the algorithm based on convolution operation in the current edge detection algorithm based on FPGA has a slow operation speed, which is not conducive to real-time processing; therefore, how to further improve the efficiency and speed of edge detection by optimizing the algorithm, while reducing the power consumption of the system to ensure the edge detection effect, further improve the speed and efficiency of edge detection, the embodiment of the present application provides an image edge detection processing system based on FPGA, such as Figure 1 As shown, including:

[0042] The image acquisition module is used to obtain the processed image to be edge detected; wherein the above-mentioned image acquisition module is a camera of model OV7670.

[0043] Among them, OV7670 is a commonly used CMOS image sensor with advantages such as high resolution and low power consumption. It has been widely used in the field of digital image processing. When using OV7670 for image acquisition, it is necessary to perform timing and configuration work. For the timing control of OV7670, it is necessary to use a hardware-based configuration method and implement it through FPGA or other embedded systems. This process needs to take into account multiple parameters such as the clock signal, data line, frame synchronization signal of OV7670 to ensure that the image data can be transmitted and collected correctly. Secondly, for the configuration of OV7670, you can use I 2 C bus or SPI bus (depending on the specific model). During the configuration process, it is necessary to set various parameters of OV7670, including image output format, resolution, exposure time, gain and white balance; these parameters can be set by reading and writing corresponding registers, and can be optimized and adjusted according to specific application scenarios and requirements.

[0044] Specifically, for the configuration of OV7670, you need to pay attention to the following points: First, you need to ensure that the I 2 C bus or SPI bus to match the communication rate of OV7670; since the maximum clock frequency of OV7670 is 24MHz, 2 When communicating via C or SPI, it is necessary to set a suitable transmission rate to avoid data transmission errors. Secondly, when setting parameters, it is necessary to select the appropriate image output format and resolution according to the specific application scenario; different image output formats and resolutions will affect the quality of the acquired image and processing efficiency, so they need to be selected according to actual needs. In addition, it is also necessary to set parameters such as exposure time, gain, and white balance according to actual conditions. These parameters can affect aspects such as image brightness, contrast, and color balance, so they need to be adjusted and optimized according to specific application scenarios and needs.

[0045] Optional. Since FPGA is a programmable logic device, it requires a stable power supply. Usually, the power supply of the FPGA system includes two parts: core power supply and IO power supply. The core power supply is mainly used to provide power to the inside of the FPGA chip, and is usually stabilized by a DC-DC converter or a linear regulator to provide a stable and high-quality power supply. Capacitors, inductors and other components may also be used in the design for filtering and noise reduction to further improve the power quality. The IO power supply is mainly used to provide power for the input and output interfaces of the FPGA chip, so its voltage level and current capacity need to be configured according to the specific IO interface type and usage scenario. Usually the IO power supply is designed separately from the core power supply, and an independent voltage stabilization solution is used to avoid electromagnetic interference from the IO interface to the core power supply.

[0046] Furthermore, the above system also includes: an image storage module, used to store the processed image acquired by the image acquisition module; wherein the type of the above image storage module is SDRAM.

[0047] Specifically, SDRAM (Synchronous Dynamic Random-Access Memory) is a commonly used memory type that plays an important role in FPGA design; SDRAM is a synchronous dynamic random access memory with large capacity and high-speed data transmission capabilities. Data reading and writing operations can be achieved through a synchronized clock, and data can be stored and retrieved on demand. FPGAs usually communicate with SDRAM through controllers and interface circuits; these interface circuits are responsible for generating and receiving the timing signals and control signals required to communicate with SDRAM to ensure correct data transmission and storage operations.

[0048] Since SDRAM is based on synchronous clock for data transmission, clock synchronization must be ensured in FPGA design. The capacity and bandwidth of SDRAM are important factors to consider during design. FPGA designers need to select the appropriate SDRAM capacity and type based on application requirements and resource constraints to meet data storage and processing requirements.

[0049] Furthermore, the above system also includes: an image processing module, which is used to preprocess the processed image stored in the image storage module, and is also used to perform edge detection on the processed image after preprocessing; wherein the preprocessing includes denoising processing, smoothing processing and enhancement processing.

[0050] Among them, the processed image is preprocessed including denoising, smoothing and enhancement to extract clearer image features that are more conducive to edge detection; specifically, denoising is an important step in image preprocessing. Images usually carry various noises, such as Gaussian noise, salt and pepper noise, etc.; in the denoising process, we need to use some filters to eliminate these noises. Smoothing can be achieved using a series of convolution kernels. The most common convolution kernels include mean convolution kernels and Gaussian weighted convolution kernels. The mean convolution kernel can be achieved by taking the average value of the neighborhood around each pixel. Gaussian weighted convolution kernels are similar to Gaussian filters, but they not only consider distance, but also the grayscale difference between pixels. Therefore, Gaussian weighted convolution kernels can better retain edge information. Enhancement is another important step in image preprocessing. Contrast stretching technology can be used to make the color of the image more vivid, making the edges easier to detect.

[0051] Furthermore, in the implementation of FPGA, these preprocessing operations can use the reconfigurable nature of digital signal processing (DSP) modules, making it an efficient image processing platform. By implementing different preprocessing algorithms on FPGA, it is possible to quickly adapt to different image features and application scenarios, and the use of hardware resources can be optimized as needed, thereby improving system performance. In addition, FPGA-based image edge detection involves a large amount of calculation and data transmission, and the real-time and resource consumption of the system need to be considered. In order to ensure the real-time performance of the system, factors such as hardware delay and throughput need to be considered when designing and optimizing the algorithm, and some optimization techniques need to be used to reduce the response time of the system. At the same time, resource consumption is also a key issue because the number of DSP modules and available resources of FPGA are limited. When designing the algorithm, it is necessary to minimize the use of hardware resources and take into account system performance to achieve efficient image processing and edge detection.

[0052] Specifically, when performing filtering, Gaussian filtering can be used to smooth the image and reduce noise to provide better edge detection results. The following are the general steps of Gaussian filtering in image edge detection:

[0053] (1) Define the Gaussian kernel. First, the size and standard deviation of the Gaussian filter need to be determined; the Gaussian kernel is a two-dimensional matrix, usually square, and its size depends on the desired degree of smoothing.

[0054] (2) Convolution operation. The defined Gaussian kernel is applied to each pixel on the image. For each pixel, the Gaussian kernel is convolved with its surrounding neighborhood to calculate the weighted average. The convolution operation can be implemented using discrete convolution operations. Generally, a 3×3 matrix is ​​selected for weighting: After weighting the pixels at the center of the image, we get:

[0055]

[0056] (3) Edge preservation. Gaussian filtering will blur edge information while smoothing the image, so edge preservation is required. A common method is to calculate the difference between the original image and the smoothed image to obtain edge information.

[0057] Among them, the role of Gaussian filtering in image edge detection is to remove noise and details and smooth the image. This helps to provide a more reliable input for the algorithm. It should be noted that Gaussian filtering is a linear smoothing filter, which is not only used in image edge detection, but also can be used for other image processing tasks, such as image enhancement and blurring effects. The selection of specific Gaussian filter parameters should be adjusted according to the specific application scenario and image characteristics.

[0058] Optionally, the above edge detection is specifically:

[0059] S11, converting the pre-processed processed image into a grayscale image in YCbCr format.

[0060] When converting the processed image of RGB565 image data into grayscale image data in YCbCr format, it is necessary to add 0 to the end of RGB565 to convert it into image data in RGB888 format, and then convert it to YCbCr color space; YCbCr is an 8-bit 3-channel format, Y represents the brightness component, Cb and Cr represent the chromaticity information of blue and red respectively. When performing grayscale conversion here, only the information of the Y component needs to be retained, so as to complete the grayscale conversion of the image from three channels to single channel. The conversion relationship is: Y = 0.299R + 0.587G + 0.114B.

[0061] Specifically, when FPGA is implemented in hardware, floating-point operations will consume too many logic resources. Therefore, the floating-point number is first enlarged by 256 times and the decimal part is discarded, and then right-shifted by 8 bits to restore it, as shown in the following formula:

[0062] Y=77R+150G+29B; Y=77R+150G+29B>>8; In the above formulas, Y represents the Y component in the YCbCr color space, and R, G, and B respectively represent the R component, G component, and B component of the processed image in the RGB space.

[0063] S12, obtaining image pixels of each pixel point in the grayscale image through a sliding window of a preset size, and calculating the gradient amplitude of each pixel point in the grayscale image using the image pixels of each pixel point and a convolution factor template preset based on multiple directions.

[0064] Specifically, the number of gradient directions can be 6, the window size can be 3×3, and the gradient value can be obtained by convolving the pixel value obtained by the 3×3 sliding window with the convolution factor template in 6 directions. The absolute value average of the calculated gradients in each direction is then used as the gradient amplitude of the pixel.

[0065] The above method further comprises:

[0066] S121, using the image pixels of each pixel point and the preset convolution factor template based on multiple directions, calculate the gradient value of each pixel point in each direction.

[0067] Among them, the horizontal gradient G is calculated x Take the gradient value on as an example:

[0068] In the formula, Represents the pixel values ​​obtained by the 3×3 sliding window, It represents the convolution factor template preset in the horizontal gradient direction.

[0069] Furthermore, the corresponding angles of the above six gradient directions may be 0°, 60°, 120°, 180°, 240°, and 300°, respectively; and the convolution factor templates corresponding to the six gradient directions may be:

[0070]

[0071] S122, using the gradient value of each pixel in each direction, calculate the gradient amplitude of each pixel.

[0072] Optionally, the gradient amplitude of each pixel is specifically:

[0073]

[0074] Where G represents the gradient amplitude of one pixel, G1 represents the gradient value of the pixel in one direction, and n represents the number of directions for calculating the gradient value of the pixel.

[0075] Among them, when the gradient direction is the above 6, the calculation formula of the gradient amplitude of the pixel point is expressed as:

[0076] Where G1, G2, G3, G4, G5, and G6 represent the gradient values ​​of the pixel in the six gradient directions of 0°, 60°, 120°, 180°, 240°, and 300°, respectively.

[0077] S13, performing non-maximum suppression processing on the gradient amplitude of each pixel in the grayscale image, and determining the grayscale image after the non-maximum suppression processing as the processing result of edge detection.

[0078] Optionally, the above non-maximum suppression process is specifically as follows:

[0079] The gradient amplitude of each pixel point is compared with the gradient amplitudes of multiple adjacent points of the pixel point in the gradient direction. If the gradient amplitude of the pixel point is greater than the gradient amplitudes of the adjacent points, the pixel of the pixel point is retained, otherwise the pixel of the pixel point is adjusted to 0.

[0080] Among them, in order to reduce noise and effectively retain the edge information in the image, in this embodiment, 3 directions are selected from the original 6 directions for non-maximum suppression algorithm; the edge is extracted by finding the local maximum point in the gradient direction of the pixel point, and the edge of the remaining non-maximum points is suppressed; specifically, the gradient amplitude of each pixel point is compared with the gradient amplitudes of its two adjacent pixel points in the gradient direction. If it is greater than the gradient amplitude of its adjacent pixels, the pixel is retained, otherwise, it is set to 0.

[0081] Furthermore, the system further comprises: an image display module, which is used to display the processed image after edge detection, wherein the image display module is a VGA display module.

[0082] Specifically, the VGA display module is a hardware module for image display, which is commonly used in FPGA-based image processing and embedded systems. The following are the functions that the VGA display module needs to use in this embodiment:

[0083] (1) Input interface. VGA display modules usually have multiple input interface options, such as FPGA internal memory, external memory, image sensor or other image sources; these interfaces can receive image data in different formats, such as RGB, YUV, etc., and pass it to the VGA display module.

[0084] (2) Image processing. VGA can perform image processing. These processing operations can optimize and adjust the image to suit the requirements of the display device and user needs.

[0085] (3) Resolution and refresh rate control. The resolution and refresh rate of the output image can be adjusted according to the specification requirements of the display device. This allows the VGA display module to adapt to different display devices and provide the best image quality and performance.

[0086] (4) Color depth and palette. The VGA display module supports different color depths, such as 8-bit, 16-bit, 24-bit, etc. It can also use palette technology to map the color of the input image to the color range supported by the display device to achieve richer color expression.

[0087] (5) Double buffering. VGA display modules usually have a double buffering function, where one buffer is used for image processing and display, and the other buffer is used to receive new image data. This mechanism can avoid image flickering and unstable display effects.

[0088] (6) Output interface: The VGA display module sends the processed image data to the VGA monitor through the standard VGA output interface to achieve accurate image display.

[0089] Furthermore, the above system also includes: a system clock module, which is used to synchronize the reference clock signal of each module operation.

[0090] Specifically, in the FPGA-based image edge detection processing system proposed in this embodiment, the setting of the system clock plays a vital role in the performance and function of the entire system; the system clock refers to the reference clock signal used to synchronize the operation of each module. Reasonable setting of the system clock can ensure the correct timing relationship between the modules and avoid clock conflicts and data errors. In FPGA, a stable external clock source can be used as the system clock. This external clock source is usually provided by a crystal oscillator, and its frequency is called the system clock frequency. During the design process, it is necessary to select a suitable system clock frequency based on system requirements and hardware platform limitations. In this embodiment, 50MHz is selected.

[0091] Among them, for the clock setting of each module, the clock divider can be divided; this can simplify the clock wiring and reduce the complexity of the clock network. Since each module may have different requirements for different operations and processing speeds, in order to simplify the clock design and meet the needs of each module, the frequency of the system clock can be divided into a module clock frequency of 25MHz. In this way, each module can perform operations and process data according to the clock frequency of 25MHz, so as to better adapt to the functions and performance requirements of each module; specifically, when setting the clock frequency of each module, it is also necessary to consider the data transmission speed, computing requirements and timing requirements between modules; the appropriate module clock frequency can be selected according to the workload and performance requirements of the module. At the same time, it is also necessary to ensure that the clock frequency of each module can meet the overall performance and timing requirements of the system to ensure the normal operation of the system.

[0092] Specifically, the function of the above-mentioned system clock module can be realized by a phase-locked loop (PLL). PLL is a circuit system. In FPGA design, the phase-locked loop can be used to generate stable clock signals, frequency synthesis and clock adjustment and other functions; the phase-locked loop adjusts the output signal frequency and phase based on a feedback control mechanism. It contains a phase comparator, a low-pass filter and a controllable oscillator. Among them, the phase-locked loop can generate a stable clock signal inside the FPGA by inputting an external reference clock into the phase-locked loop, which is used to synchronize the operation of each module. By adjusting the parameters in the phase-locked loop, the output clock frequency and phase can be fine-tuned and precisely controlled. The phase-locked loop plays an important role in digital system design, and can provide stable clock signals and frequency synthesis functions to meet complex timing requirements and clock synchronization requirements.

[0093] In this embodiment, the FPGA development board and its RTL circuit may adopt the MP801 development board.

[0094] Embodiment 2: The embodiment of the present application provides an application of an FPGA-based image edge detection processing system as described in any one of Embodiments 1 in image edge detection.

[0095] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An image edge detection processing system based on FPGA, characterized in that: include: An image acquisition module, used to obtain a processed image to be edge detected; An image storage module, used for storing the processed image acquired by the image acquisition module; An image processing module, used for preprocessing the processed image stored in the image storage module, and for performing edge detection on the processed image after preprocessing; An image display module, used for displaying the processed image after edge detection; The system clock module is used to synchronize the reference clock signal of each module operation.

2. The FPGA-based image edge detection processing system according to claim 1, characterized in that: The image acquisition module is a camera of model OV7670.

3. The FPGA-based image edge detection processing system according to claim 1, characterized in that: The type of the image storage module is SDRAM.

4. The FPGA-based image edge detection processing system according to claim 1, characterized in that: The image display module is a VGA display module.

5. The FPGA-based image edge detection processing system according to claim 1, characterized in that: The preprocessing includes denoising, smoothing and enhancing.

6. An FPGA-based image edge detection processing system according to any one of claims 1 to 5, characterized in that: The edge detection is specifically as follows: Convert the preprocessed processed image into a grayscale image in YCbCr format; Obtaining image pixels of each pixel point in the grayscale image through a sliding window of a preset size, and calculating the gradient amplitude of each pixel point in the grayscale image using the image pixels of each pixel point and a convolution factor template preset based on multiple directions; The non-maximum suppression process is performed on the gradient amplitude of each pixel in the grayscale image, and the grayscale image after the non-maximum suppression process is determined as the processing result of edge detection.

7. The FPGA-based image edge detection processing system according to claim 6, characterized in that: The method further comprises: The gradient value of each pixel in each direction is calculated by using the image pixels of each pixel and the preset convolution factor template based on multiple directions; The gradient value of each pixel in each direction is used to calculate the gradient amplitude of each pixel.

8. The FPGA-based image edge detection processing system according to claim 7, characterized in that: The gradient amplitude of each pixel is specifically: Where G represents the gradient amplitude of one pixel, G1 represents the gradient value of the pixel in one direction, and n represents the number of directions for calculating the gradient value of the pixel.

9. The FPGA-based image edge detection processing system according to claim 8, characterized in that: The non-maximum suppression process is specifically as follows: The gradient amplitude of each pixel point is compared with the gradient amplitudes of multiple adjacent points of the pixel point in the gradient direction. If the gradient amplitude of the pixel point is greater than the gradient amplitudes of the adjacent points, the pixel of the pixel point is retained; otherwise, the pixel of the pixel point is adjusted to 0.

10. Application of an FPGA-based image edge detection processing system according to any one of claims 1 to 9 in image edge detection.

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