Memory drive circuit and memory
By adding a control unit to the SRAM memory, the on-off between the word line and the memory unit is adaptively controlled, the problem of frequent pseudo-read operations is solved, and the stability of the memory is improved and power consumption is reduced.
Patent Information
- Application Number
- CN202411473925.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-02-11
AI Technical Summary
In existing SRAM memory, due to the increasing number of columns of multiplexers, pseudo-read operations are frequent, increasing circuit leakage current and power consumption, and at the same time, the stability of the storage unit is reduced, and the risk of data flip is higher.
Add a control unit between the word line and the row control end of the memory unit, and adaptively control the on-off between the word line and the memory unit through the column decoding signal, ensuring that only the memory units that are fully selected for the word line and bit line can be read Write operations to eliminate the possibility of false reading damage.
It effectively avoids the risk of data flip caused by pseudo-reading, improves memory stability, and reduces memory power consumption.
Smart Images
Figure CN119418740A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a memory driving circuit and a memory. Background Art
[0002] Static Random-Access Memory (SRAM) is a type of random access memory. Figure 1 As shown in the circuit diagram on the left, a typical SRAM memory has tens of thousands or millions of words, but each word has only 8 to 64 bits, which makes its layout tall and thin, making it difficult to fit into the chip plane layout, and the long vertical wiring reduces its speed. Therefore, SRAM is often folded into fewer rows but more columns, that is, MUX (multiplexer) is introduced, and the resulting drive circuit is as follows Figure 1 The circuit diagram is shown on the right.
[0003] Figure 2 and Figure 3 FIG. 2 schematically shows a structure of a memory driving circuit in the prior art. Figure 2 and Figure 3 As shown in the figure, taking the multiplexer controlling 4 columns as an example, the multiplexer receives the column decoding signal MUX<0:3>, and outputs the read column decoding signal YSR<0:3> and the write column decoding signal YSW<0:3>. The memory cells in the memory cell array are arranged in multiple rows, each row is connected to the same word line WL, and each column is connected to the same bit lines BL and BLB. Assuming that the decoding selects memory cell 0 for the read operation, the word line WL <0> Set high potential and read column decoding signal YSR <0> Set low potential and write column decoding signal YSW <0> The PG transistor corresponding to memory cell 0 is turned on for read operation and output. At the same time, memory cells 1 to 3 are in the semi-selected cell state where the word line is selected. They will also be read, but will not be output. Here, the memory cell read operation but not output is called pseudo read. This large number of pseudo read operations is accompanied by the risk of storage data flipping and will cause the circuit leakage current to increase. Assume that the decoder selects memory cell 0 for write operation and sets the word line WL <0> Set the potential high, similar to the read operation, the memory cells 1 to 3 in the half-selected cell state will also be pseudo-read. In addition, with the evolution of technology nodes, on the one hand, the stability of the memory cell is reduced, and the introduction of read-write assist technology (such as word line overdrive technology) leads to a higher risk of pseudo-read damage; on the other hand, the number of columns required for the multiplexer increases (such as the number of columns = 16, 32, etc.), which leads to a further increase in the risk of data flipping and additional power consumption caused by pseudo-reading.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] In response to the problems in the prior art, the purpose of the present application is to provide a memory driving circuit and a memory, by adding a control unit between the word line and the row control terminal of the memory cell, adaptively controlling the on-off between the word line and the memory cell through a column decoding signal, ensuring that only the memory cell fully selected by the word line and the bit line can perform read and write operations, eliminating the possibility of false read damage without affecting normal reading and writing, and reducing the power consumption of the memory.
[0006] The present application provides a memory driving circuit, including:
[0007] A memory cell array, comprising a plurality of memory cells arranged in a plurality of rows and columns;
[0008] A row decoder, used for outputting a row decoding signal to a word line corresponding to each row of the storage cells;
[0009] A column decoder, used for outputting a column decoding signal;
[0010] a multiplexer configured to receive a column decoding signal of the column decoder and output a column control signal for controlling a column control terminal of each column of the storage unit, wherein the column control signal is input to the column control terminal of each column of the storage unit through a bit line;
[0011] A control unit array includes a plurality of control units arranged in a plurality of rows and columns, wherein the control units correspond to the storage cells, the control units are connected between the corresponding word lines and the row control terminals of the corresponding storage cells, and the control units are configured to control the on / off between the word lines and the row control terminals of the storage cells in response to the column decoding signals.
[0012] In some embodiments, each of the control units includes a first transistor, which is connected between a corresponding word line and a row control terminal of a corresponding memory cell, and the first transistor is configured to control the on / off between the word line and the row control terminal of the memory cell in response to the column decoding signal.
[0013] In some embodiments, each of the control units further includes a second transistor connected between a ground line and a row control terminal of the storage unit, and the second transistor is configured to control the on / off between the ground line and the row control terminal of the storage unit in response to the column decoding signal.
[0014] In some embodiments, the second transistor is an NMOS transistor, and a gate of the second transistor inputs the column decoding signal.
[0015] In some embodiments, the first transistor is a PMOS transistor, and a gate of the first transistor inputs the column decoding signal.
[0016] In some embodiments, the memory cell comprises a PG transistor, a row control terminal of the memory cell is a gate of the PG transistor, and a column control terminal of the memory cell is a source or a drain of the PG transistor.
[0017] In some embodiments, the control unit corresponds one-to-one to the storage unit.
[0018] In some embodiments, the column control signal includes a read column decode signal and a write column decode signal.
[0019] In some embodiments, the memory is static random access memory.
[0020] An embodiment of the present application also provides a memory, comprising the above-mentioned memory driving circuit.
[0021] The memory driving circuit and memory provided in this application have the following advantages:
[0022] By adopting the present application, a control unit is added between the word line and the row control end of the storage unit, and the on-off between the word line and the storage unit is adaptively controlled through the column decoding signal, ensuring that only the storage unit fully selected by the word line and the bit line can perform read and write operations, eliminating the possibility of false reading damage without affecting normal reading and writing, avoiding the risk of data flipping caused by false reading, improving the stability of the memory, and reducing the power consumption of the memory.
[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings. The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative work.
[0025] Figure 1 It is a schematic diagram of adding a multiplexer to a memory driving circuit;
[0026] Figure 2 It is a partial schematic diagram of a memory driving circuit in the prior art;
[0027] Figure 3 It is a schematic diagram of a memory driving circuit in the prior art;
[0028] Figure 4 A control schematic diagram of a single control unit according to an embodiment of the present application;
[0029] Figure 5 is a schematic diagram of a memory driving circuit according to an embodiment of the present application. DETAILED DESCRIPTION
[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. In the figures, the same reference numerals represent the same or similar structures, and thus their repeated description will be omitted. "or" and "or" in the specification may both mean "and" or "or".
[0031] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.
[0032] In SRAM memory, the memory cell row is controlled by the word line, and the data is transmitted through the bit line. The word line (WordLine) is the control line used to select the memory cell row in the memory. When a specific word line is activated, a row of memory cells connected to the word line is selected. The bit line (Bit Line) is the line used to transmit data in the memory. Each column of memory cells is connected to a bit line, which is responsible for transmitting data bits between the memory cell and the external circuit. The data in the memory cell can be read out to the outside, and the external data can be written into the memory cell. In the read operation, when the corresponding word line is activated, the data in the memory cell is transmitted to the external circuit for processing through the bit line. During the write operation, the external data is written to the memory cell corresponding to the selected word line through the bit line. The memory cell in which the word line and the bit line are selected at the same time is called a selected cell, and the memory cell in which only the word line or the bit line is selected is called a half-selected cell. Such as Figure 2 As shown, assuming that the word line and the bit line simultaneously select the memory cell 0 for read and write operations, the memory cell 0 is called the selected cell, and the memory cells 1 to 3 that share the word line WL(0) with the selected cell are called half-selected cells. Since the PG transistor in the memory cell is turned on to perform a read operation, the memory cell 4 that shares the bit line with the selected cell is also a half-selected cell, but will not perform a read operation, and does not involve the problem of pseudo read. The subsequent half-selected cell specifically refers to the memory cell that shares the word line with the selected cell.
[0033] When the existing selection unit is turned on, the half-selected unit of the shared word line will also perform a read operation but will not output it in the end. There are a large number of pseudo read operations, which will cause the risk of storage data flipping and increase the circuit leakage current, thereby additionally increasing the power consumption of the memory. In view of the technical problems in the prior art, the embodiment of the present application provides a memory driving circuit, including a memory cell array, a row decoder, a column decoder and a multiplexer. The memory cell array includes a plurality of memory cells arranged in multiple rows and columns. The memory cell array is the core part of the memory. Each memory cell is usually composed of a plurality of transistors for storing one bit of binary data. The row decoder is used to output a row decoding signal to the word line corresponding to each row of the memory cell. The column decoder is used to output a column decoding signal. The multiplexer is configured to receive the column decoding signal of the column decoder and output a column control signal for controlling the column control end of each column of the memory cell, and the column control signal is input to the column control end of each column of the memory cell through the bit line. The row decoder and the column decoder are used to convert the input address signal into a selection signal of the memory cell so as to select a specific memory cell for read and write operations.
[0034] Under the control of the memory drive circuit, the memory can perform specific read and write operations. When performing a write operation, external data is transferred to the storage unit through the data input buffer. The address decoder selects a specific storage unit according to the input address signal, and the read-write control circuit sets the control signal to the write mode, so that the storage unit stores the input data. When performing a read operation, the address decoder selects a specific storage unit according to the input address signal, and the read-write control circuit sets the control signal to the read mode. The data in the storage unit is transferred to the external circuit through the data output buffer for use by other devices.
[0035] Figure 4 Detailed description of the control principle block diagram of a storage unit in the memory driving circuit provided in an embodiment of the present application is shown in FIG. Figure 5 FIG. 1 shows a schematic diagram of a memory driving circuit provided by an embodiment of the present application. Figure 4 and Figure 5 As shown, the memory driving circuit further includes a control unit array, including a plurality of control units arranged in multiple rows and columns, and the control units correspond to the storage units. In this embodiment, the control units correspond to the storage units one by one, and each control unit controls a storage unit separately. The control unit is connected between the corresponding word line and the row control terminal of the corresponding storage unit, and the control unit is configured to control the on-off between the word line and the row control terminal of the storage unit in response to the column decoding signal.
[0036] The row decoder contains a series of logic gate circuits, which convert the input row address binary code into the corresponding row decoding signal output according to a specific decoding algorithm. When a row decoding signal is activated, it will open the connection channel between the storage unit of the corresponding row and the bit line, so that the data in the row storage unit can be read out or new data can be written into the row storage unit. The column decoding signal is a control signal used to select a specific storage unit column in a digital circuit system such as a memory. In a memory, the address bus is usually divided into two parts: the row address and the column address. When a storage access request arrives, the address decoder first receives the address signal. For the column address part, the column decoder performs a decoding operation. The column decoder converts the input column address binary code into the corresponding column decoding signal output according to a specific logic circuit design. When a column decoding signal is activated, it will open the connection channel between the storage unit of the corresponding column and the data bus, so that the data in the column storage unit can be read out or new data can be written into the column storage unit.
[0037] By adopting the present application, a control unit is added between the word line and the row control terminal of the storage unit, and the on-off between the word line and the storage unit is adaptively controlled by the column decoding signal, ensuring that only the storage unit fully selected by the word line and the bit line can perform read and write operations, eliminating the possibility of false reading damage without affecting normal reading and writing, avoiding the risk of data flipping caused by false reading, improving the stability of the memory, and reducing the power consumption of the memory. The memory of the present application is, for example, a static random access memory, but the present application is not limited to this. In other alternative embodiments, the memory may also be other types of memories, not limited to those listed in the present application, and all belong to the protection scope of the present application.
[0038] like Figure 5 As shown, each memory cell includes a PG (Pass Gate) transistor. The PG transistor plays a role in controlling the reading and writing of data in the memory cell. During a read operation, the PG transistor is turned on to transfer the data in the memory cell to the column line. During a write operation, the PG transistor is also turned on to write external data into the memory cell. The row control terminal of the memory cell is the gate of the PG transistor, and the column control terminal of the memory cell is the source or drain of the PG transistor. Figure 5 In the example, a multiplexer connected to four columns of storage units is used. The column decoding signal is Figure 5 The column control signal includes a read column decoding signal ( Figure 5 YSR<0:3>) and the write column decode signal ( Figure 5 In the Figure 5 In FIG. 1 , the word lines are labeled WL<0:3>. Figure 5 In the memory cell, the bit line is marked as BL / BLB. BL is a line used to transmit data in the memory cell. During the read operation, the data in the memory cell is connected to the bit line through the PG transistor, and then transmitted to the subsequent circuit (such as the sense amplifier) for amplification and processing. During the write operation, the external data is written into the memory cell through the bit line. BLB is the complementary bit line of BL. BL and BLB work together to transmit and store data. When the data in the memory cell is "1", BL is a high potential and BLB is a low potential; when the data in the memory cell is "0", BL is a low potential and BLB is a high potential. The existence of BLB can improve the reliability and anti-interference ability of the data. By comparing the levels of BL and BLB, errors in data transmission can be detected and corrected.
[0039] like Figure 5 As shown, in this embodiment, each of the control units includes a first transistor. The first transistor is, for example, a PMOS tube. Figure 5Indicated as WLPMOS. PMOS (P-type metal oxide semiconductor field effect transistor) consists of a P-type substrate, two N-type regions (source and drain) and an insulated gate. The two N-type regions formed on the P-type substrate serve as the source and drain respectively, and the gate is separated from the substrate and the source and drain by an insulating layer. When a low potential is applied to the gate of the PMOS, the PMOS tube is turned on, allowing current to flow from the source to the drain. The gate of the first transistor inputs the column decoding signal. The first transistor is connected between the corresponding word line and the row control terminal of the corresponding storage unit, and the first transistor is configured to control the on and off between the word line and the row control terminal of the storage unit in response to the column decoding signal.
[0040] like Figure 5 As shown, in this embodiment, each of the control units further includes a second transistor. The second transistor is an NMOS tube. Figure 5 The column decoding signal is input to the gate of the second transistor. When a high potential is applied to the gate of the NMOS (N-type metal oxide semiconductor field effect transistor), the NMOS tube is turned on, allowing current to flow from the source to the drain. The second transistor is connected to the ground line ( Figure 5 The second transistor is configured to control the connection between the ground line and the row control terminal of the memory cell in response to the column decoding signal.
[0041] Combine the following Figure 5 The specific process of the read operation and write operation of the memory driving circuit is specifically introduced. After adding the control unit, the process of the read operation includes: taking the address bit to select the storage unit 0 for the read operation as an example, BL / BLB is precharged. <0> Set to high potential. Column decoding signal MUX <0> Set to low potential. Read column decoding signal YSR <0> The first transistor WLPMOS corresponding to the memory cell 0 is turned on in response to the column decoding signal, and the word line WL <0> The gate of the PG transistor of memory cell 0 is turned on to ensure that only the PG transistor of memory cell 0 is turned on and only memory cell 0 is read. After the read operation is completed, the column decoding signal MUX <0> The second transistor WLNMOS is set to a high potential, and is turned on by the adaptive column decoding signal, and the gate of the PG transistor is turned on to the ground line, and the PG transistor is turned off, and the read operation of the memory cell 0 is stopped. Since the first transistors of the memory cells 1 to 3 as the half-selected units remain turned off during the read operation of the memory cell 0 as the half-selected unit, the PG transistors of the memory cells 1 to 3 are not turned on, which effectively prevents the occurrence of pseudo reads, eliminates the damage to the memory performance caused by pseudo reads, eliminates the risk of data flipping caused by pseudo reads, makes the memory more stable, and reduces the overall power consumption of the memory.
[0042] After adding the control unit, the write operation process includes: taking the address bit to select storage unit 0 for write operation as an example, BL / BLB is precharged. <0> Set to high potential. Column decoding signal MUX <0> Set to low potential. Write column decoding signal YSW <0> The first transistor WLPMOS corresponding to the memory cell 0 is turned on in response to the column decoding signal, and the word line WL <0> The gate of the PG transistor of memory cell 0 is turned on to ensure that only the PG transistor of memory cell 0 is turned on and only memory cell 0 is written. After the write operation is completed, the column decoding signal MUX <0> The second transistor WLNMOS is set to a high potential, and is turned on by the adaptive column decoding signal, and the gate of the PG transistor is turned on to the ground line, and the PG transistor is turned off, and the write operation of the memory cell 0 is stopped. Since the first transistors of the memory cells 1 to 3 as the half-selected units remain turned off during the write operation of the memory cell 0 as the half-selected unit, the PG transistors of the memory cells 1 to 3 are not turned on, which effectively prevents the occurrence of pseudo reads, eliminates the damage to the memory performance caused by pseudo reads, eliminates the risk of data flipping caused by pseudo reads, makes the memory more stable, and reduces the overall power consumption of the memory.
[0043] By adopting the memory driving circuit of the present application, the column decoding signal already existing in the existing memory driving circuit is used to adaptively control the conduction and shutdown of the control unit, without adding other control signals, and only two transistors need to be added at each memory cell to realize the separate read and write control of each memory cell. The overall structure is simple, the change to the existing driving circuit is small, and the feasibility is higher. In the above embodiment, the first transistor is PMOS and the second transistor is NMOS as an example for explanation, but the present application is not limited to this. According to the different designs of the memory driving circuit, the types of the first transistor and the second transistor can be selected and adjusted according to actual needs, and are not limited to those listed here, and all belong to the protection scope of the present application.
[0044] After adopting the memory driving circuit of the present application, a simulation test was performed on the memory, and the simulation test results are shown in Table 1 below.
[0045] Table 1 Simulation test results
[0046]
[0047] It can be seen from Table 1 above that after adopting the driving circuit of the present application, the noise margin is improved by 105%, and the transient power consumption is reduced by 41% (taking the multiplexer connected to four columns of storage cells as an example). As the number of columns of storage cells connected to the multiplexer increases further, the transient power consumption reduction effect will be more significant. The memory using the driving circuit of the present application can better adapt to the future development trend of memory.
[0048] The embodiment of the present application also provides a memory, including the above-mentioned memory driving circuit. The memory is, for example, a static random access memory or other types of memory. The static random access memory has a very fast read and write speed, has relatively low power consumption, and has been widely used. By adopting the present application, a control unit is added between the word line and the row control end of the memory cell, and the on and off between the word line and the memory cell is adaptively controlled by the column decoding signal, ensuring that only the memory cell fully selected by the word line and the bit line can perform read and write operations, eliminating the possibility of false read damage without affecting normal reading and writing, and reducing the power consumption of the memory.
[0049] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.
Claims
1. A memory driving circuit, characterized in that: include: A memory cell array, comprising a plurality of memory cells arranged in a plurality of rows and columns; A row decoder, used for outputting a row decoding signal to a word line corresponding to each row of the storage cells; A column decoder, used for outputting a column decoding signal; a multiplexer configured to receive a column decoding signal of the column decoder and output a column control signal for controlling a column control terminal of each column of the storage unit; A control unit array includes a plurality of control units arranged in a plurality of rows and columns, wherein the control units correspond to the storage cells, the control units are connected between the corresponding word lines and the row control terminals of the corresponding storage cells, and the control units are configured to control the on / off between the word lines and the row control terminals of the storage cells in response to the column decoding signals.
2. The memory driving circuit according to claim 1, characterized in that: Each of the control units includes a first transistor connected between a corresponding word line and a row control terminal of a corresponding storage unit, and configured to control the on / off between the word line and the row control terminal of the storage unit in response to the column decoding signal.
3. The memory driving circuit according to claim 2, characterized in that: Each of the control units further includes a second transistor connected between a ground line and a row control terminal of the storage unit, and the second transistor is configured to control the connection and disconnection between the ground line and the row control terminal of the storage unit in response to the column decoding signal.
4. The memory driving circuit according to claim 3, characterized in that: The second transistor is an NMOS transistor, and the column decoding signal is input to the gate of the second transistor.
5. The memory driving circuit according to claim 2, characterized in that: The first transistor is a PMOS transistor, and the column decoding signal is input to the gate of the first transistor.
6. The memory driving circuit according to claim 1, characterized in that: The storage unit includes a PG transistor, a row control terminal of the storage unit is a gate of the PG transistor, and a column control terminal of the storage unit is a source or a drain of the PG transistor.
7. The memory driving circuit according to claim 1, characterized in that: The control unit corresponds to the storage unit in a one-to-one manner.
8. The memory driving circuit according to claim 1, wherein: The column control signal includes a read column decoding signal and a write column decoding signal.
9. The memory driving circuit according to claim 1, characterized in that: The memory is a static random access memory.
10. A memory, characterized in that: A memory driving circuit comprising the memory driving circuit according to any one of claims 1 to 9.