Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises an intermediary layer and a chip stacking structure, the intermediary layer comprises a chip setting area and a first electric connection area located at the periphery of the chip setting area, the chip stacking structure is arranged in the chip setting area, the chip stacking structure comprises a plurality of chips which are arranged in a stacked mode, and the first electric connection area is located at the periphery of the chip setting area. At least part of the chips are connected with the first electric connection area through wires. According to the semiconductor structure, the signal transmission distance between the chip and the first electric connection area can be effectively reduced, so that the signal transmission quality and the signal transmission speed are improved, and signal distortion and noise can be reduced. Besides, the chip and the first electric connection area do not need to be connected through structures such as solder balls and conductive bumps, so that the distance between the chip and the interposer can be effectively reduced, the thickness of the semiconductor structure is further reduced, and the integration level of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In order to meet the requirements of high functionality, high speed and miniaturization of electronic components, semiconductor packages are now mostly formed by stacking packaging technology. However, semiconductor packages formed by existing technologies have problems such as long signal paths and complex process. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] A first aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0005] An interposer, comprising a chip setting area and a first electrical connection area located outside the chip setting area;

[0006] A chip stacking structure is arranged in the chip setting area, and the chip stacking structure includes a plurality of chips that are stacked, wherein at least part of the chips are connected to the first electrical connection area through wires.

[0007] According to some embodiments of the present disclosure, the multiple chips include a bottom chip, a plurality of stacks are arranged on the bottom chip, each of the stacks includes a plurality of the stacked chips, and each of the chips in the stack is connected to the first electrical connection area through the wire.

[0008] According to some embodiments of the present disclosure, the bottom chip is connected to the first electrical connection area through the wire; or, the bottom chip is connected to the chip setting area through a conductive connection structure;

[0009] Each chip in the stack includes a second electrical connection area, the second electrical connection area is arranged near the edge of the chip, and one end of the wire is connected to the second electrical connection area;

[0010] The edges of the chips in the same stack are flush with each other; or, in two adjacent chips in the same stack, the second electrical connection region of the lower chip is exposed through the upper chip.

[0011] According to some embodiments of the present disclosure, the conductive connection structure includes a first conductive block disposed on the bottom chip and a second conductive block disposed in the chip setting area, and the first conductive block and the second conductive block are electrically connected.

[0012] According to some embodiments of the present disclosure, a first adhesive layer is provided between adjacent chips in the same stack; and / or,

[0013] A second adhesive layer is disposed between the stack and the bottom chip; and / or,

[0014] When the bottom chip is connected to the first electrical connection region through the wire, a third adhesive layer is disposed between the bottom chip and the interposer.

[0015] According to some embodiments of the present disclosure, the semiconductor structure further includes a carrier disposed on the interposer, the carrier being disposed at the periphery of the bottom chip, and the carrier and the bottom chip jointly supporting the plurality of stacked components.

[0016] A second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0017] forming an interposer, the interposer comprising a chip setting region and a first electrical connection region located outside the chip setting region;

[0018] A chip stacking structure is formed on the chip setting area, wherein the chip stacking structure includes a plurality of stacked chips, wherein at least part of the chips are connected to the first electrical connection area through wires.

[0019] According to some embodiments of the present disclosure, forming a chip stacking structure on the chip setting area includes:

[0020] Arranging a bottom chip in the chip arrangement area;

[0021] A plurality of stacks are arranged on the bottom chip, each of the stacks includes a plurality of the chips that are stacked, and each of the chips in the stack is connected to the first electrical connection area through the wire.

[0022] According to some embodiments of the present disclosure, a bottom chip is arranged in the chip arrangement area, including:

[0023] The bottom chip is arranged in the chip arrangement area through a third adhesive layer, and the bottom chip is connected to the first electrical connection area through a wire; or,

[0024] Bonding the bottom chip to the chip setting area through a bonding process;

[0025] Each chip in the stack includes a second electrical connection area, and the second electrical connection area is arranged near the edge of the chip. The plurality of stacks are arranged on the bottom chip, including:

[0026] When forming each stack, each time a layer of chips is arranged, the chips of the layer are connected to the first electrical connection area through a wire, and then the next layer of chips is arranged, and the edges of the chips in the same stack are flush; or

[0027] After each chip in each stack is stacked on the bottom chip, each chip in each stack is connected to the first electrical connection area through a wire. Among two adjacent chips in the same stack, the second electrical connection area of ​​the lower chip is exposed through the upper chip.

[0028] According to some embodiments of the present disclosure, before arranging a plurality of stacked components on the bottom chip, the method for manufacturing the semiconductor structure further includes:

[0029] A carrying portion is formed on the intermediary layer, the carrying portion is disposed at the periphery of the bottom chip, and the carrying portion is used to support the plurality of stacked components together with the bottom chip.

[0030] The semiconductor structure and the manufacturing method thereof provided by the embodiment of the present disclosure can effectively reduce the signal transmission distance between the chip and the first electrical connection area by connecting the chip to the first electrical connection area located outside the chip setting area through a wire, thereby reducing the signal loss during the transmission process, improving the signal transmission quality and signal transmission speed, and reducing signal distortion and noise. In addition, since there is no need to connect the chip and the first electrical connection area through structures such as solder balls and conductive bumps, the distance between the chip and the interposer can be effectively reduced, thereby reducing the thickness of the semiconductor structure and improving the integration of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a schematic diagram of the structure of a semiconductor package in the related art;

[0033] Figure 2 is a schematic structural diagram of a semiconductor structure for forming an interposer according to an exemplary embodiment;

[0034] Figure 3is a schematic structural diagram of a semiconductor structure forming a first conductive block, a second conductive block and a bottom chip according to an exemplary embodiment;

[0035] Figure 4 is a schematic structural diagram of a semiconductor structure for forming a first adhesive layer according to an exemplary embodiment;

[0036] Figure 5 is a schematic structural diagram of a semiconductor structure forming a chip and a wire connected to the chip according to an exemplary embodiment;

[0037] Figure 6 is a schematic structural diagram of a semiconductor structure for forming another first adhesive layer according to an exemplary embodiment;

[0038] Figure 7 is a schematic structural diagram of a semiconductor structure for forming other chips and wires connected to the chips according to an exemplary embodiment;

[0039] Figure 8 is a schematic structural diagram of a semiconductor structure for forming a packaging layer according to an exemplary embodiment;

[0040] Fig. 9 is a schematic structural diagram of a semiconductor structure for forming solder balls according to another exemplary embodiment;

[0041] Fig.10 is a schematic structural diagram of a semiconductor structure for forming a third adhesive layer according to another exemplary embodiment;

[0042] Fig.11 is a schematic structural diagram of a semiconductor structure forming a bottom chip according to another exemplary embodiment;

[0043] Fig.12 is a schematic structural diagram of a semiconductor structure for forming a conductive line connected to an underlying chip according to another exemplary embodiment;

[0044] Fig.13 is a schematic structural diagram of a semiconductor structure for forming a first adhesive layer according to another exemplary embodiment;

[0045] Fig.14 is a schematic structural diagram of a semiconductor structure for forming a wire connected to a chip according to another exemplary embodiment;

[0046] Fig.15 is a schematic structural diagram of a semiconductor structure for forming another first adhesive layer according to another exemplary embodiment;

[0047] Fig.16is a schematic structural diagram of a semiconductor structure for forming other chips and wires connected to the chips according to another exemplary embodiment;

[0048] Fig.17 is a schematic structural diagram of a semiconductor structure for forming a packaging layer according to another exemplary embodiment;

[0049] Fig.18 is a schematic structural diagram of a semiconductor structure for forming solder balls according to another exemplary embodiment;

[0050] Fig.19 is a schematic structural diagram of a semiconductor structure forming a carrier according to another exemplary embodiment;

[0051] Fig. 20 is a schematic structural diagram of a semiconductor structure for forming a conductive line according to another exemplary embodiment;

[0052] Fig.21 is a schematic structural diagram of a semiconductor structure for forming a second adhesive layer according to another exemplary embodiment;

[0053] Fig. 22 is a schematic structural diagram of a semiconductor structure forming a stack and a conductive line according to another exemplary embodiment;

[0054] Fig.23 is a schematic structural diagram of a semiconductor structure with a carrier according to another exemplary embodiment;

[0055] Fig.24 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0056] Fig.25 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0057] Reference numerals:

[0058] This application:

[0059] 1. Intermediary layer; 101. Substrate; 102. Conductive circuit layer; 2. Chip stacking structure; 201. Bottom chip; 202. Stacking member; 3. Chip setting area; 4. First electrical connection area; 5. Chip; 6. Wire; 7. First surface; 8. Second surface; 9. Bottom chip; 10. Carrying part; 11. First conductive block; 12. Second conductive block; 14. First adhesive layer; 15. Second adhesive layer; 16. Second electrical connection area; 18. Packaging layer; 19. Solder ball; 20. Base; 21. Packaging structure; 35. Solder pad; 36. Third adhesive layer.

[0060] Related technologies:

[0061] 22. First packaging substrate; 23. Plastic packaging layer; 24. Filling layer; 25. Second packaging substrate; 26. Chip layer; 27. First chip; 28. First chip connection unit; 29. ​​Second chip; 30. Second chip connection unit; 31. External connection unit; 32. First packaging layer; 33. Second packaging layer; 34. Inter-package connection unit. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0063] In order to meet the requirements of high functionality, high speed and miniaturization of electronic components, package-on-package (POP) technology is often used to form semiconductor packages. Figure 1The semiconductor package in the related art includes a first package substrate 22, a plastic layer 23, a filling layer 24, a second package substrate 25 and a chip layer 26 which are stacked, wherein a first chip 27 and a first chip connection unit 28 are arranged in the plastic layer 23, and the first chip 27 is electrically connected to the first package substrate 22 through the first chip connection unit 28, and an inter-package connection unit 34 is arranged in the filling layer 24, and the inter-package connection unit 34 is used to electrically connect the first chip connection unit 28 and the second package substrate 25, and the chip layer 26 includes at least one second chip 29, and the second chip 29 is electrically connected to the second package substrate 25 through the second chip connection unit 30, and the first package substrate 22 is provided with an external connection unit 31 on the surface away from the filling layer 24. Since the first chip 27 and the second chip 29 are respectively arranged on different package substrates, and the first package substrate 22 needs to be provided with a first package layer 32 on the surface, and the second package substrate 25 needs to be provided with a second package layer 33 on the surface, that is, the semiconductor package in the related art needs to be packaged twice, and the packaging cost is relatively high. In addition, the semiconductor package formed by the stacked package has a relatively large packaging thickness, which is not suitable for the miniaturization requirements of electronic devices. The signal transmission between the second chip 29 and the external circuit needs to pass through the first packaging substrate 22, the first chip connection unit 28, the package connection unit 34, the second packaging substrate 25 and the second chip connection unit 30. Due to the long signal transmission distance, signal losses will occur during the transmission process, resulting in poor signal integrity and low signal transmission speed.

[0064] Based on this, the present disclosure provides a semiconductor structure and a method for manufacturing the same. By connecting a chip to a first electrical connection area located outside a chip setting area through a wire, the signal transmission distance between the chip and the first electrical connection area can be effectively reduced, thereby reducing signal loss during transmission, improving signal transmission quality and signal transmission speed, and reducing signal distortion and noise. In addition, since there is no need to connect the chip and the first electrical connection area through structures such as solder balls and conductive bumps, the distance between the chip and the interposer can be effectively reduced, thereby reducing the thickness of the semiconductor structure and improving the integration of the semiconductor structure.

[0065] An exemplary embodiment of the present disclosure provides a semiconductor structure, which may be a packaging structure, for example. Fig. 9The semiconductor structure includes an interposer 1 and a chip stacking structure 2. The interposer 1 may be, for example, a silicon interposer, and the bottom of the silicon interposer is electrically connected to the package substrate. The interposer 1 includes a chip setting area 3 and a first electrical connection area 4 located outside the chip setting area 3. The chip stacking structure 2 is arranged in the chip setting area 3. The chip stacking structure 2 includes a plurality of chips 5 arranged in a stacked manner, wherein at least some of the chips 5 are connected to the first electrical connection area 4 through wires 6. Of course, it can be understood that some of the plurality of chips 5 may be connected to the first electrical connection area 4 through wires 6, or all of the chips 5 may be connected to the first electrical connection area 4 through wires 6.

[0066] Among them, reference Fig. 9 The interposer 1 may have a first surface 7 and a second surface 8, the first surface 7 and the second surface 8 are arranged opposite to each other, and the chip stacking structure 2 is arranged on the first surface 7 of the interposer 1. The chip setting area 3 may be located at the center of the first surface 7, and the first electrical connection area 4 may be located at the periphery of the chip setting area 3. The first electrical connection area 4 may be in a ring shape or a strip shape, and this embodiment does not limit this.

[0067] In this embodiment, the chip 5 is connected to the first electrical connection area 4 located outside the chip setting area 3 through the wire 6, which can effectively reduce the signal transmission distance between the chip 5 and the first electrical connection area 4, thereby reducing the signal loss during the transmission process, so as to improve the signal transmission quality and signal transmission speed, and reduce signal distortion and noise. In addition, since there is no need to connect the chip 5 and the first electrical connection area 4 through structures such as solder balls and conductive bumps, the distance between the chip 5 and the interposer 1 is effectively reduced, thereby reducing the thickness of the semiconductor structure and improving the integration of the semiconductor structure.

[0068] In some embodiments, reference Fig. 9 The multiple chips 5 include a bottom chip 201, and a plurality of stacking members 202 are arranged on the bottom chip 201. Each stacking member 202 includes a plurality of stacked chips 5, and each chip 5 in the stacking member 202 is connected to the first electrical connection area 4 through a wire 6.

[0069] Multiple stacking members 202 can be evenly arranged on the underlying chip 201 according to a certain pattern. For example, multiple stacking members 202 can be arranged in an array, that is, on the underlying chip 201, the stacking members 202 can be distributed in multiple rows and columns, and the multiple stacking members 202 are arranged at equal intervals in the row direction and the column direction. By arranging the stacking members 202 in an array, the integration of the semiconductor structure can be further improved, so that more stacking members 202 can be arranged within the limited size of the underlying chip 201, so as to improve the functional density and data processing capability of the semiconductor structure.

[0070] The bottom chip 201 may be, for example, a logic chip or a memory chip. The logic chip may include, for example, a memory controller chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. The memory chip may be, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip, and the present embodiment does not limit this.

[0071] Exemplarily, the chip 5 constituting the stack 202 may be, for example, a logic chip or a memory chip, and the chip 5 constituting the stack 202 may be a semiconductor chip of the same type as the underlying chip 201 or a semiconductor chip of a different type from the underlying chip 201. The chips in the same stack 202 may be of the same type or different types, and the chips in different stacks 202 may be the same or different types.

[0072] In this embodiment, by arranging a plurality of stacking members 202 on the bottom chip 201, and arranging the stacking member 202 to include a plurality of chips 5, the functional density and integration of the semiconductor structure can be improved. The chip 5 of the stacking member 202 is connected to the first electrical connection area 4 of the interposer 1 through the wire 6, and the chip 5 in the stacking member 202 can transmit signals to the first electrical connection area 4 without passing through the bottom chip 201, which can effectively reduce the signal transmission distance between the chip 5 of the stacking member 202 and the interposer 1, so as to improve the signal response speed and the performance of the semiconductor structure.

[0073] In some embodiments, reference Fig.18 , the bottom chip 201 is connected to the first electrical connection area 4 through the wire 6.

[0074] In this embodiment, the interconnection between the bottom chip 201 and the first electrical connection area 4 is achieved through the wire 6, which can reduce the electrical connection cost between the bottom chip 201 and the intermediate layer 1 while ensuring the signal transmission speed between the bottom chip 201 and the intermediate layer 1. At the same time, since there is no need to set structures such as solder balls and conductive bumps for connecting the chip and the first electrical connection area, the distance between the bottom chip 201 and the intermediate layer 1 can be effectively reduced, thereby reducing the thickness of the semiconductor structure.

[0075] In some other embodiments, the bottom chip 201 is connected to the chip setting area 3 via a conductive connection structure.

[0076] like Fig. 9As shown, the conductive connection structure includes a first conductive block 11 arranged on the bottom chip 201 and a second conductive block 12 arranged in the chip setting area 3. The first conductive block 11 is exposed through the bottom surface of the bottom chip 201, and the second conductive block 12 is exposed through the top surface of the intermediate layer 1. The first conductive block 11 and the second conductive block 12 can be bonded and connected by a bonding process.

[0077] Exemplarily, the material of the first conductive block 11 may be one or more of gold (Au), copper (Cu), nickel (Ni), tin (Sn), and lead (Pb), and the material of the second conductive block 12 may be the same as or different from that of the first conductive block 11.

[0078] In this embodiment, the electrical connection between the bottom chip 201 and the interposer 1 can be achieved through the first conductive block 11 and the second conductive block 12. In addition, the bottom chip 201 and the interposer 1 connected by the bonding process are in contact with each other, which can shorten the transmission distance between the bottom chip 201 and the interposer 1, thereby further improving the signal transmission speed of the semiconductor structure and further reducing the thickness of the semiconductor structure.

[0079] In other embodiments, the first conductive block 11 and the second conductive block 12 can also be connected by reflow soldering or other welding processes. Exemplarily, the first conductive block 11 protrudes from the bottom surface of the bottom chip 201, and the second conductive block 12 protrudes from the top surface of the interposer 1. Solder is provided between the first conductive block 11 and the second conductive block 12 to weld and connect the first conductive block 11 and the second conductive block 12. There is a gap between the bottom chip 201 and the interposer 1, and the gap can be filled with a filling material. Among them, the filling material can be selected from one or more of thermosetting resins, thermoplastic resins, and UV curing resins. The filling material can be the same as the material of the encapsulation layer 18. The filling material can play a role in improving the connection stability of the first conductive block 11 and the second conductive block 12.

[0080] In this embodiment, the electrical connection between the bottom chip 201 and the interposer 1 can be achieved through the first conductive block 11 and the second conductive block 12. In addition, the conductive connection structure formed by the first conductive block 11 and the second conductive block 12 can provide a good support for the chip stacking structure 2, ensuring that the semiconductor structure has good stability under external effects such as vibration and impact.

[0081] In some embodiments, reference Fig. 9 as well as Fig.18A first adhesive layer 14 is disposed between adjacent chips 5 in the same stack 202, and two adjacent chips 5 can be bonded together by the first adhesive layer 14. The first adhesive layer 14 can be located in an overlapping region of projections of the two adjacent chips 5 on the first surface 7, and the thickness of the first adhesive layer 14 is less than the thickness of any chip 5 in the stack 202.

[0082] In this embodiment, the first adhesive layer 14 can achieve good bonding effect on each chip 5 in the same stack 202, and the first adhesive layer 14 has a small thickness, which can reduce the thickness of the semiconductor structure to reduce the space occupied by the semiconductor structure, and more chips 5 can be arranged in the direction perpendicular to the first surface 7 to improve the integration of the semiconductor structure.

[0083] In some embodiments, reference Fig. 9 as well as Fig.18 A second adhesive layer 15 is provided between the stack 202 and the bottom chip 201. The second adhesive layer 15 may be located within the projection area of ​​the chip 5 in the stack 202 close to the bottom chip 201 on the first surface 7, and the thickness of the second adhesive layer 15 is less than the thickness of any chip 5 in the stack 202 and the thickness of the bottom chip 201.

[0084] In this embodiment, the second adhesive layer 15 can achieve good bonding effect on the stack 202 and the underlying chip 201, and the thickness of the second adhesive layer 15 is relatively small, so the overall thickness of the semiconductor structure can be reduced to reduce the space occupied by the semiconductor structure, and more chips 5 can be arranged in the direction perpendicular to the first surface 7 to improve the integration of the semiconductor structure.

[0085] In some embodiments, reference Fig.18 When the bottom chip 201 is connected to the first electrical connection area 4 through the wire 6, a third adhesive layer 36 is provided between the bottom chip 201 and the interposer 1. In a direction perpendicular to the first surface 7, the third adhesive layer 36 may be located within the projection area of ​​the bottom chip 201 on the first surface 7.

[0086] In this embodiment, when the bottom chip 201 is connected to the first electrical connection area 4 through the wire 6, the third adhesive layer 36 can play a good bonding role on the bottom chip 201 to prevent the position of the bottom chip 201 from shifting during use of the semiconductor structure.

[0087] Of course, it is understandable that the first adhesive layer 14, the second adhesive layer 15 and the third adhesive layer 36 can be provided at the same time. The first adhesive layer 14, the second adhesive layer 15 and the third adhesive layer 36 can be liquid or film-state organic materials, for example, they can include one or more of non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive paste (ACP), anisotropic conductive film (ACF), polyimide (PI), epoxy resin, resin, PP (Pre Preg), ABF (Ajinomoto Build-up Film), glue, etc. The materials of the first adhesive layer 14, the second adhesive layer 15 and the third adhesive layer 36 can be the same or different.

[0088] In some embodiments, reference Fig. 9 Each chip 5 in the stack 202 includes a second electrical connection region 16, which is arranged near the edge of the chip 5, and one end of the wire 6 is connected to the second electrical connection region 16. The edges of the chips 5 in the same stack 202 are flush, and the chips 5 in the same stack 202 can be vertically distributed and the centers of the multiple chips 5 are located on the same straight line perpendicular to the surface of the bottom chip 201.

[0089] Among them, after forming a chip 5, a wire bonding operation can be performed on the chip 5 so that the second electrical connection area 16 at the edge of the chip 5 is connected to the first electrical connection area 4 of the intermediate layer 1 through the wire 6, and then the first adhesive layer 14 is covered on the surface of the chip 5 to arrange another chip 5 above the first adhesive layer 14.

[0090] In this embodiment, the first adhesive layer 14 can have a larger bonding area with the chip 5, so the overall stability of the stack 202 can be improved. The first adhesive layer 14 can cover the position where the wire 6 is connected to the chip 5 while covering the surface of the chip 5, thereby improving the connection reliability between the wire 6 and the chip 5. In addition, the edges of the chips 5 in the same stack 202 are made flush, which can improve the space utilization of the stack 202.

[0091] In other embodiments, reference Fig.18Each chip 5 in the stack 202 includes a second electrical connection area 16, which is arranged near the edge of the chip 5, and one end of the wire 6 is connected to the second electrical connection area 16. In two adjacent chips 5 in the same stack 202, the second electrical connection area 16 of the lower chip 5 is exposed through the upper chip 5.

[0092] In this embodiment, multiple chips 5 of the same stack 202 may be arranged vertically and staggered with each other, for example, the sizes of adjacent chips 5 may be the same or different, but the edges of adjacent chips 5 are not flush. Alternatively, multiple chips 5 may be arranged in a stepped manner, and the centers of the multiple chips 5 arranged in a stepped manner may not be on the same straight line or may be located on a straight line inclined at a preset angle to the surface of the bottom chip 201, wherein the preset angle ranges from 0-90°, but does not include 0° and 90°.

[0093] In this embodiment, the second electrical connection area 16 of the chip 5 in the stack 202 is exposed through the upper chip 5, which can reduce the difficulty of wire bonding. After the stack 202 is formed as a whole, the wire bonding operation can be performed uniformly on each chip 5, thereby improving the manufacturing efficiency of the semiconductor structure.

[0094] In some embodiments, reference Fig.19 The semiconductor structure further includes a carrier 10 disposed on the interposer 1 . The carrier 10 is disposed at the periphery of the bottom chip 201 . The carrier 10 and the bottom chip 201 jointly support a plurality of stacked components 202 .

[0095] The carrier part 10 may be formed after the bottom chip 201 is formed. The carrier part 10 may contact the edge of the bottom chip 201 , and the top surface of the carrier part 10 may be flush with the top surface of the bottom chip 201 .

[0096] When the size of the bottom chip 201 is small, the supporting function of the stacking member 202 can be achieved by the supporting part 10 and the bottom chip 201. At this time, the second adhesive layer 15 can be set on the top surface of the bottom chip 201 and the supporting part 10. As mentioned above, the stacking members 202 can be arranged in an array, and the size of the supporting part 10 can be determined according to the number of rows and / or columns of the stacking members 202 to be supported.

[0097] In this embodiment, the actual bearing area of ​​the semiconductor structure for the stacked components 202 can be increased by providing the bearing portion 10. Therefore, the bearing portion 10 and the underlying chip 201 can bear more stacked components, thereby increasing the number of chips included in the semiconductor structure and improving the integration of the semiconductor structure.

[0098] In some embodiments, reference Fig. 9 and Fig.18The semiconductor structure further includes a packaging layer 18 , which covers the chip stacking structure 2 and each wire 6 .

[0099] In this embodiment, the encapsulation layer 18 can provide a physical barrier for the semiconductor structure as a whole, especially the bottom chip 201 and the chip stacking structure 2, so as to provide good protection for the semiconductor structure, for example, to prevent the semiconductor structure from being damaged by collision, and to prevent electrostatic discharge from causing damage to the bottom chip 201 and the chip stacking structure 2. In addition, the encapsulation layer 18 can discharge the heat generated during the operation of the semiconductor structure by heat conduction, so as to prevent the semiconductor structure from overheating.

[0100] In some embodiments, reference Fig. 9 and Fig.18 A plurality of solder balls 19 are disposed on a side of the interposer 1 facing away from the chip stacking structure 2 , and this side may be the second surface 8 of the interposer 1 .

[0101] Among them, the solder ball 19 can be located on the second surface 8 of the intermediate layer 1 and electrically connected to the external circuit. The solder ball 19 can be formed before the underlying chip 201 and the chip stacking structure 2 are formed, or can be formed after the underlying chip 201 and the chip stacking structure 2 are formed. This embodiment is not limited to this. The material of the solder ball 19 can be, for example, one or more of copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), and gold (Au).

[0102] In this embodiment, the solder ball 19 can realize the circuit connection and signal transmission between the semiconductor structure and the external circuit. In addition, it can also provide stable mechanical support for the semiconductor structure as a whole to prevent the position of the semiconductor structure from shifting during operation. The solder ball 19 can discharge the heat generated by the semiconductor structure during operation through heat conduction to control the operating temperature of the semiconductor structure within a safe range.

[0103] Of course, it is understandable that the semiconductor structure may have both the packaging layer 18 and a plurality of solder balls 19 located on a side away from the interposer 1 where the chip stacking structure 2 is disposed.

[0104] In some embodiments, reference Fig. 9 as well as Fig.18 The interposer 1 includes a substrate 101 and a conductive circuit layer 102 disposed in the substrate 101. Each chip 5 is electrically connected to the conductive circuit layer 102. The substrate 101 may be, for example, a polyimide substrate, an epoxy resin substrate, or a phenolic resin substrate, or a combination thereof. Exemplarily, the substrate 101 may also include one or more materials selected from the group consisting of flame retardant, tetrafunctional epoxy resin, polyphenylene ether, bismaleimide triazine, cyanate ester, polyimide, and liquid crystal polymer.

[0105] The chip stacking structure 2 is disposed on the first surface 7 of the substrate 101, and the second surface 8 of the interposer 1 opposite to the first surface 7 can be electrically connected to an external circuit. The conductive circuit layer 102 can be connected to the wire 6 and the second conductive block 12 to realize information exchange between each chip 5 and the external circuit.

[0106] Exemplarily, the material of the conductive circuit layer 102 may be one or more of copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), and gold (Au).

[0107] In this embodiment, the substrate 101 provides mechanical support for the semiconductor structure, and the semiconductor structure can be positioned and the conductive circuit layer 102 can be electrically connected to the external circuit through the solder balls 19 arranged at the bottom of the substrate 101, thereby realizing signal transmission between each chip 5 and the external circuit through the conductive circuit layer 102.

[0108] An exemplary embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be applied to wafer-level packaging (Wafer-Level Packaging, WLP), wherein the semiconductor structure can have a wafer-level size, and after being processed by a semiconductor process, the semiconductor structure can include a single-layer wafer or a stacked multi-layer wafer, such as Fig.24 As shown, the production method includes:

[0109] Step S100: forming an intermediate layer.

[0110] refer to Figure 2 The interposer 1 includes a chip setting region 3 and a first electrical connection region 4 located outside the chip setting region 3. The chip setting regions 3 on the interposer 1 can be arranged in an array, and the first electrical connection region 4 is arranged outside each chip setting region 3.

[0111] The interposer 1 may include, for example, a substrate 101 and a conductive circuit layer 102 disposed in the substrate 101 . The material of the substrate 101 may be, for example, polyimide.

[0112] Among them, continue to refer to Figure 2 The intermediary layer 1 may be formed on a substrate 20. For example, the material of the substrate 20 may include one or more of polypropylene, polyethylene, polystyrene, polyvinyl alcohol, etc. The substrate 20 may also be a wafer. Fig. 9 and Fig.18 After forming the packaging layer 18 described below, the substrate 20 may be removed to facilitate forming solder balls 19 on the second surface 8 of the interposer 1 .

[0113] Step S200: forming a chip stacking structure on a chip placement area.

[0114] refer to Figure 7 as well as Fig.16 The chip stacking structure 2 includes a plurality of chips 5 which are stacked together, wherein at least some of the chips 5 are connected to the first electrical connection region 4 via wires 6 .

[0115] For example, a wire bonding process may be used to form a wire 6 connecting the chip 5 and the first electrical connection area 4, and a soldering pad 35 may be formed between the chip 5 and the first electrical connection area 4 by ball bonding or flat bonding, which is not limited in this embodiment.

[0116] Step S300: forming a packaging layer.

[0117] refer to Figure 8 as well as Fig.17 In this step, after forming the interposer 1, the bottom chip 201, the chip stacking structure 2 and the wire 6, a packaging layer 18 may be formed, so that the packaging layer 18 covers each chip stacking structure 2 and each wire 6. The packaging layer 18 can provide good protection for the semiconductor structure, and can accelerate the heat dissipation speed of the semiconductor structure to avoid the problem of overheating of the semiconductor structure.

[0118] Exemplarily, the material of the encapsulation layer 18 may include one or more of a thermosetting resin, a thermoplastic resin, and a UV curing resin, which is not limited in this embodiment.

[0119] Step S400: dividing the package into multiple package structures.

[0120] like Fig. 9 and Fig.18 As shown, each packaging structure 21 includes a chip stacking structure 2 .

[0121] Illustratively, after the package is formed, a cutting process may be used to form a plurality of package structures 21 . For example, a blade saw may be used to cut corresponding regions of the package to form a package structure 21 including a chip stacking structure 2 .

[0122] In this embodiment, the chip 5 is connected to the first electrical connection area 4 located outside the chip setting area 3 through the wire 6, which can effectively reduce the signal transmission distance between the chip 5 and the first electrical connection area 4, thereby reducing the signal loss during the transmission process, so as to improve the signal transmission quality and signal transmission speed, and reduce signal distortion and noise. In addition, arranging multiple chips 5 on the intermediate layer 1 in a stacked manner can reduce the packaging thickness and packaging cost of the semiconductor structure, achieve a high degree of integration of the semiconductor structure, and thus improve the functional density of the semiconductor structure. In addition, since there is no need to connect the chip and the first electrical connection area 4 through structures such as solder balls and conductive bumps, the distance between the chip 5 and the intermediate layer 1 can be effectively reduced, thereby reducing the thickness of the semiconductor structure and improving the integration of the semiconductor structure. Only one packaging process is required during the entire manufacturing process, which simplifies the process of the semiconductor structure.

[0123] In some embodiments, forming the chip stacking structure 2 on the chip setting area 3 includes:

[0124] Step S201A: arrange the bottom chip in the chip arrangement area.

[0125] When the bottom chip 201 is arranged in the chip arrangement area 3, the bottom chip 201 is connected to the interposer 1 through a bonding process. Figure 3 The bottom chip 201 and the chip setting area 3 may be respectively provided with a first conductive block 11 and a second conductive block 12, and the first conductive block 11 and the second conductive block 12 are connected by a bonding process to achieve electrical connection between the bottom chip 201 and the chip setting area 3, referring to Fig. 9 The first conductive block 11 is located inside the bottom chip 201 and is exposed through the bottom surface of the bottom chip 201. The second conductive block 12 is located inside the intermediate layer 1 and is connected to the conductive connection layer 102. The second conductive block 12 is exposed through the top surface of the intermediate layer 1. The first conductive block 11 and the second conductive block 12 are connected through a bonding process.

[0126] In addition, the first conductive block 11 and the second conductive block 12 can also be connected through a reflow process or other welding processes. Before the reflow process, the intermediate layer 1 and the bottom chip 201 must be preheated to avoid damage to the material due to excessive temperature changes. Welding can be performed using different heating methods such as a reflow furnace, an infrared heating lamp or a hot air gun, wherein the first conductive block 11 protrudes from the bottom surface of the bottom chip 201, and the second conductive block 12 protrudes from the top surface of the intermediate layer 1. The first conductive block 11 and the second conductive block 12 are fixedly welded by the solder located between the first conductive block 11 and the second conductive block 12.

[0127] Step S202A: disposing a plurality of stacked components on the bottom chip.

[0128] like Figure 7 As shown, the plurality of stacks 202 disposed on the bottom chip 201 each include a plurality of stacked chips 5, each chip 5 in the stack 202 is connected to the first electrical connection region 4 via a wire 6. Each chip 5 in the stack 202 includes a second electrical connection region 16, and the second electrical connection region 16 is disposed near the edge of the chip 5. The stack 202 can be connected to the first electrical connection region 4 by a wire 6. Figure 4 The second adhesive layer 15 is shown disposed on the bottom chip 201 .

[0129] refer to Figure 5 and Figure 6 When forming each stack 202, each time a layer of chips 5 is arranged, the chips 5 of the layer are connected to the first electrical connection area 4 through the wire 6, and then the next layer of chips 5 is arranged. Figure 7 As shown, the edges of the chips 5 in the same stack 202 are flush. After forming a layer of chips 5, the chip 5 is wire bonded so that the second electrical connection area 16 at the edge of the chip 5 is connected to the first electrical connection area 4 of the interposer 1 through the wire 6, and then the first adhesive layer 14 is covered on the surface of the chip 5. The projection area of ​​the first adhesive layer 14 on the first surface 7 should be located within the projection area of ​​the chip 5 on the first surface 7. Then, another chip 5 can be formed above the surface of the first adhesive layer 14. Among them, making the edges of the same stack 202 flush can improve the space utilization of the stack 202. In addition, the first adhesive layer 14 can cover the position where the wire 6 is connected to the chip 5 while covering the surface of the chip 5, thereby improving the connection reliability between the wire 6 and the chip 5.

[0130] In some other embodiments, forming the chip stacking structure 2 on the chip setting area 3 includes:

[0131] Step S201B: arrange the bottom chip in the chip arrangement area.

[0132] The bottom chip 201 is connected to the interposer 1 by wire bonding. Fig.10 Combined with Fig.11 The bottom chip 201 can be placed in the chip placement area 3 through the third adhesive layer 36, combined with Fig.12 The bottom chip 201 is connected to the first electrical connection area 4 through the wire 6 , and the projection area of ​​the third adhesive layer 36 on the first surface 7 of the interposer 1 should be located within the projection area of ​​the bottom chip 201 on the first surface 7 .

[0133] Step S202B: disposing a plurality of stacked components on the bottom chip.

[0134] like Fig.13 Shown and combined Fig.14, a second adhesive layer 15 is disposed on the bottom chip 201 , so that the bottommost chip 5 in the stack 202 is bonded to the bottom chip 201 through the second adhesive layer 15 .

[0135] refer to Fig.15 Combined with Fig.16 After all the chips 5 in each stack 202 are stacked on the bottom chip 201, each chip 5 in each stack 202 is connected to the first electrical connection area 4 through the wire 6. In two adjacent chips 5 in the same stack 202, the second electrical connection area 16 of the lower chip 5 is exposed through the upper chip 5 to reduce the difficulty of wire bonding. After forming a layer of chips 5, a first adhesive layer 14 can be directly formed on the surface of the layer of chips 5. The next layer of chips 5 formed above the layer of chips 5 has an overlapping area with the projection of the chip 5 on the first surface 7. The projection of the first adhesive layer 14 on the first surface 7 should be located in the overlapping area to avoid the overflow of the adhesive of the first adhesive layer 14 to contaminate the semiconductor structure. After that, the next layer of chips 5 can be formed on the surface of the first adhesive layer 14. After forming the stack 202 as a whole, wire bonding can be uniformly performed on each chip 5, thereby improving the manufacturing efficiency of the semiconductor structure.

[0136] In other embodiments, Fig.25 As shown, forming a chip stacking structure 2 on the chip setting area 3 includes the following steps:

[0137] Step S210: Arrange a bottom chip in a chip arrangement area.

[0138] This step is similar to step S201A and step S201B, and will not be repeated here.

[0139] Step S220: forming a carrier portion on the interposer layer.

[0140] In this step, refer to Fig.19 After forming the bottom chip 201, a carrier 10 may be formed on the periphery of the bottom chip 201. The carrier 10 is used to support the plurality of stacked components 202 together with the bottom chip 201, and the top surface of the carrier 10 may be flush with the top surface of the bottom chip 201. When the edge of the bottom chip 201 is flush with the edge of the stacked components 202, or when the projection of at least part of the stacked components 202 on the first surface 7 is outside the projection of the bottom chip 201 on the first surface 7, the carrier 10 and the bottom chip 201 may jointly support the stacked components 202, thereby increasing the actual bearing area of ​​the semiconductor structure for the stacked components 202. Therefore, the carrier 10 and the bottom chip 201 may carry more stacked components, thereby increasing the number of chips included in the semiconductor structure and improving the integration of the semiconductor structure.

[0141] It is understandable that the bottom chip 201 can be connected to the interposer 1 by wire bonding, or by bonding. When the bottom chip 201 is connected to the interposer 1 by wire bonding, the wire bonding operation can be performed before forming the carrier 10, or as shown in FIG. Fig. 20 As shown, the wire bonding operation is performed after the carrier portion 10 is formed.

[0142] Step S230: Dispose a plurality of stacked components on the bottom chip.

[0143] refer to Fig. 22 , and combined with Fig.21 The stack 202 is disposed on the bottom chip 201 through the second adhesive layer 15. The formation process of the stack 202 can refer to the formation process of the stack 202 in step S202A and step S202B. After the stack 202 is formed, the semiconductor structure can be packaged and cut to obtain Fig.23 The packaging structure 21.

[0144] The projection of the second adhesive layer 15 on the first surface 7 may be located within the projection of the bottom chip 201 and the carrier 10 on the first surface 7. Fig.21 The bonding position between the wire 6 and the bottom chip 201 can be covered by the second adhesive layer 15. The second adhesive layer 15 can be flush with the edge of the bottom chip 201, so as to improve the connection reliability between the wire 6 and the bottom chip 201 through the second adhesive layer 15.

[0145] In this embodiment, by stacking the chips 5 to form a stack 202, the overall thickness of the stack 202 can be ensured, thereby reducing the overall thickness of the semiconductor structure. The chips 5 of the stack 202 are connected to the first electrical connection area 4 located outside the chip setting area 3 through the wire 6, which can effectively reduce the signal transmission distance between the chip 5 and the first electrical connection area 4, thereby reducing the signal loss during the transmission process and further reducing the thickness of the semiconductor structure. In addition, when the size of the bottom chip 201 is small, the stack 202 can be supported by the carrier 10 and the bottom chip 201 to ensure the stability of the stack 202.

[0146] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0147] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0148] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0149] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0150] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0151] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: An interposer, comprising a chip setting area and a first electrical connection area located outside the chip setting area; A chip stacking structure is arranged in the chip setting area, and the chip stacking structure includes a plurality of chips that are stacked, wherein at least part of the chips are connected to the first electrical connection area through wires.

2. The semiconductor structure according to claim 1, characterized in that: The multiple chips include a bottom chip, a multiple stacking members are arranged on the bottom chip, each of the stacking members includes a multiple of the chips that are stacked, and each of the chips in the stacking members is connected to the first electrical connection area through the wire.

3. The semiconductor structure according to claim 2, characterized in that: The bottom chip is connected to the first electrical connection area through the wire; or the bottom chip is connected to the chip setting area through a conductive connection structure; Each chip in the stack includes a second electrical connection region, and the second electrical connection region is arranged near an edge of the chip; One end of the wire is connected to the second electrical connection area, and the edges of the chips in the same stack are flush with each other; Alternatively, in two adjacent chips in the same stack, the second electrical connection region of the lower chip is exposed through the upper chip.

4. The semiconductor structure according to claim 3, characterized in that: The conductive connection structure includes a first conductive block disposed on the bottom chip and a second conductive block disposed in the chip setting area, and the first conductive block and the second conductive block are electrically connected.

5. The semiconductor structure according to claim 2, characterized in that: A first adhesive layer is provided between adjacent chips in the same stack; and / or, A second adhesive layer is disposed between the stack and the bottom chip; and / or, When the bottom chip is connected to the first electrical connection region through the wire, a third adhesive layer is disposed between the bottom chip and the interposer.

6. The semiconductor structure according to any one of claims 2 to 5, characterized in that: The semiconductor structure further includes a supporting portion disposed on the interposer, the supporting portion being disposed at the periphery of the bottom chip, and the supporting portion and the bottom chip jointly supporting the plurality of stacked components.

7. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: forming an interposer, the interposer comprising a chip setting region and a first electrical connection region located outside the chip setting region; A chip stacking structure is formed on the chip setting area, wherein the chip stacking structure includes a plurality of stacked chips, wherein at least part of the chips are connected to the first electrical connection area through wires.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The forming of a chip stacking structure on the chip setting area includes: Arranging a bottom chip in the chip arrangement area; A plurality of stacks are arranged on the bottom chip, each of the stacks includes a plurality of the chips that are stacked, and each of the chips in the stack is connected to the first electrical connection area through the wire.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The bottom chip is arranged in the chip arrangement area, including: The bottom chip is arranged in the chip arrangement area through a third adhesive layer, and the bottom chip is connected to the first electrical connection area through a wire; or, Bonding the bottom chip to the chip setting area through a bonding process; Each chip in the stack includes a second electrical connection area, and the second electrical connection area is arranged near the edge of the chip. The plurality of stacks are arranged on the bottom chip, including: When forming each stack, each time a layer of chips is arranged, the chips of the layer are connected to the first electrical connection area through a wire, and then the next layer of chips is arranged, and the edges of the chips in the same stack are flush; or After each chip in each stack is stacked on the bottom chip, each chip in each stack is connected to the first electrical connection area through a wire. Among two adjacent chips in the same stack, the second electrical connection area of ​​the lower chip is exposed through the upper chip.

10. The method for manufacturing a semiconductor structure according to claim 8 or 9, characterized in that: Before arranging a plurality of stacked components on the bottom chip, the method for manufacturing the semiconductor structure further includes: A carrying portion is formed on the intermediary layer, the carrying portion is disposed at the periphery of the bottom chip, and the carrying portion is used to support the plurality of stacked components together with the bottom chip.

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