Power supply ring for chip, chip and electronic equipment

Abstract

A power supply ring for a chip, a chip and an electronic device, the power supply ring comprises a circle of loop line structure arranged around a chip circuit, the loop line structure comprises a structure formed by stacking at least two metal layers, insulating layers used for mutual isolation are arranged between the adjacent metal layers, the at least two metal layers comprise a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, the first metal layer is used for connecting a grounding end of the chip circuit; and the second metal layer is used for connecting a power supply end of the chip circuit. The structure of the power supply ring can save the chip area.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically to a power ring for a chip, a chip and an electronic device. Background Art

[0002] Power ring design is a relatively important topic in chip design. For large-scale digital-analog hybrid chips such as system-on-chip (SOC), the power ring design is combined with the input and output (IO), relying on the IO ring to form multiple groups of power and ground rings, and the form is relatively fixed; for smaller-scale analog chips, metal wire power rings or no power rings (pads PAD directly connected to power supply and ground) are often used for power supply and grounding.

[0003] Regarding the power supply mode design of the above-mentioned metal wire power ring, the conventional design usually consists of at least a group of power and ground metal wire rings surrounding the chip circuit to form a power ring, wherein the ground metal wire ring is designed around the power metal wire ring, that is, the power metal wire ring is the inner ring and the ground metal wire ring is the outer ring. Such a structure uses two metal rings, which will cause a waste of area. Summary of the invention

[0004] The present application is proposed to solve the above problems. According to one aspect of the present application, a power ring for a chip is provided, characterized in that the power ring comprises a ring wire structure arranged around the chip circuit, and the ring wire structure comprises:

[0005] At least two metal layers, the at least two metal layers are stacked, and the at least two metal layers include:

[0006] A first metal layer, wherein the first metal layer is used to connect a ground terminal of the chip circuit;

[0007] A second metal layer, the second metal layer is used to connect the power supply terminal of the chip circuit;

[0008] The insulating layer is disposed between adjacent metal layers and is used to electrically isolate the adjacent metal layers.

[0009] The above technical solution has the following technical effects: the power ring includes a structure formed by stacking at least two metal layers, and the at least two metal layers include at least a ground potential layer and a power potential layer. Since the ground potential layer and the power potential layer are stacked up and down, the two form a ring structure from a top view, which makes full use of the effective space under the metal wire, can effectively save chip area, and is conducive to product miniaturization.

[0010] In one embodiment of the present application,

[0011] The at least two metal layers further include:

[0012] At least one third metal layer is located between the first metal layer and the second metal layer, and the third metal layer is used to connect the ground terminal of the chip circuit and / or the power terminal of the chip circuit.

[0013] The above technical solution has the following technical effects: since the power ring also includes a customized potential layer, the power ring can more flexibly meet the requirements of different chips.

[0014] In one embodiment of the present application,

[0015] A first through hole is provided between the third metal layer and the first metal layer, and the third metal layer is electrically connected to the first metal layer through the first through hole, so that the third metal layer is connected to the ground terminal of the chip circuit.

[0016] The above technical solution has the following technical effects: the third metal layer serves as a customized potential layer, and eventually becomes a ground potential layer together with the first metal layer, making the ground of the chip thicker and the ability to release current more quickly, and can be better suited to chips with greater demands for electrostatic release.

[0017] In one embodiment of the present application,

[0018] A second through hole is provided between the third metal layer and the second metal layer, and the third metal layer is electrically connected to the second metal layer through the second through hole, so that the third metal layer is connected to the power supply terminal of the chip circuit.

[0019] The above technical solution has the following technical effects: the third metal layer serves as a customized potential layer, and eventually becomes a power supply potential layer together with the second metal layer, so that the chip has stronger overcurrent capability and lower line resistance, and can be better suitable for chips that have more emphasis on overcurrent capability and line resistance.

[0020] In one embodiment of the present application,

[0021] The third metal layer includes:

[0022] a first portion of the third metal layer, a third through hole being provided between the first portion of the third metal layer and the first metal layer, the third through hole being used to electrically connect the first portion of the third metal layer to the first metal layer, so that the first portion of the third metal layer is connected to the ground terminal of the chip circuit;

[0023] A fourth through hole is provided between the second part of the third metal layer and the second metal layer, and the fourth through hole is used to electrically connect the second part of the third metal layer with the second metal layer, so that the second part of the third metal layer is connected to the power supply terminal of the chip circuit.

[0024] The above technical solution has the following technical effects: the third metal layer, as a customized potential layer, can be divided into two parts that are electrically isolated from each other, one part is connected to the power supply together with the second metal layer, and the other part is grounded together with the first metal layer, so that the overcurrent capability, line resistance and electrostatic release capability of the chip can all be taken into account, and it can be better suitable for chips with balanced requirements for overcurrent capability, line resistance and electrostatic release capability.

[0025] In one embodiment of the present application,

[0026] The second metal layer includes electrically isolated:

[0027] a first portion of the second metal layer, wherein a fifth through hole is disposed between the first portion of the second metal layer and the first metal layer, and the fifth through hole is used to electrically connect the first portion of the second metal layer to the first metal layer, so that the first portion of the second metal layer is connected to the ground terminal of the chip circuit;

[0028] The second part of the second metal layer is used to connect the power supply terminal of the chip circuit.

[0029] The above technical solution has the following technical effects: part of the second metal layer is grounded, making the ground of the chip thicker and the ability to quickly release current stronger, which can be better suitable for chips with greater requirements for electrostatic release, and such customized requirements are achieved through two metal layers, and the structure is simpler.

[0030] In one embodiment of the present application,

[0031] The first metal layer includes:

[0032] a first portion of the first metal layer, wherein the first portion of the first metal layer is connected to a ground terminal of the chip circuit;

[0033] A sixth through hole is provided between the second part of the first metal layer and the second metal layer, and the sixth through hole is used to electrically connect the second part of the first metal layer with the second metal layer, so that the second part of the first metal layer is connected to the power supply terminal of the chip circuit.

[0034] The above technical solution has the following technical effects: part of the first metal layer is connected to the power supply, so that the chip has stronger overcurrent capability and lower line resistance, and can be better suitable for chips that have more emphasis on overcurrent capability and line resistance, and such customized requirements are achieved through two metal layers, and the structure is simpler.

[0035] In one embodiment of the present application, the loop structure includes at least two parts that are electrically isolated from each other, and the second metal layers in each of the at least two parts are respectively connected to different power supply terminals of the chip circuit.

[0036] The above technical solution has the following technical effects: the power ring is designed to include at least two parts that are electrically isolated from each other, which can realize multiple power domains and is particularly suitable for chips with special design requirements such as divided power or divided ground.

[0037] In one embodiment of the present application, below each metal layer is provided:

[0038] A capacitor device, two ends of which are respectively connected to a power supply end of the chip circuit and a ground end of the chip circuit.

[0039] The above technical solution has the following technical effects: the capacitance value of power supply interference and noise can be filtered through the capacitor component to ensure the stability and cleanliness of the power supply, thereby ensuring the stability of the chip system.

[0040] In one embodiment of the present application, the corners of the loop structure are cut corners.

[0041] The above technical solution has the following technical effects: the corners of the loop structure are cut corners, which can avoid stress damage at the corners caused by chip cutting.

[0042] According to another aspect of the present application, a chip is further provided, the chip comprising a chip circuit and the above-mentioned power ring for the chip, the power ring being arranged around the chip circuit.

[0043] In one embodiment of the present application, the chip is an analog chip.

[0044] According to another aspect of the present application, an electronic device is provided, comprising the above-mentioned chip.

[0045] The structure of the power ring for a chip according to the embodiment of the present application can save chip area, customize current distribution, support multi-power domain design, and have the functions of filtering power disturbances and stabilizing power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0047] Figure 1 A schematic diagram of the top view structure of an existing power ring for a chip is shown.

[0048] Figure 2 A schematic diagram of the structure of a power ring in a top view and a three-dimensional view according to an embodiment of the present application is shown.

[0049] Figure 3 A schematic diagram of the structure of a power ring in a top view and a three-dimensional view according to another embodiment of the present application is shown.

[0050] Figure 4 Shows Figure 3 A cross-sectional structural schematic diagram of an example of a power ring is shown.

[0051] Figure 5 Shows Figure 3 A cross-sectional structural schematic diagram of another example of a power ring is shown.

[0052] Figure 6 Shows Figure 3 A cross-sectional structural diagram of yet another example of a power ring is shown.

[0053] Figure 7 A cross-sectional structural diagram of a power ring according to yet another embodiment of the present application is shown.

[0054] Figure 8 A top view and a partially enlarged structural schematic diagram of a power ring according to another embodiment of the present application are shown.

[0055] Fig. 9 A schematic diagram of the structure of a power ring in a top view and a three-dimensional view according to another embodiment of the present application is shown.

[0056] Fig.10 A schematic diagram of the structure of a power ring in a top view and a three-dimensional view according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present application more obvious, the example embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0058] Figure 1 FIG. 1 shows a schematic diagram of a top view of a power supply ring 1 for an existing chip (mainly an analog chip). Figure 1 As shown, the power supply ring 1 includes two circles of metal wire rings surrounding the internal module of the chip, namely the power supply metal wire ring 11 and the ground metal wire ring 12. The power supply metal wire ring 11 is used to connect the power supply for the internal module of the chip, and the ground metal wire ring 12 is used to connect the ground terminal of the internal module of the chip. Among them, the ground metal wire ring 12 is arranged on the periphery of the power supply metal wire ring 11, and the distance between the two is relatively large (about tens of microns), and the power supply metal wire ring 11 is closer to the internal module of the chip than the ground metal wire ring 12. That is, the power supply metal wire ring 11 is the inner circle metal wire ring, and the ground metal wire ring 12 is the outer circle metal wire ring, and the two of them are connected from Figure 1 The top view shows a separated inner and outer ring structure, while the cross-sectional view (not shown) shows an overlapped structure, that is, the two are not three-dimensional structures. The structure of the power ring 1 requires the use of two metal rings, which makes the overall area of ​​the chip including the power ring 1 and the internal module of the chip larger, which is not conducive to product miniaturization.

[0059] Based on this, the present application provides a new power supply ring solution. Figures 2 to 10 to describe.

[0060] Figure 2 FIG. 2 shows a schematic diagram of a power ring 2 in a top view and a three-dimensional structure according to an embodiment of the present application. Figure 2 As shown, from the perspective of the top view on the left, the power ring 2 includes a ring structure arranged around the chip circuit (i.e., the chip internal module); from the perspective of the stereoscopic view on the right, the ring structure includes a structure formed by stacking at least two layers of metal layers, wherein an insulating layer is arranged between adjacent metal layers for isolating each other (to prevent short circuits caused by connection to each other when they are set to different potentials). Figure 2In the illustrated embodiment, the at least two metal layers include a first metal layer 21 and a second metal layer 22. The first metal layer 21 (when not being cut) can be used to connect the ground terminal of the chip circuit (when being cut, at least partially used to connect the ground terminal of the chip circuit, as described in subsequent embodiments), and the second metal layer 22 (when not being cut) is used to connect the power terminal of the chip circuit (when being cut, at least partially used to connect the power terminal of the chip circuit, as described in subsequent embodiments). Therefore, the first metal layer 21 can be called a ground potential layer, and the second metal layer 22 can be called a power potential layer.

[0061] In the embodiment of the present application, the power ring 2 includes a structure formed by stacking at least two metal layers, and the at least two metal layers include at least a ground potential layer and a power potential layer. Since the ground potential layer and the power potential layer are stacked up and down (for example, the ground potential layer is located at the bottom and the power potential layer is located at the top, or the direction is also reversed), the two form a circle of loop structure in the top view. Figure 1 The power ring 1 shown makes full use of the effective space under the metal wire, can effectively save chip area, and is conducive to product miniaturization.

[0062] In an embodiment of the present application, the at least two metal layers mentioned above may further include at least one third metal layer. The third metal layer may be located between the first metal layer and the second metal layer and is used to connect the ground terminal of the chip circuit and / or the power terminal of the chip circuit. Figures 3 to 6 to describe.

[0063] Figure 3 FIG. 2 shows a schematic diagram of a power ring 3 in a top view and a three-dimensional structure according to another embodiment of the present application. Figure 3 As shown, from the perspective of the top view on the left, the power ring 3 includes a circle of ring wire structure arranged around the chip circuit (i.e., the chip internal module); from the perspective of the stereoscopic view on the right, the ring wire structure includes a structure formed by stacking at least two layers of metal layers, wherein an insulating layer is arranged between adjacent metal layers for isolating each other (to prevent short circuits caused by connection to each other when they are set to different potentials). Figure 3 In the embodiment shown, the at least two metal layers include a first metal layer 21, a second metal layer 22 and a third metal layer 23. The first metal layer 21 can be used to connect the ground terminal of the chip circuit; the second metal layer 22 is used to connect the power terminal of the chip circuit; the third metal layer 23 is located between the first metal layer 21 and the second metal layer 22, and the third metal layer 23 can be connected to the ground terminal and / or the power terminal of the chip circuit according to the needs (later combined Figures 4 to 6 Therefore, the first metal layer 21 can be called a ground potential layer, the second metal layer 22 can be called a power supply potential layer, and the third metal layer 23 can be called a custom potential layer.

[0064] In the embodiment of the present application, the power ring 3 includes a structure formed by stacking at least three metal layers, and the at least three metal layers include at least a ground potential layer, a power potential layer and a customized potential layer. Since they are stacked up and down, the three of them form a ring line structure in the top view. Figure 1 The power ring 1 shown in the figure makes full use of the effective space under the metal wire, which can effectively save the chip area and is conducive to product miniaturization. Furthermore, since the power ring 3 also includes a customized potential layer, the power ring 3 can more flexibly meet the needs of different chips. Figures 4 to 6 Further description.

[0065] Figure 4 Shows Figure 3 FIG. 1 is a schematic diagram of a cross-sectional view of an example of a power ring. Figure 4 As shown, the first metal layer 21 is a ground potential layer, the second metal layer 22 is a power supply potential layer, and a first through hole 24 is provided between the third metal layer 23 and the first metal layer 21. The first through hole 24 is used to electrically connect the third metal layer 23 to the first metal layer 21, so that the third metal layer 23 is connected to the ground terminal of the chip circuit.

[0066] In this embodiment, the third metal layer 23 serves as a customized potential layer, and eventually becomes a ground potential layer together with the first metal layer 21, so that the chip ground is thicker and the current rapid release capability is stronger, which can be better suitable for chips with greater demands for electrostatic discharge (ESD). In a further embodiment, the second metal layer 22 can also be divided into two parts electrically isolated from each other, one part of which is connected to the power supply, and the other part is electrically connected to the third metal layer 23 through a through hole, so that the part is also grounded, thereby further improving the electrostatic release capability, and better suitable for chips with greater demands for electrostatic release.

[0067] Figure 5 Shows Figure 3 FIG. 1 is a cross-sectional view of another example of a power ring. Figure 5 As shown, the first metal layer 21 is a ground potential layer, the second metal layer 22 is a power supply potential layer, and a second through hole 25 is provided between the third metal layer 23 and the second metal layer 22. The second through hole 25 is used to electrically connect the third metal layer 23 to the second metal layer 22, so that the third metal layer 23 is connected to the power supply end of the chip circuit.

[0068] In this embodiment, the third metal layer 23 serves as a customized potential layer, and eventually becomes a power potential layer together with the second metal layer 22, so that the chip has a stronger overcurrent capability and a lower line resistance, and can be better suited for chips that have a greater emphasis on overcurrent capability and line resistance. In a further embodiment, the first metal layer 21 can also be divided into two electrically isolated parts, one of which is grounded, and the other is electrically connected to the third metal layer 23 through a through hole, so that this part is also connected to the power supply, thereby further improving the overcurrent capability, and better suited for chips that have a greater demand for overcurrent capability.

[0069] Figure 6 Shows Figure 3 FIG. 2 is a cross-sectional view of another example of a power supply ring. Figure 6 As shown, the first metal layer 21 is a ground potential layer, the second metal layer 22 is a power supply potential layer, and the third metal layer 23 is cut into a first part 231 and a second part 232. A third through hole 26 is provided between the first part 231 of the third metal layer 23 and the first metal layer 21, and the third through hole 26 is used to electrically connect the first part 231 of the third metal layer 23 with the first metal layer 26, so that the first part 231 of the third metal layer 23 is connected to the ground terminal of the chip circuit. A fourth through hole 27 is provided between the second part 232 of the third metal layer 23 and the second metal layer 22, and the fourth through hole 27 is used to electrically connect the second part 232 of the third metal layer 23 with the second metal layer 22, so that the second part 232 of the third metal layer 23 is connected to the power terminal of the chip circuit.

[0070] In this embodiment, the third metal layer 23 serves as a customized potential layer and can be divided into two parts that are electrically isolated from each other (for example, cut into two parts and electrically isolated from each other by an insulating layer), one part is connected to the power supply together with the second metal layer 22, and the other part is grounded together with the first metal layer 21, so that the overcurrent capability, line resistance and electrostatic release capability of the chip can all be taken into account, and it can be better suitable for chips with balanced requirements for overcurrent capability, line resistance and electrostatic release capability.

[0071] In the above combination Figures 4 to 6 In the described embodiment, for the sake of simplicity, only three metal layers are described. In more complex embodiments, more metal layers may be included to more flexibly meet different chip requirements. For example, four metal layers may be included, with the upper two layers being power potential layers and the lower two layers being ground potential layers; for another example, five metal layers may be included, with the upper three layers being power potential layers and the lower two layers being ground potential layers, and so on. In addition, no matter how many metal layers there are, each metal layer may be divided into several electrically isolated parts to achieve different customized requirements, as described above.

[0072] Now return to continue reference Figure 2 In the embodiment of the present application, customized requirements can also be achieved by only using two metal layers.

[0073] For example, in one embodiment, the second metal layer 22 may include two parts electrically isolated from each other, one part is connected to a power source, and the other part is electrically connected to the first metal layer 21 through a through hole and thus grounded. Figure 7 Such an example is shown. Figure 7 As shown, the second metal layer 22 includes a first portion 221 and a second portion 222. A fifth through hole 28 is provided between the first portion 221 of the second metal layer 22 and the first metal layer 21, and the fifth through hole 28 is used to electrically connect the first portion 221 of the second metal layer 22 to the first metal layer 21, so that the first portion 221 of the second metal layer 22 is connected to the ground terminal of the chip circuit; the second portion 222 of the second metal layer 22 is used to connect the power terminal of the chip circuit.

[0074] In this embodiment, part of the second metal layer 22 is grounded, so that the ground of the chip is thicker and the ability to quickly release current is stronger, which can be better suitable for chips with greater requirements for electrostatic release. Such customized requirements are achieved through two metal layers, and the structure is simpler.

[0075] In another embodiment, the first metal layer 21 may include two parts electrically isolated from each other, one part is grounded, and the other part is electrically connected to the second metal layer 22 through a through hole to connect to a power source (not shown). Specifically, the first metal layer 21 may include a first part and a second part electrically isolated from each other. Among them, the first part of the first metal layer 21 is connected to the ground terminal of the chip circuit; a sixth through hole (not shown) is provided between the second part of the first metal layer 21 and the second metal layer 22, and the sixth through hole is used to electrically connect the second part of the first metal layer 21 to the second metal layer 22, so that the second part of the first metal layer 21 is connected to the power terminal of the chip circuit.

[0076] In this embodiment, part of the first metal layer 21 is connected to the power supply, so that the chip has stronger overcurrent capability and lower line resistance, and can be better suitable for chips that have more emphasis on overcurrent capability and line resistance. Such customized requirements are achieved through two metal layers, and the structure is simpler.

[0077] In the present application, due to the above-mentioned stacking (laminated) design, additional beneficial metal parasitic decoupling capacitors will be introduced into the power supply, because the capacitor has the characteristics of isolating DC and passing AC, and the power supply noise is usually an AC signal, so these parasitic capacitors can filter the power supply noise and noise, and play a beneficial role. In a further embodiment of the present application, a capacitor device can be set under each of the above-mentioned metal layers or at least one metal layer, and the two ends of the capacitor device are respectively connected to the power supply end of the chip circuit and the ground end of the chip circuit, so that the capacitance value can be further used to filter the power supply noise and noise, ensuring the stability and cleanliness of the power supply, thereby ensuring the stability of the chip system.

[0078] Figure 8 Figure 1 shows a schematic diagram of capacitors placed under the power ring. Figure 8 As shown, the left figure is an overall schematic diagram of the capacitor laid under the power loop according to the embodiment of the present application, wherein the capacitor 29 can be laid along the loop. The right figure is a selected point enlarged figure of the left figure, where the NMOS capacitor is laid as a specific example. It can be seen that the main body of the NMOS capacitor is arranged below the power (ground) metal line, and the lower plate of the capacitor is directly connected to the first metal layer 21 (ground potential) through the contact hole 30, and the upper plate of the capacitor is connected to the second metal layer 22 (power potential) through the contact hole 31 and the through hole (not shown). Among them, because the second metal layer 22 and the first metal layer 21 are connected to the MOS electrode, the second metal layer 22 will have a very small offset relative to the first metal layer 21 (such as Figure 8 The second metal layer 22 is slightly exposed on the left side relative to the first metal layer 21. Since the offset is less than 1 micron at most, relative to Figure 1 The distance between the inner and outer circles is very small in tens of microns and can be ignored, that is, the first metal layer 21 and the second metal layer 22 are still overlapped in the top view, forming a metal wire structure in one circle instead of two circles. In this embodiment, the space below the power ring is further fully utilized, and the decoupling capacitor is placed between the power supply and the ground, so as to filter the power disturbance and stabilize the power supply.

[0079] In a further embodiment of the present application, the corners of the loop structure of the power ring according to the embodiment of the present application can be cut, for example, a 45-degree cut, so as to avoid stress damage at the corners caused by chip cutting. Fig. 9 Such an example is shown, Fig. 9 As shown, the four cut corners of the power ring according to the embodiment of the present application can be cut at 45 degrees. The capacitive devices mentioned above can also be arranged at the cut corners.

[0080] In a further embodiment of the present application, the power ring according to the embodiment of the present application is designed as a multi-power domain, that is, it may include at least two parts electrically isolated from each other, and the second metal layers 22 of the at least two parts are respectively connected to different power terminals of the chip circuit. Fig.10 to describe.

[0081] Fig.10 is Figure 3 The structural diagram obtained based on the embodiment shown in FIG. Fig.10 As shown, the power ring can be divided into two parts, namely power (ground) 1 and power (ground) 2, and the three internal metal layers are also divided accordingly. After the division, power domain 1 and power domain 2 are formed, and the two power domains are independently powered and grounded. This embodiment is particularly suitable for chips with special design requirements such as divided power supply or divided ground.

[0082] Here, it should be noted that Fig.10 In the figure, the three metal layers are shown as being segmented, but in actual applications, the first metal layer 21 may not need to be segmented, because the two power domains can generally meet the needs of independent power supply, and generally do not need to be grounded separately. Similarly, the third metal layer 23 may not need to be segmented (for example, when the entire layer is connected to the first metal layer 21 through a through hole, or when the entire layer is connected to the second metal layer 22 through a through hole). In addition, Fig.10 In the figure, only two power domains are shown, but this is only an example for the sake of simplicity. In actual applications, the power ring can also be divided into more power domains, such as three power domains, four power domains or more power domains.

[0083] The above exemplifies the power ring for a chip according to an embodiment of the present application. Based on the above description, the power ring for a chip according to an embodiment of the present application saves more chip area than the conventional structure. Through stacking processing and refined power line division, it can ensure that the power (ground) line meets the design requirements and avoids the waste of resources (chip area); the design margin (metal routing resources) can also be purposefully tilted to ensure the robustness of the design; it can support multi-power domain design; because of the stacking design, it will also introduce additional beneficial metal parasitic decoupling capacitors to the power supply, and at the same time, placing decoupling MOS capacitors under the stacked metal can filter power disturbances and stabilize the power supply.

[0084] According to another aspect of the present application, a chip is further provided, which may include a chip circuit and the power ring according to the embodiment of the present application described above, wherein the power ring is arranged around the chip circuit.

[0085] According to another aspect of the present application, an electronic device is provided, which includes the above-mentioned chip.

[0086] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0087] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0088] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0089] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0090] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0091] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0092] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0093] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some modules in the article analysis device according to the embodiment of the present application. The present application can also be implemented as a device program (e.g., computer program and computer program product) for executing part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0094] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0095] The above is only a specific implementation method or description of a specific implementation method of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A power ring for a chip, characterized in that: The power ring includes a ring wire structure arranged around the chip circuit, and the ring wire structure includes: At least two metal layers, the at least two metal layers are stacked, and the at least two metal layers include: A first metal layer, wherein the first metal layer is used to connect a ground terminal of the chip circuit; A second metal layer, the second metal layer is used to connect the power supply terminal of the chip circuit; The insulating layer is disposed between adjacent metal layers and is used to electrically isolate the adjacent metal layers.

2. The power ring according to claim 1, characterized in that: The at least two metal layers further include: At least one third metal layer is located between the first metal layer and the second metal layer, and the third metal layer is used to connect the ground terminal of the chip circuit and / or the power terminal of the chip circuit.

3. The power ring according to claim 2, characterized in that: A first through hole is provided between the third metal layer and the first metal layer, and the third metal layer is electrically connected to the first metal layer through the first through hole, so that the third metal layer is connected to the ground terminal of the chip circuit.

4. The power ring according to claim 2, characterized in that: A second through hole is provided between the third metal layer and the second metal layer, and the third metal layer is electrically connected to the second metal layer through the second through hole, so that the third metal layer is connected to the power supply terminal of the chip circuit.

5. The power ring according to claim 2, characterized in that: The third metal layer includes: a first portion of the third metal layer, a third through hole being provided between the first portion of the third metal layer and the first metal layer, the third through hole being used to electrically connect the first portion of the third metal layer to the first metal layer, so that the first portion of the third metal layer is connected to the ground terminal of the chip circuit; A fourth through hole is provided between the second part of the third metal layer and the second metal layer, and the fourth through hole is used to electrically connect the second part of the third metal layer with the second metal layer, so that the second part of the third metal layer is connected to the power supply terminal of the chip circuit.

6. The power ring according to claim 1, characterized in that: The second metal layer includes electrically isolated: a first portion of the second metal layer, wherein a fifth through hole is disposed between the first portion of the second metal layer and the first metal layer, and the fifth through hole is used to electrically connect the first portion of the second metal layer to the first metal layer, so that the first portion of the second metal layer is connected to the ground terminal of the chip circuit; The second part of the second metal layer is used to connect the power supply terminal of the chip circuit.

7. The power ring according to claim 1, characterized in that: The first metal layer includes: a first portion of the first metal layer, wherein the first portion of the first metal layer is connected to a ground terminal of the chip circuit; A sixth through hole is provided between the second part of the first metal layer and the second metal layer, and the sixth through hole is used to electrically connect the second part of the first metal layer with the second metal layer, so that the second part of the first metal layer is connected to the power supply terminal of the chip circuit.

8. The power supply ring according to any one of claims 1 to 7, characterized in that: The loop structure includes at least two parts which are electrically isolated from each other, and the second metal layers in each of the at least two parts are respectively connected to different power supply terminals of the chip circuit.

9. The power supply ring according to any one of claims 1 to 7, characterized in that: Below each metal layer is provided: A capacitor device, two ends of which are respectively connected to a power supply end of the chip circuit and a ground end of the chip circuit.

10. The power supply ring according to any one of claims 1 to 7, characterized in that: The corners of the loop structure are cut corners.

11. A chip, characterized in that: The chip comprises: Chip circuit; The power ring for a chip as described in claims 1-10 is arranged around the chip circuit.

12. The chip according to claim 11, characterized in that: The chip is an analog chip.

13. An electronic device, characterized in that: The electronic device comprises the chip according to claim 11 or 12.

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