Micro light-emitting diode light-emitting unit, device and preparation method of device

Abstract

The invention relates to the technical field of micro light-emitting diodes, and discloses a light-emitting unit and device of a micro light-emitting diode and a preparation method of the device. Comprising a driving circuit layer, an epitaxial structure, a first transparent conductive layer, a passivation layer, a second transparent conductive layer, an electrode structure, a dielectric material layer and a metal collimation structure, the epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer; the first transparent conductive layer is arranged between the driving circuit layer and the epitaxial structure; the passivation layer is arranged on the epitaxial structure, the side wall of the first transparent conductive layer and the upper surface of the driving circuit layer; the second transparent conductive layer covers the outer surfaces of the epitaxial structure and the passivation layer; the electrode structure is arranged on the second transparent conductive layer; the dielectric material layer is arranged on the epitaxial structure; the metal collimation structure is arranged on the dielectric material layer to form a through hole and an annular groove. According to the dielectric material layer, the critical angle of emergent light is increased, and the light extraction efficiency is improved; the metal collimation structure reduces divergence angles and light crosstalk, and convergence collimation is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of micro light emitting diodes, and in particular to a micro light emitting diode light emitting unit, a device and a method for preparing the device. Background Art

[0002] In recent years, with the rapid development of high-tech electronic products such as smart phones, tablets, and wearable devices, the requirements for product resolution and display performance have been increasing. Micro-light-emitting diodes (hereinafter referred to as Micro-LEDs) have become a promising next-generation new display and light-emitting device because they can achieve extremely high pixel density and resolution, and have the advantages of high brightness, high contrast, and fast response time.

[0003] In the related technology, the light extraction efficiency of the Micro-LED device itself is a major bottleneck restricting its development. The light extraction efficiency of the Micro-LED device can be reflected as the light extraction efficiency, that is, the number of photons emitted by the Micro-LED device. Inside the Micro-LED device, there is the absorption of photons by the material, and the loss of photons reflected back to the inside at the interface caused by the high reflectivity of the material. Although the reflection of photons inside can increase the proportion of photons emitted from some side walls, the light extraction efficiency in the forward direction, that is, the light-emitting side, is limited, thereby affecting the light extraction efficiency on the light-emitting side of the device. On the other hand, each Micro-LED light-emitting unit of the Micro-LED device can be regarded as an approximate Lambertian light source, and its light intensity in a certain direction is cosine-distributed. The divergence angle of the emitted light beam is large. The presence of a large amount of invalid light will cause the light to disperse and greatly reduce the quality of the light beam. In addition, with the demand for high-resolution and low-power displays, the size of a single light-emitting unit, or pixel, in a Micro-LED device and the spacing between pixels will also decrease as the resolution requirements increase, resulting in increased optical crosstalk between pixels. Especially when Micro-LED devices are used in small-size optical devices, lateral optical crosstalk will be more obvious. Summary of the invention

[0004] In view of this, the present invention provides a micro light emitting diode light emitting unit, a device and a method for preparing the device to solve the problems of low light output efficiency, large light beam divergence angle and optical crosstalk in existing Micro-LED devices.

[0005] In the first aspect, the present invention provides a micro-light emitting diode light-emitting unit, comprising: a driving circuit layer, an epitaxial structure, a first transparent conductive layer, a passivation layer, a second transparent conductive layer, an electrode structure, a dielectric material layer and a metal alignment structure; the epitaxial structure is arranged on the driving circuit layer, comprising a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence; the first transparent conductive layer is arranged between the driving circuit layer and the epitaxial structure; the passivation layer is arranged on the side walls of the epitaxial structure and the first transparent conductive layer, and covers the exposed surface of the driving circuit layer close to the epitaxial structure; the second transparent conductive layer covers the outer surface of the epitaxial structure and the passivation layer; the electrode structure is arranged on the second transparent conductive layer; the dielectric material layer is arranged on the second transparent conductive layer on the side of the epitaxial structure away from the driving circuit layer; the metal alignment structure is arranged on the side of the dielectric material layer away from the driving circuit layer, and the metal alignment structure is formed with a through hole penetrating the metal alignment structure and a plurality of concentric annular grooves surrounding the through hole.

[0006] In the present invention, the light beam is a surface light beam that is perpendicular to the surface of the driving circuit layer and is emitted upward from one side of the metal collimation structure. A voltage is applied to the electrode structure to achieve electrical connection with the driving circuit layer, thereby promoting the recombination of carriers in the epitaxial structure to generate photons. When the photons reach the dielectric material layer, compared with being emitted directly from the semiconductor layer of the epitaxial structure to the outside, this embodiment passes through the dielectric material layer, which greatly increases the critical angle of the emitted light, allowing photons with a larger incident angle to escape. The electrode structure does not block the light-emitting side, allowing more light to be emitted, thereby improving the forward light extraction on the light-emitting side. Efficiency; when the photons reach the interface between the dielectric material layer and the metal collimation structure, some photons are directly emitted from the through-hole, which is equivalent to the light emitted by a point light source, and the generated light beam is concentratedly emitted. The other part of the photons propagate along the interface to the through-hole at the center under the action of the surface plasmon resonance effect, and then emit from the through-hole. The concentrically spaced multiple annular grooves are equivalent to forming a grating structure. When the photons reaching the annular grooves escape from the annular grooves, the light divergence angle will also become smaller, ultimately achieving the effect of reducing lateral optical crosstalk and converging and collimating, thereby improving the light output quality.

[0007] In an optional embodiment, a plurality of concentric annular grooves surrounding the through hole are formed on a side of the metal alignment structure away from the driving circuit layer.

[0008] In the present invention, etching is performed on the side of the metal alignment structure facing outward and away from the epitaxial structure to form a through hole penetrating the middle position and a plurality of concentric annular grooves surrounding the through hole. The contact surface between the metal alignment structure and the dielectric material layer is a plane, which facilitates the molding of the metal alignment structure, and the plane interface contributes to the stability of the surface plasmon resonance enhancement.

[0009] In an optional embodiment, a plurality of concentric annular grooves surrounding the through hole are formed on a side of the metal alignment structure close to the driving circuit layer, and a cylindrical protrusion and a plurality of concentric annular protrusions surrounding the cylindrical protrusion are formed on a side of the dielectric material layer away from the driving circuit layer, the cylindrical protrusion is located in the through hole, and the annular protrusion is engaged with the annular groove.

[0010] In the present invention, the through hole of the metal collimation structure and the multiple concentric annular grooves surrounding the through hole are formed on the side facing inward and close to the epitaxial structure; the surface of the metal collimation structure on the side away from the driving circuit layer is flat and not easily damaged, and the contact surface where the surface plasmon resonance occurs is a plurality of small contact surfaces of bent contact, the overall contact area is increased, the surface plasmon resonance effect is enhanced, the divergence angle is further constrained, and the beam quality is improved.

[0011] In an optional embodiment, the depth of the annular groove accounts for 30% to 80% of the depth of the through hole; the spacing between adjacent annular grooves ranges from 0.4 μm to 0.7 μm, and the ratio of the width of the annular groove to the spacing between adjacent annular grooves ranges from 0.3 to 0.8.

[0012] In the present invention, the depth and diameter of the through hole, the depth and diameter of the annular groove, and the duty cycle within the above range help to ensure that the surface plasmon resonance effect is enhanced, further constrain the divergence angle of the outgoing light beam, avoid optical crosstalk, and improve the light beam quality.

[0013] In an optional embodiment, the epitaxial structure is formed into a step-like structure, including a bottom region and a ridge region, the bottom region includes a portion of the second semiconductor layer, the ridge region includes another portion of the second semiconductor layer, the active layer and the first semiconductor layer, and the projection area of ​​the ridge region on the driving circuit layer is smaller than the projection area of ​​the bottom region on the driving circuit layer.

[0014] In the present invention, the epitaxial structure is formed into a stepped structure, and the light beam is emitted from one side of the ridge area with a smaller cross-sectional size, so that the light output is better concentrated; the bottom area with a larger cross-sectional size is electrically connected to the driving circuit, which helps the carriers flow to the active layer for recombination and improves the light output efficiency.

[0015] In an optional embodiment, it further includes: a reflective layer disposed between the first transparent conductive layer and the driving circuit layer, and a bonding layer disposed between the reflective layer and the driving circuit layer.

[0016] In the present invention, the reflective layer can reflect the emitted photons on the reverse side to increase the photons emitted in the forward direction on the light emitting side, and the bonding layer is used to achieve a reliable electrical connection between the Micro-LED chip and the driving circuit layer, namely the Si-CMOS driving circuit layer.

[0017] In an optional embodiment, the cross-sectional dimensions of the reflective layer and the bonding layer are equal, and the cross-sectional dimensions of the first transparent conductive layer and the bottom region of the epitaxial structure are equal; in the direction from the driving circuit layer to the metal alignment structure, among the driving circuit layer, the reflective layer and the bonding layer, the first transparent conductive layer and the bottom region, and the ridge region, the cross-sectional dimension of the structure relatively close to the metal alignment structure is smaller than the cross-sectional dimension of the structure relatively far from the metal alignment structure.

[0018] In the present invention, the sidewall of each micro-LED light-emitting unit is formed into a step shape according to the structure and preparation process, and the cross-sectional size decreases from bottom to top. The cross-sectional size of the driving circuit layer is the largest, and the bonding layer and the reflective layer thereon are smaller than the driving circuit layer. The area smaller than the driving circuit layer is used to set the electrode structure to ensure that the electrode structure does not block the forward light. At the same time, the cross-sectional size of the bonding layer and the reflective layer is larger than the cross-sectional size of the first transparent conductive layer and the bottom area of ​​the epitaxial structure to ensure that the reflective layer can reflect all the photons emitted in the reverse direction, effectively increase the number of photons emitted in the forward direction, and reversely ensure that there is sufficient carrier flow between the first transparent conductive layer and the driving circuit layer to ensure that the electrons and holes in the epitaxial structure are fully recombined in the active layer to generate photons. The cross-sectional size of the ridge area is further smaller than the cross-sectional size of the first transparent conductive layer to ensure the concentrated light emission on the light-emitting side of the upper surface. The same cross-sectional size can be formed simultaneously using the same process to ensure the molding accuracy.

[0019] In a second aspect, the present invention further provides a micro light emitting diode device, comprising:

[0020] A plurality of the aforementioned micro-LED light-emitting units are arranged in an array and share a common driving circuit layer.

[0021] In the present invention, multiple micro-light emitting diode light-emitting units arranged in an array are set on the same driving circuit layer, thereby forming a two-dimensional micro-light emitting diode device with high pixel density. Each pixel can be addressed and controlled and independently driven to emit light. Each light-emitting unit has high light intensity and small divergence angle. The optical crosstalk between different light-emitting units is reduced, so that the overall light output of the device is concentrated and the light beam quality is good. It can be used for small-sized display devices and has a wide range of applications.

[0022] In a third aspect, the present invention further provides a method for preparing a micro-light emitting diode device, which is used to prepare the above-mentioned micro-light emitting diode device, and the preparation method comprises:

[0023] forming an epitaxial structure, wherein the epitaxial structure comprises a first semiconductor layer, an active layer, and a second semiconductor layer arranged in sequence;

[0024] forming a first transparent conductive layer on one side of the second semiconductor layer of the epitaxial structure;

[0025] The epitaxial structure and the first transparent conductive layer are arranged on the driving circuit layer, and the first transparent conductive layer is arranged toward the driving circuit layer;

[0026] A passivation layer is disposed on the side walls of the epitaxial structure and the first transparent conductive layer and on the surface of the driving circuit layer exposed on one side close to the epitaxial structure;

[0027] forming a second transparent conductive layer on the outer surface of the epitaxial structure and the passivation layer;

[0028] forming an electrode structure on the second transparent conductive layer;

[0029] forming a dielectric material layer on the second transparent conductive layer on the side of the epitaxial structure away from the driving circuit layer;

[0030] A metal alignment structure is formed on the side of the dielectric material layer away from the driving circuit layer to form a plurality of light-emitting units; the metal alignment structure is formed with a through hole penetrating the metal alignment structure and a plurality of concentric annular grooves surrounding the through hole.

[0031] In the present invention, after the Micro-LED chip is prepared by epitaxy, it is flip-chip fixed on the driving circuit layer, and a voltage is applied to the electrode structure to achieve electrical connection with the driving circuit layer, thereby promoting the recombination of carriers in the epitaxial structure to generate photons. When the photons reach the dielectric material layer, compared with directly emitting from the semiconductor layer of the epitaxial structure to the outside, this embodiment further arranges a dielectric material layer on the light-emitting side, which greatly increases the critical angle of the emitted light, allowing photons with a larger incident angle to escape, and the electrode structure does not block the light-emitting side, so that more light can be emitted, thereby improving the forward light on the light-emitting side. Extraction efficiency; when the photons reach the interface between the dielectric material layer and the metal collimation structure, some photons are directly emitted from the through-hole, which is equivalent to the light emitted by a point light source, and the generated light beam is concentratedly emitted. The other part of the photons propagate along the interface to the through-hole at the center under the action of the surface plasmon resonance effect, and then emit from the through-hole. The concentrically spaced multiple annular grooves are equivalent to forming a grating structure. When the photons reaching the annular grooves escape from the annular grooves, the light divergence angle will also become smaller, ultimately achieving the effect of reducing lateral optical crosstalk and converging and collimating, thereby improving the light output quality.

[0032] In an optional implementation, forming a metal alignment structure on a side of the dielectric material layer away from the driving circuit layer includes:

[0033] forming a metal layer on a side of the dielectric material layer away from the driving circuit layer;

[0034] An etching process is performed on the side of the metal layer away from the driving circuit layer to form a through hole penetrating the metal layer and a plurality of concentric annular grooves surrounding the through hole to form a metal alignment structure.

[0035] In the present invention, etching is performed on the side of the metal layer facing outward and away from the epitaxial structure in the above-mentioned manner to form a through hole penetrating the middle position and a plurality of concentric annular grooves surrounding the through hole; the contact surface between the metal alignment structure and the dielectric material layer is a plane, which is convenient for the metal layer to adhere and form, and the planar interface contributes to the stability of the surface plasmon resonance enhancement, thereby improving the light output quality.

[0036] In an optional embodiment, after forming a dielectric material layer on the second transparent conductive layer on the side of the epitaxial structure away from the driving circuit layer and before forming a metal alignment structure on the side of the dielectric material layer away from the driving circuit layer, the method further includes: etching on the side of the dielectric material layer away from the driving circuit layer to form a columnar protrusion and a plurality of concentric annular protrusions surrounding the columnar protrusion;

[0037] Forming a metal alignment structure on the side of the dielectric material layer away from the driving circuit layer includes: growing a metal layer on the side of the dielectric material layer away from the driving circuit layer, filling the gaps between the columnar protrusions and the annular protrusions and between adjacent annular protrusions on the side of the metal layer close to the driving circuit layer, forming a through hole penetrating the metal layer and a plurality of concentric annular grooves surrounding the through hole to form a metal alignment structure, the columnar protrusion is located in the through hole, and the annular protrusion is embedded in the annular groove.

[0038] In the present invention, a metal layer is grown on the surface after the dielectric material layer is etched, and the metal layer fills the gaps between adjacent annular protrusions, and finally forms a metal alignment structure with an annular groove facing the epitaxial structure. The metal alignment structure is formed by filling the metal material, and the molding quality is good. Finally, the surface on the side away from the driving circuit layer is formed into a plane, which reduces the possibility of damage to the metal alignment structure. The contact surface where the surface plasmon resonance occurs is a plurality of small contact surfaces of bent contact, and the overall contact area is increased, the surface plasmon resonance effect is enhanced, and the divergence angle is further constrained, and the beam quality is improved.

[0039] In an optional embodiment, forming the epitaxial structure includes:

[0040] providing a substrate layer;

[0041] forming a buffer layer on one surface of the substrate layer;

[0042] forming a first semiconductor layer on a surface of the buffer layer facing away from the substrate layer;

[0043] forming an active layer on a surface of the first semiconductor layer facing away from the substrate layer;

[0044] A second semiconductor layer is formed on a surface of the active layer facing away from the substrate layer.

[0045] In the present invention, the substrate layer serves as a supporting structure for epitaxially preparing a high-quality gallium nitride epitaxial structure, and then a buffer layer is arranged on the substrate layer to effectively improve lattice matching, improve surface flatness, relieve stress, enhance electrical performance, provide a high-quality template, and reduce optical performance degradation, thereby providing necessary support and guarantee for the growth of high-quality epitaxial structures, and significantly improving the overall performance and production yield of Micro-LED devices.

[0046] In an optional embodiment, after the epitaxial structure and the first transparent conductive layer are disposed on the driving circuit layer, and before the passivation layer is disposed on the side walls of the epitaxial structure and the first transparent conductive layer and the surface of the driving circuit layer exposed near the epitaxial structure, the method further includes:

[0047] Etching is performed on a side of the epitaxial structure away from the driving circuit layer to form a plurality of step-like structures, wherein the step-like structures include a bottom region and a ridge region, wherein the bottom region includes a portion of the second semiconductor layer, and the ridge region includes another portion of the second semiconductor layer, the active layer, and the first semiconductor layer, and a projection area of ​​the ridge region on the driving circuit layer is smaller than a projection area of ​​the bottom region on the driving circuit layer.

[0048] In the present invention, etching is performed on an epitaxial structure in which the first semiconductor layer, the active layer, and the second semiconductor layer are completely corresponding to each other, and etching is performed from one side of the first semiconductor layer to a portion of the second semiconductor layer. The first semiconductor layer, the active layer, and a portion of the second semiconductor layer form a ridge-shaped area with a smaller cross-sectional size. The light beam is emitted from the ridge-shaped area, which is more concentrated and has a good light output quality.

[0049] In an optional embodiment, after forming the first transparent conductive layer on one side of the second semiconductor layer of the epitaxial structure and before arranging the epitaxial structure and the first transparent conductive layer on the driving circuit layer, the method further includes:

[0050] forming a reflective layer on a surface of the first transparent conductive layer facing away from the second semiconductor layer;

[0051] forming a bonding layer on a surface of the reflective layer facing away from the second semiconductor layer;

[0052] The flip-chip epitaxial structure, the first transparent conductive layer, the reflective layer and the bonding layer are arranged such that the bonding layer faces the driving circuit layer.

[0053] In the present invention, the reflective layer can reflect the emitted photons on the opposite side of the light emitting side, thereby increasing the photons emitted in the forward direction of the light emitting side; the bonding layer is used to realize the electrical connection between the Micro-LED chip and the driving circuit layer, namely the Si-CMOS driving circuit layer; after the above structure is flipped, the bonding layer with excellent conductive performance directly contacts the driving circuit layer, thereby realizing efficient conduction with the driving circuit layer.

[0054] In an optional implementation, after the epitaxial structure and the first transparent conductive layer are disposed on the driving circuit layer and before the side of the epitaxial structure facing away from the driving circuit layer is etched, the method further includes:

[0055] The substrate layer and the buffer layer of the epitaxial structure are removed to expose the second semiconductor layer.

[0056] In the present invention, the sapphire substrate layer can be removed by laser lift-off technology before the epitaxial structure is subjected to a subsequent etching process, and the buffer layer can be completely removed by etching, so that subsequent process treatment can be performed on the epitaxial structure.

[0057] In an optional embodiment, a passivation layer is disposed on the sidewalls of the epitaxial structure and the first transparent conductive layer and on the surface of the driving circuit layer exposed on one side close to the epitaxial structure, including:

[0058] Covering one side of the ridge region with a first passivation sublayer;

[0059] Etching is performed at the edge of the first passivation sublayer to remove a portion of the first passivation sublayer, the second semiconductor layer and the first transparent conductive layer to expose the reflective layer;

[0060] Etching is performed at the edge of the reflective layer to remove part of the reflective layer and the bonding layer to expose the driving circuit layer;

[0061] The second passivation sublayer is covered on the side walls of the first passivation sublayer, the side walls of the second semiconductor layer, the side walls of the first transparent conductive layer, the exposed surface and side walls of the reflective layer, the side walls of the bonding layer, and the exposed surface of the driving circuit layer. The first passivation sublayer and the second passivation sublayer constitute a passivation layer.

[0062] In the present invention, a passivation layer is formed by etching a stepped main structure in steps and depositing in steps; step-by-step etching can adopt different etching methods for different materials, improve etching accuracy and ensure the performance of the structural layer; the passivation layer is formed by step-by-step deposition, and different materials can be selected to achieve the purpose, which helps to save costs, and the reliability of the passivation layer is relatively high. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1 is a structural schematic diagram of a micro light emitting diode light emitting unit according to an embodiment of the present invention;

[0065] Figure 2 is a structural schematic diagram of another micro light emitting diode light emitting unit according to an embodiment of the present invention;

[0066] Figure 3 It is a schematic flow chart of a method for preparing a micro-LED light-emitting unit according to an embodiment of the present invention;

[0067] Figure 4 is a schematic diagram of the structure after forming an epitaxial structure according to an embodiment of the present invention;

[0068] Figure 5 is a schematic structural diagram of forming a first transparent conductive layer on an epitaxial structure according to an embodiment of the present invention;

[0069] Figure 6 is a schematic structural diagram of forming a reflective layer and a bonding layer on a first transparent conductive layer according to an embodiment of the present invention;

[0070] Figure 7 It is a schematic diagram of a structure in which all structures formed by epitaxy are flipped and arranged behind a driving circuit layer according to an embodiment of the present invention;

[0071] Figure 8 is a schematic diagram of the structure of an embodiment of the present invention after removing the substrate layer and the buffer layer;

[0072] Fig. 9 is a schematic diagram of the structure after etching to form a ridge region in an embodiment of the present invention;

[0073] Fig.10 is a schematic structural diagram of an embodiment of the present invention after a first passivation sublayer is disposed on a ridge region;

[0074] Fig.11 is a schematic diagram of the structure after etching is performed on the edge of the first passivation sublayer according to an embodiment of the present invention;

[0075] Fig.12 is a schematic diagram of the structure after forming a passivation layer according to an embodiment of the present invention;

[0076] Fig.13 is a schematic structural diagram of an embodiment of the present invention after forming a second transparent conductive layer and an electrode structure;

[0077] Fig.14 is a schematic structural diagram of forming a dielectric material layer in a first micro-LED light-emitting unit according to an embodiment of the present invention;

[0078] Fig.15 is a schematic structural diagram of a first micro-LED light-emitting unit after a metal alignment structure is formed in the first micro-LED light-emitting unit according to an embodiment of the present invention;

[0079] Fig.16is a schematic structural diagram of the second micro-LED light-emitting unit after the dielectric material layer is etched in the embodiment of the present invention;

[0080] Fig.17 It is a schematic structural diagram after a metal alignment structure is formed in the second micro-LED light-emitting unit according to an embodiment of the present invention.

[0081] Description of reference numerals:

[0082] 1. Driving circuit layer; 2. First semiconductor layer; 3. Active layer; 4. Second semiconductor layer; 5. Ridge region; 6. First transparent conductive layer; 7. Passivation layer; 8. Second transparent conductive layer; 9. Electrode structure; 10. Dielectric material layer; 101. Columnar protrusion; 102. Annular protrusion; 11. Metal alignment structure; 111. Through hole; 112. Annular groove; 12. Reflective layer; 13. Bonding layer; 14. Substrate layer; 15. Buffer layer. DETAILED DESCRIPTION

[0083] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only some structures related to the present invention are shown in the accompanying drawings, rather than all structures. In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if one layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0084] Micro-LED devices are composed of an array of micron-scale light-emitting units, each of which is equivalent to a pixel, and each pixel can be addressed, controlled, and independently driven to emit light. Micro-LED devices in related technologies have problems with poor light extraction efficiency, light dispersion, and optical crosstalk in applications. Specifically, on the one hand, the light extraction efficiency or light extraction efficiency of the Micro-LED device itself is low, that is, the number of photons that can escape forward from the Micro-LED device is small. On the other hand, the photons of each Micro-LED light-emitting unit have a large divergence angle when escaping to form a light beam, resulting in light dispersion and poor beam quality. As the demand for high-resolution and low-power display increases, the size of pixels and the spacing between pixels in Micro-LED devices are decreasing, which increases the optical crosstalk between pixels. Especially when Micro-LED devices are used in small-sized optical devices, the lateral optical crosstalk will be more obvious, which ultimately leads to poor light quality of Micro-LED devices.

[0085] Based on this, the present embodiment provides a micro-LED light-emitting unit, a micro-LED device including a plurality of micro-LED light-emitting units, and a preparation method thereof. On the one hand, each micro-LED light-emitting unit adopts a flip-chip structure and a dielectric material layer 10 is arranged on the light-emitting side, so that more photons escape on the light-emitting side to improve the forward light extraction efficiency; on the other hand, a metal collimation structure 11 is arranged on the dielectric material layer 10 on the light-emitting side, and an electromagnetic mode is formed in the interface region between the metal collimation structure 11 and the dielectric material layer, thereby improving the light output efficiency and reducing the optical crosstalk between adjacent sub-pixels, and utilizing the surface plasmon resonance effect to effectively constrain the light output divergence angle, perform light beam collimation and shaping, and improve the light output quality.

[0086] See also Figure 1 and Figure 2A micro light emitting diode light emitting unit provided in this embodiment includes: a driving circuit layer 1, an epitaxial structure, a first transparent conductive layer 6, a passivation layer 7, a second transparent conductive layer 8, an electrode structure 9, a dielectric material layer 10 and a metal alignment structure 11; the epitaxial structure is arranged on the driving circuit layer 1, and includes a first semiconductor layer 2, an active layer 3 and a second semiconductor layer 4 arranged in sequence; the first transparent conductive layer 6 is arranged between the driving circuit layer 1 and the epitaxial structure; the passivation layer 7 is arranged on the side walls of the epitaxial structure and the first transparent conductive layer 6, and covers The exposed surface of the driving circuit layer 1 is close to the epitaxial structure; the second transparent conductive layer 8 covers the outer surface of the epitaxial structure and the passivation layer 7; the electrode structure 9 is arranged on the second transparent conductive layer 8; the dielectric material layer 10 is arranged on the second transparent conductive layer 8 on the side of the epitaxial structure away from the driving circuit layer 1; the metal alignment structure 11 is arranged on the side of the dielectric material layer 10 away from the driving circuit layer 1, and the metal alignment structure 11 is formed with a through hole 111 penetrating the metal alignment structure 11 and a plurality of concentric annular grooves 112 surrounding the through hole 111.

[0087] Specifically, the driving circuit layer 1 uses a Si-CMOS driving circuit layer, that is, a CMOS integrated circuit is processed on a silicon wafer to serve as the driving circuit layer 1; the first semiconductor layer 2 of the epitaxial structure is located on a side of the active layer 3 relatively far away from the driving circuit layer 1, and the first semiconductor layer 2 is an N-type gallium nitride (n-GaN) semiconductor layer formed by doping, providing majority carrier electrons; the active layer 3 uses an indium gallium nitride / gallium nitride (InGaN / GaN) quantum well structure, and the active layer 3 is the main photon generation region in the Micro-LED, and photons are generated and light is emitted through the recombination of electrons and holes in the active layer 3; the second semiconductor layer 4 is a P-type gallium nitride (p-GaN) semiconductor layer formed by doping, which provides majority carrier holes and forms a pn junction with the first semiconductor layer 2; the first transparent conductive layer 6 is arranged on the side of the second semiconductor layer 4 of the epitaxial structure close to the driving circuit layer 1, and indium tin oxide (IndiumTin Oxide, hereinafter referred to as ITO) material, provides good transparency and excellent conductivity, so that the Micro-LED can work normally. A certain ohmic contact is formed between the first transparent conductive layer 6 and the second semiconductor layer 4, creating conditions for achieving electrical connectivity, while avoiding current crowding and improving current uniformity; a passivation layer 7 is set on the sidewalls of the stacked epitaxial structure and the first transparent conductive layer 6, and extends to cover the surface of the driving circuit layer 1 exposed on the side close to the epitaxial structure, that is, used to isolate the electrically connected epitaxial structure, the first transparent conductive layer 6 and the driving circuit layer 1 from the external environment. The passivation layer 7 of this embodiment adopts one or more of silicon nitride, aluminum oxide, and silicon oxide. The thickness of the passivation layer 7 is usually several hundred nanometers. In this embodiment, it is set to 260nm, which protects the device structure and surface, improves optical and electrical properties, and provides a basis and operating conditions for subsequent process steps; the second transparent conductive layer 7 is entirely covered on the outer side of the passivation layer 7 and the upper surface of the epitaxial structure. The first transparent conductive layer 8 is provided with an electrode structure 9, so as to realize an electrical path through the second transparent conductive layer 8, the epitaxial structure, the first transparent conductive layer 6 and the driving circuit layer 1, so that the N-type electrons and the P-type holes in the epitaxial structure are recombined to generate photons; a dielectric material layer 10 is provided on the epitaxial structure, and in this embodiment, silicon oxide (SiO2) with a positive dielectric constant is used, and the thickness is also usually several hundred nanometers, which is set to about 800nm ​​in this embodiment, so as to form a surface plasmon resonance effect with a metal alignment structure 11 with a negative dielectric constant; the metal alignment structure 11 is made of silver (Ag) or gold (Au), and the metal alignment structure 11 is formed with a through hole 111 at the center position of the surface perpendicular to the light emitting direction, and a concentric annular groove 112 is formed around the through hole 111, and the cross-sections of the through hole 111 and the annular groove 112 are circular, and the metal alignment structure 11 and the dielectric material layer 10 are combined to form a bull's eye structure for alignment.

[0088] The light beam of the micro-LED light-emitting unit of this embodiment is a plane light beam that is perpendicular to the surface of the driving circuit layer 1 and is emitted upward from the side of the metal collimating structure 11. A voltage is applied to the electrode structure 9 to achieve electrical connection with the driving circuit layer 1, thereby promoting the recombination of carriers in the epitaxial structure to generate photons. When the photons reach the dielectric material layer 10, compared with being emitted directly from the semiconductor layer of the epitaxial structure to the outside, this embodiment passes through the dielectric material layer 10 again, which greatly increases the critical angle of the emitted light, allowing photons with a larger incident angle to escape. The electrode structure 9 does not block the light-emitting side, so that more light can be emitted, thereby improving the forward light extraction on the light-emitting side. Efficiency; when the photons reach the interface between the dielectric material layer 10 and the metal collimation structure 11, some photons are directly emitted from the through hole 111, which is equivalent to the light emitted by the point light source, and the generated light beam is concentratedly emitted, and the other part of the photons propagate along the interface to the through hole 111 at the center position under the action of the surface plasmon resonance effect, and then emit from the through hole 111, and the multiple concentrically spaced annular grooves 112 are equivalent to forming a grating structure. When the photons reaching the annular groove 112 escape from the annular groove 112, the light divergence angle will also become smaller, and finally the lateral optical crosstalk is reduced, the effect of convergence and collimation is achieved, and the light quality is improved.

[0089] The surface plasmon resonance effect mentioned above refers to an electromagnetic mode formed by the interaction between free electrons and photons in the interface region between metal and dielectric. When the light wave in the SiO2 of the dielectric material layer is incident on the interface between metal and SiO2, it will collectively oscillate with the free electrons on the metal surface, and then couple to form a near-field electromagnetic wave that propagates along the metal surface. If the oscillation frequency of the free electrons is consistent with the frequency of the incident light wave, resonance will occur. In the resonant state, the energy of the electromagnetic field is effectively converted into the collective vibration energy of the free electrons on the metal surface, thereby forming a special electromagnetic mode. In this electromagnetic mode, the electromagnetic field is confined to a very small range on the metal surface and is enhanced, and propagates along the metal surface, so that the photons propagate along the metal surface to the central through hole 111 and are emitted. Moreover, the photons propagating to the part of the annular groove 112 can also constrain the divergence angle when escaping, which ultimately reduces the overall divergence angle of the light beam and reduces the lateral optical crosstalk.

[0090] In an optional embodiment, if Figure 1 As shown, a plurality of concentric annular grooves 112 surrounding the through hole 111 are formed on a side of the metal alignment structure 11 facing away from the driving circuit layer 1 .

[0091] That is, etching is performed on the side of the metal alignment structure 11 facing outward and away from the epitaxial structure to form a through hole 111 penetrating the middle and a plurality of concentric annular grooves 112 surrounding the through hole 111. Figure 1The contact surface between the metal alignment structure 11 and the dielectric material layer 10 is a plane, which facilitates the molding of the metal alignment structure 11 , and the plane interface is conducive to the stability of the surface plasmon resonance enhancement.

[0092] In another optional embodiment, if Figure 2 As shown, a plurality of concentric annular grooves 112 surrounding the through hole 111 are formed on the side of the metal alignment structure 11 close to the driving circuit layer 1, and a cylindrical protrusion 101 and a plurality of concentric annular protrusions 102 surrounding the cylindrical protrusion 101 are formed on the side of the dielectric material layer 10 away from the driving circuit layer 1, the cylindrical protrusion 101 is located in the through hole 111, and the annular protrusion 102 is embedded in the annular groove 112.

[0093] Figure 2 The metal alignment structure 11 shown can be regarded as Figure 1 The metal collimation structure 11 is inverted as shown; the through hole 111 of the metal collimation structure 11 and a plurality of concentric annular grooves 112 surrounding the through hole 111 are formed on the side facing inward and close to the epitaxial structure. Correspondingly, in order to ensure the stability of the metal collimation structure 11, a cylindrical protrusion 101 is formed in the middle position of the surface of one side of the dielectric material layer 10 for setting the metal collimation structure 11, and a plurality of concentric annular protrusions 102 are formed around the cylindrical protrusion 101. The bottom of the annular groove 112 is connected to the top surface of the annular protrusion 102. The through hole 111 and the cylindrical protrusion 101 are arranged with the same radial size to fix the metal collimation structure 11 on the dielectric material layer 10. Under this arrangement, the surface of the side of the metal collimation structure 11 away from the driving circuit layer 1 is a plane and is not easily damaged. The contact surface where the surface plasmon resonance occurs is a plurality of small contact surfaces of bent contact, the overall contact area is increased, the surface plasmon resonance effect is enhanced, the divergence angle is further constrained, and the beam quality is improved.

[0094] In one embodiment, the depth of the annular groove 112 accounts for 30% to 80% of the depth of the through hole 111; the spacing between adjacent annular grooves 112 ranges from 0.4 μm to 0.7 μm, and the ratio of the width of the annular groove 112 to the spacing between adjacent annular grooves 112 ranges from 0.3 to 0.8.

[0095] Further, the diameter of the through hole 111 of the present embodiment is about 0.4 μm, and the ratio of the width of the annular groove 112 to the spacing between adjacent annular grooves 112 is defined as the duty cycle, that is, the duty cycle in the present embodiment is between 0.3 and 0.8, and the depth of the annular groove 112 is preferably 40% to 70% of the depth of the through hole 111; the thickness of the metal alignment structure 11 is set between 25 nm and 40 nm, such as 25 nm, 30 nm, 35 nm, 40 nm, etc. The thickness of the metal alignment structure 11 in the figure is only for schematic illustration, and the specific thickness is referred to the above definition.

[0096] The ratio of the depth of the annular groove 112 to the depth of the through hole 111, that is, the ratio of the etching depth of the annular groove 112 in the metal collimation structure 11, limits the depth and diameter of the through hole 111, the depth and diameter of the annular groove 112 and the duty cycle within the above range to ensure that the effect of the surface plasmon resonance is enhanced, further constrain the divergence angle of the outgoing light beam, avoid optical crosstalk, and improve the light beam quality.

[0097] In this embodiment, the epitaxial structure is formed into a step-like structure, including a bottom region and a ridge region 5, the bottom region includes a portion of the thickness of the second semiconductor layer 4, the ridge region 5 includes another portion of the thickness of the second semiconductor layer 4, the active layer 3 and the first semiconductor layer 2, and the projection area of ​​the ridge region 5 on the driving circuit layer 1 is smaller than the projection area of ​​the bottom region on the driving circuit layer 1.

[0098] The epitaxial structure is etched from the edge of one side of the first semiconductor layer 2, and the first semiconductor layer 2, the active layer 3 and the second semiconductor layer 4 are gradually etched from top to bottom, retaining a certain thickness of the second semiconductor layer 4 to ensure a complete planar second semiconductor layer 4 for uniform carriers.

[0099] In one embodiment, the micro LED light emitting unit further includes: a reflective layer 12 and a bonding layer 13 , wherein the reflective layer 12 is disposed between the first transparent conductive layer 6 and the driving circuit layer 1 , and the bonding layer 13 is disposed between the reflective layer 12 and the driving circuit layer 1 .

[0100] The material of the reflective layer 12 is silver (Ag), and the material of the bonding layer 13 is metal titanium (Ti) or gold (Au). The total thickness of the reflective layer 12 and the metal layer is about 0.7μm, of which the thickness of the reflective layer 12 is very small and can be ignored. The reflective layer 12 can reflect the photons emitted on the reverse side and increase the photons emitted in the forward direction on the light-emitting side. The bonding layer 13 is used to achieve a reliable electrical connection between the Micro-LED chip and the driving circuit layer 1, i.e., the Si-CMOS driving circuit layer. The Micro-LED chip includes an epitaxial structure and a main structure such as the first transparent conductive layer 6 for collecting carrier flow and realizing electro-optical conversion.

[0101] like Figure 1 As shown, the cross-sectional dimensions of the above-mentioned reflective layer 12 and bonding layer 13 are equal, and the cross-sectional dimensions of the first transparent conductive layer 6 and the bottom region of the epitaxial structure are equal; in the direction from the driving circuit layer 1 to the metal alignment structure 11, among the driving circuit layer 1, the reflective layer 12 and bonding layer 13, the first transparent conductive layer 6 and the bottom region, and the ridge region 5, the cross-sectional dimension of the structure relatively close to the metal alignment structure 11 is smaller than the cross-sectional dimension of the structure relatively far from the metal alignment structure 11.

[0102] In this embodiment, the side wall of each micro-LED light-emitting unit is formed into a step shape according to the structure and the manufacturing process. Figure 1 As shown, the cross-sectional dimensions decrease from bottom to top. The driving circuit layer 1 has the largest cross-sectional dimension, followed by the bonding layer 13 and the reflective layer 12 thereon. The area smaller than the driving circuit layer 1 is used to set the electrode structure 9 to ensure that the electrode structure 9 does not block the forward light. At the same time, the cross-sectional dimensions of the bonding layer 13 and the reflective layer 12 are larger than the cross-sectional dimensions of the first transparent conductive layer 6 and the bottom layer to ensure that the reflective layer 12 can reflect all the reversely emitted photons, effectively increasing the number of forward emitted photons. In the reverse direction, it can also ensure that there is sufficient carrier flow between the first transparent conductive layer 6 and the driving circuit layer 1 to ensure that the electrons and holes in the epitaxial structure are fully recombined in the active layer 3 to generate photons. The cross-sectional dimension of the ridge region 5 is further smaller than the cross-sectional dimension of the first transparent conductive layer 6 to ensure the concentrated light emission on the light-emitting side of the upper surface. The same cross-sectional dimensions can be formed simultaneously using the same process to ensure the molding accuracy.

[0103] This embodiment also provides a micro light emitting diode device, comprising: a plurality of the above-mentioned micro light emitting diode light emitting units, the plurality of micro light emitting diode light emitting units are arranged in an array, and a common driving circuit layer 1 is provided.

[0104] Multiple micro-light emitting diode light-emitting units arranged in an array are set on the same driving circuit layer 1 serving as a driving circuit, thereby forming a two-dimensional micro-light emitting diode device with high pixel density. Each pixel can be addressed and controlled and independently driven to emit light. Each light-emitting unit has high light intensity and a small divergence angle. The optical crosstalk between different light-emitting units is reduced, so that the overall light output of the device is concentrated and the light beam quality is good. It can be used for small-sized display devices and has a wide range of applications.

[0105] like Figures 3 to 17 As shown, this embodiment also provides a method for preparing a micro light emitting diode device, which is used to prepare the above-mentioned micro light emitting diode device. Figure 3 The figure is a flow chart of a method for preparing a micro light emitting diode device, the method comprising:

[0106] S301 , forming an epitaxial structure, wherein the epitaxial structure includes a first semiconductor layer 2 , an active layer 3 , and a second semiconductor layer 4 arranged in sequence.

[0107] refer to Figure 4 , exemplarily, the epitaxial structure is epitaxially formed on the substrate layer 14 through the buffer layer 15, and the lattice matching is ensured. The substrate layer 14 and the buffer layer 15 are described below. The first semiconductor layer 2 is an N-type gallium nitride (n-GaN) semiconductor layer formed by doping Si, and the doping concentration is about 10 19 cm -3, with a thickness of about 1 μm to provide majority carrier electrons; the active layer 3 uses an indium gallium nitride / gallium nitride (InGaN / GaN) quantum well structure, InGaN is a quantum well layer material with a thickness of 3 nm, GaN is a barrier layer material with a thickness of 10 nm or 12 nm, a quantum well layer and a barrier layer form a quantum well structure, and the quantum well structure is set to 3-10, and the quantum well layer is sandwiched between two barrier layers to form a barrier layer-quantum well layer-barrier layer structure. The indium (In) content in the active layer 3 accounts for 0.18, so that the peak emission wavelength is about 460 nm; the second semiconductor layer 4 is a P-type gallium nitride (p-GaN) semiconductor layer formed by doping with Mg, and the doping concentration is about 10 19 cm -3 , with a thickness of about 0.15μm to provide majority carrier holes and form a pn junction with n-GaN.

[0108] S302, forming a first transparent conductive layer 6 on one side of the second semiconductor layer 4 of the epitaxial structure.

[0109] refer to Figure 5 The first transparent conductive layer 6 is arranged on one side of the second semiconductor layer 4 of the epitaxial structure, and is made of indium tin oxide (ITO) material, which provides good transparency and excellent conductivity. In addition, after the first transparent conductive layer 6 is formed, the first transparent conductive layer 6 is annealed in this embodiment to form an ohmic contact between the first transparent conductive layer 6 and the second semiconductor layer 4, creating conditions for achieving electrical connectivity, while avoiding current crowding and improving current uniformity.

[0110] S303 , disposing the epitaxial structure and the first transparent conductive layer 6 on the driving circuit layer 1 , with the first transparent conductive layer 6 facing the driving circuit layer 1 .

[0111] refer to Figure 6 and Figure 7 , the driving circuit layer 1 uses a Si-CMOS driving circuit layer, that is, a CMOS integrated circuit is processed on a silicon wafer to serve as the driving circuit layer 1, and the epitaxial structure and the first transparent conductive layer 6 are transferred to the driving circuit layer 1 to achieve electrical connection between the epitaxial structure and the driving circuit layer 1. It can be known that the first transparent conductive layer 6 is formed on the upper surface of the epitaxial structure, and when the epitaxial structure and the first transparent conductive layer 6 are arranged on the driving circuit layer 1, the first transparent conductive layer 6 faces the driving circuit layer 1. At this time, the first transparent conductive layer 6 is on the lower surface of the epitaxial structure, that is, this step is to flip the epitaxial structure and place it on the driving circuit layer 1.

[0112] S304 , a passivation layer 7 is disposed on the side walls of the epitaxial structure and the first transparent conductive layer 6 and on the surface of the driving circuit layer 1 .

[0113] like Fig.12 As shown, a passivation layer 7 is provided on the side walls of the stacked epitaxial structure and the first transparent conductive layer 6, and extends to cover the surface of the driving circuit layer 1, that is, it is used to isolate the electrically connected epitaxial structure, the first transparent conductive layer 6 and the driving circuit layer 1 from the external environment. The passivation layer 7 of this embodiment adopts one or more of silicon nitride, aluminum oxide, and silicon oxide. The thickness of the passivation layer 7 is usually several hundred nanometers, and is set to 260nm in this embodiment to protect the device structure and surface, improve the optical and electrical properties, and provide a basis and operating conditions for subsequent process steps.

[0114] S305 , forming a second transparent conductive layer 8 on the outer surface of the epitaxial structure and the passivation layer 7 .

[0115] like Fig.13 As shown, the second transparent conductive layer 8 is entirely covered on the outer side of the passivation layer 7 and the upper surface of the epitaxial structure, forming an ohmic contact with the epitaxial structure, thereby realizing an electrical path through the second transparent conductive layer 8, the epitaxial structure, the first transparent conductive layer 6 and the driving circuit layer 1.

[0116] S306 , forming an electrode structure 9 on the second transparent conductive layer 8 .

[0117] like Fig.13 As shown, an electrode structure 9 is arranged on the second transparent conductive layer 8. In this embodiment, the electrode structure 9 is arranged on the second transparent conductive layer 8 above the edge driving circuit layer 1. The Si-CMOS driving circuit layer is used as the positive electrode of the power supply to connect the second semiconductor layer 4 of P-GaN, and the electrode structure 9 is used as the negative electrode to reach the first semiconductor layer 2 of N-GaN through the second transparent conductive layer 8 connected to the side wall, so as to realize an electrical path. The carrier recombination is that the positive P-GaN second semiconductor layer 4 provides holes, and the negatively charged N-GaN first semiconductor layer 2 provides electrons. The electron-hole pairs are radiatively recombinated in the active layer 3 to generate photons.

[0118] S307 , forming a dielectric material layer 10 on the second transparent conductive layer 8 on the side of the epitaxial structure away from the driving circuit layer 1 .

[0119] like Fig.14As shown, a dielectric material layer 10 is provided on the epitaxial structure. In this embodiment, silicon oxide (SiO2) with a positive dielectric constant is used. The thickness of the dielectric material layer 10 is several hundred nanometers, which is set to about 800nm ​​in this embodiment. On the one hand, the dielectric material layer 10 can increase the critical angle, from the critical angle of 23.8° when the first semiconductor layer 2 of the direct epitaxial structure of the traditional scheme is emitted to the air layer, to the critical angle of 36.2° when the first semiconductor layer 2 of GaN is emitted to the dielectric material layer 10 of SiO2 in this embodiment, that is, the provision of the dielectric material layer 10 in this embodiment can allow photons with a larger incident angle to escape, and the dielectric material layer 10 also has the function of serving as a substrate when the metal collimation structure 11 is subsequently prepared on the light-emitting side.

[0120] S308 , forming a metal alignment structure 11 on the side of the dielectric material layer 10 away from the driving circuit layer 1 to form a plurality of light-emitting units; the metal alignment structure 11 is formed with a through hole 111 penetrating the metal alignment structure 11 , and a plurality of concentric annular grooves 112 surrounding the through hole 111 .

[0121] The metal collimation structure 11 is made of silver (Ag) or gold (Au). The metal collimation structure 11 has a through hole 111 formed at the center of the surface perpendicular to the light emitting direction, and a concentric annular groove 112 is formed around the through hole 111. The cross-sections of the through hole 111 and the annular groove 112 are circular. The metal collimation structure 11 is combined with the dielectric material layer 10 to form a bull's eye structure for collimation.

[0122] In the preparation method of the micro-light emitting diode device of this embodiment, the light beam is a surface light beam that is perpendicular to the surface of the driving circuit layer 1 and is emitted upward from one side of the metal collimating structure 11. The Micro-LED chip is prepared by epitaxy and then flipped and fixed on the driving circuit layer 1. A voltage is applied to the electrode structure 9 to achieve electrical connection with the driving circuit layer 1, thereby promoting the recombination of carriers in the epitaxial structure to generate photons. When the photons reach the dielectric material layer 10, compared with directly emitting from the semiconductor layer of the epitaxial structure to the outside, this embodiment further sets the dielectric material layer 10 on the light-emitting side, which greatly increases the critical angle of the emitted light, allowing photons with a larger incident angle to escape, and the electrode structure 9 does not block the light-emitting side, making it more More light can be emitted, thereby improving the forward light extraction efficiency on the light-emitting side; when the photons reach the interface between the dielectric material layer 10 and the metal collimation structure 11, some photons are directly emitted from the through hole 111, which is equivalent to the light emitted by the point light source, and the generated light beam is concentratedly emitted, while the other photons propagate along the interface to the through hole 111 at the center position under the action of the surface plasmon resonance effect, and then emit from the through hole 111, and the multiple concentrically spaced annular grooves 112 are equivalent to forming a grating structure, and when the photons reaching the annular groove 112 escape from the annular groove 112, the light divergence angle will also become smaller, ultimately achieving the effect of reducing lateral optical crosstalk and converging and collimating, thereby improving the light output quality.

[0123] In an optional embodiment, the forming of the metal alignment structure 11 on the side of the dielectric material layer 10 away from the driving circuit layer 1 comprises:

[0124] S3081a, forming a metal layer on a side of the dielectric material layer 10 facing away from the driving circuit layer 1.

[0125] The metal layer is formed by electroplating. The thickness of the metal layer is between 25nm and 40nm, and can be 35nm. The material is silver or gold.

[0126] S3082a, such as Fig.15 As shown, etching is performed on the side of the metal layer away from the driving circuit layer 1 to form a through hole 111 penetrating the metal layer and a plurality of concentric annular grooves 112 surrounding the through hole 111. The plurality of annular grooves 112 are sequentially arranged along the radial direction of the through hole 111 to form a metal alignment structure 11.

[0127] For example, the through hole 111 and the annular groove 112 can be formed by photolithography after setting a mask layer on the metal layer. The method of setting the mask layer for photolithography is a conventional method and will not be described in detail here. The mask layer can be SiO2 or photoresist, and the mask layer is removed by wet removal after etching.

[0128] By etching the metal layer on the side facing outward and away from the epitaxial structure in the above manner, a through hole 111 penetrating the middle and a plurality of concentric annular grooves 112 surrounding the through hole 111 are formed. Fig.15 The metal alignment structure 11 shown has a contact surface with the dielectric material layer 10 that is a plane, which facilitates the metal layer to be attached and formed, and the plane interface helps to enhance the stability of the surface plasmon resonance, thereby improving the light output quality.

[0129] In an optional embodiment, after forming the dielectric material layer 10 on the second transparent conductive layer 8 on the side of the epitaxial structure away from the driving circuit layer 1, and before forming the metal alignment structure 11 on the side of the dielectric material layer 10 away from the driving circuit layer 1, the method further includes: Fig.16 As shown, etching is performed on the side of the dielectric material layer 10 facing away from the driving circuit layer 1 to form a cylindrical protrusion 101 and a plurality of concentric annular protrusions 102 surrounding the cylindrical protrusion 101 .

[0130] Specifically, similarly, photoresist can be spin-coated on the upper surface of the dielectric material layer 10 or SiO2 can be deposited as a mask layer, and then the dielectric material layer 10 can be partially removed by etching using photolithography technology to form a columnar protrusion 101 and a plurality of concentric annular protrusions 102 surrounding the columnar protrusion 101, and finally the remaining mask layer can be removed by wet removal.

[0131] On the basis of the above, forming a metal alignment structure 11 on the side of the dielectric material layer 10 away from the driving circuit layer 1 includes: S3081b, such as Fig.17 As shown, a metal layer is grown on the side of the dielectric material layer 10 facing away from the driving circuit layer 1, and the side of the metal layer close to the driving circuit layer 1 fills the gaps between the cylindrical protrusions 101 and the annular protrusions 102 and between adjacent annular protrusions 102 to form a through hole 111 penetrating the metal layer and a plurality of concentric annular grooves 112 surrounding the through hole 111 to form a metal alignment structure 11, the cylindrical protrusion 101 is located in the through hole 111, and the annular protrusion 102 is embedded in the annular groove 112.

[0132] That is, a metal layer is grown on the surface of the dielectric material layer 10 after etching, and the metal layer fills the gaps between adjacent annular protrusions 102, and finally forms a metal collimation structure 11 with an annular groove 112 facing the epitaxial structure. The metal collimation structure 11 is formed by filling with metal materials, and the molding quality is good. Finally, the surface on the side away from the driving circuit layer 1 is formed into a plane, which reduces the possibility of damage to the metal collimation structure 11, and the contact surface where the surface plasmon resonance occurs is a plurality of small contact surfaces of bent contact, the overall contact area is increased, the surface plasmon resonance effect is enhanced, the divergence angle is further constrained, and the beam quality is improved.

[0133] In one embodiment, forming the epitaxial structure includes:

[0134] S3011, providing a substrate layer 14.

[0135] Exemplarily, the substrate layer 14 may be a sapphire substrate selected for the preparation of a high-quality gallium nitride epitaxial layer.

[0136] S3012 , forming a buffer layer 15 on one side surface of the substrate layer 14 .

[0137] The non-intentionally doped gallium nitride buffer layer 15 (u-GaN) is epitaxially grown on the substrate layer 14 by using the metal organic chemical vapor deposition (MOCVD) technology, and the thickness of the buffer layer 15 is about 2μm-3μm. The buffer layer 15 can effectively improve lattice matching, improve surface flatness, relieve stress, enhance electrical performance, provide high-quality templates, and reduce optical performance degradation, providing the necessary support and guarantee for the growth of high-quality epitaxial structures, and significantly improving the overall performance and production yield of Micro-LED devices.

[0138] S3013 , forming a first semiconductor layer 2 on a surface of the buffer layer 15 facing away from the substrate layer 14 .

[0139] S3014 , forming an active layer 3 on a surface of the first semiconductor layer 2 facing away from the substrate layer 14 .

[0140] S3015 , forming a second semiconductor layer 4 on a surface of the active layer 3 facing away from the substrate layer 14 .

[0141] The epitaxial structure formed on the substrate layer and the buffer layer is as follows Figure 4 As shown, the specific configurations of the first semiconductor layer 2, the active layer 3 and the second semiconductor layer 4 are as described above and will not be elaborated herein.

[0142] In one embodiment, after the epitaxial structure and the first transparent conductive layer 6 are disposed on the driving circuit layer 1, and before the passivation layer 7 is disposed on the sidewalls of the epitaxial structure and the first transparent conductive layer 6 and the surface of the driving circuit layer 1 exposed near the epitaxial structure, the method further includes:

[0143] Etching is performed on the side of the epitaxial structure facing away from the driving circuit layer 1 to form a plurality of step-like structures, wherein the step-like structures include a bottom region and a ridge region 5, wherein the bottom region includes a portion of the second semiconductor layer 4, and the ridge region 5 includes another portion of the second semiconductor layer 4, the active layer 3 and the first semiconductor layer 2, and the projection area of ​​the ridge region 5 on the driving circuit layer 1 is smaller than the projection area of ​​the bottom region on the driving circuit layer 1.

[0144] refer to Fig. 9 The epitaxial structure is etched from the edge of one side of the first semiconductor, and the first semiconductor layer 2, the active layer 3 and the second semiconductor layer 4 are gradually etched from top to bottom by inductively coupled plasma technology (ICP), retaining a certain thickness of the second semiconductor layer 4 to ensure a complete planar second semiconductor layer 4 to uniformly distribute carriers.

[0145] For the sake of illustration, a single light-emitting unit is taken as an example to explain the preparation method after etching the ridge region.

[0146] In one embodiment, after forming the first transparent conductive layer 6 on one side of the second semiconductor layer 4 of the epitaxial structure and before arranging the epitaxial structure and the first transparent conductive layer 6 on the driving circuit layer 1, the method further includes:

[0147] A reflective layer 12 is formed on a surface of the first transparent conductive layer 6 that is away from the second semiconductor layer 4 .

[0148] like Figure 6 As shown, the material of the reflective layer 12 is silver (Ag), and the reflective layer 12 can reflect the emitted photons on the opposite side of the light emitting side, thereby increasing the number of photons emitted in the forward direction of the light emitting side.

[0149] A bonding layer 13 is formed on a surface of the reflective layer 12 that is away from the second semiconductor layer 4 .

[0150] like Figure 6 As shown, the bonding layer 13 material is metal titanium (Ti) or gold (Au), the total thickness of the reflective layer 12 and the metal layer is about 0.7μm, wherein the thickness of the reflective layer 12 is very small and can be ignored, and the bonding layer 13 is used to realize the electrical connection between the Micro-LED chip and the driving circuit layer 1, namely the Si-CMOS driving circuit layer.

[0151] refer to Figure 7 , a flip-chip epitaxial structure, a first transparent conductive layer 6 , a reflective layer 12 and a bonding layer 13 , with the bonding layer 13 facing the driving circuit layer 1 side.

[0152] After the above structure is flipped, the bonding layer 13 with excellent conductive performance directly contacts the driving circuit layer 1 , so as to realize efficient conduction with the driving circuit layer 1 .

[0153] On the basis of the above solution, after the epitaxial structure and the first transparent conductive layer 6 are arranged on the driving circuit layer 1, and before the side of the epitaxial structure away from the driving circuit layer 1 is etched, the method further includes:

[0154] The substrate layer 14 and the buffer layer 15 of the epitaxial structure are removed to expose the second semiconductor layer 4 .

[0155] like Figure 8 As shown, the substrate layer 14 is removed by laser lift-off (LLO) technology, and the buffer layer 15 is completely removed by etching, so as to facilitate subsequent process processing on the epitaxial structure.

[0156] In one embodiment, the above-mentioned step of providing the passivation layer 7 on the sidewalls of the epitaxial structure and the first transparent conductive layer 6 and the surface of the driving circuit layer 1 includes:

[0157] S3041, such as Fig.10 As shown, the ridge region 5 is covered on one side by the first passivation sublayer.

[0158] The first passivation sublayer is made of one or more of silicon nitride, aluminum oxide, and silicon oxide. The first passivation sublayer is formed to be several hundred nanometers thick. The thickness in this embodiment is 260nm, covering the upper surface, side wall surface of the ridge area 5 and the exposed surface of the second semiconductor layer 4, with a focus on protecting the side wall of the ridge area 5 to ensure that the ridge area 5 is not damaged.

[0159] S3042, such as Fig.11 As shown, etching is performed at the edge of the first passivation sublayer to remove a portion of the first passivation sublayer, the second semiconductor layer 4 and the first transparent conductive layer 6 to expose the reflective layer 12 .

[0160] Exemplarily, the first passivation sublayer, the remaining second semiconductor layer 4 and the first transparent conductive layer 6 are etched using an inductively coupled plasma technique, so that the reflective layer 12 at the edge is exposed.

[0161] S3043 , etching is performed at the edge of the reflective layer 12 to remove a portion of the reflective layer 12 and the bonding layer 13 to expose the driving circuit layer 1 .

[0162] The edge of the exposed reflective layer 12 is etched by ion beam etching technology until the driving circuit layer 1 is etched, and a portion of the surface of the reflective layer 12 is retained to form a step, providing space for the subsequent deposition of the second passivation sublayer, thereby improving the reliability of the second passivation sublayer on the side wall. The physical structure isolation between each light-emitting unit is achieved through the above three etchings. At the same time, the electrode structure 9 can be arranged above the exposed driving circuit layer 1 to avoid blocking the forward light.

[0163] S3044, such as Fig.12 As shown, the second passivation sublayer covers the side walls of the first passivation sublayer, the side walls of the second semiconductor layer 4, the side walls of the first transparent conductive layer 6, the exposed surface and side walls of the reflective layer 12, the side walls of the bonding layer 13, and the exposed surface of the driving circuit layer 1, and the first passivation sublayer and the second passivation sublayer constitute a passivation layer 7.

[0164] The second passivation sublayer is mainly used to isolate the bonding layer 13 to ensure electrical insulation between the bonding layer 13 and the outside. The second passivation sublayer has the same thickness and material as the first passivation sublayer, forming a consistent passivation layer 7 .

[0165] The passivation layer 7 is formed by etching the stepped main structure in steps and depositing in steps. Step-by-step etching can adopt different etching methods for different materials, improve etching accuracy and ensure the performance of the structural layer. The passivation layer 7 formed by step-by-step deposition can use different materials to achieve the purpose, which helps to save costs, and the passivation layer 7 has high reliability.

[0166] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0167] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A micro light emitting diode light emitting unit, characterized in that: include: Driving circuit layer; An epitaxial structure, arranged on the driving circuit layer, comprising a first semiconductor layer, an active layer, and a second semiconductor layer arranged in sequence; A first transparent conductive layer, disposed between the driving circuit layer and the epitaxial structure; A passivation layer, disposed on the side walls of the epitaxial structure and the first transparent conductive layer, and covering the surface of the driving circuit layer exposed on a side close to the epitaxial structure; A second transparent conductive layer covering the outer surface of the epitaxial structure and the passivation layer; An electrode structure, disposed on the second transparent conductive layer; A dielectric material layer, disposed on the second transparent conductive layer on a side of the epitaxial structure away from the driving circuit layer; The metal alignment structure is arranged on a side of the dielectric material layer away from the driving circuit layer; the metal alignment structure is formed with a through hole penetrating the metal alignment structure and a plurality of concentric annular grooves surrounding the through hole.

2. The micro light emitting diode light emitting unit according to claim 1, characterized in that: A plurality of concentric annular grooves surrounding the through hole are formed on a side of the metal alignment structure away from the driving circuit layer.

3. The micro light emitting diode light emitting unit according to claim 1, characterized in that: A plurality of concentric annular grooves surrounding the through hole are formed on a side of the metal alignment structure close to the driving circuit layer, and a cylindrical protrusion and a plurality of concentric annular protrusions surrounding the cylindrical protrusion are formed on a side of the dielectric material layer away from the driving circuit layer, the cylindrical protrusion is located in the through hole, and the annular protrusion is embedded in the annular groove.

4. The micro light emitting diode light emitting unit according to claim 2 or 3, characterized in that: The depth of the annular groove accounts for 30% to 80% of the depth of the through hole; the spacing between adjacent annular grooves ranges from 0.4 μm to 0.7 μm, and the ratio of the width of the annular groove to the spacing between adjacent annular grooves ranges from 0.3 to 0.

8.

5. The micro light emitting diode light emitting unit according to claim 4, characterized in that: The epitaxial structure is formed into a step-like structure, including a bottom region and a ridge region, the bottom region includes a portion of the second semiconductor layer, the ridge region includes another portion of the second semiconductor layer, the active layer and the first semiconductor layer, and the projection area of ​​the ridge region on the driving circuit layer is smaller than the projection area of ​​the bottom region on the driving circuit layer.

6. The micro light emitting diode lighting unit according to claim 5, characterized in that: Also includes: A reflective layer, disposed between the first transparent conductive layer and the driving circuit layer; The bonding layer is arranged between the reflective layer and the driving circuit layer.

7. The micro light emitting diode lighting unit according to claim 6, characterized in that: The cross-sectional dimensions of the reflective layer and the bonding layer are equal, and the cross-sectional dimensions of the first transparent conductive layer and the bottom layer region of the epitaxial structure are equal; In the direction from the driving circuit layer to the metal alignment structure, in the driving circuit layer, the reflective layer and the bonding layer, the first transparent conductive layer and the bottom layer, and the ridge region, the cross-sectional size of the structure relatively close to the metal alignment structure is smaller than the cross-sectional size of the structure relatively far from the metal alignment structure.

8. A micro light emitting diode device, characterized in that: include: A plurality of micro-light emitting diode light-emitting units according to any one of claims 1 to 7, wherein the plurality of micro-light emitting diode light-emitting units are arranged in an array and are provided on the same driving circuit layer.

9. A method for preparing a micro light emitting diode device, for preparing the micro light emitting diode device according to claim 8, characterized in that: The preparation method comprises: forming an epitaxial structure, wherein the epitaxial structure comprises a first semiconductor layer, an active layer, and a second semiconductor layer arranged in sequence; forming a first transparent conductive layer on one side of the second semiconductor layer of the epitaxial structure; Disposing the epitaxial structure and the first transparent conductive layer on the driving circuit layer, with the first transparent conductive layer being disposed toward the driving circuit layer; Disposing a passivation layer on the side walls of the epitaxial structure and the first transparent conductive layer and on the surface of the driving circuit layer exposed on one side close to the epitaxial structure; forming a second transparent conductive layer on the outer surface of the epitaxial structure and the passivation layer; forming an electrode structure on the second transparent conductive layer; forming a dielectric material layer on the second transparent conductive layer on a side of the epitaxial structure away from the driving circuit layer; A metal alignment structure is formed on the side of the dielectric material layer away from the driving circuit layer to form a plurality of light-emitting units; the metal alignment structure is formed with a through hole penetrating the metal alignment structure and a plurality of concentric annular grooves surrounding the through hole.

10. The method for preparing a micro light emitting diode device according to claim 9, characterized in that: The forming of a metal alignment structure on a side of the dielectric material layer away from the driving circuit layer comprises: forming a metal layer on a side of the dielectric material layer facing away from the driving circuit layer; An etching process is performed on a side of the metal layer away from the driving circuit layer to form a through hole penetrating the metal layer and a plurality of concentric annular grooves surrounding the through hole to form a metal alignment structure.

11. The method for preparing a micro light emitting diode device according to claim 9, characterized in that: After forming a dielectric material layer on the second transparent conductive layer on the side of the epitaxial structure away from the driving circuit layer, and before forming a metal alignment structure on the side of the dielectric material layer away from the driving circuit layer, the method further includes: etching on the side of the dielectric material layer away from the driving circuit layer to form a columnar protrusion and a plurality of concentric annular protrusions surrounding the columnar protrusion; The forming of the metal alignment structure on the side of the dielectric material layer away from the driving circuit layer includes: growing a metal layer on the side of the dielectric material layer away from the driving circuit layer, the metal layer filling the gaps between the cylindrical protrusions and the annular protrusions and between adjacent annular protrusions on the side close to the driving circuit layer, forming a through hole penetrating the metal layer and a plurality of concentric annular grooves surrounding the through hole to form a metal alignment structure, the cylindrical protrusion is located in the through hole, and the annular protrusion is embedded in the annular groove.

12. The method for preparing a micro light emitting diode device according to claim 9, characterized in that: The forming of the epitaxial structure comprises: providing a substrate layer; forming a buffer layer on one side surface of the substrate layer; forming a first semiconductor layer on a surface of the buffer layer facing away from the substrate layer; forming an active layer on a surface of the first semiconductor layer facing away from the substrate layer; A second semiconductor layer is formed on a surface of the active layer that is away from the substrate layer.

13. The method for preparing a micro light emitting diode device according to claim 12, characterized in that: After the epitaxial structure and the first transparent conductive layer are disposed on the driving circuit layer, and before a passivation layer is disposed on the sidewalls of the epitaxial structure and the first transparent conductive layer and on the surface of the driving circuit layer exposed near the epitaxial structure, the method further includes: Etching is performed on a side of the epitaxial structure away from the driving circuit layer to form a plurality of step-like structures, wherein the step-like structures include a bottom region and a ridge region, wherein the bottom region includes a portion of the second semiconductor layer, and the ridge region includes another portion of the second semiconductor layer, the active layer, and the first semiconductor layer, and a projection area of ​​the ridge region on the driving circuit layer is smaller than a projection area of ​​the bottom region on the driving circuit layer.

14. The method for preparing a micro light emitting diode device according to claim 13, characterized in that: After forming a first transparent conductive layer on one side of the second semiconductor layer of the epitaxial structure and before arranging the epitaxial structure and the first transparent conductive layer on the driving circuit layer, the method further includes: forming a reflective layer on a surface of the first transparent conductive layer facing away from the second semiconductor layer; forming a bonding layer on a surface of the reflective layer on a side away from the second semiconductor layer; The epitaxial structure, the first transparent conductive layer, the reflective layer and the bonding layer are flipped upside down so that the bonding layer faces the driving circuit layer.

15. The method for preparing a micro light emitting diode device according to claim 14, characterized in that: After the epitaxial structure and the first transparent conductive layer are disposed on the driving circuit layer, and before the side of the epitaxial structure facing away from the driving circuit layer is etched, the method further includes: The substrate layer and the buffer layer of the epitaxial structure are removed to expose the second semiconductor layer.

16. The method for preparing a micro light emitting diode device according to claim 15, characterized in that: The passivation layer is disposed on the side walls of the epitaxial structure and the first transparent conductive layer and on the surface of the driving circuit layer exposed on one side close to the epitaxial structure, comprising: Covering one side of the ridge region with a first passivation sublayer; Performing etching at an edge position of the first passivation sublayer to remove a portion of the first passivation sublayer, the second semiconductor layer, and the first transparent conductive layer to expose the reflective layer; Etching is performed at the edge of the reflective layer to remove a portion of the reflective layer and the bonding layer to expose the driving circuit layer; A second passivation sublayer is covered on the side walls of the first passivation sublayer, the side walls of the second semiconductor layer, the side walls of the first transparent conductive layer, the exposed surface and side walls of the reflective layer, the side walls of the bonding layer, and the exposed surface of the driving circuit layer, and the first passivation sublayer and the second passivation sublayer constitute a passivation layer.

Images