Digital-time conversion method and device based on embedded digital phase-locked loop
By introducing an embedded digital phase-locking loop into the number-time conversion method, the offset error problem caused by the phase interpolation is solved, the circuit design is simplified and the cost is reduced.
Patent Information
- Application Number
- CN202310928498.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-27
- Publication Date
- 2025-02-11
AI Technical Summary
In the prior art, the number-time conversion method based on the phase interpoler has offset errors, resulting in inaccurate data sampling and additional DCDL and logic circuits are required for calibration, which increases circuit complexity and cost.
Using the digital time conversion method based on the embedded digital phase-locking loop, by receiving two phase-separated input signals, setting the frequency division number of the digital phase-locking loop, locking the phase difference of the input signal, and selecting the control word of the phase interpolation Input the signal and drive the calibration engine to eliminate errors.
It effectively eliminates the offset error caused by input signal delay, reduces the complexity of circuit design, eliminates the need for additional logic circuit design, and saves hardware resource overhead.
Smart Images
Figure CN119420352A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a digital-time conversion method and device based on a digital phase-locked loop. Background Art
[0002] Digital time conversion (DTC) technology is widely used in circuits. There are many methods for realizing time interval generation in the prior art, which can be divided into analog methods and digital methods according to different implementation methods. The time interval generation system constructed using the digital method has good temperature stability and is beneficial to large-scale integration.
[0003] In DTC circuits, resistor-capacitance circuits (RC) are often used for digital-to-time conversion, that is, by changing the parameters of resistors and capacitors, the digital-to-time conversion method of changing the signal delay length will produce gain errors. Therefore, the digital-to-time conversion method based on phase interpolator can automatically track the input phase separation when the DTC generates gain, which is beneficial to the application of frequency modulated carrier wave (FMCW).
[0004] When using a phase interpolator, because the two phase-separated input signals of the phase interpolation mechanism require their own separate clock paths, the delay difference between them causes an offset error in the phase interpolator, thereby affecting the correct and accurate sampling of the data.
[0005] In the prior art, digitally controlled delay lines (DCDL) are mainly used to assist in delay calibration to solve offset errors, which will produce periodic interference. DCDL is heavy and bulky, and requires additional logic circuits to implement functions, which is costly and not conducive to low-noise designs. Summary of the invention
[0006] The present invention aims to solve all or part of the problems of the above-mentioned prior art and provides a digital-to-time conversion method and device based on a digital phase-locked loop to eliminate the offset error caused by input signal delay, reduce the complexity of circuit design, eliminate the need for additional logic circuit design, and save hardware resource overhead.
[0007] To achieve the above object, the technical solution of the present invention is achieved as follows:
[0008] A first aspect of an embodiment of the present invention provides a method for converting data into time based on an embedded digital phase-locked loop, comprising:
[0009] Receive an input signal and predefine operating parameters; wherein the input signal includes a first input signal and a second input signal; connect the input signal to the core of a phase interpolator and determine a first time interval according to the predefined operating parameters; set the frequency division number of the embedded digital phase-locked loop to lock the phase difference of the input signal; switch the frequency division number of the embedded digital phase-locked loop to change the value of the control word of the phase interpolator; select the input signal according to the value of the control word of the phase interpolator; determine the calibration engine setting through the input signal and drive the digital-to-time conversion.
[0010] The input signal includes a first input signal and a second input signal; wherein the first input signal and the second input signal are two signals separated in phase and have an error.
[0011] The operation parameters include at least one of the following: operation mode; control word duration; control word length; clock frequency. The time interval between the two phase separation signals is created by setting the operation parameters.
[0012] The input signal is connected to the core of the phase interpolator, and the first time interval is determined according to the predefined operating parameters, and the first time interval is determined by retiming the clock of the internal crystal oscillator of the digital phase-locked loop according to the operating parameters; wherein the first time interval refers to the time interval between the first input signal and the second input signal. The phase interpolator can meet the gain automatic tracking input phase separation, which is beneficial to the frequency modulation carrier application.
[0013] The frequency division number of the embedded digital phase-locked loop is set to lock the phase difference of the input signal; when the frequency division number of the embedded digital phase-locked loop is set to N, the value of the control word is set to 0, and the phase difference between the first input signal and the second input signal is stabilized to 0. In this way, in the locked state, the average value of the phase error should gradually converge and stabilize to "0".
[0014] Switching the frequency division number of the embedded digital phase-locked loop and changing the value of the phase interpolator control word also includes: when the frequency division number of the embedded digital phase-locked loop is set to the first frequency division number, setting the value of the phase interpolator control word to full scale; when the frequency division number of the embedded digital phase-locked loop is set to the second frequency division number, setting the value of the control word to 0; switching the frequency division number of the embedded digital phase-locked loop back and forth between the first frequency division number and the second frequency division number; wherein the average value of the frequency division number of the embedded digital phase-locked loop is N.
[0015] According to the value of the control word of the phase interpolator, the input signal is selected, and further includes: if the value of the control word of the phase interpolator is 0, the first input signal is selected; if the value of the control word of the phase interpolator is full scale, the second input signal is selected. In this way, the input signal reflects the relative relationship between the delay of the phase interpolator under the control of FS and the accurate 1UI generated by the embedded digital phase-locked loop divider through the embedded digital phase-locked loop, thereby driving the calibration engine to eliminate errors.
[0016] According to a second aspect of an embodiment of the present disclosure, there is provided a digital-to-time conversion device based on an embedded digital phase-locked loop, the device comprising: an acquisition module for receiving an input signal and predefining operating parameters; wherein the input signal comprises a first input signal and a second input signal; a first processing module for connecting the input signal to the core of a phase interpolator and determining a time interval according to predefined operating parameters; a setting module for setting a frequency division number of the embedded digital phase-locked loop and locking a phase difference of the input signal; a control module for switching the frequency division number of the embedded digital phase-locked loop by changing the value of a control word of the phase interpolator; a selection module for selecting the input signal according to the value of the control word of the phase interpolator; and a confirmation module for determining the calibration engine setting through the input signal and driving the digital-to-time conversion.
[0017] A third aspect of an embodiment of the present disclosure provides an electronic device, comprising: a memory; and a processor, connected to the memory, for executing computer executable instructions stored on the memory, and capable of implementing the digital-to-time conversion method based on an embedded digital phase-locked loop provided by any technical solution of any of the first aspect or the second aspect mentioned above.
[0018] The fourth aspect of the embodiments of the present disclosure provides a computer storage medium, including: the computer storage medium stores computer executable instructions; after the computer executable instructions are executed, the digital-to-time conversion method based on the embedded digital phase-locked loop provided by any technical solution of any first aspect or second aspect mentioned above can be implemented.
[0019] Compared with the prior art, the main beneficial effects of the present invention are as follows: by receiving two phase-separated input signals, a signal whose phase delay is proportional to the control word is output. The gain error is eliminated by the phase interpolator; the offset error generated by the phase interpolator is calibrated by the digital phase-locked loop. In this way, the complexity of circuit design is reduced, no additional logic circuit design is required, and hardware resource overhead is saved. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A schematic flow chart of a method for converting data into time based on an embedded digital phase-locked loop provided in an embodiment of the present invention;
[0021] Figure 2 An operation schematic diagram of a digital-to-time conversion method based on an embedded digital phase-locked loop provided in an embodiment of the present invention;
[0022] Figure 3 A schematic diagram of a calibration flow of a method for converting data to time based on an embedded digital phase-locked loop provided in an embodiment of the present invention;
[0023] Figure 4 A schematic diagram of the structure of a digital-to-time conversion device based on an embedded digital phase-locked loop provided in an embodiment of the present invention;
[0024] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0025] In order to enable a more detailed understanding of the features and technical contents of the present application, the implementation of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the present application.
[0026] like Figure 1 As shown, this embodiment provides a method for converting data to time based on an embedded digital phase-locked loop, the method comprising:
[0027] S110: receiving an input signal and predefining an operation parameter; wherein the input signal includes a first input signal and a second input signal;
[0028] S120: Connecting the input signal to the core of the phase interpolator, and determining a first time interval according to predefined operating parameters;
[0029] S130: Setting the frequency division number of the embedded digital phase-locked loop to lock the phase difference of the input signal;
[0030] S140: Switching the frequency division number of the embedded digital phase-locked loop to change the value of the control word of the phase interpolator;
[0031] S150: Selecting the input signal according to the value of the control word of the phase interpolator;
[0032] S160: Determine calibration engine settings through the input signal and drive digital-to-time conversion.
[0033] The digital-to-time conversion method based on an embedded digital phase-locked loop provided in this embodiment can be applied to various electronic devices, including but not limited to: integrated circuits.
[0034] Input signal refers to an electronic signal in electronics that generally needs to be detected by instruments and meters, and needs to be frequency-converted or amplified for audio, video, carrier, photoelectric, program controller, etc. The input signal can be an analog signal, a digital signal, or a mixed signal of a digital signal and an analog signal. In the present invention, the input signal is a digital signal.
[0035] In addition, in the present invention, the input signal includes a first input signal and a second input signal; wherein there is an error in the signal interval of phase separation between the first input signal and the second input signal; the signal interval can be a predetermined empirical value or experimental value such as 10ps, 100ps or 1000ps.
[0036] A phase interpolator refers to a tool for performing phase difference, which is used to adjust the phase of the sampled clock in order to achieve correct data sampling. The phase interpolator requires multiple input clocks of different phases, usually two-phase input, four-phase input or eight-phase input, and then it will select two adjacent input phases and perform weighted interpolation on them. By adjusting the weights of the two phases, the phase interpolator can output a clock of any phase. The phase interpolator can be used to eliminate the quantization noise generated during frequency division, and can also eliminate the gain error by automatically tracking the input phase separation through gain, which is beneficial to the application of frequency modulated carriers. However, in the process of using the phase interpolator, due to the working principle of the phase interpolator itself, that is, a separate clock path, the delay error between the clock paths produces an offset error of the phase interpolator, and the error can be eliminated by delay calibration of the digital phase-locked loop, which makes the present invention of great significance in low-noise design.
[0037] The digital phase-locked loop is a phase feedback control system. In the digital phase-locked loop, since the error control signal is a discrete digital signal rather than an analog voltage, the change of the controlled output voltage is discrete rather than continuous. In addition, all loop components are implemented with digital circuits. The digital phase-locked loop is mainly composed of a phase reference extraction circuit, a crystal oscillator, a frequency divider, a phase comparator, a pulse fill gate, etc. The signal frequency output by the frequency divider is very close to the required frequency. It is sent to the phase comparator at the same time as the phase reference signal extracted from the signal. When the comparison result shows that the local frequency is high, a pulse input to the frequency divider is erased through the fill gate, which is equivalent to a decrease in the local oscillation frequency; on the contrary, if it shows that the local frequency is low, a pulse is inserted between the two input pulses at the input end of the frequency divider, which is equivalent to an increase in the local oscillation frequency, thereby achieving synchronization.
[0038] In some embodiments, S110 may include: receiving an input signal and predefining an operation parameter; wherein the input signal includes a first input signal and a second input signal;
[0039] The input signal includes a first input signal and a second input signal; wherein the first input signal and the second input signal are two phase-separated signals and have an error, for example, the error may be a predetermined empirical value or experimental value such as 1, 10 or 100; and in the present invention, the error is 100ps.
[0040] The operating parameters include at least one of the following: operating mode; byte duration; byte length; clock frequency.
[0041] The operation mode refers to a mode for controlling the working state of a digital phase-locked loop, which can be 0, 1, or 2.
[0042] The byte duration refers to the time length of the sending byte of the control word of the phase interpolator. For example, the duration may be a predetermined empirical value or experimental value such as 0.1, 1 or 10.
[0043] The byte length refers to the length of the control word of the phase interpolator. For example, the length may be a predetermined empirical value or experimental value such as 4, 8 or 16.
[0044] The clock frequency refers to the basic frequency of the clock in the synchronous circuit. For example, the frequency may be a predetermined empirical value or experimental value such as 10, 100 or 1000.
[0045] In some embodiments,
[0046] By receiving two phase-separated input signals, and setting the operation mode to 0, the clock frequency to 100 ps, the control word length to 8 bits, and the control word duration to 0.1 ns, the two phase-separated input signals are respectively the first input signal and the second input signal.
[0047] In some embodiments, the S120 may include:
[0048] According to the operating parameters, the crystal oscillator clock of the digital phase-locked loop is re-timed to determine a first time interval; wherein the first time interval refers to the time interval between the first input signal and the second input signal, for example, the time interval can be a predetermined empirical value or experimental value such as one cycle, two cycles or three cycles.
[0049] In some embodiments, the crystal oscillator clock of the digital phase-locked loop refers to a voltage-controlled oscillator inside the digital phase-locked loop.
[0050] In some embodiments, the S130 may include:
[0051] When the frequency division number of the embedded digital phase-locked loop is set to N, the value of the control word is set to 0, and the phase difference between the first input signal and the second input signal is stabilized to 0. In this way, in the locked state, the average value of the phase error should gradually converge and stabilize to "0".
[0052] In some embodiments, the S140 may include:
[0053] When the frequency division number of the embedded digital phase-locked loop is set to the first frequency division number, the number of the phase interpolator control word is set to full scale; the first frequency division number can be a predetermined empirical value or experimental value such as N-1, N-2 or N-3.
[0054] When the frequency division number of the embedded digital phase-locked loop is set to the second frequency division number, the value of the control word is set to 0; wherein the second frequency division number can be a predetermined empirical value or experimental value such as N+1, N+2 or N+3.
[0055] The frequency division number of the embedded digital phase-locked loop is switched back and forth between a first frequency division number and a second frequency division number, wherein the average value of the frequency division number of the embedded digital phase-locked loop is N. In this way, the signal output by the digital phase detector in the digital phase-locked loop reflects the relative proportional relationship between the delay of the phase interpolator under the control of the control word and the accurate unit interval generated by the frequency divider, thereby eliminating errors.
[0056] In some embodiments, the S150 may include: selecting the input signal according to the value of the control word of the phase interpolator, and further including:
[0057] If the value of the control word of the phase interpolator is 0, the first input signal is selected;
[0058] If the value of the control word of the phase interpolator is full scale, the second input signal is selected; wherein the full scale refers to the maximum value determined when setting the control word length; for example, when the control word length is 8, the full scale value is 256.
[0059] In some embodiments, S160 may include: determining calibration engine settings through the input signal and driving digital-to-clock conversion.
[0060] For example, when the control word i_dtc_cw of the phase interpolator is 8'd0, all charging units are enabled by ckfb_0;
[0061] When the control word i_dtc_cw of the phase interpolator is 8'd256, all charging units are enabled by ckfb_2;
[0062] ckfb_0 is the first input signal, and ckfb_2 is the second input signal.
[0063] like Figure 2 As shown, this embodiment provides an operation schematic diagram of a digital-to-time conversion method based on an embedded digital phase-locked loop;
[0064] In some embodiments,
[0065] By receiving two phase-separated input signals and setting the operation mode to 0, the clock frequency to 100ps, the byte length to 8bit, and the byte duration of one byte to 0.1ns.
[0066] Connect i_ckfb_0 and i_ckfb_2 to the core of the phase interpolator; wherein i_ckfb_0 and i_ckfb_2 are two phase-separated input signals, and there is a 100ps error in the signal interval between the two input signals; re-time the clock through the 10GHz pre-divided voltage-controlled oscillator to create a separation of the two phase-separated signals with a time interval of 1 unit interval.
[0067] When the control word i_dtc_cw of the phase interpolator is 8'd0, all charging units are enabled by ckfb_0;
[0068] When the control word i_dtc_cw of the phase interpolator is 8'd256, all charging units are enabled by ckfb_2;
[0069] When the control word i_dtc_cw of the phase interpolator takes other values, the clock edge is output according to the control word; thus, the received input signal is converted into a signal whose output phase delay is proportional to the control word.
[0070] like Figure 3 As shown, a calibration flow diagram of a method for converting data to time based on an embedded digital phase-locked loop provided by an embodiment of the present invention;
[0071] In some embodiments,
[0072] The calibration process is divided into two parts. The first part is the integer division lock of N, and the second part is the division "lock" state of N-1 and N+1 for calibration. In these two parts, the phase-locked loop is always in the "integer division" state from the external system's point of view, so it is called the calibration scheme embedded in the digital phase-locked loop.
[0073] In the first link, the frequency divider of the digital phase-locked loop in the integer frequency division state is set to a positive integer N, and the control word of the phase interpolator is set to 0. In this way, in the locked state, the average value of the phase error should gradually converge and stabilize to "0".
[0074] In the second link, the frequency division number of the frequency divider of the digital phase-locked loop is continuously switched between N-1 and N+1, but the average value of the frequency division number is always N.
[0075] When the frequency division number is N-1, the signal output by the frequency divider will be one unit interval, such as 100ps, ahead of the clock cycle of the voltage-controlled oscillator when it is set to N; at the same time, the PI control word is set to full scale, such as 8'd256. When the frequency division number is N+1, the signal output by the frequency divider will be exactly aligned with N, and the PI control word will be set to 0, such as 8'd0. Under the above conditions, the signal output by the digital phase-locked loop reflects the relative relationship between the delay of PI under FS control and the accurate 1UI generated by the frequency divider, thereby driving the calibration engine to eliminate errors.
[0076] like Figure 4 As shown, a structural schematic diagram of a digital-to-time conversion device based on an embedded digital phase-locked loop provided in this embodiment;
[0077] The acquisition module 110 is used for receiving an input signal and predefining an operation parameter; wherein the input signal includes a first input signal and a second input signal;
[0078] A first processing module 120, for connecting the input signal to the core of the phase interpolator and determining the time interval according to predefined operating parameters;
[0079] A setting module 130, used to set the frequency division number of the embedded digital phase-locked loop to lock the phase difference of the input signal;
[0080] A control module 140, for switching the frequency division number of the embedded digital phase-locked loop by changing the value of the phase interpolator control word;
[0081] A selection module 150, configured to select the input signal according to the value of the phase interpolator control word;
[0082] The confirmation module 160 is used to determine the calibration engine settings through the input signal and drive the digital-to-time conversion.
[0083] In some embodiments, the definition module 110, the first processing module 120, the setting module 130, the control module 140, the selection module 150 and the confirmation module 160 may be program modules; after the program modules are executed by the processor, the operations of the above-mentioned modules can be implemented.
[0084] In other embodiments, the definition module 110, the first processing module 120, the setting module 130, the control module 140, the selection module 150 and the confirmation module 160 may be a combination of soft and hard modules; the combination of soft and hard modules includes but is not limited to: various programmable arrays; the programmable arrays include but are not limited to: field programmable arrays and / or complex programmable arrays.
[0085] In some other embodiments, the definition module 110, the first processing module 120, the setting module 130, the control module 140, the selection module 150 and the confirmation module 160 may be pure hardware modules; the pure hardware modules include but are not limited to: dedicated integrated circuits.
[0086] This embodiment provides an electronic device, including:
[0087] Memory;
[0088] A processor is connected to the memory and is used to implement the method provided by any of the above embodiments by executing computer executable instructions stored in the memory, such as executing Figures 1 to 4 Any of the methods shown.
[0089] The electronic device may be a terminal device and / or a server in a service platform.
[0090] like Figure 5 As shown, the electronic device may also include a network interface, which can be used to interact with a peer device through a network.
[0091] This embodiment provides a computer storage medium, wherein the computer storage medium stores computer executable instructions; after the computer executable instructions are executed by a processor, the method provided by any of the above embodiments can be implemented, for example, Figures 1 to 3 Any of the methods shown.
[0092] It should be understood that in the several embodiments provided in the present application, the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.
[0093] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A method for converting data into time based on an embedded digital phase-locked loop, characterized in that: include: Receiving an input signal and predefining an operating parameter; wherein the input signal comprises a first input signal and a second input signal; connecting the input signal to a core of a phase interpolator and determining a first time interval according to the operating parameter; Setting the frequency division number of the embedded digital phase-locked loop to lock the phase difference of the input signal; Switching the frequency division number of the embedded digital phase-locked loop to change the value of the control word of the phase interpolator; Selecting the input signal according to the value of the control word of the phase interpolator; The input signal determines the calibration engine settings and drives the digital-to-clock conversion.
2. The method for converting data into time based on an embedded digital phase-locked loop according to claim 1, characterized in that: The input signal includes a first input signal and a second input signal; wherein the first input signal and the second input signal are two signals separated in phase and have an error.
3. The method for converting data into time based on an embedded digital phase-locked loop according to claim 1, characterized in that: The operating parameters include at least one of the following: Operation mode; Control word duration; Control word length; Clock frequency.
4. The method for converting data into time based on an embedded digital phase-locked loop according to claim 1, characterized in that: Connecting the input signal to a core of a phase interpolator and determining a first time interval according to predefined operating parameters comprises: According to the operating parameters, the oscillator clock of the digital phase-locked loop is delayed to determine a first time interval; wherein the first time interval refers to the time interval between the first input signal and the second input signal.
5. The method for converting data into time based on an embedded digital phase-locked loop according to claim 1, characterized in that: The frequency division number of the embedded digital phase-locked loop is set to lock the phase difference of the input signal; when the frequency division number of the embedded digital phase-locked loop is set to N, the value of the control word is set to 0 to stabilize the phase difference between the first input signal and the second input signal to 0.
6. The method for converting data into time based on an embedded digital phase-locked loop according to claim 1, characterized in that: Switching the frequency division number of the embedded digital phase-locked loop and changing the value of the phase interpolator control word includes: When the frequency division number of the embedded digital phase-locked loop is set to the first frequency division number, the value of the phase interpolator control word is set to full scale; When the frequency division number of the embedded digital phase-locked loop is set to the second frequency division number, the value of the control word is set to 0; The frequency division number of the embedded digital phase-locked loop is switched back and forth between a first frequency division number and a second frequency division number; wherein the average value of the frequency division number of the embedded digital phase-locked loop is N.
7. The method for converting data into time based on an embedded digital phase-locked loop according to any one of claims 1 to 6, characterized in that: Selecting the input signal according to the value of the control word of the phase interpolator includes: If the value of the control word of the phase interpolator is 0, the first input signal is selected; If the value of the control word of the phase interpolator is full scale, the second input signal is selected.
8. A digital-to-time conversion device based on an embedded digital phase-locked loop, characterized in that: include: An acquisition module, configured to receive an input signal and predefine an operation parameter; wherein the input signal comprises a first input signal and a second input signal; A first processing module, configured to connect the input signal to a core of a phase interpolator and determine a time interval according to predefined operating parameters; A setting module, used to set the frequency division number of the embedded digital phase-locked loop to lock the phase difference of the input signal; A control module, used for switching the frequency division number of the embedded digital phase-locked loop by changing the value of the phase interpolator control word; A selection module, used for selecting the input signal according to the value of the phase interpolator control word; The confirmation module is used to determine the calibration engine setting through the input signal and drive the digital-to-time conversion.
9. An electronic device, characterized in that: include: Memory; A processor is connected to the memory and is used to execute computer executable instructions stored in the memory and implement the digital-to-time conversion method based on an embedded digital phase-locked loop provided by any one of claims 1 to 7.
10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions; after the computer executable instructions are executed, the digital-to-time conversion method based on the embedded digital phase-locked loop provided in any one of claims 1 to 7 can be implemented.