Implementation method of optical transport network pseudo-random sequence parallel scrambling and descrambling code device

Abstract

The invention relates to the technical field of digital communication, in particular to an implementation method of an optical transport network pseudo-random sequence parallel scrambling descrambler, which comprises the following steps of: deducing a parallel scrambling code based on an original digital sequence signal of a scrambling code encoding label; designing a frame synchronization scrambler based on the parallel scrambling codes; a frame synchronization descrambling code device is designed based on the parallel scrambling codes, the method is based on a linear feedback shift register (LFSR) circuit, a parallel pseudorandom sequence generation method is achieved through a field programmable gate array (FPGA), the scrambling / descrambling code function of OTN system high-speed code stream (1.25 Gbps to 10 Gbps) data is simply and efficiently achieved through the method, the scrambling / descrambling code function is achieved, and the method is suitable for large-scale popularization and application. By performing modulo 2 operation on the OTUk code stream and the pseudo-random sequence, the frequency spectrum of the digital baseband signal of the OTN system is smooth so as to adapt to the transmission of the baseband system, the transmission performance of the OTN system is improved, and the problems of low efficiency and slow speed of the existing software calculation scrambling method are solved.

Description

Technical Field

[0001] The present invention relates to the field of digital communication technology, and in particular to a method for realizing a pseudo-random sequence parallel scrambling and descrambling device of an optical transmission network. Background Art

[0002] In digital communication systems, designers use random noise to test communication performance. However, random noise is random and difficult to reuse. With the development of coding technology, the invention of pseudo-random noise has solved the above problems. Pseudo-random noise, also known as pseudo-noise (PN), has the properties of random noise. However, pseudo-random noise has been widely used in practice because it can be generated according to a specific regular period. Pseudo-random noise is a periodic sequence generated by a linear shift register (LSR), also known as a pseudo-random sequence. Pseudo-random sequences generated based on FPGA are widely used in communication ranging, positioning navigation, digital data disruptors, noise generators, and communication encryption.

[0003] Scrambling codes are widely used in digital signal processing. Their function is to randomize the input signal to reduce the number of consecutive "0" and "1" in the data and ensure that the receiving end can perform bit synchronization clock recovery and extraction. The generation of scrambling codes is usually achieved through a circular shift register, and the structure of the circular shift register is determined by the scrambling code generator polynomial. No input signal is required to generate scrambling codes. It is only necessary to set the initial value of the shift register according to the requirements of the system. Driven by the system clock, the circular shift register outputs the scrambling code according to the rules of the scrambling code generator polynomial. The output scrambling code and the signal to be scrambled are XORed to obtain the scrambled signal. Conversely, the descrambling process at the receiving end uses a circular shift register with the same structure and the same register initial value to generate a local scrambling code. The local scrambling code is XORed with the received signal to obtain the original signal sent by the transmitter.

[0004] The method of calculating the scrambling code by software will lead to two problems, such as low efficiency and slow speed: 1) The signals processed by the software are all in bytes. The program that generates 8-bit or 16-bit scrambling codes by circular shift requires a large number of shift operations, which takes up a lot of memory space and running time, and is not suitable for use in real-time applications with high requirements for memory capacity; 2) Using software circular shift to generate scrambling codes can only generate 1 bit of scrambling code each time, which is too slow. Summary of the invention

[0005] The object of the present invention is to provide a method for realizing a pseudo-random sequence parallel scrambling and descrambling device of an optical transport network, aiming to solve the problems of low efficiency and slow speed of the existing software scrambling method.

[0006] To achieve the above object, the present invention provides a method for implementing a pseudo-random sequence parallel scrambling and descrambling device in an optical transport network, comprising the following steps:

[0007] Derivation of parallel scrambling codes based on the original digital sequence signal of the scrambling code signature;

[0008] Designing a frame synchronization scrambler based on the parallel scrambling code;

[0009] A frame synchronization descrambler is designed based on the parallel scrambling.

[0010] The specific method of deriving the parallel scrambling code based on the original digital sequence signal of the scrambling code signature is as follows:

[0011] The transmitting end adds the transmitted digital sequence signal to the pseudo-random number sequence generated locally by the transmitting end modulo 2 to obtain the scrambling code sequence;

[0012] The receiving end receives the scrambling code sequence and adds it modulo 2 with the pseudo-random number sequence generated locally at the receiving end to obtain a digital sequence signal of the receiving end;

[0013] When the pseudo-random number sequence generated locally by the receiving end has the same generating polynomial and phase as the transmitting end, the original digital sequence signal of the scrambling code signature is obtained.

[0014] The condition for the receiving end to recover the signal is that the pseudo-random sequences of the sending end and the receiving end are the same and work synchronously.

[0015] Among them, the specific method of designing a frame synchronization scrambler based on the parallel scrambling code is:

[0016] Entering a frame synchronization scrambler module based on the parallel scrambling and checking a reset signal;

[0017] Check the scrambling enable signal and generate the previous attitude data;

[0018] The output and attitude are updated and the output is selected, and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

[0019] The specific method of designing a frame synchronization descrambler based on the parallel scrambling code is as follows:

[0020] Entering a frame synchronization descrambler module based on the parallel scrambling code and checking a reset signal;

[0021] Check the scrambling enable signal and generate the descrambling logic;

[0022] The output and attitude are updated and the output is selected, and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

[0023] The invention discloses a method for realizing a parallel scrambling and descrambling device of a pseudo-random sequence of an optical transport network. The method comprises the following steps: deriving a parallel scrambling code based on an original digital sequence signal of a scrambling code signature; designing a frame synchronization scrambler based on the parallel scrambling code; and designing a frame synchronization descrambling device based on the parallel scrambling code. The method is based on a linear feedback shift register (LFSR) circuit and is a parallel pseudo-random sequence generation method realized by a field programmable gate array (FPGA). The method simply and efficiently realizes the scrambling and descrambling functions of high-speed code stream (1.25 Gbps to 10 Gbps) data of an OTN system. By performing a modulo-2 operation on an optical channel transport unit (OTUk) code stream and a pseudo-random sequence, the spectrum of a digital baseband signal of the OTN system is smoothed to adapt to the transmission of the baseband system, thereby improving the transmission performance of the OTN system and solving the problems of low efficiency and slow speed of the existing software scrambling code calculation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 The present invention provides an OTN system principle block diagram.

[0026] Figure 2 is a schematic diagram of an n-stage LFSR.

[0027] Figure 3 It is the functional block diagram of the frame synchronization scrambler.

[0028] Figure 4 This is a schematic diagram of the OTUk FEC frame structure.

[0029] Figure 5 It is a flow chart of the frame synchronization scrambler.

[0030] Figure 6 It is a flow chart of the frame synchronization descrambler.

[0031] Figure 7 is a block diagram of the frame synchronization scrambler module.

[0032] Figure 8 is a block diagram of the frame synchronization descrambler module.

[0033] Fig. 9 Schematic diagram of the start of scrambling and descrambling simulation test results.

[0034] Fig.10 Schematic diagram of the end of the scrambling and descrambling simulation test results.

[0035] Fig.11 The present invention provides a flowchart of a method for implementing a pseudo-random sequence parallel scrambling and descrambling device for an optical transmission network. DETAILED DESCRIPTION

[0036] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0037] See also Figures 1 to 11 The present invention provides a method for implementing a pseudo-random sequence parallel scrambling and descrambling device of an optical transport network, comprising the following steps:

[0038] S1 derives the parallel scrambling code based on the original digital sequence signal of the scrambling code signature;

[0039] Specific method:

[0040] S11 The transmitting end adds the transmitted digital sequence signal to the pseudo-random number sequence generated locally by the transmitting end modulo 2 to obtain a scrambling code sequence;

[0041] Specifically, at the transmitting end, the digital sequence signal {t k} and the pseudo-random number sequence generated locally by the sender Modulo 2 addition is performed to obtain a scrambling sequence that approximates white noise sent to the transmission line.

[0042] S12 A receiving end receives the scrambling code sequence and adds it modulo 2 to a pseudo-random number sequence generated locally at the receiving end to obtain a digital sequence signal of the receiving end;

[0043] Specifically, the receiving end receives After the signal, the pseudo-random number sequence generated locally Add modulo 2, and we get Digital sequence signal.

[0044] S13 When the pseudo-random number sequence generated locally by the receiving end has the same generating polynomial and phase as the transmitting end, the original digital sequence signal of the scrambling code signature is obtained.

[0045] Specifically, the pseudo-random sequence signal generated locally at the receiving end has the same generating polynomial and phase as the sending end, that is, but The original digital sequence signal of the scrambling code signature of the sending end can be obtained. Therefore, the condition for the receiving end to correctly recover the signal is that the pseudo-random sequences of the receiving and sending ends are the same and work synchronously.

[0046] exist Figure 1 In the optical transport network (OTN) system shown in the figure, at the transmitting end: 1) OPU mapping maps user data into the optical channel payload unit (OPUk) payload, and calculates the overhead (OH) and fills it into the overhead field; 2) OPUk is mapped to the optical channel data unit (ODUk) low order, and then the low-order ODUk layer overhead bytes are added, multiplexed to the ODUk high order, and then the high-order ODUk layer overhead bytes are added; 3) OTUk overhead bytes (including frame alignment signal Frame Alignment Signal, FAS) and forward error correction (FEC) encoding are encapsulated; 4) OTUk frames are pseudo-randomized through a scrambler.

[0047] At the receiving end: 1) Recover the code stream through the descrambler; 2) Determine whether there are errors and correct them through FEC decoding; 3) Complete OTU framing through FAS alignment; 4) Demodulate the high-order ODUk from the OTUk frame signal and demultiplex the low-order ODUk; 5) Demultiplex the user data from the OPUk signal.

[0048] Pseudo-random sequences are deterministic sequences with certain random properties. Although they are generated by shift registers, they are random sequences with certain random properties. Pseudo-random sequences have good randomness and a correlation function close to white noise, and have pre-determinability and repeatability. These characteristics make pseudo-random sequences widely used in digital communication systems.

[0049] Figure 2 FIG. 1 is a block diagram of an n-stage linear feedback register (LFSR). Figure 2 The connection status of the feedback line is indicated by C i Indicates that the feedback coefficient C i =1 means there is a connection (participation feedback), C i =0 means no connection (not participating in feedback), Indicates modulo 2 operation, the state of the n-stage LFSR is represented by D i Indicates that D i ∈{0, 1}.

[0050] according to Figure 2 The line feedback relationship can define the characteristic polynomial of LFSR:

[0051]

[0052] In formula (1), x i It only indicates that its coefficient 1 or 0 represents the feedback line C i Connected or disconnected, the value of x itself is related to the feedback line C i For an n-stage LFSR, there are at most 2n states. Since the all-0 state will not transition to other states, the period P of the output sequence of the n-stage LFSR is ≤ 2n-1. If the feedback coefficient C i With proper selection, the period of the n-stage LFSR output sequence can reach a maximum value of 2n-1. The pseudo-random sequence generated at this time is called the longest linear feedback shift register sequence, or m-sequence for short.

[0053] The m-sequence is a longest linear feedback shift sequence. It is a sequence with the longest period generated by a shift register with linear feedback. The output sequence of the circuit that generates the m-sequence is shifted out one by one by the shift register. Although the state of the shift register changes once for each shift beat, it is cyclic. If the distribution of the feedback line is appropriate, the shift register state must pass before the cycle so that all states appear. This sequence is periodic, and the period can be very long when n is large enough. In one cycle, there are many different arrangements of 0 and 1, and each bit is 0 or 1, which is almost random, so it is also called a pseudo-random code, and because some of its properties are very similar to random noise, it is also called a pseudo-noise code.

[0054] The m-sequence is a pseudo-random sequence that is widely used in the field of communications, such as digital data encryption, scrambling, synchronization, bit error rate measurement, etc. The m-sequence has some statistical properties similar to random noise and can be generated repeatedly by calculation. Among them, the m-sequence is a common random sequence in communications. The generating polynomial of the m-sequence must be an n-order primitive polynomial. The m-sequence is a cyclic sequence with a period of p=2n-1. The m-sequence has similar characteristics to random sequences:

[0055] Balance. In a cycle of the m sequence, the number of "1" and "0" is basically equal, with only one more "1" than "0";

[0056] Shift-add property. p Add modulo 2 to another sequence M generated by any delay and shift of the m sequence r On, still get M p A delayed shift sequence M s ,Right now:

[0057]

[0058] Correlation characteristics. According to the cyclic autocorrelation characteristics, it is easy to prove that the autocorrelation function of the m sequence is:

[0059]

[0060] If p=2n-1 is very large, then this autocorrelation function is very close to the autocorrelation function of a random sequence.

[0061] The ITU-T G.709 standard specifies that the OTUk signal must have sufficient bit timing information at the Optical Network Node Interface (ONNI). A scrambler is used to provide a suitable bit pattern to prevent the appearance of long sequences of "0" and "1". The operation of the scrambler should be functionally equivalent to the operation of a frame synchronization scrambler operating at the OTUk rate with a sequence length of 65535. The generating polynomial should be 1+x+x 3 +x 12 +x 16 . Figure 3 The functional block diagram of the OTN frame synchronization scrambler is shown.

[0062] When the most significant bit of the first byte after a frame alignment byte, i.e. the MSB of the MFAS, appears, the scrambler shall be reset to 0xFFFF. This bit and all subsequent bits to be scrambled shall be reset modulo 2 to the x position of the scrambler. 1 6 position output. The scrambler should run continuously throughout the FEC frame period. The OTUk frame FAS should not be scrambled. Scrambling is processed before FA insertion. The scrambler should continue to scramble throughout the OTUk frame. The FAS in the OTUk overhead is not scrambled. Scrambling is performed after FEC calculation, and then the scrambling structure is inserted into the OTUk signal.

[0063] by Figure 3 As an example, the 64-bit parallel scrambling code of the 16 scrambling code registers are output from left to right as s0, s1, s2, ..., s 15 , the input of information code element is b. Let S = [s 15 ,s 14 , ..., s0] T Indicates the current state of the register, B = [b 63 , b 62 , ..., b0] represents the input of the 1st to 64th clock information codewords, and the vector Indicates the next state of the scrambler, S 64 represents the state of the scrambler after 64 clock cycles, so the 64-bit scrambler is to find the relationship S 64=f(S).

[0064] Figure 3 The serial scrambler functional block diagram shown is equivalent to the serial scrambling circuit diagram, and the relationship can be obtained:

[0065]

[0066] Let formula (4) be S 1 =M′[Sb0] T ,in,

[0067]

[0068] Similarly, after 2 clock cycles, the state of the scrambler is S 2 =M′[S 1 b1] T . So, by analogy, we have:

[0069] S n =M′[S n-1 b n-1 ] T , where n = (1, 2, ..., 64) (6) That is:

[0070]

[0071] Let M′ be M′=[MA]. Where M is a 16×16 matrix, i.e., the first 16 columns of M′, and A is a 16×1 matrix, i.e., the last column of M′. Then S n =[MA][S n-1 b n-1 ] T , which can be further derived from matrix transformation:

[0072]

[0073] Therefore, the state of the scrambler after n clock cycles is:

[0074]

[0075] The additions in formulas (8) to (9) are all modulo 2 additions.

[0076] Let vector B′=[b′ 63 , b′ 62 , ..., b′0] T Represents the output of a 64-bit parallel scrambler, then:

[0077]

[0078] In the parallel scrambling logic design, the pre-calculated results are realized through XOR circuit combination logic or sequential logic. This method has fast operation speed and simple implementation, which is very conducive to hardware implementation.

[0079] From the derivation process of formulas (4) to (10), it can be seen that the state value of the scrambler after calculating 64 clock cycles can be represented by the XOR combination of the current state value of the scrambler and the input data, as shown in formula (8). The 64-bit scrambling circuit can be implemented in parallel through the circuit, and M, S, A and b are all known, then the problem is converted into the power calculation of the M matrix.

[0080] In order to smooth the baseband signal spectrum, reduce low-frequency components, and facilitate the recovery and extraction of bit timing signals in the OTN system, scrambling processing is required at the transmitter. The OTN system uses the OTUk encoding format, such as Figure 4 Each OTUk frame contains 3824×4=15296 bytes, the first 6 bytes are frame alignment overhead (FA OH), the value is 0xF6F6F6282828. When adding FEC coding, all fields except FA OH are scrambled, that is, Figure 4 From row 1, column 7 to row 4, column 4080.

[0081] S2 designs a frame synchronization scrambler based on the parallel scrambling code;

[0082] Specific methods such as Figure 5 :

[0083] S21 enters the frame synchronization scrambler module based on the parallel scrambling code and checks the reset signal;

[0084] Specifically, entering the frame synchronization scrambler module, checking the reset signal (reset) includes: if reset is high: setting dout_r to 0; setting scram_state to 16'hFFFF; jumping to the step of waiting for the next clock cycle or reset signal.

[0085] S22 checks the scrambling enable signal and generates the previous attitude data;

[0086] Specifically, check the scrambling enable signal (ena): if ena is low, jump to the selected output (end), generate the previous state data (history): assign the value of scram_state to history[16:0]; for i from 16 to WIDTH+16-1: parallel calculation history[i]=history[i-16]^history[i-12]^history[i-3]^history[i-1]^din[i-58], where WIDTH is the input data bit width, which is 64 bits.

[0087] S23 updates the output and attitude, and selects the output, and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

[0088] Specifically, assign the value of history[WIDTH+16-1:16] to dout_r;

[0089] Assign the value of history[WIDTH+16-1:WIDTH] to scram_state. If use_scrambler is 1, dout_r is output. If use_scrambler is 0, din is output and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

[0090] S3 designs a frame synchronization descrambler based on the parallel scrambling.

[0091] Specific methods such as Figure 6 :

[0092] S31 enters the frame synchronization descrambler module based on the parallel scrambling code and checks the reset signal;

[0093] Specifically, entering the frame synchronization descrambler module and checking the reset signal (reset) includes: if reset is high: setting dout_r to 0; setting descram_state to 16'hFFFF; jumping to the frame synchronization scrambler module to wait for the next clock cycle or reset signal.

[0094] S32 checks the scrambling enable signal and generates descrambling logic;

[0095] Specifically, check the descrambling enable signal (ena_d): if ena_d is 0, jump to the frame synchronization scrambler module and wait for the next clock cycle or reset signal. Use generate and for loops to calculate dout_w[i] = history[16+i-16]^history[16+i-12]^history[16+i-3]^history[16+i-1]^history[16+i] for each bit of WIDTH (the input data width is 64 bits), where i ranges from 0 to 63.

[0096] S33 updates the output and attitude, and selects the output, and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

[0097] Specifically, if the descrambling enable signal ena_d is 1, descram_state is updated to history[WIDTH+16-1:WIDTH], and the descrambling output dout_r is dout_w; if use_descrambler is 1, dout_r is output. Otherwise, if use_descrambler is 0, din is output, and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

[0098] according to Figure 5 The scrambling module is designed as Figure 7 The input and output ports of its module units are defined as shown in Table 1.

[0099] Table 1 Scrambling module signal interface

[0100]

[0101] according to Figure 6 The designed descrambling module is as follows Figure 8 The input and output ports of its module units are defined as shown in Table 2.

[0102] Table 2 Scrambling module signal interface

[0103]

[0104]

[0105] The VIVADO software of XILINX company is used to simulate the Register Transfer Level (RTL) behavior of the scrambling and descrambling modules. A total of 239 bytes are tested, the first 64 bits are 0xf6f6f62828280011, the last 64 bits are 0x445566778899aabb, and the rest are random values ​​(generated by the random function). The simulation test results of scrambling and descrambling are as follows: Fig. 9 and Fig.10 .

[0106] The above disclosure is only a preferred embodiment of a method for implementing a pseudo-random sequence parallel scrambling and descrambling device for an optical transport network of the present invention. Of course, this cannot be used to limit the scope of the present invention. A person skilled in the art can understand that all or part of the processes of the above embodiment can be implemented, and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A method for implementing a pseudo-random sequence parallel scrambling and descrambling device in an optical transport network, characterized in that: The following steps are involved: Derivation of parallel scrambling codes based on the original digital sequence signal of the scrambling code signature; Designing a frame synchronization scrambler based on the parallel scrambling code; A frame synchronization descrambler is designed based on the parallel scrambling.

2. The method for implementing a pseudo-random sequence parallel scrambling and descrambling device for an optical transport network as claimed in claim 1, characterized in that: The specific method of deriving the parallel scrambling code based on the original digital sequence signal of the scrambling code signature is as follows: The transmitting end adds the transmitted digital sequence signal to the pseudo-random number sequence generated locally by the transmitting end modulo 2 to obtain the scrambling code sequence; The receiving end receives the scrambling code sequence and adds it modulo 2 with the pseudo-random number sequence generated locally at the receiving end to obtain a digital sequence signal of the receiving end; When the pseudo-random number sequence generated locally by the receiving end has the same generating polynomial and phase as the transmitting end, the original digital sequence signal of the scrambling code signature is obtained.

3. The method for implementing a pseudo-random sequence parallel scrambling and descrambling device for an optical transport network as claimed in claim 2, characterized in that: The condition for the receiving end to recover the signal is that the pseudo-random sequences of the sending end and the receiving end are the same and work synchronously.

4. The method for implementing a pseudo-random sequence parallel scrambling and descrambling device for an optical transport network as claimed in claim 1, characterized in that: The specific method of designing a frame synchronization scrambler based on the parallel scrambling code is as follows: Entering a frame synchronization scrambler module based on the parallel scrambling and checking a reset signal; Check the scrambling enable signal and generate the previous attitude data; The output and attitude are updated and the output is selected, and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

5. The method for implementing a pseudo-random sequence parallel scrambling and descrambling device for an optical transport network as claimed in claim 1, characterized in that: The specific method of designing a frame synchronization descrambler based on the parallel scrambling code is as follows: Entering a frame synchronization descrambler module based on the parallel scrambling code and checking a reset signal; Check the scrambling enable signal and generate the descrambling logic; The output and attitude are updated and the output is selected, and the frame synchronization scrambler module waits for the next clock cycle or reset signal.

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