Wafer structure

Abstract

The invention provides a wafer structure which comprises a plurality of crystal grains, a plurality of cutting channels and a plurality of processing patterns, the cutting channels are adjacent to the first sides and the second sides of the crystal grains, and the processing patterns are concentrated in the cutting channels adjacent to the first sides or concentrated in the crystal grains. Therefore, after the width of the cutting channel without the processing pattern is reduced, the number of crystal grains which can be produced by each wafer can be increased.

Description

Technical Field

[0001] The present invention relates to a wafer structure, and more particularly to a wafer structure in which process patterns are concentrated in partial scribe lines or concentrated in die. Background Art

[0002] In the development of electronic products and the evolution of technology, both integrated circuit (IC) design companies and wafer foundries want to increase the number of die that can be produced from a single wafer. One common way is to reduce the width of the scribe line. However, during the manufacturing process of the die, the process patterns on the scribe line are often relied on to detect their correctness. However, the capabilities of manufacturing equipment have their limits, and the process patterns cannot be reduced beyond the capabilities of the manufacturing equipment, resulting in limitations in reducing the scribe line. Based on the above problems, the Chinese National Intellectual Property Administration Publication No. "CN103176350A" and the Authorization Publication No. "CN101533229B", and the Japanese Patent Office Patent Application Publication No. "JP 2005-283609" etc. have all proposed relevant technologies, but their effects are not remarkable.

[0003] Furthermore, after the wafer is cut to divide the die, if there are process patterns on the scribe line but they are not completely cut, there will be a phenomenon of residual process patterns at the edge of the die. The residual process patterns may cause a short circuit between the input / output channels of the die, or cause a short circuit problem when the die is assembled with other components (such as a flexible printed circuit board, FPC). In addition, generally, the process patterns are designed in the scribe lines around the die. Thus, in the cutting process, the problems caused by the existence of the process patterns and the selection of cutting process parameters that are affected need to be considered, making the cutting process complicated. Therefore, the present invention provides a wafer structure that reduces the width of the scribe line, even reaching the limit width of the cutting process, to increase the number of die that can be produced from a single wafer, and further simplifies the cutting process and improves the short circuit phenomenon caused by the residual process patterns. Summary of the Invention

[0004] The object of the present invention is to provide a wafer structure in which process patterns are concentrated in the scribe line on one side of adjacent die, thereby simplifying the cutting process, and reducing the width of the scribe lines on the other sides adjacent to the die to increase the number of die that can be produced from a single wafer.

[0005] The object of the present invention is to provide a wafer structure in which process patterns are concentrated in the scribe line on the first side of adjacent die and concentrated in partial scribe lines on the second side of adjacent die, thereby reducing the width of the scribe lines without process patterns to increase the number of die that can be produced from a single wafer.

[0006] The purpose of the present invention is to provide a wafer structure, wherein the process pattern and the input / output part of the chip are adjacent to different sides of the chip, so as to avoid the process pattern remaining on the cutting path after cutting the wafer from affecting the input / output part of the chip, thereby avoiding short circuit phenomenon.

[0007] The purpose of the present invention is to provide a wafer structure whose process pattern is concentrated on the grains, thereby simplifying the cutting procedure and reducing the width of the cutting path to increase the number of grains that can be produced from a wafer, and to avoid the process pattern remaining on the cutting path, thereby improving the short circuit phenomenon caused by the residual process pattern.

[0008] The present invention discloses a wafer structure, which includes multiple grains, multiple cutting paths and multiple process patterns, wherein the grains have multiple first edges and multiple second edges; the cutting paths are adjacent to the first edges and the second edges of the grains, and the width of the cutting paths adjacent to the second edges is smaller than the width of the cutting paths adjacent to the first edges; the process patterns are located on the cutting paths adjacent to the first edges.

[0009] The present invention discloses a wafer structure, which includes multiple grains, multiple cutting paths and multiple process patterns, wherein the grains have multiple first edges and multiple second edges; the cutting paths are adjacent to the first edges and the second edges of the grains; the process patterns are located at 5% of the cutting paths adjacent to the second edges and the cutting paths adjacent to the first edges; wherein the width of the cutting paths adjacent to the second edges without the process patterns is smaller than the width of the cutting paths with the process patterns.

[0010] The invention discloses a wafer structure, which comprises a plurality of crystal grains, a plurality of cutting paths and a plurality of process patterns. The crystal grains have a plurality of first edges and a plurality of second edges. The cutting paths are adjacent to the first edges and the second edges of the crystal grains. The process patterns are located in the crystal grains. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 : It is a schematic diagram of an embodiment of the wafer structure of the present invention; Figure 2 : It is an enlarged schematic diagram of a first embodiment of the wafer structure of the present invention; Figure 3 : It is an enlarged schematic diagram of a second embodiment of the wafer structure of the present invention; and Figure 4 : It is an enlarged schematic diagram of a third embodiment of the wafer structure of the present invention.

Figure number comparison

[0011] Certain words are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the technical field of the present invention should understand that manufacturers may use different terms to refer to the same component. Moreover, the specification and claims do not use the difference in name as a way to distinguish components, but use the difference in overall technology of the components as the criterion for distinction. The term "including" mentioned throughout the specification and claims is an open term and should be interpreted as "including but not limited to".

[0012] In order to further understand and appreciate the structural features and effects of the present invention, a preferred embodiment and detailed description are provided as follows:

[0013] See also Figure 1 , which is a schematic diagram of an embodiment of the wafer structure of the present invention. As shown in the figure, a wafer structure 10 includes a plurality of dies 20 and a plurality of cutting lanes 30, 32, wherein the cutting lanes 30 are cutting lanes in a first direction (or called horizontal direction) X, and the cutting lanes 32 are cutting lanes in a second direction (or called vertical direction) Y. According to the figure, the cutting lanes 30 in the first direction X are adjacent to the upper and lower sides of the dies 20, and the cutting lanes 32 in the second direction Y are adjacent to the left and right sides of the dies 20, so the cutting lanes 30, 32 surround the dies. Furthermore, Figure 1 In the embodiment, the dies 20 of the wafer structure 10 are rectangular. The following describes various embodiments of the present invention in conjunction with a region 12 of the wafer structure 10 .

[0014] See also Figure 2 , which is Figure 1 FIG. 1 is an enlarged view of the region 12 of the wafer structure 10 shown in FIG. As shown in the figure, the die 20 has a first side 21, a second side 22, a third side 23 and a fourth side 24, wherein the first side 21 and the third side 23 are short sides of the die 20, and the second side 22 and the fourth side 24 are long sides of the die 20. The die 20 may include a plurality of input / output portions (or referred to as input / output channels) 25, which are arranged along the second side 22 or the fourth side 24 of the die 20, and, Figure 2 In the embodiment, the input / output portions 25 are disposed along the second side 22 and the fourth side 24 of the die 20 . Therefore, the input / output portions 25 may be located at two long sides of the die 20 .

[0015] See also Figure 2 The process pattern 40 is concentrated in the sawing streets 32 of the first side 21 of the adjacent die 20. Figure 2 In the embodiment, the process pattern 40 may not be located in the cutting lanes 30 of the second side 22 and the fourth side 24 of the adjacent die 20. In other words, the process pattern 40 may be entirely located in the cutting lanes 32 of the adjacent first side (short side) 21. Therefore, the input / output parts 25 and the process pattern 40 are located on different sides of the adjacent die 20. In this way, after the cutting process, even if the process pattern 40 is not completely cut and remains, the electrical connection state of the input / output parts 25 is not affected. For example, the residue of the process pattern 40 is located in the cutting lanes 32 of the adjacent first side (short side) 21. Since the cutting lanes 30 of the adjacent second side (long side) 22 and the fourth side (long side) 24 do not have the residue of the process pattern 40, a short circuit will not be caused between the input / output parts 25, and the electrical connection state of the assembly of the die 20 with other accessories (for example, the wires of the test device or the flexible printed circuit board (FPC)) will not be affected. The process pattern includes an alignment pattern, a width measurement pattern, a thickness measurement pattern or an electrical test component.

[0016] Furthermore, Figure 2The width of the scribe line 32 in the second direction Y of the embodiment is the first width W1, and the width of the scribe line 30 in the first direction X is the second width W2. As shown in the figure, since the process pattern 40 does not need to be set in the scribe line 30 in the first direction X, the second width W2 can be smaller than the first width W1. In other words, the width of the scribe line 30 of the second side 22 of the adjacent die 20 is smaller than the width of the scribe line 32 of the first side 21 of the adjacent die 20. In addition, if the process pattern 40 located in the scribe line 32 in the second direction Y has a maximum width W3, since the process pattern 40 does not need to be set in the scribe line 30 in the first direction X, the second width W2 of the scribe line 30 can be smaller than the maximum width W3. Therefore, the width of the scribe line 30 of the adjacent second side 22 without the process pattern 40 can be smaller than the width of the process pattern 40. Furthermore, in order to simplify the cutting process by eliminating the need to replace the cutting tool multiple times, the width of the cutting street 30 on the second side 22 and the fourth side 24 of the adjacent die 20 can be the same as the second width W2. However, Figure 2 The structure shown is only one implementation structure, so the widths of the scribe lines 30 adjacent to the second side 22 and the fourth side 24 can be different. From the above description, it can be seen that since the process pattern 40 is concentrated on the scribe lines 32 adjacent to the first side 21 of the die 20, the widths of the scribe lines 30 adjacent to the second side 22 can be reduced, and the space occupied by the scribe lines 30 on the wafer can be reduced. Therefore, the saved space can be used to form additional die 20, thereby increasing the number of die 20 that can be produced on a wafer.

[0017] See also Figure 3 , which is an enlarged schematic diagram of a second embodiment of the wafer structure of the present invention, Figure 3 for Figure 1 An enlarged view of region 12 of wafer structure 10 is shown. As shown, Figure 3 Example and Figure 2 The difference between the embodiments is that Figure 3 The widths of the cutting lanes 30, 34, 36 in the first direction X can be different widths, wherein the width of the cutting lane 30 is a narrower second width W2. In addition, the widths of the cutting lanes 34, 36 can be changed to the wider first width W1 of the cutting lane 32 in the second direction Y for setting the process patterns 42, 43.

[0018] Furthermore, the number of the scribe lines 34 and 36 in the first direction X with the first width W1 may account for 5%, and preferably 2%, of the number of all scribe lines in the first direction X. In other words, if there are 100 scribe lines in the first direction X, the second embodiment of the present invention allows at most 5 scribe lines to be provided with the process patterns 42 and 43. Therefore, in addition to the scribe lines 32 that are concentrated on the adjacent first side 21, some of the process patterns 42 and 43 are located in the scribe lines 34 and 36 that are adjacent to the second side 22, which is less than 5% (or preferably less than 2%). In this way, the width W2 of the scribe line 30 adjacent to the second side 22 without the process patterns 41, 42, 43 is smaller than the width W1 of the scribe lines 32, 34, 36 that have the process patterns 41, 42, 43. In addition, the width of the process patterns 41, 42, 43 is the maximum width W3, and the second width W2 may be smaller than the maximum width W3.

[0019] The first and second embodiments of the wafer structure of the present invention centrally arrange the process patterns required for the wafer in the scribe lines 32 of the short sides of the adjacent dies 20, so that all or at least 95% (or preferably 98%) of the scribe lines of the long sides of the adjacent dies 20 do not need to be arranged with process patterns, so that the width of the scribe lines of the long sides of the adjacent dies 20 can be effectively reduced to reduce the space occupied by the scribe lines of the long sides of the adjacent dies 20. Therefore, the saved space can be used to form additional dies 20, thereby increasing the number of dies 20 that can be produced on a wafer. The first and second embodiments are particularly effective when applied to rectangular dies 20 with a large difference between the long and short sides. For example, if the ratio of the second side (long side) 22 of the dies 20 to the first side (short side) 21 is more than 5 times (preferably more than 10 times), the first and second embodiments of the present invention are applied to centrally arrange the process patterns in the scribe lines of the short sides of the adjacent dies 20, and the effect of saving the wafer area occupied by the scribe lines is particularly good.

[0020] See also Figure 4 , which is an enlarged schematic diagram of a third embodiment of the wafer structure of the present invention, Figure 4 for Figure 1 An enlarged view of region 12 of wafer structure 10 is shown. As shown, Figure 4 Embodiment and second Figure 3 The difference between the embodiments is that the process pattern 44 is located in the die 20 and is not placed in any of the cut streets 30, 38. Therefore, the width of the cut street 38 in the second direction Y and the width of the cut street 30 in the first direction X can be the same as the narrower second width W2, and all the cut streets 30 in the first direction X and all the cut streets 38 in the second direction Y can be the same as Figure 4The same width is shown, so that there is no need to change the tool during the cutting process, and the cutting procedure is further simplified. In this way, the second width W2 of the cutting paths 30 and 38 can be smaller than a fourth width W4 of the process pattern 44. Since the process pattern 44 is concentrated in the die 20, the width of the cutting paths 30 and 38 can be reduced, and the space occupied by the cutting paths 30 and 38 on the wafer can be reduced, so the number of die 20 that can be produced on a wafer can be increased. Furthermore, since there is no process pattern 44 in all the cutting paths 30 and 38, there is no need to consider the problem of the process pattern 44 in the cutting process, and the selection of the cutting process parameters is simplified, thereby simplifying the cutting procedure and reducing the width of the cutting path to the minimum limit width of the cutting process. The minimum limit width of the cutting process can vary according to the capacity of the manufacturing equipment, which is not limited by the technology of the present invention.

[0021] See also Figure 4 In addition to the process pattern 44, the die 20 also includes a plurality of electronic components 50. The process pattern 44 is located in a useless area in the die 20 where no electronic components 50 or other circuits are originally designed. Therefore, the process pattern 44 can be located in the useless area at any position in the die 20, and the electronic components 50 are located in the electronic component area in the die 20 where various components are to be designed. Therefore, the electronic components 50 are located outside the useless area. Furthermore, the die 20 may further include an input / output portion 25. However, the shape of the pattern of the electronic components 50 formed in the die 20, the formation position of the input / output portion 25, and the formation position of the process pattern 44 are not Figure 4 The aforementioned useless area may be a useless area of ​​a specific layer structure in the wafer (e.g., a useless area in a polysilicon layer or a metal layer) to place single-layer process patterns such as alignment patterns, width measurement patterns, or thickness measurement patterns; or, when designing the circuit of the die 20, a specific area of ​​the die 20 may be reserved in advance as a useless area. This useless area may span the multi-layer structure of the wafer, so it may be used to place multi-layer process patterns such as electrical test components. In addition, according to the above description, it can be known that, according to the process requirements, in addition to concentrating the process pattern 44 in the die 20, part of the process pattern 44 may also be distributed in part of the cutting lanes 30 or 38, so that the space occupied by the cutting lanes 30 and 38 on the wafer can still be reduced.

[0022] In summary, the present invention discloses a wafer structure, which includes multiple grains, multiple cutting lanes and multiple process patterns, the grains have multiple first edges and multiple second edges; the cutting lanes are adjacent to the first edges and the second edges of the grains, and the width of the cutting lanes adjacent to the second edges is smaller than the width of the cutting lanes adjacent to the first edges; the process patterns are located on the cutting lanes adjacent to the first edges.

[0023] The present invention discloses a wafer structure, which includes multiple grains, multiple cutting paths and multiple process patterns, wherein the grains have multiple first edges and multiple second edges; the cutting paths are adjacent to the first edges and the second edges of the grains; the process patterns are located at 5% of the cutting paths adjacent to the second edges and the cutting paths adjacent to the first edges; wherein the width of the cutting paths adjacent to the second edges without the process patterns is smaller than the width of the cutting paths with the process patterns. The invention discloses a wafer structure, which comprises a plurality of crystal grains, a plurality of cutting paths and a plurality of process patterns. The crystal grains have a plurality of first edges and a plurality of second edges. The cutting paths are adjacent to the first edges and the second edges of the crystal grains. The process patterns are located in the crystal grains.

[0024] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications to the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A wafer structure, characterized in that: It contains: A plurality of crystal grains having a plurality of first sides and a plurality of second sides, the crystal grains having a plurality of input / output parts, the input / output parts being arranged along the second sides, the first sides being short sides of the crystal grains, and the second sides being long sides of the crystal grains; A plurality of scribe lines, adjacent to the first sides and the second sides of the die, wherein the widths of the scribe lines adjacent to the second sides of the die are smaller than the widths of the scribe lines adjacent to the first sides of the die; and A plurality of process patterns are located in the die, and the input / output parts and the process patterns are located at different sides of the die; The die respectively include a plurality of electronic components, the process patterns are further located in a useless area of ​​the die where the electronic components are not disposed, the wafer structure includes a multi-layer structure, and the useless area spans across the multi-layer structure.

2. The wafer structure according to claim 1, characterized in that: in, The process patterns are all located on the cutting streets adjacent to the first sides.

3. The wafer structure according to claim 1, characterized in that: in, The widths of the scribe lines adjacent to the second sides are smaller than the maximum width of the process patterns.

4. The wafer structure according to claim 1, characterized in that: in, The widths of the cutting streets adjacent to the second sides are the same.

5. The wafer structure according to claim 4, characterized in that: in, The widths of the cutting streets adjacent to the first sides are the same.

6. A wafer structure, characterized in that: It contains: A plurality of crystal grains having a plurality of first sides and a plurality of second sides; A plurality of sawing lanes adjacent to the first sides and the second sides of the die, the first sides being short sides of the die, and the second sides being long sides of the die; and A plurality of process patterns are located in the die; Among them, the grains respectively include multiple electronic components, the process patterns are further located in a useless area of ​​the grains where the electronic components are not set, the wafer structure includes a multi-layer structure, the useless area spans the multi-layer structure, the width of the cutting paths of the second edges of the adjacent grains is smaller than the width of the cutting paths of the first edges of the adjacent grains, and the ratio of the second edges of the grains to the first edges differs by more than 5 times.

7. The wafer structure according to claim 6, characterized in that: in, The die have a plurality of input / output portions, and the input / output portions are arranged along the second sides.

8. The wafer structure according to claim 6, characterized in that: in, The widths of the scribe lines adjacent to the second sides without the process patterns are smaller than the maximum width of the process patterns.

9. A wafer structure, characterized in that: It contains: A plurality of crystal grains having a plurality of first sides and a plurality of second sides; A plurality of sawing streets adjacent to the first sides and the second sides of the dies; and A plurality of process patterns are located in the die; The die respectively include a plurality of electronic components, the process patterns are located in a useless area of ​​the die where the electronic components are not set, the wafer structure includes a multi-layer structure, and the useless area spans across the multi-layer structure.

10. The wafer structure according to claim 9, characterized in that: in, The width of the scribe lines is smaller than the maximum width of the process patterns.

11. The wafer structure according to claim 9, characterized in that: in, The widths of the cutting streets adjacent to the second sides are the same.

12. The wafer structure according to claim 9, characterized in that: in, The widths of the cutting streets adjacent to the first sides are the same.

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