Manufacturing method of metal gate transistor

Abstract

The invention discloses a manufacturing method of a metal gate transistor, which comprises the following steps of: completing a metal gate process flow to form a metal gate which contains Cl; and forming an interlayer film. And forming a contact hole, wherein the step of forming the contact hole comprises the sub-steps of performing graphical etching to form a contact hole opening. And performing pre-cleaning by using F-containing plasmas, wherein F replaces Cl in the metal gate under the action of the plasmas and enables the Cl to be diffused to the bottom surface of the opening of the contact hole. And NH3 plasma processing is carried out to consume Cl in the metal gate. And an adhesion barrier layer is deposited, wherein the adhesion barrier layer comprises a first Ti layer and a second TiN layer which are stacked in sequence. The content of Cl in the metal gate is reduced to ensure that in the metal silicification reaction, the first Ti layer at the top of the metal gate does not form a cavity under the action of Cl. And filling metal in the contact hole opening to form a contact hole. The stability of the metal gate can be improved.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a metal gate (MG) transistor. Background Art

[0002] Since the atomic layer deposition (ALD) TiN in MG is deposited by the reaction of titanium tetrachloride (TiCl4) and NH3, and the TiAl of ALD is the reaction of titanium tetrachloride and aluminum, the metal gate formed will contain Cl elements, and the presence of Cl elements will have a great negative effect on the device stability of the metal gate process (loop). In the preclean process of the contact hole (CT) process, F will replace Cl under the action of plasma, so that Cl reaches the surface of MG. After the high temperature process required for the formation of titanium silicide (TiSix), Cl in MG will volatilize to the bottom of the CT hole, react with Ti therein and form TiClx, the chloride of Ti. The reactant TiClx sublimates to form a void. This defect will seriously affect the conductive resistance of the CT hole and the stability of MG.

[0003] like Figures 1A to 1E FIG. 1 is a schematic diagram of a device structure in each step of a conventional method for manufacturing a metal gate transistor; the conventional method for manufacturing a metal gate transistor comprises the following steps:

[0004] like Figure 1A As shown, the metal gate 102 process flow is completed to form the metal gate 102, and the metal gate 102 is formed in the gate trench between the zero-th interlayer film. Figure 1A In the embodiment, the zeroth interlayer film includes a partial thickness of the oxide layer 104, and a silicon nitride layer 103 is formed at the bottom of the oxide layer 104. The metal gate 102 includes a TiN layer formed by an ALD process, and the reactants include TiCl4 and NH3, so that the ALD TiN layer contains Cl, and the TiN layer can be used as a component of the bottom barrier layer or the top barrier layer in the metal gate, and can also be used as a component of the P-type metal work function layer. For NMOS, the metal gate 102 also includes TiAl formed by an ALD process, and the Ti source in the ALD process also uses TiCl4, so the TiAl layer also contains Cl. Figure 1A In the diagram, Cl ions are denoted by 201.

[0005] An interlayer film is formed, and the interlayer film covers the metal gate 102 and the top surface of the zeroth interlayer film. Figure 1A In FIG. 1 , the interlayer film includes a top portion of an oxide layer 104 , a silicon nitride layer 105 , and an oxide layer 106 .

[0006] The contact hole 109 is formed, including the following steps:

[0007] like Figure 1A As shown, pattern etching is performed to form a contact hole opening 107, and the contact hole opening 107 passes through the corresponding interlayer film or the bottom zeroth interlayer film. For the corresponding semiconductor device, an active region and a drain region are formed in the semiconductor substrate 101 on both sides of the metal gate 102, and corresponding contact hole openings 107 are formed on the top of the metal gate 102, the source region, and the drain region. Figure 1A Only the contact hole opening 107 at the top of the metal gate 102 is shown. In the prior art, the contact hole opening 107 at the top of the source region and the drain region will expose the surface of the bottom semiconductor substrate 101. The semiconductor substrate 101 includes a silicon substrate.

[0008] like Figure 1B As shown, a plasma containing F is used for pre-cleaning. The pre-cleaning is shown by the arrow line corresponding to the mark 203. Under the action of plasma, F will replace Cl in the metal gate 102 and make Cl diffuse to the bottom surface of the contact hole opening 107. Figure 1B In the figure, the F ion, i.e., F-, is indicated by the label 202.

[0009] like Figure 1C As shown, a glue barrier layer 108 is deposited, and the glue barrier layer 108 includes a Ti layer and a TiN layer stacked in sequence. Figure 1B , Ti is indicated by reference numeral 204 .

[0010] like Figure 1D As shown, a metal silicide reaction is performed to form TiSi in the Ti layer in contact with silicon, wherein the Ti layer in the contact hole opening 107 at the top of the source region and the drain region reacts with the metal silicon in the semiconductor substrate 101 at the bottom to form TiSi.

[0011] In the metal silicidation reaction, Cl in the metal gate diffuses upward, and the Ti layer and Cl come into contact and react to form Ti Cl compounds, namely TiClx, which volatilizes through high-temperature sublimation to form voids 110 .

[0012] like Figure 1E As shown, metal is filled in the contact hole opening 107 to form a contact hole 109 .

[0013] like Figure 2 , is a photograph of a contact hole on top of a metal gate formed by a conventional method for manufacturing a metal gate transistor; it can be seen that there is a void in a region 110a between the contact hole and the metal gate. Summary of the invention

[0014] The technical problem to be solved by the present invention is to provide a method for manufacturing a metal gate transistor, which can increase the stability of the metal gate.

[0015] In order to solve the above technical problems, the present invention provides a method for manufacturing a metal gate transistor, comprising the following steps:

[0016] A metal gate process flow is completed to form a metal gate, wherein the metal gate contains Cl.

[0017] An interlayer film is formed, the interlayer film covering the metal gate and top surfaces of the zeroth interlayer film.

[0018] The contact hole is formed, comprising the following steps:

[0019] Patterned etching is performed to form a contact hole opening, wherein the contact hole opening passes through the corresponding interlayer film or the zeroth interlayer film at the bottom.

[0020] The pre-cleaning is performed by using plasma containing F. Under the action of plasma, F will replace Cl in the metal gate and make Cl diffuse to the bottom surface of the contact hole opening.

[0021] An NH 3 plasma treatment is performed to consume Cl in the metal gate.

[0022] An adhesion barrier layer is deposited, the adhesion barrier layer including a first Ti layer and a second TiN layer stacked in sequence.

[0023] A metal silicidation reaction is performed to form TiSi in the first Ti layer in contact with silicon, and the Cl content in the metal gate is reduced to ensure that in the metal silicidation reaction, the first Ti layer on the top of the metal gate will not form a cavity under the action of Cl.

[0024] The contact hole is formed by filling metal in the contact hole opening.

[0025] A further improvement is that the metal gate is formed in a gate trench located between the zeroth interlayer film, and a gate dielectric layer is separated between the metal gate and the surface of the semiconductor substrate; the metal gate includes a bottom barrier layer, a metal work function layer, a top barrier layer and a gate conductive material layer.

[0026] The bottom barrier layer includes a first TiN layer, which is formed by an ALD process. Reactants for forming the first TiN layer include TiCl 4 and NH 3 , and the first TiN layer contains Cl.

[0027] A further improvement is that the bottom barrier layer further includes a first TaN layer and the bottom barrier layer is formed by stacking the first TiN layer and the first TaN layer.

[0028] A further improvement is that the top barrier layer is composed of a third TiN layer or a stacked layer of a third TiN layer and a second Ti layer; the third TiN layer is also formed by an ALD process and contains Cl.

[0029] A further improvement is that the metal gate transistor includes NMOS and PMOS.

[0030] In the PMOS formation region, the metal work function layer of the metal gate adopts a P-type metal work function layer, the material of the P-type metal work function layer includes TiN, and the TiN of the P-type metal work function layer is also formed by ALD process and contains Cl.

[0031] A further improvement is that, in the NMOS formation region, the metal work function layer of the metal gate adopts an N-type metal work function layer.

[0032] A further improvement is that, in the PMOS formation region, the metal work function layer of the metal gate adopts a P-type metal work function layer.

[0033] A further improvement is that the material of the N-type metal work function layer includes TiAl.

[0034] The TiAl of the N-type metal work function layer is also formed by the ALD process, the Ti source is TiCl4, and the N-type metal work function layer also contains Cl.

[0035] A further improvement is that the metal filled in the contact hole opening includes Co.

[0036] A further improvement is that the step of filling the contact hole opening with metal to form the contact hole comprises:

[0037] A Co seed layer is formed.

[0038] An electroplating process is performed to form a Co main layer, wherein the Co main layer completely fills the interior of the contact hole opening and extends to the outer surface of the contact hole opening.

[0039] A chemical mechanical polishing process is performed to remove the Co bulk layer on the outer surface of the contact hole opening and to make the Co bulk layer only located in the contact hole opening.

[0040] A further improvement is that the machine for NH3 plasma treatment and the machine for growing the first Ti layer and the second TiN layer are integrated in the same machine.

[0041] A further improvement is that a heater is also provided on the machine platform for the NH3 plasma treatment, and the heater is heated during the NH3 plasma treatment to increase the effect of removing Cl.

[0042] The present invention adds NH3 plasma treatment after pre-cleaning after the contact hole opening is formed and before the adhesion barrier layer is deposited, and NH3 plasma is used to react with Cl to achieve Cl removal. That is, the present invention can timely remove Cl in the metal gate before the first Ti layer of the adhesion barrier layer is deposited, and prevent the Cl in the metal gate from diffusing to the bottom area of ​​the contact hole at the top of the metal gate in the subsequent metal silicidation reaction and reacting with Ti to form Ti Cl compounds such as TiCl4. After TiCl4 volatilizes at high temperature, the area where Ti is lost will become a cavity. Therefore, the present invention can prevent the formation of voids, which can increase the stability of the metal gate and prevent the on-resistance at the bottom of the contact hole from increasing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0044] Figure 1A-1E It is a schematic diagram of the device structure in each step of the manufacturing method of the existing metal gate transistor;

[0045] Figure 2 is a photograph of a contact hole on top of a metal gate formed by a conventional method for manufacturing a metal gate transistor;

[0046] Figure 3 is a flow chart of a method for manufacturing a metal gate transistor according to an embodiment of the present invention;

[0047] Figure 4A-4E is a schematic diagram of the device structure in each step of the method for manufacturing a metal gate transistor according to an embodiment of the present invention;

[0048] Figure 5 This is a photograph of a contact hole on top of a metal gate formed by a method for manufacturing a metal gate transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] like Figure 3 As shown, it is a flow chart of a method for manufacturing a metal gate 302 transistor according to an embodiment of the present invention; FIG. 4A to FIG. 4E , which is a schematic diagram of the device structure in each step of the method for manufacturing the metal gate 302 transistor according to an embodiment of the present invention; the method for manufacturing the metal gate 302 transistor according to an embodiment of the present invention includes the following steps:

[0050] Step S101: Figure 4A As shown, the metal gate 302 process flow is completed to form the metal gate 302 , and the metal gate 302 contains Cl, and the Cl ion, namely C−, is marked with a mark 401 .

[0051] The metal gate 302 is formed in the gate trench between the zeroth interlayer films. Figure 4AIn the embodiment, the zeroth interlayer film includes a partial thickness of the oxide layer 304, and a silicon nitride layer 303 is formed at the bottom of the oxide layer 304.

[0052] The embodiment of the present invention does not involve any improvement in the formation process of the metal gate 302 itself. Figure 4A The structure inside the metal gate 302 is not described in detail. A gate dielectric layer (not shown) is provided between the metal gate 302 and the surface of the semiconductor substrate 301; the metal gate 302 includes a bottom barrier layer (not shown), a metal work function layer (not shown), a top barrier layer (not shown) and a gate conductive material layer (not shown); the bottom barrier layer includes a first TiN layer, which is formed by an ALD process, and the reactants for forming the first TiN layer include TiCl4 and NH3, and the first TiN layer contains Cl.

[0053] In the embodiment of the present invention, the bottom barrier layer further includes a first TaN layer, and the bottom barrier layer is formed by stacking the first TiN layer and the first TaN layer.

[0054] The top barrier layer consists of a third TiN layer or a stacked layer of a third TiN layer and a second Ti layer; the third TiN layer is also formed by the ALD process and contains Cl.

[0055] Metal gate transistors include NMOS and PMOS.

[0056] In the PMOS formation region, the metal work function layer of the metal gate 302 uses a P-type metal work function layer. The material of the P-type metal work function layer includes TiN. The TiN of the P-type metal work function layer is also formed by the ALD process and contains Cl.

[0057] In the NMOS formation region, the metal work function layer of the metal gate 302 uses an N-type metal work function layer.

[0058] In the PMOS formation region, the metal work function layer of the metal gate adopts a P-type metal work function layer.

[0059] The material of the N-type metal work function layer includes TiAl. TiAl is also formed by the ALD process and the Ti source is TiCl4. The N-type metal work function layer also contains Cl.

[0060] Step S102: Figure 4A As shown, an interlayer film is formed, and the interlayer film covers the metal gate 302 and the top surface of the zeroth interlayer film. Figure 4A In FIG. 3 , the interlayer film includes a top portion of an oxide layer 304 , a silicon nitride layer 305 , and an oxide layer 306 .

[0061] Step S103, forming a contact hole 309, includes the following steps:

[0062] Step S1031: Figure 4A As shown, pattern etching is performed to form a contact hole opening 307, and the contact hole opening 307 passes through the corresponding interlayer film or the bottom zeroth interlayer film.

[0063] For the semiconductor device, an active region and a drain region are formed in the semiconductor substrate 301 on both sides of the metal gate 302, and corresponding contact hole openings 307 are formed on the top of the metal gate 302, the source region, and the drain region. Figure 4A Only the contact hole opening 307 at the top of the metal gate 302 is shown, corresponding to the metal zero layer (M0P) on polysilicon. In the embodiment of the present invention, the contact hole opening 307 at the top of the source region and the drain region will expose the surface of the semiconductor substrate 301 at the bottom. The semiconductor substrate 301 includes a silicon substrate, and an embedded epitaxial layer can be further formed in the source region and the drain region, such as an embedded SiP epitaxial layer formed in NMOS and an embedded SiGe epitaxial layer formed in PMOS.

[0064] Step S1032: Figure 4B As shown, a plasma containing F is used for pre-cleaning, and the pre-cleaning is shown by the arrow line corresponding to the mark 402. Under the action of plasma, F will replace Cl in the metal gate 302 and make Cl diffuse to the bottom surface of the contact hole opening 307. Figure 4B In the figure, the F ion, i.e., F-, is marked with label 403.

[0065] Step S1033: Figure 4C As shown, NH3 plasma treatment is performed to consume Cl in the metal gate 302. The NH3 plasma treatment is shown by the arrow line corresponding to the mark 404. This will reduce the Cl content in the metal gate 302.

[0066] It can be seen that NH3 will combine with Cl to form a structure shown in mark 405, thereby achieving the removal of Cl. At the same time, NH3 will also combine with F to form a structure shown in mark 406.

[0067] Step S1034: Figure 4D As shown, an adhesion barrier layer 308 is deposited, and the adhesion barrier layer 308 includes a first Ti layer and a second TiN layer stacked in sequence.

[0068] Figure 4D In FIG. 4 , Ti in the adhesion barrier layer 308 is indicated by a mark 407 .

[0069] In the embodiment of the present invention, the machine for NH3 plasma treatment and the machine for growing the first Ti layer and the second TiN layer are integrated into the same machine.

[0070] Preferably, a heater is also provided on the machine platform for NH3 plasma treatment, and the heater is heated during NH3 plasma treatment to increase the effect of removing Cl.

[0071] Step S1035: Figure 4D As shown, a metal silicidation reaction is performed to form TiSi in the first Ti layer in contact with silicon, and the Cl content in the metal gate 302 is reduced to ensure that during the metal silicidation reaction, the first Ti layer on the top of the metal gate 302 will not form a cavity under the action of Cl. The metal silicidation reaction is achieved by high temperature annealing.

[0072] In the embodiment of the present invention, the first Ti layer in the contact hole opening 307 at the top of the source region and the drain region reacts with the metal silicon in the bottom semiconductor substrate 301 to form TiSi.

[0073] Step S1036: Figure 4E As shown, metal is filled in the contact hole opening 307 to form a contact hole 309 .

[0074] In the embodiment of the present invention, the metal filled in the contact hole opening 307 includes Co.

[0075] The sub-step of filling metal in the contact hole opening 307 to form the contact hole 309 includes:

[0076] A Co seed layer is formed.

[0077] An electroplating process is performed to form a Co body layer, which completely fills the inside of the contact hole opening 307 and extends to the outer surface of the contact hole opening 307 .

[0078] A chemical mechanical polishing process is performed to remove the Co bulk layer on the outer surface of the contact hole opening 307 and to leave the Co bulk layer only in the contact hole opening 307 .

[0079] In the embodiment of the present invention, after the contact hole opening 307 is formed and before the adhesion barrier layer 308 is deposited, NH3 plasma treatment is added after pre-cleaning, and NH3 plasma is used to react with Cl to achieve Cl removal. That is, the embodiment of the present invention can timely remove Cl in the metal gate 302 before the first Ti layer of the adhesion barrier layer 308 is deposited, so as to prevent Cl in the metal gate 302 from diffusing to the bottom area of ​​the contact hole 309 at the top of the metal gate 302 in the subsequent metal silicidation reaction and reacting with Ti to form Ti Cl compounds such as TiCl4. After TiCl4 volatilizes at high temperature, the area where Ti is lost will become a cavity. Therefore, the embodiment of the present invention can prevent the formation of voids, which can increase the stability of the metal gate 302 and prevent the on-resistance at the bottom of the contact hole 309 from increasing.

[0080] like Figure 5 , is a photograph of a contact hole at the top of a metal gate formed by the method for manufacturing a metal gate transistor according to an embodiment of the present invention; it can be seen that no void is formed at the bottom of the adhesion barrier layer 308 .

[0081] The embodiment of the present invention adds a step of NH3 Plasma treatment before the preclean of Ti / TiN deposition (dep) of the Ti glue layer (layer), thereby consuming the Cl element in the front layer ALD TiAl or TiN, and finally eliminating the void condition at the connection between MG and contact, thereby improving the stability of the MG device performance and reducing the contact resistance of the contact.

[0082] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a metal gate transistor, characterized in that: The steps include: completing a metal gate process flow to form a metal gate, wherein the metal gate contains Cl; forming an interlayer film, wherein the interlayer film covers the top surface of the metal gate and the zeroth interlayer film; The contact hole is formed, comprising the following steps: Performing patterned etching to form a contact hole opening, wherein the contact hole opening passes through the corresponding interlayer film or the zeroth interlayer film at the bottom; Pre-cleaning is performed using plasma containing F, where F replaces Cl in the metal gate under the action of plasma and causes Cl to diffuse toward the bottom surface of the contact hole opening; performing NH3 plasma treatment to consume Cl in the metal gate; depositing an adhesion barrier layer, the adhesion barrier layer comprising a first Ti layer and a second TiN layer stacked in sequence; Performing a metal silicidation reaction to form TiSi in the first Ti layer in contact with silicon, and reducing the Cl content in the metal gate to ensure that the first Ti layer on the top of the metal gate does not form a cavity under the action of Cl in the metal silicidation reaction; The contact hole is formed by filling metal in the contact hole opening.

2. The method for manufacturing a metal gate transistor according to claim 1, wherein: The metal gate is formed in a gate trench between the zeroth interlayer film, and a gate dielectric layer is separated between the metal gate and the surface of the semiconductor substrate; the metal gate includes a bottom barrier layer, a metal work function layer, a top barrier layer and a gate conductive material layer; The bottom barrier layer includes a first TiN layer, which is formed by an ALD process. Reactants for forming the first TiN layer include TiCl 4 and NH 3 , and the first TiN layer contains Cl.

3. The method for manufacturing a metal gate transistor according to claim 2, wherein: The bottom barrier layer further includes a first TaN layer and is formed by stacking the first TiN layer and the first TaN layer.

4. The method for manufacturing a metal gate transistor according to claim 2, wherein: The top barrier layer is composed of a third TiN layer or a stacked layer of a third TiN layer and a second Ti layer; the third TiN layer is also formed by an ALD process and contains Cl.

5. The method for manufacturing a metal gate transistor according to claim 2, wherein: Metal gate transistors include NMOS and PMOS; In the PMOS formation region, the metal work function layer of the metal gate adopts a P-type metal work function layer, the material of the P-type metal work function layer includes TiN, and the TiN of the P-type metal work function layer is also formed by ALD process and contains Cl.

6. The method for manufacturing a metal gate transistor according to claim 5, wherein: In the NMOS formation region, the metal work function layer of the metal gate adopts an N-type metal work function layer.

7. The method for manufacturing a metal gate transistor according to claim 6, wherein: In the PMOS formation region, the metal work function layer of the metal gate adopts a P-type metal work function layer.

8. The method for manufacturing a metal gate transistor according to claim 6, wherein: The material of the N-type metal work function layer includes TiAl; The TiAl of the N-type metal work function layer is also formed by the ALD process, the Ti source is TiCl4, and the N-type metal work function layer also contains Cl.

9. The method for manufacturing a metal gate transistor according to claim 1, wherein: The metal filled in the contact hole opening includes Co.

10. The method for manufacturing a metal gate transistor according to claim 9, wherein: The step of filling metal in the contact hole opening to form the contact hole comprises: forming a Co seed layer; Performing an electroplating process to form a Co main layer, wherein the Co main layer completely fills the interior of the contact hole opening and extends to the outer surface of the contact hole opening; A chemical mechanical polishing process is performed to remove the Co bulk layer on the outer surface of the contact hole opening and to make the Co bulk layer only located in the contact hole opening.

11. The method for manufacturing a metal gate transistor according to claim 1, wherein: The NH3 plasma treatment machine and the machine for growing the first Ti layer and the second TiN layer are integrated into the same machine.

12. The method for manufacturing a metal gate transistor according to claim 11, wherein: The machine platform for the NH3 plasma treatment is also provided with a heater, and the heater is heated during the NH3 plasma treatment to increase the effect of removing Cl.

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