Semiconductor chip packaging structure and forming method thereof

Abstract

The invention provides a semiconductor chip packaging structure and a forming method thereof. The semiconductor chip packaging structure comprises a chip wafer; the substrate is in press fit with the chip wafer; wherein a pressing area of the packaging structure comprises a bonding pad and an open hole correspondingly formed above the bonding pad, and the open hole penetrates through the back surface of the chip wafer to expose the bonding pad; the metal wire is arranged in the open hole, the first end of the metal wire is connected with the bonding pad, and the second end of the metal wire extends to the back surface of the chip wafer along the side wall of the open hole; and the solder mask layer is arranged on the back surface of the chip wafer and covers the metal wires, and the part, corresponding to the interior of the opening, of the solder mask layer comprises one or more cavities by controlling the viscosity of solder mask liquid and the time from the time when the solder mask layer covers the back surface of the chip wafer to the time when the solder mask layer starts to bake. According to the semiconductor chip packaging structure, the stress of the solder mask layer acting on the bonding pad is reduced, and the stability and reliability of the semiconductor chip packaging structure are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor chip manufacturing, and in particular relates to a semiconductor chip packaging structure and a forming method thereof. Background Art

[0002] CMOS Image Sensor (CIS) is an important component of digital cameras. Its imaging principle is to sense light through photosensors, thereby converting light signals into electrical signals and then outputting images. As the pixel requirements of CIS products in digital security products become higher and higher, the pixel area of ​​CIS chips is getting larger and larger, and the overall size of the chip is also getting larger and larger.

[0003] Wafer Level Chip Size Packaging (WLCSP) is the mainstream semiconductor chip packaging technology today. It forms a dielectric layer and a conductive structure through steps such as layer-by-layer deposition, patterning, electroplating, and curing. Since the dielectric layer and the conductive structure are made of materials with different thermal expansion coefficients (CTE), when the temperature changes during the packaging or reliability process, different materials expand or contract to different degrees, which can easily cause the connection between the metal wire and the pad of the CIS chip to break or delaminate, thereby causing the chip function to fail, affecting the product yield and the subsequent reliability of the product. Summary of the invention

[0004] The purpose of the present invention is to provide a semiconductor chip packaging structure and a method for forming the same, so as to reduce the stress generated by materials with different thermal expansion coefficients on the pad, thereby reducing the risk of fracture of the pad metal layer and improving the stability and reliability of the semiconductor chip packaging structure.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a semiconductor chip packaging structure, which includes: a chip wafer; a substrate, which is pressed together with the chip wafer; wherein the pressing area of ​​the packaging structure includes a solder pad, and an opening correspondingly formed above the solder pad, the opening extending from the back side of the chip wafer to expose the solder pad; a metal wire, which is arranged in the opening, with a first end connected to the solder pad and a second end extending along the side wall of the opening to the back side of the chip wafer; a solder mask layer, which is arranged on the back side of the chip wafer and covers the metal wire, and by controlling the viscosity of the solder mask liquid and the time from the solder mask layer covering the back side of the chip wafer to the start of baking, the portion of the solder mask layer corresponding to the opening contains one or more cavities.

[0006] Optionally, a portion of the back side of the chip wafer corresponding to the pressing area is removed to form a step, and the opening is arranged at the step position, wherein the thickness of the step portion of the chip wafer is between 1 / 3 and 1 / 2 of the thickness of the middle portion of the chip wafer.

[0007] Optionally, a dielectric layer is provided on the surface of the pad; and after the chip wafer and the substrate are pressed together, the back side of the chip wafer is also covered with an insulating layer; and the opening penetrates the insulating layer and the dielectric layer.

[0008] Optionally, the surface of the dielectric layer is configured as an uneven surface to disperse contact pressure.

[0009] Optionally, the chip wafer includes a photosensitive chip, and the pads are symmetrically or asymmetrically arranged around a photosensitive area of ​​the photosensitive chip.

[0010] A second aspect of the present invention provides a method for forming a semiconductor chip packaging structure as described above, the method comprising a step of forming a solder resist layer, wherein the solder resist layer is formed by controlling the viscosity of the solder resist liquid and the time from the formation of the solder resist to the start of baking, so that the solder resist layer includes one or more cavities in the portion corresponding to the opening.

[0011] Optionally, the method comprises the following steps: step S1: providing a substrate and a chip wafer, and pressing the substrate and the chip wafer together; step S2: thinning the back side of the pressed chip wafer to form a step; step S3: forming an opening on the step through multiple exposure, development and etching to expose the pad; step S4: forming a metal wire in the opening, wherein the first end of the metal wire is connected to the pad, and the second end extends along the side wall of the opening to the back side of the chip wafer; step S5: covering the chip wafer with solder resist, wherein the solder resist flows along the back side of the chip wafer and the side wall of the opening to cover the metal wire; wherein the time from the formation of the solder resist layer to the start of baking is controlled to form a solder resist layer with a cavity in the opening.

[0012] Optionally, the time from forming the solder mask layer to starting baking is controlled to be within 60 minutes.

[0013] Optionally, the solder resist layer includes a cavity, and a diameter of the cavity is greater than 1 / 3 of the size of the opening.

[0014] Optionally, the step height is 1 / 3 to 1 / 2 of the thickness of the back side of the chip wafer after the thinning operation.

[0015] Optionally, coating the back side of the chip wafer with solder resist, for example by printing, includes: placing a silk screen above the back side of the chip wafer, and using a scraper to drive the solder resist to move along the surface of the silk screen, and the solder resist flows along the opening to the back side of the chip wafer and into the opening.

[0016] Optionally, the viscosity range of the solder mask is (15000±3000) mPa·s.

[0017] Optionally, a thinning operation is performed on the back side of the pressed chip wafer, including the following steps: S21, grinding and thinning the back side of the pressed chip wafer; S22, forming a thinned photoresist layer on the back side of the chip wafer after grinding and thinning, and performing exposure, development and thinning etching to remove the peripheral edge portion of the back side of the chip wafer to form the step.

[0018] Optionally, a dielectric layer is formed on the pad surface of the chip wafer, wherein forming an opening on the step includes the following steps: S31, forming a first photoresist layer on the step, and forming a first opening through the back side of the chip wafer through a first exposure, development and a first etching to expose the dielectric layer; S32, forming an insulating layer on the back side of the chip wafer including the first opening, forming a second photoresist layer on the insulating layer or using the insulating layer as a photoresist layer, and performing a second exposure, development and a second etching to remove the insulating layer and the dielectric layer at the bottom of the first opening to form a second opening, and the first opening and the second opening are connected to form the opening to expose the pad.

[0019] Optionally, before forming an insulating layer on the back side of the chip wafer including the first opening in step S32, the method further includes: pre-etching the dielectric layer to reduce the thickness of the dielectric layer to 30% to 95% of the original thickness, so that the surface of the dielectric layer is formed into an uneven surface to disperse the contact pressure.

[0020] Optionally, forming the metal wire in the opening includes the following steps: sputtering a metal seed layer on the back side of the chip wafer including the opening, electroplating and thickening the metal seed layer to form a metal layer, forming a third photoresist layer on the metal layer, and performing third exposure, development and metal etching to obtain the metal wire.

[0021] Optionally, the method further includes forming a third opening on the solder resist layer to expose the second end of the metal wire, and forming solder paste in the third opening.

[0022] Compared with the prior art, the present invention provides a semiconductor chip packaging structure and a method for forming the same. By controlling the viscosity of the solder paint liquid and the time from when the solder resist layer covers the back of the chip wafer to when baking begins, a solder resist layer with a cavity can be formed in the opening. On the one hand, the contact area between the solder resist layer and the opening is reduced, and the stress of the solder resist layer on the metal wire is eliminated, thereby avoiding the fracture of the connection between the metal wire and the pad and the detachment of the sealing layer; on the other hand, the cavity provides a redundant space for accommodating deformation, absorbs part of the deformation caused by different thermal expansion coefficients, thereby reducing the stress of the solder resist layer on the metal wire and improving the reliability of the chip wafer. The surface of the dielectric layer is formed into an uneven surface to further alleviate the residual stress. The uneven surface provided by the dielectric layer can provide multiple directions of contact with the material layer in contact with it, avoiding the accumulation of stress in the same direction caused by planar contact, thereby dispersing and releasing the stress originally concentrated in a certain direction in the opening, so that the combination of the metal wire and the pad position is more firm. Furthermore, by setting the opening at the position of the step on the back of the chip wafer and strictly controlling the thickness of the step to be set between 1 / 3 and 1 / 2 of the thickness of the middle part (non-thinned part) of the chip wafer, it is possible to conveniently control the time to form a solder mask layer with a cavity in the opening, wherein the control of the step thickness can make the stresses generated by the metal wire and the solder mask layer point in different directions as much as possible, while taking into account reducing the difficulty of forming the opening to facilitate exposing the pad, thereby generally improving the manufacturing yield stability of the semiconductor chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic cross-sectional structure diagram of a semiconductor chip packaging structure of the present invention;

[0024] Figure 2 It is a schematic cross-sectional structure diagram of another semiconductor chip packaging structure of the present invention;

[0025] Figure 3 to Figure 8 A schematic cross-sectional structure diagram of a formation process of a semiconductor chip packaging structure of the present invention;

[0026] Fig. 9 The present invention is a flow chart of a method for forming a semiconductor chip packaging structure. DETAILED DESCRIPTION

[0027] The technical solutions, structural features, achieved objectives and effects of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0028] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0029] It should be noted that, in the present invention, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or equipment including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment.

[0030] The study found that the packaging structure formed by the existing image sensor packaging method has low reliability. This is because during the packaging process, the dielectric layer and the conductive structure formed above the chip pad have different thermal expansion coefficients (CTE). When the temperature changes during the packaging process, the expansion or contraction deformation caused by the materials with different thermal expansion coefficients is converted into stress acting on the pad, which can easily lead to breakage and delamination of the conductive structure connected to the pad, causing electrical connection failure and affecting chip performance and life.

[0031] In view of the above defects, the present invention provides a semiconductor chip packaging structure, please refer to Figure 1 The semiconductor chip packaging structure includes: a chip wafer 101; a substrate 102, wherein the substrate 102 is pressed together with the chip wafer 101; wherein the pressing area (such as Figure 1 The dotted line framed portion in the chip wafer 101 includes a pad 111, and an opening 112 formed correspondingly above the pad 111, the opening 112 penetrates from the back of the chip wafer 101 to expose the pad 111; a metal wire 103, which is arranged in the opening 112, the first end 131 is connected to the pad 111, and the second end 132 extends along the side wall of the opening 112 to the back of the chip wafer 101; a solder mask layer 104, which is arranged on the back of the chip wafer 101, covers the metal wire 103, and controls the viscosity of the solder mask liquid and the time from the solder mask layer 104 covering the back of the chip wafer 101 to the start of baking so that the portion of the solder mask layer 104 corresponding to the opening 112 contains one or more cavities 105. By controlling the viscosity of the solder mask liquid and the baking time after the solder mask layer is coated under certain conditions, the manufacturing flexibility of the packaging structure can be improved, and the manufacturing yield and production efficiency can be improved.

[0032] In this embodiment, the substrate 102 may be a glass substrate, a sapphire substrate or a plastic substrate. For example, the substrate 102 may be a large glass substrate.

[0033] Among them, Figures 4 to 6 As shown, the surface of the pad 111 is provided with a dielectric layer 115 to prevent the pad 111 from being damaged during the packaging process; and after the chip wafer 101 and the substrate 102 are pressed together, the back of the chip wafer 101 is also covered with an insulating layer 116; the opening 112 penetrates the insulating layer 116 and the dielectric layer 115 to expose the pad 111 at the bottom of the opening 112. In particular, the surface of the dielectric layer is also set to an uneven surface to disperse the stress generated by the contact between each material structure and the dielectric layer, thereby dispersing the contact pressure, which can further improve the bonding stability of each functional layer in the opening.

[0034] Further, if Figure 1 As shown, in this embodiment, the opening 112 contains a cavity 105, and the cavity 105 is composed of the solder mask layer 104 and the side wall and bottom of the opening 112. That is, the solder mask layer 104 only covers the top of the opening 112 and does not extend into the opening 112, thereby forming the cavity 105, thereby reducing the contact area between the solder mask layer 104 and the opening 112, eliminating the stress of the solder mask layer 104 on the metal wire 103, thereby avoiding the problem of fracture and delamination at the connection between the metal wire 103 and the pad 111. This is because the solder mask layer 104 and the metal wire 103 have different thermal expansion coefficients, resulting in different deformation sizes, and the deformation of the solder mask layer 104 is larger, so the stress acting on the metal wire 103 is greater. By setting the cavity 105, the contact between the solder mask layer 104 and the metal wire 103 can be reduced, thereby reducing the stress of the solder mask layer 104 on the metal wire 103.

[0035] In another embodiment, if Figure 2 As shown, the cavity 205 in the opening 112 is a circular bubble, that is, the solder mask layer 104 extends along the side wall of the opening 112 to the bottom of the opening 112 and covers the bottom of the opening 112, so that the cavity 205 is wrapped in the solder mask layer 104. In this embodiment, the cavity 205 provides a space for the deformation of the solder mask layer 104, thereby reducing the stress of the solder mask layer 104 on the metal wire 103, and avoiding the problem of fracture and delamination at the connection between the metal wire 103 and the pad 111.

[0036] In order to further improve the stability of semiconductor packaging structures, such as Figure 1As shown, the portion of the back side of the chip wafer 101 corresponding to the pressing area is removed to form a step 113, and the opening 112 is arranged on the step 113. The step 113 is arranged at the circumferential edge of the back side of the chip wafer 101, and is arranged around the middle part 114 of the back side of the chip wafer 101, so that the back side of the chip wafer 101 forms a cross-sectional shape with a high middle and low edges. Preferably, the thickness of the step 113 on the back side of the chip wafer 101 is between 1 / 3 and 1 / 2 of the thickness of the middle part 114 of the chip wafer 101. If the thickness of the step 113 is too thin, when the metal wire 103 and the solder mask layer 104 are formed on the step 113, the stresses generated by the metal wire 103 and the solder mask layer 104 are in different directions, which may cause damage to the step 113 and further cause failure of the semiconductor packaging structure; if the thickness of the step 113 is too thick, the opening 112 may not penetrate the back side of the chip wafer 101 and the pad 111 may not be exposed, thereby failing to form an effective electrical connection and failing to realize communication and data transmission between the chip wafer 101 and the external circuit.

[0037] The chip wafer 101 includes a photosensitive chip 121, and the pads 111 are symmetrically or asymmetrically arranged around the photosensitive chip 121. Specifically, the front side ( Figure 1 The lower surface (ie, the photosensitive surface) shown in FIG. 1 has a photosensitive area and a pad area (not labeled) surrounding the photosensitive area. The photosensitive area has a photosensitive structure 1211, and the pads 111 are symmetrically or asymmetrically arranged in the pad area.

[0038] In this embodiment, the photosensitive chip 121 included in the chip wafer 101 can be a CMOS image sensor chip (in this case, the chip wafer 101 is a CMOS image sensor wafer), so the image sensor packaging structure finally formed can be a CMOS image sensor packaging structure. Among them, the photosensitive structure 1211 can specifically include structures such as an optical lens layer, a color film layer, and a photodiode. The photosensitive structure 1211 is used to realize photoelectric conversion. The CMOS image sensor chip can also be formed with a MOS tube, a floating diffusion area, an amplification circuit, and an interconnection structure that cooperates with the photodiode. These semiconductor devices and structures process the photoelectric signal generated by the photosensitive structure 1211 and electrically connect the photosensitive structure 1211 to the pad 111.

[0039] Furthermore, in order to prevent the photosensitive structure 1211 from being damaged during the packaging process, Figure 1 As shown, the packaging structure of this embodiment forms a cavity 203 between the chip wafer 101 and the substrate 102 , and the photosensitive structure 1211 is disposed in the cavity 203 to protect the photosensitive structure 1211 .

[0040] In order to form the above-mentioned semiconductor chip packaging structure, the present invention also provides a method for forming a semiconductor chip packaging structure, the forming method comprising the steps of forming a solder mask layer 104, such as Figure 1 As shown, in this step, the solder resist paint layer 104 is formed by controlling the viscosity of the solder resist paint liquid and the time from the formation of the solder resist paint to the start of baking, so that the solder resist paint layer 104 includes one or more cavities 105 in the portion corresponding to the opening 112.

[0041] Please continue to refer to Figure 3 to Figure 9 The method for forming the semiconductor chip packaging structure specifically comprises the following steps:

[0042] Step S1: providing a substrate 102 and a chip wafer 101, and pressing the substrate 102 and the chip wafer 101 together, such as Figure 3 As shown;

[0043] After the substrate 102 and the chip wafer 101 are pressed and fixed, step S2 is performed: a thinning operation is performed on the back side of the pressed chip wafer 101 to form a step 113, such as Figure 4 As shown;

[0044] Step S3: Through multiple exposure, development and etching, an opening 112 is formed on the step 113, and the opening 112 passes through the back side of the chip wafer 101 to expose the pad 111. Figure 6 As shown;

[0045] Step S4: forming a metal wire 103 in the opening 112, wherein a first end 131 of the metal wire 103 is connected to the pad 111, and a second end 132 extends along the side wall of the opening 112 to the back side of the chip wafer 101. Figure 7 As shown;

[0046] Step S5: The back side of the chip wafer 101 is coated with solder resist, for example by printing, and the solder resist flows along the back side of the chip wafer 101 and the side wall of the opening 112 to cover the metal wire 103; wherein, by controlling the time from the formation of the solder resist to the start of baking, a solder resist layer 104 having a cavity 105 is formed in the opening 112.

[0047] Among them, the control of the time from the formation of the solder mask layer to the start of baking is within 60 minutes. This is because the solder mask is usually a liquid photosensitive material (such as a 2-methoxyethyl acrylate system). When the control of the time from the formation of the solder mask layer to the start of baking is within 0 to 60 minutes, the solder mask has not completely filled the opening 112. At this time, baking and curing are performed to form a cavity 105 in the opening 112. At the same time, the viscosity range of the solder mask is (15000±3000) mPa·s. Within this viscosity range, the flow speed of the solder mask on the back of the chip wafer 101 is more uniform, and the thickness of the solder mask layer formed is also more uniform, which is more conducive to forming a cavity 105 in the opening 112 by controlling the time from the formation of the solder mask layer to the start of baking.

[0048] Further, when the solder mask layer 104 includes a cavity 105, the diameter of the cavity 105 is greater than 1 / 3 of the size of the opening 112. If the cross-sectional shape of the opening 112 is a trapezoid, that is, the top width of the opening 112 is greater than its bottom width, then the diameter of the cavity 105 is greater than 1 / 3 of the top width of the opening 112, so as to provide sufficient deformation accommodation space, reduce the stress caused by the deformation of the solder mask layer 104 on the metal wire 103, reduce the risk of the metal wire 103 breaking, and ensure the electrical connection stability between the metal wire 103 and the pad 111.

[0049] Specifically, Figure 7 As shown, the step S5 of covering the back of the chip wafer 101 (e.g., coating by printing) with solder mask includes: placing a screen 301 above the back of the chip wafer 101, and a scraper 302 drives the solder mask 303 to move along the surface of the screen 301, and the screen 301 is provided with a plurality of openings 311, and the solder mask 303 flows along the openings 311 to the back of the chip wafer 101 and the opening 112, and within 30 minutes after the solder mask is formed, baking and curing are performed to form a solder mask layer 104 having a cavity 105 in the opening 112. By setting the openings 311 of the screen 301, the uniformity and thickness of the solder mask layer 104 can be adjusted.

[0050] Specifically, Figure 3 As shown, the surface of the substrate 102 described in step S1 has an adhesive layer (not shown in the figure), and the adhesive layer is made of a viscous material. The position of the adhesive layer corresponds to the position of the pad 111 on the chip wafer 101. In this embodiment, the viscous material can be glue, and the substrate 102 and the chip wafer 101 can be bonded by dispensing glue, painting glue, printing glue, rolling glue or photolithography process patterned glue. The photolithography process patterned glue refers to removing unnecessary parts of the glue layer through processes such as exposure and development after glue coating, so as to obtain the desired patterned glue layer.

[0051] Wherein, the back side of the pressed chip wafer is thinned as described in step S2. Figure 3-4 As shown, the steps include: S21, grinding and thinning the back side of the pressed chip wafer 101; S22, forming a thinned photoresist layer 201 on the back side of the ground and thinned chip wafer 101, and performing exposure, development and thinning etching to remove the peripheral edge portion of the back side of the chip wafer 101 to form the step 113. The thinning operation in step S2 can not only ensure that the overall thickness of the subsequently formed packaging structure is small, but also ensure that the packaging structure has sufficient strength.

[0052] Further, if Figure 5-6 As shown, a dielectric layer 115 is formed on the surface of the pad 111 of the chip wafer 101, and the forming of the opening 112 on the step 113 in step S3 includes the following specific steps:

[0053] S31, forming a first photoresist layer (not shown) on the step 113, and forming a first opening 1121 penetrating the back side of the chip wafer 101 through a first exposure, development and first etching to expose the dielectric layer 115;

[0054] S32. An insulating layer 116 is formed on the back side of the chip wafer 101 including the first opening 1121, and a second photoresist layer (not shown) is formed on the insulating layer 116 or the insulating layer 116 is used as a photoresist layer. A second exposure, development and second etching are performed to remove the insulating layer 116 and the dielectric layer 115 at the bottom of the first opening 1121 to form a second opening 1122. The first opening 1121 and the second opening 1122 are connected to form the opening 112, so that the pad 111 is exposed at the bottom of the opening 112.

[0055] Wherein, before forming the insulating layer 116 on the back side of the chip wafer 101 including the first opening 1121 as described in step S32, it also includes: pre-etching the dielectric layer 115 to reduce the thickness of the dielectric layer 115 to 30% to 95% of the original thickness, so that the surface of the dielectric layer is formed into an uneven surface to disperse the contact pressure. In one embodiment, the original thickness of the dielectric layer 115 is 2 μm. By pre-etching the dielectric layer 115, the stress can be dispersed, thereby reducing the fracture or warping of the metal layer of the pad 111.

[0056] Specifically, in one embodiment, Figure 7As shown, the step S4 of forming the metal wire 103 in the opening 112 includes the following steps: sputtering a metal seed layer on the back side of the chip wafer 101 including the opening 112, electroplating and thickening the metal seed layer to form a metal layer, forming a third photoresist layer (not shown) on the metal layer, and performing a third exposure, development and metal etching to obtain the metal wire 103. Furthermore, in order to prevent the wafer chip 102 from short-circuiting during the assembly process and to protect the metal wire 103 from physical damage, chemical corrosion or contamination, after the solder resist layer 104 having a cavity 105 is formed by controlling the viscosity of the solder resist liquid and the time from the formation of the solder resist to the start of baking, in order to achieve communication and data transmission between the chip wafer 101 and the external circuit, a third opening 141 is formed on the solder resist layer 104 to expose the second end 132 of the metal wire 103, and a solder paste 134 is formed (for example, printed) in the third opening, and the solder paste 134 serves as a signal derivation structure for electrically connecting the metal wire 105, thereby achieving signal derivation of the chip wafer 101.

[0057] In summary, the semiconductor chip packaging structure and its forming method provided by the present invention can form a solder mask layer 104 with a cavity 105 in the opening 112 by controlling the viscosity of the solder mask liquid and the time from when the solder mask layer 104 covers the back of the chip wafer 101 to when baking begins. On the one hand, the contact area between the solder mask layer 104 and the opening 112 is reduced, and the stress of the solder mask layer 104 acting on the metal wire 103 is eliminated, thereby avoiding the fracture of the connection between the metal wire 103 and the pad 111 and the phenomenon of the sealing layer detaching; on the other hand, the cavity 105 provides a redundant space for accommodating deformation, absorbs part of the deformation caused by different thermal expansion coefficients, thereby reducing the stress of the solder mask layer 104 on the metal wire 103, and improving the reliability of the chip wafer 101. At the same time, the thickness of the step 113 on the back of the chip wafer 101 is set to between 1 / 3 and 1 / 2 of the thickness of the middle part 114 of the chip wafer 101, which can improve the stability of the semiconductor chip packaging structure.

[0058] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A semiconductor chip packaging structure, characterized in that: include: Chip wafers; A substrate, the substrate being pressed together with the chip wafer; The pressing area of ​​the packaging structure includes a pad and an opening formed above the pad, wherein the opening is through the back of the chip wafer to expose the pad; A metal wire is disposed in the opening, a first end of which is connected to the pad, and a second end of which extends along the side wall of the opening to the back side of the chip wafer; A solder mask layer is arranged on the back side of the chip wafer and covers the metal wire. The viscosity of the solder mask liquid and the time from when the solder mask layer covers the back side of the chip wafer to when baking begins are controlled so that the portion of the solder mask layer corresponding to the opening contains one or more cavities.

2. The semiconductor chip packaging structure according to claim 1, characterized in that: A portion of the back side of the chip wafer corresponding to the pressing area is removed to form a step, and the opening is arranged at the step position, wherein the thickness of the step portion of the chip wafer is between 1 / 3 and 1 / 2 of the thickness of the middle portion of the chip wafer.

3. The semiconductor chip packaging structure according to claim 1, wherein: A dielectric layer is arranged on the surface of the pad; and after the chip wafer and the substrate are pressed together, the back of the chip wafer is also covered with an insulating layer; and the opening penetrates through the insulating layer and the dielectric layer.

4. The semiconductor chip packaging structure according to claim 3, characterized in that: The surface of the dielectric layer is configured as an uneven surface to disperse the contact pressure.

5. The semiconductor chip packaging structure according to claim 1, wherein: The chip wafer includes a photosensitive chip, and the pads are symmetrically or asymmetrically arranged around a photosensitive area of ​​the photosensitive chip.

6. A method for forming a semiconductor chip packaging structure according to any one of claims 1 to 5, characterized in that: The method includes a step of forming a solder resist layer, wherein the solder resist layer is formed by controlling the viscosity of the solder resist liquid and the time from forming the solder resist to starting baking, so that the solder resist layer includes one or more cavities in the portion corresponding to the opening.

7. The forming method according to claim 6, characterized in that: The following steps are included: Step S1: providing a substrate and a chip wafer, and pressing the substrate and the chip wafer together; Step S2: thinning the back side of the pressed chip wafer to form a step; Step S3: forming an opening on the step through multiple exposure, development and etching to expose the pad; Step S4: forming a metal wire in the opening, wherein a first end of the metal wire is connected to the pad, and a second end of the metal wire extends along the side wall of the opening to the back side of the chip wafer; Step S5: Covering the back side of the chip wafer with solder resist, the solder resist flows along the back side of the chip wafer and the side wall of the opening to cover the metal wire; wherein, the time from the formation of the solder resist layer to the start of baking is controlled to form a solder resist layer with a cavity in the opening.

8. The forming method according to claim 7, characterized in that: The time from forming the solder mask layer to starting baking is controlled to be within 60 minutes.

9. The forming method according to claim 7, characterized in that: The solder resist layer includes a cavity, and the diameter of the cavity is greater than 1 / 3 of the size of the opening.

10. The forming method according to claim 7, characterized in that: The step height is 1 / 3 to 1 / 2 of the thickness of the back side of the chip wafer after the thinning operation.

11. The forming method according to claim 7, characterized in that: Covering the back of the chip wafer with solder mask includes: placing a screen above the back of the chip wafer, driving the solder mask to move along the surface of the screen with a scraper, and flowing the solder mask along the opening to the back of the chip wafer and into the opening.

12. The forming method according to claim 7, characterized in that: The viscosity range of the solder mask is (15000±3000) mPa·s.

13. The forming method according to claim 7, characterized in that: The back side of the laminated chip wafer is thinned, including the following steps: S21, grinding and thinning the back side of the pressed chip wafer; S22, forming a thinned photoresist layer on the back side of the chip wafer after grinding and thinning, and performing exposure, development and thinning etching to remove the peripheral side edge portion of the back side of the chip wafer to form the step.

14. The forming method according to claim 7, characterized in that: A dielectric layer is formed on the pad surface of the chip wafer, wherein forming an opening on the step comprises the following steps: S31, forming a first photoresist layer on the step, and forming a first opening penetrating through the back side of the chip wafer through a first exposure, development and a first etching to expose the dielectric layer; S32. Form an insulating layer on the back side of the chip wafer including the first opening, form a second photoresist layer on the insulating layer or use the insulating layer as the photoresist layer, and perform a second exposure and development and a second etching to remove the insulating layer and the dielectric layer at the bottom of the first opening to form a second opening. The first opening and the second opening are connected to form the opening to expose the pad.

15. The forming method according to claim 14, characterized in that: Before forming an insulating layer on the back side of the chip wafer including the first opening in step S32, the method further includes: pre-etching the dielectric layer to reduce the thickness of the dielectric layer to 30% to 95% of the original thickness, so that the surface of the dielectric layer is formed into an uneven surface to disperse the contact pressure.

16. The forming method according to claim 7, characterized in that: The forming of the metal wire in the opening includes the following steps: sputtering a metal seed layer on the back of the chip wafer including the opening, electroplating and thickening the metal seed layer to form a metal layer, forming a third photoresist layer on the metal layer, and performing third exposure, development and metal etching to obtain the metal wire.

17. The forming method according to claim 6, characterized in that: The method also includes forming a third opening on the solder resist layer to expose the second end of the metal wire, and forming solder paste in the third opening.

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