Capacitor, memory and manufacturing method of memory

Abstract

The invention belongs to the field of chips, and particularly relates to a capacitor, a memory and a manufacturing method of the memory. The capacitor may include: a first electrode layer; a second electrode layer; the strontium titanate dielectric layer is formed between the first electrode layer and the second electrode layer, and in the direction from the center of the strontium titanate dielectric layer to the two opposite sides of the strontium titanate dielectric layer, the ratio of Sr / (Sr + Ti) in the strontium titanate dielectric layer is gradually decreased, and the ratio of Sr / (Sr + Ti) in the strontium titanate dielectric layer is gradually decreased. One side of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side of the strontium titanate dielectric layer is close to the second electrode layer. The capacitor of the scheme has the characteristics of high K value and low electric leakage.

Description

Technical Field

[0001] The present disclosure belongs to the field of chips, and in particular relates to a capacitor, a memory, and a method for manufacturing the memory. Background Art

[0002] With the development of the chip industry, the market demand for DRAM (Dynamic Random Access Memory) chips with higher storage density is increasing. How to achieve higher storage density of DRAM chips is an important research topic for many chip industries.

[0003] For DRAM chips with a 1T1C (1 transistor + 1 capacitor) structure, the capacitor is an important factor that restricts the critical size of the DRAM chip. How to increase the DRAM storage density while reducing the critical size and ensure that the DRAM chip has sufficient signal resolution, that is, how to ensure that the capacitor achieves a higher dielectric constant (abbreviated as: K value) and a lower leakage density, has become an urgent problem that needs to be solved. Summary of the invention

[0004] The embodiments of the present disclosure provide a capacitor, a memory and a method for manufacturing the memory, which can achieve the effects of high K value and low leakage.

[0005] A first aspect of the present disclosure provides a capacitor, comprising:

[0006] a first electrode layer;

[0007] a second electrode layer; and

[0008] A strontium titanate dielectric layer is formed between the first electrode layer and the second electrode layer, wherein:

[0009] In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases,

[0010] One of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is close to the second electrode layer.

[0011] A second aspect of the present disclosure provides a memory, comprising a substrate and any one of the capacitors described above, wherein the capacitor is formed on the substrate.

[0012] A third aspect of the present disclosure provides a method for manufacturing a memory, which may include:

[0013] providing a substrate;

[0014] forming a first electrode layer on the substrate;

[0015] A strontium titanate dielectric layer is formed on a side of the first electrode layer away from the substrate, and in a direction from the center of the strontium titanate dielectric layer to two opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases, and one of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is away from the first electrode layer;

[0016] A second electrode layer is formed on a side of the strontium titanate dielectric layer away from the first electrode layer to form a capacitor.

[0017] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by making the proportion of Sr content in the strontium titanate dielectric layer gradually decrease from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer, and the proportion of Ti content gradually increase from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer, while ensuring that the strontium titanate dielectric layer as a whole is in a high Sr content so that it has a higher K value, it can also be beneficial to release or relax the stress caused by the easy crystallization of the strontium titanate dielectric layer due to the high Sr content, that is, the stress is gradually released from the center of the strontium titanate dielectric layer to its two sides, and by reducing the internal stress of the strontium titanate dielectric layer, the occurrence of cracks in the strontium titanate dielectric layer can be reduced, and the surface uniformity of the strontium titanate dielectric layer is improved, so that it has low leakage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0019] Figures 1 to 5 A schematic diagram of the structure of the memory corresponding to the various solutions mentioned in the first embodiment of the present disclosure is shown in FIG.

[0020] Figure 6 A schematic diagram of the three-dimensional structure of the memory mentioned in the first embodiment of the present disclosure is shown in FIG.

[0021] Figure 7 A schematic diagram of the structure of a capacitor in a solution mentioned in the first embodiment of the present disclosure is shown in FIG.

[0022] Figures 8 to 10 Schematic diagram showing the corresponding changes in the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer when different gradient designs are performed in the first embodiment of the present disclosure.

[0023] Fig.11A schematic diagram of the structure of a capacitor in another solution mentioned in the first embodiment of the present disclosure is shown in FIG.

[0024] Figure 12 to Figure 14 The figure shows a schematic diagram of the structure of capacitors corresponding to various schemes in the second embodiment of the present disclosure.

[0025] Figures 15 to 25 A structural schematic diagram corresponding to each step in the memory manufacturing method provided in the third embodiment of the present disclosure is shown.

[0026] Description of reference numerals:

[0027] 10. substrate; 100. semiconductor base; 101. insulating isolation layer;

[0028] 11. Capacitor; 11a. Ruthenium film layer; 11b. Titanium nitride film layer; 110. First electrode layer; 111. Dielectric layer; 111a. Dielectric material film; 112. Second electrode layer; 112a. Second electrode material film; 1110. Strontium titanate dielectric layer; 11101. Strontium titanate film layer; 1111. First titanium oxide dielectric layer; 1112. Second titanium oxide dielectric layer; 1113. First aluminum titanate dielectric layer; 1114. Second aluminum titanate dielectric layer;

[0029] 12. Insulating dielectric layer;

[0030] 13. Etch stop layer;

[0031] 14, measuring electrode material film; 14a, first measuring electrode; 14b, second measuring electrode; 140, via conductive portion; 141, measuring conductive portion;

[0032] 15, interlayer dielectric layer; 150, through hole; 15a, interlayer dielectric material film;

[0033] 16. Transistor;

[0034] 17. Word line;

[0035] 18. Bit line;

[0036] 19. a first photoresist mask layer;

[0037] 20. A second photoresist mask layer;

[0038] 21. First via;

[0039] 22. Second via;

[0040] 23. a third photoresist mask layer;

[0041] 24. Fourth photoresist mask layer. DETAILED DESCRIPTION

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0043] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0044] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0045] Embodiment 1

[0046] The disclosed embodiment provides a memory, which may be a DRAM, for example, a three-dimensional DRAM, that is, a memory formed by stacking multiple layers of DRAM. However, it should be understood that the memory of the present embodiment is not limited to DRAM, but may also be other types of memory, depending on the specific circumstances.

[0047] like Figure 1 As shown, the memory of this embodiment may include a substrate 10 and a plurality of memory cells formed on the substrate 10 . The memory cell may include a capacitor 11 formed on the substrate 10 .

[0048] The capacitor 11 may include a first electrode layer 110 , a dielectric layer 111 , and a second electrode layer 112 which are sequentially stacked on the substrate 10 . That is, the dielectric layer 111 is formed between the first electrode layer 110 and the second electrode layer 112 .

[0049] For example, the capacitor 11 may be a MIM (Metal-Isolation-Metal) structure, that is, the first electrode layer 110 and the second electrode layer 112 include metal or metal compounds and have conductive properties, while the dielectric layer 111 is an insulator for isolating the first electrode layer 110 and the second electrode layer 112.

[0050] like Figure 2 As shown, the substrate 10 may include a semiconductor base 100, such as a silicon base, but not limited thereto, and may also be a base formed of other semiconductor materials (such as silicon carbide, gallium compounds, germanium compounds). In order to isolate the influence of the semiconductor base 100 on the MIM structure, the substrate 10 may also include an insulating isolation layer 101 formed between the first electrode layer 110 and the semiconductor base 100, that is, before forming the first electrode layer 110 on the semiconductor base 100, an insulating isolation layer 101 may be formed on the semiconductor base 100, and then the first electrode layer 110 is formed, and the insulating isolation layer 101 is used to insulate the semiconductor base 100 from the first electrode layer 110.

[0051] For example, the insulating isolation layer 101 may be made of SiO 2 (silicon dioxide) material, but is not limited thereto and may also be made of other insulating materials, depending on the specific situation.

[0052] In order to measure the electrical properties of the dielectric layer 111 in the capacitor 11, a measuring electrode for measuring the capacitor 11 may be manufactured during the process of manufacturing the capacitor 11 on the substrate 10. The specific relationship between the capacitor 11 and the measuring electrode is as follows:

[0053] like Figure 3 As shown, in the capacitor 11, the orthographic projections of the second electrode layer 112 and the dielectric layer 111 on the substrate 10 are located in the middle area of ​​the orthographic projection of the first electrode layer 110 on the substrate 10, that is, the edge area of ​​the first electrode layer 110 is not covered by the second electrode layer 112 and the dielectric layer 111, so as to facilitate the contact between the subsequently manufactured measuring electrode and the first electrode layer 110, wherein the orthographic projection of the second electrode layer 112 on the first electrode layer 110 overlaps with the orthographic projection of the dielectric layer 111 on the first electrode layer 110, so as to ensure the storage capacity of the capacitor 11.

[0054] like Figure 4 As shown, after the capacitor 11 is formed on the substrate 10 , the memory further includes an insulating dielectric layer 12 , an etch stop layer 13 , and a first measurement electrode 14 a and a second measurement electrode 14 b which are spaced apart and formed on the substrate 10 .

[0055] The insulating dielectric layer 12 covers the edge region of the first electrode layer 110 and the second electrode layer 112, the etch stop layer 13 is formed on the side of the insulating dielectric layer 12 away from the substrate 10, and the etch stop layer 13 completely covers the insulating dielectric layer 12. The first measuring electrode 14a and the second measuring electrode 14b both include a via conductive portion 140 and a measuring conductive portion 141 connected to each other, and the measuring conductive portion 141 of the first measuring electrode 14a and the second measuring electrode 14b is formed on the side of the etch stop layer 13 away from the substrate 10, and is used to be connected to an external measuring device for measuring the performance of the capacitor 11.

[0056] Among them, the orthographic projection of the via-hole conductive portion 140 of the first measuring electrode 14a on the substrate 10 is located within the orthographic projection of the edge area of ​​the first electrode layer 110 on the substrate 10, and the via-hole conductive portion 140 of the first measuring electrode 14a sequentially penetrates the etching stop layer 13 and the insulating dielectric layer 12 and contacts the edge area of ​​the first electrode layer 110, so that one pole of the measuring device contacts the first electrode layer 110 through the first measuring electrode 14a; the orthographic projection of the via-hole conductive portion 140 of the second measuring electrode 14b on the substrate 10 is located within the orthographic projection of the second electrode layer 112 on the substrate 10, and the via-hole conductive portion 140 of the second measuring electrode 14b sequentially penetrates the etching stop layer 13 and the insulating dielectric layer 12 and contacts the second electrode layer 112, so that the other pole of the measuring device contacts the second electrode layer 112 through the second measuring electrode 14b.

[0057] In this embodiment, the material of the first measuring electrode 14a and the second measuring electrode 14b may be TiN (titanium nitride) or the like, but is not limited thereto, and may also be other conductive materials, depending on the specific situation.

[0058] Since the dielectric layer 111 in the capacitor 11 is very thin, usually only a few nanometers, the edge of the dielectric layer 111 has a large leakage current. The edge leakage current is not an intrinsic characteristic of the material and will interfere with the measurement result. Based on this, Figure 5 As shown, the memory of this embodiment may further include an interlayer dielectric layer 15 to increase the distance between the edge of the second electrode layer 112 and the first electrode layer 110 .

[0059] Specifically, Figure 5 As shown, the interlayer dielectric layer 15 may be formed between the first electrode layer 110 and the insulating dielectric layer 12. It should be understood that the via conductive portion 140 of the first measuring electrode 14a mentioned above not only penetrates the etching stop layer 13 and the insulating dielectric layer 12, but also penetrates the interlayer dielectric layer 15 to contact the edge region of the first electrode layer 110. The interlayer dielectric layer 15 also has a through hole 150 to expose a portion of the first electrode layer 110.

[0060] like Figure 5As shown, the dielectric layer 111 has a middle portion and an edge portion arranged around the middle portion, the middle portion of the dielectric layer 111 is formed in the through hole 150 and contacts the first electrode layer 110, the edge portion of the dielectric layer 111 overlaps the surface of the interlayer dielectric layer 15 away from the first electrode layer 110, so as to increase the distance between the edge of the second electrode layer 112 and the first electrode layer 110, and the orthographic projection of the via-hole conductive portion 140 of the second measuring electrode 14b on the substrate 10 is located within the orthographic projection of the through hole 150 on the substrate 10, that is, the orthographic projection of the via-hole conductive portion 140 of the second measuring electrode 14b on the substrate 10 is located within the orthographic projection of the middle portion of the dielectric layer 111 on the substrate 10, so as to accurately measure the K value and leakage condition at the middle of the dielectric layer 111.

[0061] For example, Figure 4 and Figure 5 As shown, a plurality of via conductive portions 140 are provided in the first measuring electrode 14a and the second measuring electrode 14b, and are arranged at equal intervals around the axis of the through hole 150, so that the electric field distribution during the measurement process is more uniform and the measurement effect is more accurate.

[0062] It should be noted that when multiple via conductive portions 140 are provided in the first measuring electrode 14a and the second measuring electrode 14b, there may be only one measuring conductive portion 141 in the first measuring electrode 14a and the second measuring electrode 14b, but is not limited thereto. Multiple measuring conductive portions 141 may be provided and arranged at equal intervals around the axis of the through hole 150. They may be connected to the via conductive portions 140 one-to-one or one-to-many.

[0063] Among them, the first measuring electrode 14a and the second measuring electrode 14b mentioned in this embodiment are not limited to being retained in the memory finally produced, but can also be completely cut off or partially cut off during the die (grain) cutting process after the test is completed, depending on the specific cutting situation, but it does not affect the final use of the product.

[0064] In this embodiment, combined with Figure 6 As shown, in addition to the capacitor 11, the storage unit may also include a transistor 16, a word line 17 and a bit line 18. The transistor 16, the word line 17 and the bit line 18 may all be formed on the substrate 10. The gate of the transistor 16 may be connected to the word line 17, one of the source and the drain of the transistor 16 may be connected to the bit line 18, and the other may be connected to the capacitor 11; specifically, it may be connected to the first electrode layer 110 of the capacitor 11 to realize data reading and writing operations. That is to say, the storage unit may be a 1T1C structure.

[0065] For a memory including a 1T1C (1 transistor 16 + 1 capacitor 11) structure, capacitor 11 is an important factor restricting the critical size of the memory. How to increase the DRAM storage density while reducing the critical size and ensure that the DRAM chip has sufficient signal resolution has become a technical problem that needs to be solved urgently.

[0066] Among them, when the memory is a three-dimensional DRAM, such as Figure 6 As shown, the capacitor 11 can be placed horizontally, and its storage density can be effectively increased by reducing the lateral length of the capacitor 11. In addition, the first electrode layer 110, the second electrode layer 112 and the dielectric layer 111 of the capacitor 11 can be adjusted so that the capacitor 11 has a higher dielectric constant (abbreviated as: K value), that is, the storage density is increased and the leakage is reduced. In addition to being applicable to three-dimensional DRAM, this method can also be applied to other memories including capacitor structures. The structure of the capacitor 11 in the embodiment of the present disclosure is described in detail below in conjunction with the accompanying drawings.

[0067] In this embodiment, reference Figure 7 As shown, the dielectric layer 111 of the capacitor may include a strontium titanate dielectric layer 1110 (STO dielectric layer for short), and the strontium titanate dielectric layer 1110 contains strontium (Sr) and titanium (Ti).

[0068] According to research, when the strontium titanate dielectric layer 1110 is designed to have a high Sr content, that is, when the Sr content is greater than the Ti content in the overall design of the strontium titanate dielectric layer 1110, and the strontium titanate dielectric layer 1110 is a strontium-rich layer (SrRich), the K value will be relatively large and the storage density will be high, but the strontium titanate dielectric layer 1110 is prone to cracking, which will cause the formed capacitor to have an uneven electric field distribution, thereby causing the capacitor 1110 to leak electricity, and due to Since Sr is a heavy metal, it is easy to form oxygen vacancies, which leads to further increase in leakage. When the strontium titanate dielectric layer 1110 is designed as a whole with a high Ti content, that is, the Ti content is greater than the Sr content in the overall design of the strontium titanate dielectric layer 1110, and this strontium titanate dielectric layer 1110 is a titanium-rich layer (TiRich), it is not easy to crack and has a low leakage effect, but the K value will be relatively small, which is not conducive to reducing the size of the capacitor, and thus is not conducive to increasing the storage density of the DRAM chip.

[0069] Therefore, the embodiment of the present disclosure implements a gradient design for the structure of the strontium titanate dielectric layer 1110. Specifically, in the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases (that is, the proportion of Sr content in the strontium titanate dielectric layer 1110 gradually decreases, and the proportion of Ti content gradually increases); in other words, in the direction from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases (that is, the proportion of Sr content in the strontium titanate dielectric layer 1110 gradually increases, and the proportion of Ti content gradually decreases).

[0070] Among them, one of the two opposite sides of the aforementioned strontium titanate dielectric layer 1110 is close to the first electrode layer 110, and the other side is close to the second electrode layer 112. In the direction from the center of the strontium titanate dielectric layer 1110 to the first electrode layer 110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases, and in the direction from the center of the strontium titanate dielectric layer 1110 to the second electrode layer 112, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 also gradually decreases.

[0071] In the solution of this embodiment, compared with the technical solution that the strontium titanate dielectric layer 1110 is a titanium-rich layer or a strontium-rich layer as a whole, by making the Sr content ratio in the strontium titanate dielectric layer 1110 gradually decrease from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, and the Ti content ratio gradually increases from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, so as to ensure that the strontium titanate dielectric layer 1110 is a titanium-rich layer or a strontium-rich layer as a whole. While having a high Sr content so that it has a higher K value, it is also beneficial to release or relax the stress caused by the easy crystallization of the strontium titanate dielectric layer 1110 due to the high Sr content, that is, the stress is gradually released from the center of the strontium titanate dielectric layer 1110 to both sides thereof. By reducing the internal stress of the strontium titanate dielectric layer 1110, the occurrence of cracks in the strontium titanate dielectric layer 1110 can be reduced, and the surface uniformity of the strontium titanate dielectric layer 1110 is improved, so that it has low leakage performance.

[0072] That is to say, this solution improves the K value of the capacitor 11, that is, effectively improves the storage density of the capacitor 11 while reducing its leakage, which is beneficial to reducing the key size in the 1T1C structure and improving the storage density of the three-dimensional DRAM.

[0073] For example, in this embodiment, the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 is greater than 50%, that is, the Sr content at the center of the strontium titanate dielectric layer 1110 is greater than the Ti content. The center of the strontium titanate dielectric layer 1110 is in an Sr-rich state to ensure that the center of the strontium titanate dielectric layer 1110 has a higher K value, thereby ensuring that the strontium titanate dielectric layer 1110 as a whole has a good storage density.

[0074] It should be noted that the Sr / (Sr+Ti) ratio design at the center of the strontium titanate dielectric layer 1110 may be related to its thickness to ensure the overall performance of the strontium titanate dielectric layer 1110 .

[0075] Among them, the thickness of the strontium titanate dielectric layer 1110 can range from 5nm to 7nm, such as: 5nm, 5.5nm, 6nm, 6.5nm, 7nm, etc., and the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 can range from 60% to 65%, such as: 60%, 61%, 62%, 63%, 64%, 65%, etc.

[0076] For example, when the thickness of the strontium titanate dielectric layer 1110 is about 6 nm, the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 can substantially reach 62%, so that the capacitor can achieve a high K value (>60) and a low leakage current (<10 -5 ) performance.

[0077] In one embodiment of the present disclosure, reference Figure 7 As shown, the strontium titanate dielectric layer 1110 as a whole is a single-layer structure formed in one step, that is, when the strontium titanate dielectric layer 1110 is formed on the side of the first electrode layer 110 away from the substrate 10, a film forming process can be used. For example, the strontium titanate material can be deposited on the side of the first electrode layer 110 away from the substrate 10 using an atomic layer deposition (Atomic layer deposition, abbreviated as: ALD) process to form the strontium titanate dielectric layer 1110.

[0078] In which, in the atomic layer deposition process, by adjusting the flow rate of the Sr precursor and / or the Ti precursor, the Sr content ratio in the strontium titanate dielectric layer 1110 first gradually increases and then gradually decreases, so that the ratio of Sr / (Sr+Ti) in the strontium titanate material first gradually increases and then gradually decreases to form the aforementioned strontium titanate dielectric layer 1110, that is: in the direction from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases.

[0079] Furthermore, if Figure 7As shown, in the strontium titanate dielectric layer 1110: the surface close to the first electrode layer 110 is defined as the first boundary surface a1, and the surface close to the second electrode layer 112 is defined as the second boundary surface a2, and the Sr content at the first boundary surface a1 and the second boundary surface a2 can be 0; in other words, when the strontium titanate dielectric layer 1110 is manufactured, the initial strontium titanate material deposited at the beginning of an atomic layer deposition process does not contain Sr, or the Sr content is very, very small, approximately 0, and then the Sr content in the strontium titanate material is gradually increased, and when the set amount is reached, the Sr content in the strontium titanate material is gradually reduced, so that the Sr content in the strontium titanate material at the end of the atomic layer deposition process is 0, or approximately 0.

[0080] It should be understood that when the Sr content at the first boundary surface a1 and the second boundary surface a2 in the strontium titanate dielectric layer 1110 is 0, the first boundary surface a1 and the second boundary surface a2 can be understood as the titanium dioxide (TiO2) surface. The use of TiO2 at the boundary surface can effectively reduce the oxygen vacancies in the strontium titanate dielectric layer 1110 and reduce the occurrence of leakage.

[0081] For example, when manufacturing a single-layer strontium titanate dielectric layer 1110, the strontium titanate material deposited at the beginning and end of an atomic layer deposition process, in addition to not containing Sr, may also be doped with Al (aluminum). That is, the first boundary surface a1 and the second boundary surface a2 may be ATO (aluminum titanate) boundary surfaces to increase CBO (conduction band offset) and further reduce leakage.

[0082] It should be understood that when semiconductors and semiconductors, or insulators and semiconductors contact to form an interface structure, due to the different bandgap widths, discontinuous steps, namely band offsets, will be formed at the bottom of the conduction band and the top of the valence band of the materials on both sides. The band step at the bottom of the conduction band is called the conduction band offset (CBO for short), and the band step at the top of the valence band is called the valence band offset (VBO for short).

[0083] In an optional embodiment, from the center of the strontium titanate dielectric layer 1110 (the center is Figure 7 The dashed line passes through) to the opposite sides of the strontium titanate dielectric layer 1110 ( Figure 7In other words, in the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 can decrease at a uniform rate to better balance the performance of the strontium titanate dielectric layer 1110 with high K value and low leakage.

[0084] For example, refer to Figure 8 As shown, the aforementioned linear relationship can be specifically:

[0085]

[0086] Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer 1110, D is the distance from the center of the strontium titanate dielectric layer 1110, H is the thickness of the strontium titanate dielectric layer 1110, and 0≤D≤H / 2.

[0087] For example, when C is 0.62 and H is 6 nm, the linear relationship can be:

[0088]

[0089] Among them, when the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the first electrode layer 110 is 3nm, the ratio of Sr / (Sr+Ti) is 0, which can be understood as the first boundary surface a1 mentioned above, and when the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the second electrode layer 112 is 3nm, the ratio of Sr / (Sr+Ti) is 0, which can be understood as the second boundary surface a2 mentioned above.

[0090] In another alternative embodiment, if Fig. 9 As shown, in the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110: the rate of decrease of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases. In other words, in the direction from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110: the rate of increase of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases. That is to say, when the entire strontium titanate dielectric layer 1110 is manufactured, the Sr content is first increased rapidly, then the Sr content is slowly increased to a maximum value, and then the Sr content is first slowly reduced, and then the Sr content is quickly reduced. In this way, while ensuring that the strontium titanate dielectric layer 1110 has low leakage performance, the K value of the strontium titanate dielectric layer 1110 can also be improved.

[0091] For example, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 may satisfy the following relationship:

[0092]

[0093] Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer 1110, D is the distance from the center of the strontium titanate dielectric layer 1110, H is the thickness of the strontium titanate dielectric layer 1110, and 0≤D≤H / 2.

[0094] For example, when C is 0.62 and H is 6 nm, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 satisfies the following relationship:

[0095]

[0096] Among them, when the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the first electrode layer 110 is 3nm, the ratio of Sr / (Sr+Ti) is 0, which can be understood as the first boundary surface a1 mentioned above, and when the distance from the center of the strontium titanate dielectric layer 1110 in the direction close to the second electrode layer 112 is 3nm, the ratio of Sr / (Sr+Ti) is 0, which can be understood as the second boundary surface a2 mentioned above.

[0097] In yet another alternative embodiment, Fig.10 As shown, in the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110: the rate of decrease of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 is gradually reduced. In other words, in the direction from the opposite sides of the strontium titanate dielectric layer 1110 to the center of the strontium titanate dielectric layer 1110: the rate of increase of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 is gradually increased. In other words, when the entire strontium titanate dielectric layer 1110 is manufactured, the Sr content is first slowly increased, and then the Sr content is quickly increased to a maximum value, and then the Sr content is first quickly reduced, and then the Sr content is slowly reduced. In this way, while ensuring that the strontium titanate dielectric layer 1110 has a high K value, the surface uniformity of the opposite sides of the strontium titanate dielectric layer 1110 can also be improved, so that it has a low leakage performance.

[0098] It should be understood that Figures 8 to 10 The X-axis is used to represent the distance from the strontium titanate dielectric layer 1110 in nm (nanometers), the Y-axis is used to represent the ratio of Sr / (Sr+Ti), and the line on the left side of the Y-axis is used to represent the change in the ratio of Sr / (Sr+Ti) between the center of the strontium titanate dielectric layer 1110 and the first electrode layer 110, and the line on the right side of the Y-axis is used to represent the change in the ratio of Sr / (Sr+Ti) between the center of the strontium titanate dielectric layer 1110 and the second electrode layer 112.

[0099] In addition, to further improve the performance of the capacitor, refer to Fig. 9 As shown, the first electrode layer 110 and the second electrode layer 112 of the present embodiment may include a ruthenium element film layer 11a, which is a metal ruthenium (Ru) film layer or a ruthenium oxide (RuO2) film layer with a high work function. The work function is also called the work function or the work function, which is defined in solid state physics as the minimum energy required to move an electron from the inside of a solid to the surface of the object.

[0100] For example, the dielectric layer 111 of the capacitor may only include the strontium titanate dielectric layer 1110 mentioned above, and the first boundary surface a1 of the strontium titanate dielectric layer 1110 may contact the ruthenium element film layer 11a of the first electrode layer 110, and the second boundary surface a2 of the strontium titanate dielectric layer 1110 may contact the ruthenium element film layer 11a of the second electrode layer 112. When the first boundary surface a1 and the second boundary surface a2 of the strontium titanate dielectric layer 1110 are TiO2 surfaces, the ruthenium element film layer 11a can promote the TiO2 to form a rutile structure at the boundary surface, thereby reducing leakage and increasing the K value, so that the K value of the strontium titanate dielectric layer 1110 first decreases and then increases from the middle to both sides, the middle and the boundary mainly increase the dielectric constant, and the area between the middle and the boundary mainly provides a leakage reduction effect.

[0101] Among them, Fig. 9 As shown, the first electrode layer 110 and the second electrode layer 112 also include a titanium nitride film layer 11b, and the titanium nitride film layer 11b is formed on the side of the ruthenium element film layer 11a away from the strontium titanate dielectric layer 1110. In this way, while ensuring that the overall thickness and work function of the first electrode layer 110 and the second electrode layer 112 meet the requirements, the thickness of the ruthenium element film layer 11a can be appropriately reduced by setting the titanium nitride film layer 11b, so as to promote the formation of a rutile structure of TiO2 at the boundary surface, reduce leakage, and increase the K value, while appropriately reducing the cost of the first electrode layer 110 and the second electrode layer 112.

[0102] Embodiment 2

[0103] The main difference between the embodiment of the present disclosure and the first embodiment is that the strontium titanate dielectric layer 1110 in the capacitor of the first embodiment is a single-layer structure, while the strontium titanate dielectric layer 1110 in the capacitor of the second embodiment may be a multi-layer stacked structure.

[0104] The structure of the capacitor according to the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0105] In this embodiment, reference Fig.12As shown, the strontium titanate dielectric layer 1110 may be a multi-layer stacked structure, and the strontium titanate dielectric layer 1110 may include N layers of strontium titanate film layers 11101 stacked in sequence, where N is a positive integer greater than or equal to 3; it should be understood that each molding process forms a film layer, that is, the strontium titanate dielectric layer 1110 is formed using multiple molding processes. For example, in the step of forming the strontium titanate dielectric layer 1110 on the side of the first electrode layer 110 away from the substrate 10, it may specifically include: using N atomic layer deposition processes to form N layers of strontium titanate film layers 11101 stacked in sequence on the side of the first electrode layer 110 away from the substrate 10 to form a stacked strontium titanate dielectric layer 1110.

[0106] It should be noted that the strontium titanate film layer 11101 of this embodiment is a film layer containing both Sr and Ti, that is, the ratio of Sr / (Sr+Ti) in each strontium titanate film layer 11101 is greater than 0.

[0107] In the direction from the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 decreases layer by layer, such as Fig.12 As shown, taking N equal to 3 as an example, the strontium titanate dielectric layer 1110 may include a first strontium titanate film layer 11101, a second strontium titanate film layer 11101 and a third strontium titanate film layer 11101 stacked in sequence, the ratio of Sr / (Sr+Ti) in the second strontium titanate film layer 11101 is the largest, and the ratio of Sr / (Sr+Ti) in the first strontium titanate film layer 11101 and the third strontium titanate film layer 11101 is less than the ratio of Sr / (Sr+Ti) in the second strontium titanate film layer 11101. It should be noted that the strontium titanate dielectric layer 1110 is not limited to including Fig.12 The three-layer strontium titanate film 11101 shown in the figure may also include four layers, five layers, etc., depending on the specific situation.

[0108] In this embodiment, the strontium titanate dielectric layer 1110 is designed to be a multi-layer stacked structure, so that the gradient design of the strontium titanate dielectric layer 1110 is realized to ensure that the strontium titanate dielectric layer 1110 has high K value and low leakage characteristics. At the same time, the manufacturing method is simple, and while the thickness of the strontium titanate dielectric layer 1110 is ensured to remain unchanged, the thickness of each layer is reduced through layered production, which makes it easy to control the uniformity of film formation to improve product performance, and is also conducive to rapid commissioning. Existing equipment can be used to form each layer of the strontium titanate film 11101 in sequence, without the need to re-develop the equipment, thereby reducing research and development costs.

[0109] In addition, this embodiment designs the strontium titanate dielectric layer 1110 to be composed of at least three stacked strontium titanate film layers 11101. This ensures that the strontium titanate dielectric layer 1110 close to the first electrode layer 110 and the second electrode layer 112 have a gradient design, thereby ensuring that the strontium titanate dielectric layer 1110 and the first electrode layer 110 and the second electrode layer 112 have high K value and low leakage characteristics.

[0110] For example, N in this embodiment can be an odd number greater than or equal to 3, that is, the number of strontium titanate film layers 11101 in the strontium titanate dielectric layer 1110 is an odd number and greater than or equal to 3, such as: N=3, 5, 7, 9, etc., depending on the specific situation.

[0111] In this embodiment, by designing the number of strontium titanate film layers 11101 in the strontium titanate dielectric layer 1110 to be an odd number, it can be ensured that the number of film layers on the opposite sides of the strontium titanate film layer 11101 located in the middle is the same, so as to ensure that the area of ​​the strontium titanate dielectric layer 1110 close to the first electrode layer 110 and the area close to the second electrode layer 112 both achieve a balanced gradient design, thereby improving product quality.

[0112] Among them, the Sr / (Sr+Ti) ratio at each point in the strontium titanate film layer 11101 can be equal, that is, in each atomic layer deposition process, the flow rate of the Sr precursor and the Ti precursor remains constant. In this way, each layer of the strontium titanate film layer 11101 can be formed in sequence using existing equipment, without the need to re-develop the equipment, thereby reducing research and development costs.

[0113] It should be understood that the Sr / (Sr+Ti) ratio design between each strontium titanate film layer 11101 in the strontium titanate dielectric layer 1110 can be designed according to formula (1) and formula (2) mentioned in Example 1, wherein, in this Example 2, the parameter C mentioned in formula (1) and formula (2) is the ratio of Sr / (Sr+Ti) in the middle strontium titanate film layer 11101, and the parameter D is the distance between the center of the other film layers and the center of the middle strontium titanate film layer 11101.

[0114] In an alternative embodiment, reference Fig.13As shown, the dielectric layer 111 of the capacitor 11 may include a first titanium oxide dielectric layer 1111 and a second titanium oxide dielectric layer 1112 in addition to the aforementioned strontium titanate dielectric layer 1110. The first titanium oxide dielectric layer 1111 is formed between the first electrode layer 110 and the strontium titanate dielectric layer 1110 and the strontium titanate film layer 11101, and the second titanium oxide dielectric layer 1112 is formed between the second electrode layer 112 and the strontium titanate dielectric layer 1110. A first titanium oxide dielectric layer 1111 and a second titanium oxide dielectric layer 1112 are formed on both sides, and a gradient design of the dielectric layer 111 is further realized, that is, compared with the middle strontium titanate film layer 11101, the film layers located on the outermost sides of the dielectric layer 111 do not contain Sr, so as to form the first titanium oxide dielectric layer 1111 and the second titanium oxide dielectric layer 1112. In this way, the uniformity of the outermost surfaces of the dielectric layer 111 in the capacitor 11 can be ensured, so that it has low leakage performance.

[0115] In addition, when the first electrode layer 110 and the second electrode layer 112 of the present embodiment include the ruthenium element film layer 11a mentioned in the aforementioned embodiment 1, the first titanium oxide dielectric layer 1111 can be in contact with the ruthenium element film layer 11a of the first electrode layer 110, and the second titanium oxide dielectric layer 1112 can be in contact with the ruthenium element film layer 11a of the second electrode layer 112. The ruthenium element film layer 11a can cause the first titanium oxide dielectric layer 1111 and the second titanium oxide dielectric layer 1112 to contact with it to form a rutile structure, thereby reducing leakage and increasing the K value, so that the K value of the entire dielectric layer 111 in the first electrode layer 110 and the second electrode layer 112 first decreases and then increases from the middle to both sides, the dielectric constant is mainly increased in the middle and the boundary, and the area between the middle and the boundary mainly provides the function of reducing leakage.

[0116] In another alternative embodiment, reference Fig.14 As shown, the dielectric layer 111 of the capacitor 11 may include a first aluminum titanate dielectric layer 1113 and a second aluminum titanate dielectric layer 1114 in addition to the aforementioned strontium titanate dielectric layer 1110. The first aluminum titanate dielectric layer 1113 is formed between the first electrode layer 110 and the strontium titanate dielectric layer 1110, and the second aluminum titanate dielectric layer 1114 is formed between the second electrode layer 112 and the strontium titanate dielectric layer 1110.

[0117] For example, the first aluminum titanate dielectric layer 1113 can be in contact with the ruthenium element film layer 11a of the first electrode layer 110, and the second aluminum titanate dielectric layer 1114 can be in contact with the ruthenium element film layer 11a of the second electrode layer 112. This design can increase the K value while also increasing the CBO (conduction band offset) to further reduce leakage.

[0118] It should be noted that, except for the aforementioned differences between the second embodiment and the first embodiment, the rest of the design of the second embodiment can refer to the contents of the first embodiment and will not be repeated here.

[0119] Embodiment 3

[0120] The disclosed embodiments further provide a method for manufacturing a memory, which can be used to manufacture the memory provided by the aforementioned embodiments. The detailed description of the memory can refer to the aforementioned embodiments and will not be repeated here.

[0121] Among them, combined Figures 1 to 25 The manufacturing method of the memory may at least include step S100, step S200, step S300 and step S400.

[0122] In step S100, a substrate 10 is provided. For example, a semiconductor base 100 may be provided first, and then an insulating isolation layer 101 may be formed on the semiconductor base 100. Figures 2 to 5 The semiconductor substrate 100 may be a silicon substrate, the insulating isolation layer 101 may be SiO2, and the deposition thickness of the insulating isolation layer 101 may be (Amy).

[0123] In step S200, a first electrode layer 110 is formed on the substrate 10. For example, the first electrode layer 110 may be formed on a side of the insulating isolation layer 101 away from the semiconductor substrate 100, wherein the first electrode layer 110 may include a TiN layer and a RuO2 layer sequentially formed on a side of the insulating isolation layer 101 away from the semiconductor substrate 100.

[0124] In step S300, a dielectric layer 111 is formed on a side of the first electrode layer 110 away from the substrate 10. The dielectric layer 111 at least includes a strontium titanate dielectric layer 1110. From the center of the strontium titanate dielectric layer 1110 to the opposite sides of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases. For example, the strontium titanate dielectric layer 1110 can be formed on a side of the RuO2 layer away from the semiconductor substrate 100.

[0125] In an optional embodiment, step S300 specifically includes: using a primary atomic layer deposition process to deposit a strontium titanate material on a side of the first electrode layer 110 away from the substrate 10 to form the strontium titanate dielectric layer 1110, referring to Figure 7 As shown; wherein, in the primary atomic layer deposition process, by adjusting the flow rate of the Sr precursor and / or the Ti precursor, the ratio of Sr / (Sr+Ti) in the strontium titanate material first gradually increases and then gradually decreases according to the set rules.

[0126] In another optional embodiment, step S300 specifically includes: using N atomic layer deposition processes to form N layers of strontium titanate film layers 11101 stacked in sequence on the side of the first electrode layer 110 away from the substrate 10 to form the strontium titanate dielectric layer 1110, where N is a positive integer greater than or equal to 3, with reference to Figure 12 to Figure 14 As shown; wherein, in each of the atomic layer deposition processes, the flow rates of the Sr precursor and the Ti precursor may be substantially constant, that is, within an error range.

[0127] In step S400, a second electrode layer 112 may be formed on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110 to form a capacitor. The second electrode layer 112 may include a RuO2 layer and a TiN layer sequentially formed on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110.

[0128] In an optional embodiment, before step S300 and after step S200, the manufacturing method further includes: forming a first titanium oxide dielectric layer 1111 on a side of the first electrode layer 110 away from the substrate 10; and, after step S300 and before step S400, the manufacturing method may further include: forming a second titanium oxide dielectric layer 1112 on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, such as Fig.13 shown.

[0129] In another optional embodiment, before step S300 and after step S200, the manufacturing method further includes: forming a first aluminum titanate dielectric layer 1113 on a side of the first electrode layer 110 away from the substrate 10; and, after step S300 and before step S400, the manufacturing method further includes: forming a second aluminum titanate dielectric layer 1114 on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, such as Fig.14 shown.

[0130] Among them, the step of forming a first aluminum titanate dielectric layer 1113 on the side of the first electrode layer 110 away from the substrate 10 may specifically include: forming a first titanium oxide dielectric layer 1111 on the side of the first electrode layer 110 away from the substrate 10, and then doping aluminum elements into the first titanium oxide dielectric layer 1111 to form the first aluminum titanate dielectric layer 1113; and the step of forming a second aluminum titanate dielectric layer 1114 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, including forming a second titanium oxide dielectric layer 1112 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, and then doping aluminum elements into the second titanium oxide dielectric layer 1112 to form a second aluminum titanate dielectric layer 1114.

[0131] It should be understood that aluminum elements can be doped in the boundary surface of the first titanium oxide dielectric layer 1111 toward the first electrode layer 110 to form a first aluminum titanate dielectric layer 1113, and can also expand inward by a certain space. Similarly, aluminum elements can also be doped in the boundary surface of the second titanium oxide dielectric layer 1112 toward the second electrode layer 112 to form a second aluminum titanate dielectric layer 1114, and can also expand inward by a certain space.

[0132] Before step S300 and after step S200, the manufacturing method further includes: forming an interlayer dielectric material film 15a on a side of the first electrode layer 110 away from the substrate 10, such as Fig.15 As shown; a through hole 150 exposing a portion of the first electrode layer 110 is formed on the interlayer dielectric material film 15a using a patterning process to form an interlayer dielectric layer 15.

[0133] For example, a photoresist layer may be formed on the side of the interlayer dielectric material film 15a away from the first electrode layer 110, and then the photoresist layer is exposed and developed to form the first photoresist mask layer 19. Fig.16 Afterwards, the interlayer dielectric material film 15a is etched using the first photoresist mask layer 19 to form a through hole 150, and finally, the first photoresist mask layer 19 is removed, as shown Fig.17 shown.

[0134] It should be understood that at least a portion of the strontium titanate dielectric layer 1110 is located in the through hole 150 and contacts the first electrode layer 110 .

[0135] The step of sequentially forming the strontium titanate dielectric layer 1110 and the second electrode layer 112 on the side of the first electrode layer 110 away from the substrate 10 may specifically include:

[0136] After forming the interlayer dielectric layer 15, a dielectric material film (strontium titanate dielectric material film) 111a and a second electrode material film 112a are sequentially formed in the through hole 150 and covering the interlayer dielectric layer 15. Fig.18 Afterwards, the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a covering the interlayer dielectric layer 15 are removed to form a strontium titanate dielectric layer 1110 and a second electrode layer 112, as shown in FIG. Fig. 20 shown.

[0137] For example, a photoresist layer may be first formed on the second electrode material film 112a, and the photoresist layer may be exposed and developed to form a second photoresist mask layer 20. Thereafter, the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a may be etched using the second photoresist mask layer 20 to remove portions of the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a covering the interlayer dielectric layer 15, thereby forming a strontium titanate dielectric layer 1110 and a second electrode layer 112. Fig.19 As shown, finally, the second photoresist mask layer 20 is removed, referring to Fig. 20 shown.

[0138] After step S400 , the manufacturing method further includes steps S500 , S600 , S700 and S800 .

[0139] In step S500, an insulating dielectric layer 12 and an etching stop layer 13 are sequentially formed on the side of the interlayer dielectric layer 15 and the second electrode layer 112 away from the substrate 10, such as Fig.21 For example, the material of the insulating dielectric layer 12 may be SiO2, and the material of the etch stop layer 13 may be SiN, but it is not limited thereto, and the materials of the insulating dielectric layer 12 and the etch stop layer 13 may also be selected according to actual conditions.

[0140] In step S600, a first via hole 21 and a second via hole 22 are formed. Fig.23 As shown, the orthographic projection of the first via hole 21 on the substrate 10 is located within the orthographic projection of the first electrode layer 110 on the substrate 10, and does not overlap with the orthographic projections of the second electrode layer 112 and the strontium titanate dielectric layer 1110 on the substrate 10. The first via hole 21 sequentially penetrates the insulating dielectric layer 12, the etch stop layer 13 and the interlayer dielectric layer 15, and exposes a portion of the first electrode layer 110. The orthographic projection of the second via hole 22 on the substrate 10 is located within the orthographic projection of the through hole 150 on the substrate 10. The second via hole 22 sequentially penetrates the insulating dielectric layer 12 and the etch stop layer 13, and exposes a portion of the second electrode layer 112.

[0141] For example, a photoresist layer may be first formed on the side of the etch stop layer 13 away from the insulating dielectric layer 12, and then the photoresist layer is exposed and developed to form a third photoresist mask layer 23. Fig. 22 As shown, the third photoresist mask layer 23 is then etched to form the first via hole 21 and the second via hole 22 mentioned above. Finally, the third photoresist mask layer 23 is removed. Fig.23 shown.

[0142] In step S700, a measuring electrode material film 14 is formed, and the measuring electrode material film 14 covers the surface of the etching stop layer 13 away from the insulating dielectric layer 12 and fills the first via hole 21 and the second via hole 22. Fig.24 For example, the material of the measuring electrode material film 14 may be TiN, but is not limited thereto and may also be other conductive materials.

[0143] In step S800, the measuring electrode material film 14 is patterned to form a first measuring electrode 14a and a second measuring electrode 14b. The first measuring electrode 14a and the second measuring electrode 14b both include a via conductive portion 140 and a measuring conductive portion 141. The measuring conductive portions 141 of the first measuring electrode 14a and the second measuring electrode 14b are arranged at intervals and are both formed on a side of the etching stop layer 13 away from the substrate 10. The measuring conductive portion 141 of the first measuring electrode 14a is the measuring electrode material film 14 filled in the first via hole 21, and the measuring conductive portion 141 of the second measuring electrode 14b is the measuring electrode material film 14 filled in the second via hole 22. Figure 5 shown.

[0144] For example, a photoresist layer may be first formed on the side of the measuring electrode material film 14 away from the etching stop layer 13, and then the photoresist layer is exposed and developed to form a fourth photoresist mask layer 24. Then, the measuring electrode material film 14 on the surface of the etching stop layer 13 is etched using the fourth photoresist mask layer 24. Fig.25 As shown, the measurement conductive portion 141 of the first measurement electrode 14a and the second measurement electrode 14b is formed. Finally, the fourth photoresist mask layer 24 is removed. Fig.25 shown.

[0145] After the first measuring electrode 14 a and the second measuring electrode 14 b are formed, an external measuring device may be connected to the first measuring electrode 14 a and the second measuring electrode 14 b to measure the performance of the capacitor.

[0146] It should be understood that after the performance of the capacitor is tested using the first measuring electrode 14a and the second measuring electrode 14b, the first measuring electrode 14a and the second measuring electrode 14b may be cut off when cutting the die, or may remain on the substrate 10, depending on the specific situation.

[0147] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0148] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0149] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A capacitor, characterized in that: include: a first electrode layer; a second electrode layer; as well as A strontium titanate dielectric layer is formed between the first electrode layer and the second electrode layer, wherein: In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases, One of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is close to the second electrode layer.

2. The capacitor according to claim 1, characterized in that The strontium titanate dielectric layer is a single-layer structure.

3. The capacitor according to claim 2, characterized in that In the strontium titanate dielectric layer: a surface close to the first electrode layer is defined as a first boundary surface, a surface close to the second electrode layer is defined as a second boundary surface, and the Sr content at the first boundary surface and the second boundary surface is 0.

4. The capacitor according to claim 1, characterized in that The strontium titanate dielectric layer is a multi-layer stacked structure, and the strontium titanate dielectric layer includes N layers of strontium titanate film layers stacked in sequence, where N is a positive integer greater than or equal to 3; Wherein, in a direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer decreases layer by layer.

5. The capacitor according to claim 4, characterized in that The Sr / (Sr+Ti) ratio is equal at every location in the strontium titanate film layer.

6. The capacitor according to claim 1, characterized in that In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases according to a linear relationship.

7. The capacitor according to claim 6, characterized in that The linear relationship is specifically: Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer, D is the distance in the strontium titanate dielectric layer away from the center of the strontium titanate dielectric layer, H is the thickness of the strontium titanate dielectric layer, and 0≤D≤H / 2.

8. The capacitor according to claim 1, characterized in that In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the reduction rate of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually increases.

9. The capacitor according to claim 8, characterized in that The ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer satisfies the following relationship: Wherein, C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer, D is the distance from the center of the strontium titanate dielectric layer, H is the thickness of the strontium titanate dielectric layer, and 0≤D≤H / 2.

10. The capacitor according to claim 1, characterized in that In the direction from the center of the strontium titanate dielectric layer to the opposite sides of the strontium titanate dielectric layer: the reduction rate of the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases.

11. The capacitor according to claim 1, characterized in that The Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer is greater than 50%.

12. The capacitor according to claim 11, characterized in that The thickness of the strontium titanate dielectric layer ranges from 5 nm to 7 nm, and the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer ranges from 60% to 65%.

13. The capacitor according to claim 1, characterized in that The capacitor further comprises: a first titanium oxide dielectric layer formed between the first electrode layer and the strontium titanate dielectric layer; A second titanium oxide dielectric layer is formed between the second electrode layer and the strontium titanate dielectric layer.

14. The capacitor according to claim 1, characterized in that The capacitor further comprises: a first aluminum titanate dielectric layer formed between the first electrode layer and the strontium titanate dielectric layer; A second aluminum titanate dielectric layer is formed between the second electrode layer and the strontium titanate dielectric layer.

15. The capacitor according to any one of claims 1 to 14, characterized in that The first electrode layer and the second electrode layer include a ruthenium element film layer, and the ruthenium element film layer is a metal ruthenium film layer or a ruthenium oxide film layer.

16. The capacitor according to claim 15, characterized in that The first electrode layer and the second electrode layer further include a titanium nitride film layer, and the titanium nitride film layer is formed on a side of the ruthenium element film layer away from the strontium titanate dielectric layer.

17. A memory, characterized in that: The invention comprises a substrate and the capacitor according to any one of claims 1 to 16, wherein the capacitor is formed on the substrate.

18. The memory according to claim 17, characterized in that: The orthographic projection of the second electrode layer on the first electrode layer overlaps with the orthographic projection of the strontium titanate dielectric layer on the first electrode layer, and the orthographic projections of the second electrode layer and the strontium titanate dielectric layer on the substrate are located in the middle area of ​​the orthographic projection of the first electrode layer on the substrate, and the memory further includes: an insulating dielectric layer, covering an edge region of the first electrode layer and the second electrode layer; an etch stop layer, formed on a side of the insulating dielectric layer away from the substrate; and A first measuring electrode and a second measuring electrode are arranged at intervals, and the first measuring electrode and the second measuring electrode both include a via conductive portion and a measuring conductive portion connected to each other, wherein: The measurement conductive parts of the first measurement electrode and the second measurement electrode are formed on a side of the etch stop layer away from the substrate. The orthographic projection of the via conductive portion of the first measuring electrode on the substrate is located within the orthographic projection of the edge region of the first electrode layer on the substrate, and the via conductive portion of the first measuring electrode sequentially penetrates the etching stop layer and the insulating dielectric layer and contacts the edge region of the first electrode layer; The orthographic projection of the via conductive portion of the second measuring electrode on the substrate is located within the orthographic projection of the second electrode layer on the substrate. The via conductive portion of the second measuring electrode sequentially penetrates the etching stop layer and the insulating dielectric layer and contacts the second electrode layer.

19. The memory according to claim 18, characterized in that: The memory further includes an interlayer dielectric layer, the interlayer dielectric layer is formed between the first electrode layer and the insulating dielectric layer, and the interlayer dielectric layer has a through hole to expose a portion of the first electrode layer; wherein, The strontium titanate dielectric layer comprises a middle portion and an edge portion arranged around the middle portion, wherein the middle portion is formed in the through hole and contacts the first electrode layer, and the edge portion overlaps a surface of the interlayer dielectric layer away from the first electrode layer; The via conductive portion of the first measuring electrode penetrates the etching stop layer and the insulating dielectric layer, and also penetrates the interlayer dielectric layer to contact the edge region of the first electrode layer; The orthographic projection of the via-hole conductive portion of the second measuring electrode on the substrate is located within the orthographic projection of the through hole on the substrate.

20. The memory according to claim 19, characterized in that A plurality of via conductive portions are provided in the first measuring electrode and the second measuring electrode, and are arranged at equal intervals around the axis of the through hole.

21. The memory according to claim 17, characterized in that: The substrate includes a semiconductor base and an insulating isolation layer, and the insulating isolation layer is formed between the first electrode layer and the semiconductor base.

22. A method for manufacturing a memory, characterized in that: The manufacturing method may include: providing a substrate; forming a first electrode layer on the substrate; A strontium titanate dielectric layer is formed on a side of the first electrode layer away from the substrate, and in a direction from the center of the strontium titanate dielectric layer to two opposite sides of the strontium titanate dielectric layer: the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases, and one of the two opposite sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is away from the first electrode layer; A second electrode layer is formed on a side of the strontium titanate dielectric layer away from the first electrode layer to form a capacitor.

23. The manufacturing method according to claim 22, characterized in that: The step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate comprises: Depositing a strontium titanate material on a side of the first electrode layer away from the substrate using a primary atomic layer deposition process to form the strontium titanate dielectric layer; In the primary atomic layer deposition process, the flow rate of the Sr precursor and / or the Ti precursor is adjusted so that the ratio of Sr / (Sr+Ti) in the strontium titanate material gradually increases and then gradually decreases according to a set rule.

24. The manufacturing method according to claim 22, characterized in that: The step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate comprises: N layers of strontium titanate film layers stacked in sequence are formed on a side of the first electrode layer away from the substrate by using N atomic layer deposition processes to form the strontium titanate dielectric layer, where N is a positive integer greater than or equal to 3.

25. The manufacturing method according to claim 22, characterized in that: Before the step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming a first titanium oxide dielectric layer on a side of the first electrode layer away from the substrate; and Before the step of forming the second electrode layer on the side of the strontium titanate dielectric layer away from the first electrode layer, the manufacturing method further comprises: forming a second titanium oxide dielectric layer on the side of the strontium titanate dielectric layer away from the first electrode layer.

26. The manufacturing method according to claim 22, characterized in that: Before the step of forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming a first aluminum titanate dielectric layer on a side of the first electrode layer away from the substrate; and Before the step of forming the second electrode layer on the side of the strontium titanate dielectric layer away from the first electrode layer, the manufacturing method further comprises: forming a second aluminum titanate dielectric layer on the side of the strontium titanate dielectric layer away from the first electrode layer.

27. The manufacturing method according to claim 26, characterized in that: The step of forming a first aluminum titanate dielectric layer on a side of the first electrode layer away from the substrate comprises: forming a first titanium oxide dielectric layer on a side of the first electrode layer away from the substrate, and then doping aluminum into the first titanium oxide dielectric layer to form the first aluminum titanate dielectric layer; and The step of forming a second aluminum titanate dielectric layer on a side of the strontium titanate dielectric layer away from the first electrode layer includes forming a second titanium oxide dielectric layer on a side of the strontium titanate dielectric layer away from the first electrode layer, and then doping aluminum elements into the second titanium oxide dielectric layer to form the second aluminum titanate dielectric layer.

28. The manufacturing method according to claim 22, characterized in that: Before the step of forming a strontium titanate dielectric layer on the side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming an interlayer dielectric material film on the side of the first electrode layer away from the substrate; Forming a through hole exposing the middle area of ​​the first electrode layer on the interlayer dielectric material film by a patterning process to form an interlayer dielectric layer; Wherein, at least a portion of the strontium titanate dielectric layer is located in the through hole and contacts the first electrode layer.

29. The manufacturing method according to claim 28, characterized in that: The step of sequentially forming a strontium titanate dielectric layer and a second electrode layer on a side of the first electrode layer away from the substrate comprises: After forming the interlayer dielectric layer, sequentially forming a strontium titanate dielectric material film and a second electrode material film located in the through hole and covering the interlayer dielectric layer; The portions of the strontium titanate dielectric material film and the second electrode material film covering the interlayer dielectric layer are removed to form a strontium titanate dielectric layer and a second electrode layer.

30. The manufacturing method according to claim 29, characterized in that: After the step of sequentially forming a strontium titanate dielectric layer and a second electrode layer on a side of the first electrode layer away from the substrate, the manufacturing method further comprises: forming an insulating dielectric layer and an etching stop layer in sequence on the side of the interlayer dielectric layer and the second electrode layer away from the substrate; A first via hole and a second via hole are formed, wherein the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the edge region of the first electrode layer on the substrate, and does not overlap with the orthographic projections of the second electrode layer and the strontium titanate dielectric layer on the substrate, the first via hole sequentially penetrates the insulating dielectric layer, the etch stop layer and the interlayer dielectric layer, and exposes a portion of the first electrode layer, the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the through hole on the substrate, the second via hole sequentially penetrates the insulating dielectric layer and the etch stop layer, and exposes a portion of the second electrode layer; forming a measuring electrode material film, wherein the measuring electrode material film covers the surface of the etching stop layer away from the insulating dielectric layer and fills the first via hole and the second via hole; The measuring electrode material film is patterned to form a first measuring electrode and a second measuring electrode, wherein the first measuring electrode and the second measuring electrode both include a via conductive portion and a measuring conductive portion, the measuring conductive portions of the first measuring electrode and the second measuring electrode are spaced apart and are both formed on a side of the etch stop layer away from the substrate, the measuring conductive portion of the first measuring electrode is a measuring electrode material film filled in the first via hole, and the measuring conductive portion of the second measuring electrode is a measuring electrode material film filled in the second via hole.

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