Laminated structure and thin film transistor

Abstract

A laminated structure comprising a crystalline oxide semiconductor film having I n as the main component and an insulating film laminated so as to form an interface with the crystalline oxide semiconductor film, the insulating film having a film thickness from the interface to a distance substantially equal to the film thickness of the crystalline oxide semiconductor film, and a region satisfying the following formula (1): 1.25 < = (average value of A / B) < = 1.75 (1). (In the formula, A represents the number of oxygen atoms. And B represents the number of cation atoms present by bonding to oxygen atoms. And the cation atoms are cation atom species contained in the laminated structure in an amount of 1 at% or more.)

Description

Technical Field

[0001] The invention relates to a stacked structure and a thin film transistor. Background Art

[0002] Thin film transistors (TFTs) using an amorphous oxide semiconductor for a channel layer are widely known (see Patent Document 1). However, since the mobility of such TFTs is relatively low, improvement is required.

[0003] As a TFT that can obtain higher mobility characteristics than a TFT that uses an amorphous oxide semiconductor for a channel layer, a TFT that uses a crystalline oxide thin film for a channel layer is known (for example, refer to Patent Document 2).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 5118810

[0007] Patent Document 2: International Publication No. 2013 / 035335 Summary of the invention

[0008] However, in the technology of Patent Document 2, for example, when used in an exposure environment, the threshold voltage (Vth) may fluctuate, and a problem may arise in terms of reliability.

[0009] Therefore, in the conventional TFT using a crystalline oxide semiconductor film in the channel layer, there is room for improvement in achieving both improvement in mobility and reliability of the TFT.

[0010] An object of the present invention is to provide a stacked structure that exhibits good mobility and can achieve high reliability when applied to a TFT, and also to provide a thin film transistor having the stacked structure.

[0011] According to the present invention, the following stacked structure and the like are provided.

[0012] 1. A stacked structure comprising a crystalline oxide semiconductor film having In as a main component and an insulating film stacked to form an interface with the crystalline oxide semiconductor film,

[0013] The insulating film has a region satisfying the following formula (1) in a film thickness ranging from the interface to a distance substantially equal to the film thickness of the crystalline oxide semiconductor film.

[0014] 1.25≤(average value of A / B)≤1.75 (1)

[0015] (In the formula, A is the number of oxygen atoms. B is the number of cation atoms bonded to oxygen atoms. The cation atoms are cation atom species contained in the stacked structure at 1 at % or more.)

[0016] 2. The stacked structure according to 1, wherein the crystalline oxide semiconductor film has a region satisfying the formula (1).

[0017] 3. In the multilayer structure described in 1 or 2, the insulating film is any one of an oxide film mainly composed of silicon (Si), a nitride film mainly composed of silicon (Si), or an oxynitride film mainly composed of silicon (Si).

[0018] 4. In the multilayer structure according to any one of 1 to 3, the insulating film is an oxide film containing silicon (Si) as a main component.

[0019] 5. In the stacked structure according to any one of 1 to 4, the crystalline oxide semiconductor film further contains Ga.

[0020] 6. In the stacked structure according to any one of 1 to 5, the crystalline oxide semiconductor film further contains one or more additional elements selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm and Yb.

[0021] 7. In the stacked structure according to any one of 1 to 6, an atomic ratio of In to all metal elements contained in the crystalline oxide semiconductor film ([In] / ([In]+[all metal elements other than In])×100) is 62 at % or more.

[0022] 8. In the stacked structure according to any one of 5 to 7, the atomic ratio of Ga to all metal elements contained in the crystalline oxide semiconductor film ([Ga] / ([Ga]+[all metal elements other than Ga])×100) is 30 at % or less.

[0023] 9. In the stacked structure described in any one of items 6 to 8, the total amount of the additive elements relative to the atomic ratio of all metal elements contained in the crystalline oxide semiconductor film ([total amount of additive elements] / ([total amount of additive elements]+[all metal elements other than additive elements])×100) is less than 10 at %.

[0024] 10. The stacked structure according to any one of 1 to 9, wherein the carrier concentration of the crystalline oxide semiconductor film is 1×10 18 cm -3 the following.

[0025] 11. The stacked structure according to any one of 1 to 10, wherein the crystalline oxide semiconductor film includes crystal grains of a bixbyite structure.

[0026] 12. A thin film transistor comprising the stacked structure according to any one of 1 to 11, having:

[0027] Channel layer;

[0028] a source electrode and a drain electrode respectively connected to the channel layer;

[0029] a gate electrode stacked on the channel layer via a gate insulating film,

[0030] the channel layer is the crystalline oxide semiconductor film,

[0031] The gate insulating film is the insulating film.

[0032] 13. The thin film transistor according to 12, which is a top-gate transistor.

[0033] 14. A semiconductor element using the multilayer structure according to any one of 1 to 11.

[0034] 15. A diode, a thin film transistor, a MOSFET or a MESFET using the semiconductor element described in 14.

[0035] 16. An electronic circuit comprising the diode, thin film transistor, MOSFET or MESFET according to 15.

[0036] 17. An electrical device, electronic device, vehicle or power machine, comprising the electronic circuit according to 16.

[0037] According to the present invention, it is possible to provide a stacked structure that exhibits good mobility and can obtain high reliability when applied to a TFT. In addition, it is possible to provide a thin film transistor having the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic cross-sectional view of a stacked structure according to an example of the present embodiment.

[0039] Figure 2 This is a TEM image in which the vicinity of the interface between the crystalline oxide semiconductor film and the insulating film is enlarged.

[0040] Figure 3 This is a schematic cross-sectional view of an example of a TFT according to this embodiment.

[0041] Figure 4 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0042] Figure 5 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0043] Figure 6 This is a schematic cross-sectional view of a TFT fabricated in the example.

[0044] Figure 7 This is an EDX spectrum of the stacked structures obtained in Example 1 and Comparative Example 1 obtained by EDX line analysis. DETAILED DESCRIPTION

[0045] Ordinal numbers such as "1st", "2nd" and "3rd" used in this specification are added to avoid confusion among components, and components for which no fixed order is described are not limited to the order of the numbers in the ordinal numbers.

[0046] In this specification and the like, the term "film" or "thin film" and the term "layer" can be used interchangeably as appropriate.

[0047] In the sintered body and the oxide thin film in this specification and the like, the term "compound" and the term "crystalline phase" can be used interchangeably as appropriate.

[0048] In this specification, the "oxide sintered body" may be simply referred to as a "sintered body".

[0049] In this specification, a "sputtering target" may be simply referred to as a "target".

[0050] In this specification, etc., "electrical connection" includes connection via "a substance having a certain electrical function". Here, "a substance having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "a substance having a certain electrical function" includes electrodes, wiring, switching elements (transistors, etc.), resistors, inductors, capacitors, and elements having various other functions.

[0051] In this specification, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms source and drain may be used interchangeably.

[0052] In the present specification, "x to y" represents a numerical range of "x or more and y or less." The upper limit value and the lower limit value described in the numerical range can be arbitrarily combined.

[0053] Furthermore, combinations of two or more of the aspects of the present invention described below also belong to aspects of the present invention.

[0054] 1.Layered structure

[0055] The stacked structure of this embodiment includes a crystalline oxide semiconductor film containing In as a main component and an insulating film stacked to form an interface with the crystalline oxide semiconductor film.

[0056] Figure 1 This is a schematic cross-sectional view of a stacked structure according to an example of the present embodiment.

[0057] The stacked structure 10 includes a crystalline oxide semiconductor film 11 and an insulating film 12 stacked to form an interface with the crystalline oxide semiconductor film 11 .

[0058] Figure 2 1 is a TEM image in which the vicinity of the interface between the crystalline oxide semiconductor film 11 and the insulating film 12 is magnified.

[0059] Figure 2 In the figure, S is the interface between the crystalline oxide semiconductor film 11 and the insulating film 12, and d1 is the film thickness of the crystalline oxide semiconductor film 11. The film thickness of the insulating film 12 from the interface S to a distance d2 that is substantially equal to the film thickness d1 of the crystalline oxide semiconductor film 11 is ( Figure 2 The film (shown by the dotted line in the middle) has a region satisfying the following formula (1). "Substantially equal distance" means an equal distance of ±5%, preferably ±3%, and more preferably ±1%.

[0060] 1.25≤(average value of A / B)≤1.75 (1)

[0061] In the above formula (1), A is the number of oxygen atoms, and B is the number of cationic atoms bonded to the oxygen atoms.

[0062] The cationic atom is a cationic atomic species contained in the stacked structure at 1 at % or more.

[0063] Typical examples of cation atoms that exist in combination with oxygen atoms include In, Ga, Si, B, Mg, Al, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ge, Sr, Y, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Cd, Sn, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, and W.

[0064] In each film, the number of oxygen atoms A and the number of cation atoms B bonded to oxygen atoms can be measured by energy dispersive X-ray analysis (EDX analysis). The method of measuring the number of atoms A and the number of atoms B by EDX analysis is described in detail in the Examples.

[0065] The expression "average value of A / B" in formula (1) means that the atomic number A of oxygen atoms and the atomic number B of cation atoms may vary in each film thickness portion of the crystalline oxide semiconductor film or the insulating film.

[0066] The insulating film 12 has a region satisfying the above formula (1) in the film thickness from the interface S to the distance d2, thereby improving the stability of the insulating film 12 and the crystalline oxide semiconductor film 11 connected thereto. Therefore, when the stacked structure having them is applied to a TFT, the threshold voltage (Vth) fluctuates less and the reliability is excellent.

[0067] The reason for achieving such an effect is not necessarily clear, but it is speculated that by making the insulating film have a region that satisfies formula (1), for example, when the TFT is driven in a high voltage stress environment in an exposure environment, the phenomenon in which the holes generated in the crystalline oxide semiconductor film 11 are transferred to the insulating film and the properties of the insulating film are degraded is suppressed.

[0068] The average value of A / B in the insulating film may be 1.25 or more, 1.4 or more, 1.45 or more, 1.48 or more, or 1.5 or less, and 1.75 or less, 1.7 or less, 1.64 or less, or 1.6 or less.

[0069] The average value of A / B in the insulating film is preferably 1.25 to 1.75, more preferably 1.4 to 1.75, more preferably 1.45 to 1.64, more preferably 1.48 to 1.6, and further preferably 1.5 to 1.6.

[0070] In one embodiment, the stacked structure has a region satisfying the formula (1) in the crystalline oxide semiconductor film 11 .

[0071] As a result, the stability of the insulating film 12 and the crystalline oxide semiconductor film 11 in contact therewith is further improved, so when a stacked structure including them is applied to a TFT, the threshold voltage (Vth) varies less and excellent reliability can be obtained.

[0072] The average value of A / B in the crystalline oxide semiconductor film may be 1.25 or more, 1.4 or more, 1.45 or more, 1.48 or more, or 1.5 or less, 1.78 or less, 1.75 or less, 1.6 or less, 1.56 or less, or 1.55 or less.

[0073] The average value of A / B in the crystalline oxide semiconductor film is preferably 1.25 to 1.75, more preferably 1.4 to 1.6, more preferably 1.45 to 1.56, and further preferably 1.45 to 1.55.

[0074] The region satisfying the formula (1) in the insulating film can be formed by performing surface treatment after the crystalline oxide semiconductor film is formed and / or during or after the insulating film is formed to suppress oxygen diffusion in each film. The specific surface treatment method is described in detail in the method for manufacturing a stacked structure.

[0075] (Crystalline Oxide Semiconductor Film)

[0076] The crystalline oxide semiconductor film 11 in this embodiment (hereinafter simply referred to as the crystalline oxide semiconductor film) contains In element as the main component. The main component means that the atomic ratio of In to all metal elements in the crystalline oxide semiconductor film ([In] / ([In]+[all metal elements other than In])×100) (atomic %: at%) is 50 at% or more. The atomic ratio of In is preferably 62 at% or more, preferably 70 at% or more, more preferably 80 at% or more, more preferably 84 at% or more, and further preferably 85 at% or more. If more than 50 at% of the total number of atoms of the metal elements constituting the crystalline oxide semiconductor film is In element, when the stacked structure of this embodiment is used for TFT, a sufficiently high mobility can be achieved.

[0077] The crystalline oxide semiconductor film may be composed of a single crystal oxide semiconductor or a polycrystalline oxide semiconductor. However, since it is difficult to form a uniform single crystal on a large-area substrate in many cases, it is preferably composed of a polycrystalline oxide semiconductor.

[0078] In one embodiment, the crystalline oxide semiconductor film may contain Ga in addition to In.

[0079] In the case where the crystalline oxide semiconductor film contains Ga, the atomic ratio of Ga to all metal elements in the crystalline oxide semiconductor film ([Ga] / ([Ga]+[all metal elements other than Ga])×100) (atomic %: at %) is preferably 30 at % or less, more preferably 20 at % or less, more preferably 16 at % or less, and further preferably 15 at % or less.

[0080] When the Ga element accounts for 30 at % or less of the total atomic number of metal elements constituting the crystalline oxide semiconductor film, when the multilayer structure of this embodiment is used for a TFT, sufficiently high mobility can be exhibited.

[0081] In addition to In, the crystalline oxide semiconductor film may also contain one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb and Bi.

[0082] In one embodiment, the crystalline oxide semiconductor film may contain, in addition to In, one or more additional elements Z selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm, and Yb.

[0083] In the case where the crystalline oxide semiconductor film contains an additive element Z, the atomic ratio of the total amount of the additive element Z to all metal elements in the crystalline oxide semiconductor film ([total amount of the additive element Z] / ([total amount of the additive element Z]+[all metal elements other than the additive element Z])×100) (atomic %: at%) is preferably 10 at% or less, more preferably 7.5 at% or less, and further preferably 5 at% or less.

[0084] When the multilayer structure of this embodiment is used for a TFT, if the total amount of the additional element Z in the total atomic number of metal elements constituting the crystalline oxide semiconductor film is 10 at % or less, sufficiently high mobility can be exhibited.

[0085] In this embodiment, the crystalline oxide semiconductor film may be substantially composed of only elements selected from In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanide elements), and O. Here, “substantially” means that the crystalline oxide semiconductor film having the stacked structure of this embodiment may contain other components within the range where the effect of the present invention brought about by the combination of In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O described above is produced.

[0086] In this embodiment, a more preferred first aspect of the crystalline oxide semiconductor film is that the metal element is composed of In and Ga, and the atomic ratio satisfies the following formula (11).

[0087] [Ga] / ([In]+[Ga])]<22at% (11)

[0088] In addition, as a metal element, F or H may be contained in addition to inevitable impurities and O. By setting the composition range as above, the In ratio becomes large, and even at a low temperature of annealing such as 300°C, Ga can be substituted to the In site and crystallized into a bixbyite structure. Furthermore, by adding Ga having a strong bonding force with oxygen, oxygen vacancies after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0089] In this embodiment, a more preferred second scheme of the crystalline oxide semiconductor film is composed of In as a metal element and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In is set to X, the atomic ratio satisfies the following formula (12).

[0090] [X] / ([In]+[X])]<15at% (12)

[0091] In addition, as a metal element, F or H may be contained in addition to inevitable impurities and O. By setting the composition range as described above, the In ratio becomes large, and even with low temperature annealing such as 300° C., it is possible to crystallize into a bixbyite structure in which X substitutes for the In site. Furthermore, by adding an element X having a strong bonding force with oxygen, oxygen vacancies after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0092] In this embodiment, a more preferred third scheme of the crystalline oxide semiconductor film is composed of In and Ga as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal elements other than In and Ga are set as the added element X, the atomic ratio satisfies the following formulas (13) and (14).

[0093] [Ga] / ([In]+[Ga]+[X])]<22.5at% (13)

[0094] [X] / ([In]+[Ga]+[X])]<8.0at% (14)

[0095] Furthermore, as a metal element, in addition to inevitable impurities and O, F or H may be contained.

[0096] By setting the composition range as described above, the In ratio becomes larger, and even with low temperature annealing at 300° C., it is possible to crystallize into a bixbyite structure in which Ga replaces the In site. In addition, by adding an additional element X having a strong bonding force with oxygen, oxygen vacancies after annealing can be further suppressed, and a stable film can be formed as a semiconductor.

[0097] In this embodiment, a more preferred fourth scheme of the crystalline oxide semiconductor film is composed of In and Sn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Sn is set as the element X, the atomic ratio satisfies the following formulas (15) and (16).

[0098] [Sn] / ([In]+[Sn]+[X])]<20at% (15)

[0099] [X] / ([In]+[Sn]+[X])]<8.0at% (16)

[0100] Furthermore, as a metal element, in addition to inevitable impurities and O, F or H may be contained.

[0101] By setting the composition range to this, the In ratio becomes larger, and even with low-temperature annealing at 300°C, it is possible to crystallize into a bixbyite structure in which Sn replaces the In site. Sn has a large ion radius and a large overlap with the In orbital, so it is possible to maintain a high mobility. And by adding an additional element X that has a strong bonding force with oxygen, oxygen vacancies after annealing can be further suppressed, forming a stable film as a semiconductor.

[0102] In this embodiment, a more preferred fifth embodiment of the crystalline oxide semiconductor film is composed of In and Zn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Zn is set as the element X, the atomic ratio satisfies the following formulas (17) and (18).

[0103] [Zn] / ([In]+[Zn]+[X])]<12at% (17)

[0104] [X] / ([In]+[Zn]+[X])]<8.0at% (18)

[0105] Furthermore, as a metal element, in addition to inevitable impurities and O, F or H may be contained.

[0106] By setting the composition range as described above, the In ratio becomes larger, and even with low-temperature annealing at 300°C, it is possible to crystallize into a bixbyite structure in which Zn replaces the In site. By adding Zn, the film immediately after film formation can be made amorphous, and when semiconductor patterning is performed using acid during TFT production, processing can be performed without residue. Furthermore, by adding an additional element X that has a strong bonding force with oxygen, oxygen vacancies after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0107] The content (atomic ratio) of each metal element in the crystalline oxide semiconductor film can be determined by measuring the amount of each element by ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence) measurement. In ICP measurement, an inductively coupled plasma optical emission spectrometer (ICP-OES, manufactured by Agilent) can be used. In XRF measurement, a thin film fluorescence X-ray spectrometer (AZX400, manufactured by Rigaku Corporation) can be used.

[0108] The content (atomic ratio) of each metal element in the crystalline oxide semiconductor film can be analyzed by TEM-EDS measurement using an electron microscope, ICP measurement using an inductively coupled plasma emission spectrometer, and SIMS analysis using a sector dynamic secondary ion mass spectrometer.

[0109] In one embodiment, the carrier concentration of the crystalline oxide semiconductor film is 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 16 cm -3 As a result, in the Id-Vg curve when the TFT is driven by applying Vd=0.1V, Vth is close to 0V, indicating good performance of the normally-off characteristic.

[0110] The carrier concentration was measured by the following method.

[0111] The crystalline oxide semiconductor film was cut into 1 cm squares, and electrodes were added at the four corners using In solder to make a Hall effect measurement element, and the carrier concentration was measured by performing AC Hall effect measurement at room temperature using ResiTest 8400 (manufactured by Toyo Technica Corporation).

[0112] The measurement conditions are as follows: As the measurement accuracy, the value of the electron carrier concentration when the F value is 0.9 or more and the absolute value of the Hall voltage phase is 170° to 180° is adopted.

[0113] Current value: 1×10 -12 ~1×10 -3 A

[0114] Magnetic field strength: 0.36T

[0115] The thickness of the crystalline oxide semiconductor film may be greater than 3 nm, greater than 5 nm, or greater than 8 nm, and may be less than 100 nm, less than 50 nm, less than 40 nm, less than 31 nm, less than 30 nm, or less than 20 nm.

[0116] Thus, a region satisfying Formula (1) can be stably formed in the crystalline oxide semiconductor film.

[0117] Furthermore, by setting the film thickness of the crystalline oxide semiconductor film to be equal to or greater than the above lower limit, high-quality crystals can be grown without being affected by the base during annealing and crystallization (during film formation of the crystalline oxide semiconductor film).

[0118] In this specification, the film thickness is measured based on a cross-sectional TEM observation image (sometimes referred to as a “cross-sectional TEM image”).

[0119] In one embodiment, electron beam diffraction of the crystalline oxide semiconductor film includes crystal grains of a bixbyite structure. Since the crystal grains of the bixbyite structure are cubic crystals with good symmetry, the decrease in TFT characteristics (mobility) can be suppressed even across the grain boundary.

[0120] Whether or not the crystal grains in the crystalline oxide semiconductor film have a bixbyite structure is evaluated by observing an electron beam diffraction pattern of a sample obtained by observing a cross-sectional TEM image.

[0121] Specifically, an electron microscope (JEOL "JEM-2800") was used to measure the diffraction pattern of the oxide thin film area observed in the cross-sectional TEM image. The electron beam was irradiated with an irradiation area of ​​about 100 nmφ and an acceleration voltage of 200 kV by limiting the field aperture, and the camera length was set to 2 m.

[0122] Furthermore, in order to identify the crystal structure, the electron beam diffraction pattern of the pyroxene structure of In2O3 was simulated using the electron beam diffraction simulation software ReciPro (free software ver4.641 (2019 / 03 / 04)). In the simulation, the crystal structure data of the pyroxene structure used ICSD (Inorganic Crystal Structure Database: Chemical Information Association) 14388, and the space group: Ia-3, lattice constant: Atomic coordinates In site (0.250, 0.250, 0.250), In site (0.466, 0.000, 0.250), O site (0.391, 0.156, 0.380).

[0123] Furthermore, the camera length was set to 2 m, and the simulation was carried out using 11 reciprocal lattice vectors (100), (111), (110), (211), (311), (221), (331), (210), (310), (321), and (230) as the directions of the incident electron beam.

[0124] The electron beam diffraction pattern of the oxide thin film was compared with the diffraction spot results of the obtained simulation patterns. When the pattern matched any of the 11 simulation patterns, it was determined that the oxide thin film contained crystal grains of a bixbyite structure.

[0125] The crystalline oxide semiconductor film preferably has crystal grains of a bixbyite structure, but as described above, when an electron beam diffraction pattern is confirmed in an oxide thin film region observed with an electron microscope, the oxide thin film can be regarded as a crystalline oxide semiconductor film.

[0126] (Insulation film)

[0127] The material forming the insulating film is not particularly limited, and any commonly used material can be selected, and a laminated film can be used. For example, SiO2, SiN x , silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, AlN. In addition, the oxidation number of each material may also be changed.

[0128] In one embodiment, the insulating film is any one of an oxide film mainly composed of silicon (Si), a nitride film mainly composed of silicon (Si), or an oxynitride film mainly composed of silicon (Si).

[0129] Thus, by the surface treatment step performed in the method for manufacturing the stacked structure described later, it is easy to appropriately control the ratio of cation atoms and oxygen atoms in the insulating film and the crystalline oxide semiconductor film, and a region satisfying the formula (1) can be stably obtained.

[0130] From the viewpoint of easy availability and stability of the insulating film, the insulating film is more preferably an oxide film containing silicon (Si) as a main component.

[0131] An oxide film with silicon (Si) as the main component means that the atomic ratio of silicon (Si) to all cationic atoms contained in the oxide film is greater than 90at%. A nitride film with silicon (Si) as the main component means that the atomic ratio of silicon (Si) to all cationic atoms contained in the nitride film is greater than 90at%. An oxynitride film with silicon (Si) as the main component means that the atomic ratio of silicon (Si) to all cationic atoms contained in the oxynitride film is greater than 90at%.

[0132] The thickness of the insulating film may be 50 nm or more, 98 nm or more, 100 nm or more, or 150 nm or more, and may be 500 nm or less, 300 nm or less, or 200 nm or less.

[0133] Thus, a region satisfying Formula (1) can be stably formed in the insulating film or the insulating film and the crystalline oxide semiconductor film.

[0134] Furthermore, by setting the film thickness of the crystalline oxide semiconductor film to be equal to or less than the upper limit value, a stable element shape can be obtained when the stacked structure of this embodiment is applied to a TFT.

[0135] The insulating film 12 may be a single-layer film or a laminated film. In the case of a laminated film, the appropriate film thickness described for the insulating film 12 is the film thickness of the laminated film as a whole. In addition, when a film is obtained in a surface treatment step in a method for manufacturing a laminated structure described later, it becomes integrated with the insulating film 12 and functions as a laminated film, i.e., as a gate insulating film 24 of a TFT.

[0136] 2. Method for manufacturing laminated structure

[0137] The stacked structure of this embodiment can be manufactured, for example, by forming an oxide thin film mainly composed of In oxide on a substrate, a buffer layer, an insulating layer, etc. constituting a lower layer of a TFT and performing a crystallization process to form a crystalline oxide semiconductor film (crystalline oxide semiconductor film formation process), and then forming an insulating film in contact with the crystalline oxide semiconductor film (insulating film film formation process). By performing a surface treatment between the formation of the crystalline oxide semiconductor film and the formation of the insulating film and / or during or after the formation of the insulating film, a region satisfying formula (1) can be formed in the insulating film and / or in the crystalline oxide semiconductor film.

[0138] The method for forming an oxide thin film mainly composed of In oxide is not particularly limited, and examples thereof include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, ALD, PLD, MO-CVD, ICP-CVD, sol-gel method, coating method, and atomized CVD.

[0139] When the film is formed by sputtering, the film may be formed by a device using a planar sputtering cathode or a device using a rotary sputtering cathode.

[0140] As an example of a method for forming an oxide thin film, the oxide thin film can be produced by forming a film by DC sputtering using a sputtering target including an oxide sintered body containing In oxide as a main component.

[0141] The atomic composition ratio of the oxide thin film obtained by sputtering reflects the atomic composition ratio of the oxide sintered body in the sputtering target. Therefore, it is preferable to form a film using a sputtering target including an oxide sintered body having the same atomic composition ratio as the desired oxide thin film.

[0142] In addition, after the oxide thin film is formed, heat treatment may be performed. The heat treatment process is not particularly limited, and a hot air furnace, an IR furnace, a lamp annealing device, a laser annealing device, a thermal plasma device, etc. may be used.

[0143] After annealing, plasma oxidation treatment using N2O or plasma oxidation treatment using O2 may be performed. The apparatus for plasma oxidation treatment is not particularly limited, and PE-CVD and the like may be mentioned.

[0144] The impurity metal of the target used in the sputtering method is preferably 500 ppm or less, more preferably 100 ppm or less. The content of the impurity metal in the target can be measured by ICP or SIMS, as with the crystalline oxide semiconductor film. The "impurities" contained in the target refer to elements that are mixed in the raw materials or manufacturing processes and are not intentionally added, and are trace elements that do not substantially affect the performance of the target and the semiconductor. "Impurity metals" refer to metal elements among the elements that are "impurities".

[0145] In the present embodiment, the sputtering target may be substantially composed of only In and an element selected from Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanide elements), and O. Here, "substantially" means that in addition to the above-mentioned In, the sputtering target may also contain other components within the range that the effect of the present invention brought about by the combination of Mg, Al, Si, Zn, Ga, Mo, Sn, Ln and O is produced.

[0146] Similar to the crystalline oxide semiconductor film having the stacked structure of the present invention described above, in the present embodiment, a more preferred first aspect of the sputtering target is an oxide in which the metal elements are In and Ga, and the atomic ratio satisfies the following formula (11).

[0147] [Ga] / ([In]+[Ga])]<22at% (11)

[0148] A more preferred second embodiment of the sputtering target is an oxide composed of In as a metal element and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In is set to X, the atomic ratio satisfies the following formula (12).

[0149] [X] / ([In]+[X])]<15at% (12)

[0150] A more preferred third embodiment of the sputtering target is an oxide composed of In and Ga as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Ga is set as the added element X, the atomic ratio satisfies the following formulas (13) and (14).

[0151] [Ga] / ([In]+[Ga]+[X])]<22.5at% (13)

[0152] [X] / ([In]+[Ga]+[X])]<8.0at% (14)

[0153] A more preferred fourth embodiment of the sputtering target is an oxide composed of In and Sn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Sn is set as element X, the atomic ratio satisfies the following formulas (15) and (16).

[0154] [Sn] / ([In]+[Sn]+[X])]<20at% (15)

[0155] [X] / ([In]+[Sn]+[X])]<8.0at% (16)

[0156] A more preferred fifth embodiment of the sputtering target is an oxide composed of In and Zn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Zn is set as element X, the atomic ratio satisfies the following formulas (17) and (18).

[0157] [Zn] / ([In]+[Zn]+[X])]<12at% (17)

[0158] [X] / ([In]+[Zn]+[X])]<8.0at% (18)

[0159] As a preferred embodiment of the sputtering target, the atomic ratio of In to all metal elements contained in the sputtering target ([In] / ([In]+[all metal elements other than In])×100) is 62 at % or more.

[0160] As a preferred embodiment of the sputtering target, the atomic ratio of Ga to all metal elements contained in the sputtering target ([Ga] / ([Ga]+[all metal elements other than Ga])×100) (atomic %: at %) is 30 at % or less.

[0161] As a preferred embodiment of the sputtering target, the total amount of the added element Z (one or more selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm and Yb) is less than 10 at% relative to the total metal elements contained in the sputtering target ([total amount of added elements] / ([total amount of added elements]+[total metal elements other than added elements])×100) (atomic %: at%).

[0162] The oxide thin film obtained by sputtering film formation using a sputtering target with indium oxide as the main component can be an amorphous oxide thin film. The amorphous oxide thin film is patterned into an island shape by photolithography, and heated to crystallize it before forming a protective film, thereby obtaining a crystalline oxide semiconductor film with a single crystal orientation on the surface crystal.

[0163] Below, with Figure 1 Each step will be described by taking the method for manufacturing the stacked structure shown as an example.

[0164] The stacked structure of the present embodiment can be manufactured, for example, by forming an oxide thin film mainly composed of In oxide on a substrate, a buffer layer, an insulating layer, etc. constituting the lower layer of the TFT, and then performing a crystallization treatment to form a crystalline oxide semiconductor film (a process of forming a crystalline oxide semiconductor film); and forming an insulating film in contact with the crystalline oxide semiconductor film and performing a heat treatment to form an insulating film (a process of forming an insulating film).

[0165] [Step of Forming Crystalline Oxide Semiconductor Film]

[0166] (Film formation of oxide thin films)

[0167] In the film forming step of the oxide thin film, the above-mentioned sputtering target is used, and one or more gases selected from the group consisting of argon and oxygen that are substantially free of impurity gases are used as sputtering gases to form an oxide thin film by sputtering. In this step, the sputtering target is preferably mounted on an RF magnetron sputtering device or a DC magnetron sputtering device for sputtering.

[0168] The sputtering gas "does not substantially contain impurity gases" means that, except for the introduction of adsorbed water accompanying the charging of the gas, and gases that cannot be removed (inevitable impurity gases) such as leakage or adsorbed gases in the chamber, no impurity gases other than the sputtering gas are actively introduced. If possible, it is preferred to exclude impurities from the gas (sputtering gas) introduced during sputtering film formation.

[0169] The proportion of the impurity gas in the sputtering gas is preferably 0.1 volume % or less, and more preferably 0.05 volume % or less. As long as the proportion of the impurity gas is 0.1 volume % or less, crystallization of the oxide thin film will proceed without any problem.

[0170] The purity of high-purity argon and high-purity oxygen, which are examples of sputtering gas, is preferably 99% by volume or more, more preferably 99.9% by volume or more, and even more preferably 99.99% by volume or more.

[0171] The gas introduced during sputtering film formation (sputtering gas) is not particularly limited, and examples thereof include argon, nitrogen, oxygen, water, hydrogen, or a mixed gas containing two or more of these gases.

[0172] As an example, the oxygen partial pressure in the mixed gas when using argon and oxygen is preferably greater than 0 volume % and less than 50 volume %, and more preferably greater than 0 volume % and less than 20 volume %. If the oxygen partial pressure exceeds 0 volume % and is less than 50 volume %, it is easy to crystallize and semiconductor when heated. By changing the oxygen partial pressure, the degree of oxidation of the oxide film, that is, the degree of crystallization, can be adjusted. The oxygen partial pressure can be appropriately selected as needed.

[0173] As an example, the water partial pressure in the mixed gas when using argon and water is preferably more than 0.03 volume % and less than 10 volume %, more preferably more than 0.03 volume % and less than 5 volume %. If the water partial pressure exceeds 0.03 volume % and is less than 5 volume %, it is easy to crystallize and semiconductorize when heated. In addition, a mixed gas of hydrogen and oxygen can also be used instead of water.

[0174] By heating the oxide thin film obtained by sputtering in a heat treatment process described later, crystals can be grown (for example, columnar crystals relative to the lower layer). By applying the crystalline oxide semiconductor film formed as described above to a small TFT, the electron carrier injection property is excellent during driving, and the result shows high mobility.

[0175] (Heat Treatment of Oxide Thin Films)

[0176] After the oxide thin film is formed, a heat treatment is performed. This heat treatment is sometimes called annealing. The annealing of the oxide thin film can be performed before or after the formation of the insulating film described later, but is preferably performed before the formation.

[0177] By performing annealing before forming the insulating film, oxygen and hydrogen diffuse during annealing to obtain columnar and high-quality crystals, and after forming the insulating film, a small TFT with a small interface electron trap level and high mobility can be obtained.

[0178] The temperature of the heat treatment of the oxide thin film is preferably 250°C to 500°C, more preferably 280°C to 470°C, and further preferably 300°C to 450°C.

[0179] If the heat treatment temperature after the oxide thin film is formed is 250°C or higher, the oxide thin film is easily crystallized. If the heat treatment temperature after the oxide thin film is formed is 500°C or lower, abnormal crystal growth and enlargement of crystal grains can be prevented, and the crystal grain size can be controlled to be small.

[0180] The heating time in the heat treatment step of the oxide thin film is preferably 0.1 hour to 5 hours, more preferably 0.3 hour to 3 hours, and even more preferably 0.5 hour to 2 hours.

[0181] Even if the heating time in the heat treatment process is less than 0.1 hours, the crystallization of the oxide thin film proceeds to some extent, but if it is more than 0.1 hours, the atomic diffusion in the oxide thin film is easy to proceed, and it is easy to stabilize after crystallization, so it is easy to obtain a stable crystalline oxide semiconductor film. If the heating time in the heat treatment process is less than 5 hours, the economic efficiency is excellent.

[0182] The "heating time" refers to the time (holding time) during which a predetermined maximum temperature is maintained during heat treatment.

[0183] The temperature increase rate in the heat treatment step of the oxide thin film is preferably 2° C. / minute to 40° C. / minute, more preferably 3° C. / minute to 20° C. / minute.

[0184] When the temperature increase rate in the heat treatment step of the oxide thin film is 2° C. / minute or more, the production efficiency of the oxide thin film is improved compared to a case where the temperature increase rate is less than 1° C. / minute.

[0185] When the temperature increase rate in the heat treatment step of the oxide thin film is 40° C. / min or less, the metal element diffuses uniformly during crystallization, and crystals in which the metal is not segregated at the grain boundaries can be formed.

[0186] In addition, the temperature rise rate in the heat treatment process is different from the value calculated based on the set temperature and set time of the furnace, and is the value obtained by dividing the actual temperature of the oxide film by the time. The actual temperature of the oxide film can be obtained by measuring the area within 1 cm of the oxide film in the furnace with a thermocouple, for example.

[0187] The heat treatment step of the oxide thin film is preferably performed in an atmosphere with a humidity of 10% or more at 25° C. By performing the heat treatment step in an atmosphere with a humidity of 10% or more, hydrogen and oxygen diffuse in the film during annealing, thereby promoting crystallization.

[0188] The heat treatment process of the oxide thin film is preferably performed after the patterning of the oxide thin film. By performing the heat treatment process after the patterning, the excess oxygen present in the film during film formation and the organic matter attached during patterning can be removed while promoting crystallization. As a result, a film with no organic matter, excess oxygen and fewer crystal defects in the crystal grains can be formed, and an oxide thin film with fewer electron traps and good conductive properties can be formed.

[0189] The crystal defects of the film after the heat treatment process of the oxide thin film can be evaluated by defect analysis such as cathode luminescence (CL). When there are many defects originating from oxygen, the luminescence of 680nm light is strongly detected. In order to obtain an oxide thin film with few electron traps and good conductive properties, it is necessary to adjust the film formation method and annealing conditions to obtain a film quality in which CL luminescence is as undetectable as possible.

[0190] In addition, the heat treatment process of the oxide thin film can also be performed multiple times. For example, the above-mentioned heat treatment process (first heat treatment process) can be performed after the patterning of the oxide thin film, and then after the TFT element is manufactured, a heat treatment process (second heat treatment process) is performed as the final process. The second heat treatment process is preferably performed at an annealing temperature higher than that of the first heat treatment process.

[0191] (Surface treatment process)

[0192] As a method for forming a region satisfying the above formula (1) in an insulating film, for example, a method of performing a surface treatment on the surface of a crystalline oxide semiconductor film before forming the insulating film and, if necessary, performing a heat treatment (annealing) on ​​the insulating film formed by the surface treatment. The above-mentioned surface treatment and the heat treatment (annealing) of the insulating film are sometimes collectively referred to as surface treatment.

[0193] By performing the above surface treatment, diffusion of oxygen in each of the crystalline oxide semiconductor film and the insulating film can be suppressed, and a stacked structure having a region satisfying the above formula (1) in the insulating film can be obtained.

[0194] Specifically, by performing surface treatment on the surface of the crystalline oxide semiconductor film, it is possible to suppress oxygen diffusion within the crystalline oxide semiconductor film and oxygen diffusion from the crystalline oxide semiconductor film to the side of the insulating film stacked at an interface with the crystalline oxide semiconductor film, thereby forming a stacked structure having a region satisfying the above formula (1) in the insulating film.

[0195] In addition, when a film is formed by surface treatment, by heat treating (annealing) the film, it is easier to suppress the diffusion of oxygen within the crystalline oxide semiconductor film and the diffusion of oxygen from the crystalline oxide semiconductor film to the insulating film side, and it is possible to stably manufacture a stacked structure having a region in the insulating film that satisfies the above formula (1).

[0196] In addition, in the case of forming a film by surface treatment, by heat treating (annealing) the film, oxygen diffusion within the insulating film and oxygen diffusion to the outside of the insulating film (for example, diffusion to the side of the crystalline oxide semiconductor film or to the side of the film or layer opposite to the crystalline oxide semiconductor film) can be suppressed, and a stacked structure having a region satisfying the above formula (1) can be formed in the insulating film.

[0197] Preferable conditions for heat treatment (annealing treatment) of the insulating film formed by the surface treatment are the same as those for heat treatment of the insulating film described in the step of forming the insulating film.

[0198] Furthermore, by performing the above-described surface treatment, oxygen diffusion can be suppressed not only in the insulating film but also in the crystalline oxide semiconductor film, thereby obtaining a stacked structure having a region satisfying the above-described formula (1) in the crystalline oxide semiconductor film.

[0199] As a method for forming a region satisfying the above formula (1) in an insulating film, a method of forming a film on the surface of a crystalline oxide semiconductor film by sputtering or CVD (chemical vapor deposition) as a surface treatment and heat treating (annealing) the formed film can be typically exemplified.

[0200] In addition, as another method for forming a region satisfying the above-mentioned formula (1) in an insulating film, for example, a method of performing plasma oxidation treatment using N 2 O on the surface of a crystalline oxide semiconductor film can be cited.

[0201] The film formed on the surface of the crystalline oxide semiconductor film by the surface treatment is not particularly limited as long as the characteristics of the crystalline oxide semiconductor film are not impaired, and for example, the same materials as those described as the material for forming the insulating film can be used.

[0202] From the viewpoint of production efficiency and stability of the laminate, it is preferable to form a film made of the same material as the insulating film 12 .

[0203] When the surface treatment is performed using a material for forming an insulating film, a laminated film of a film formed by the surface treatment and a film formed in a subsequent insulating film forming step can constitute an insulating film of a TFT.

[0204] The surface treatment method is not particularly limited, and examples thereof include film formation treatment using sputtering, PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, sol-gel method, coating method, atomized CVD, and the like.

[0205] When the surface treatment is performed by sputtering film formation, the sputtering film formation can be performed by the same method and conditions as those for the film formation of the insulating film by sputtering film formation described in the insulating film forming step.

[0206] When the surface treatment is performed by CVD (chemical vapor deposition) film formation, the temperature during the CVD treatment is preferably 240°C to 500°C, more preferably 280°C to 470°C, and further preferably 300°C to 450°C.

[0207] When the temperature during the CVD process is within the above range, a region satisfying the above formula (1) can be stably formed in the insulating film.

[0208] In addition, the temperature during CVD processing refers to the temperature of the substrate in the CVD apparatus.

[0209] Furthermore, when the film is formed at a temperature of 240° C. or higher and 450° C. or lower during the CVD process, the subsequent heat treatment (annealing) step may be omitted.

[0210] The thickness of the film formed by the surface treatment may be 1 nm or more and less than 50 nm, may be 3 nm to 40 nm, may be 4 nm to 35 nm, or may be 7 nm to 25 nm.

[0211] When the film thickness of the film formed by the surface treatment is within the above range, a region satisfying the above formula (1) can be stably formed in the insulating film.

[0212] The method for forming a region satisfying the above-mentioned formula (1) in an insulating film or in an insulating film and a crystalline oxide semiconductor film is not limited to the above-mentioned method using surface treatment (surface treatment of the crystalline oxide semiconductor film and heat treatment of the insulating film). For example, a method of performing plasma oxidation treatment of the surface of the crystalline oxide semiconductor film using N2O (hereinafter sometimes referred to as "N2O plasma treatment") can be used.

[0213] Regarding the N2O plasma treatment, specifically, after the surface of the crystalline oxide semiconductor film is subjected to plasma oxidation treatment using N2O, an insulating film is directly formed on the plasma treated surface of the crystalline oxide semiconductor film. As a result, the oxidation state of the compound in the film of the crystalline oxide semiconductor film and in the film of the insulating film stacked with the crystalline oxide semiconductor to form an interface or the oxygen bonding state in each film can be changed. As a result, it is possible to suppress, for example, oxygen diffusion from the crystalline oxide semiconductor film to the insulating film side, oxygen diffusion from the insulating film to the crystalline oxide semiconductor side or to other film or layer sides, and to form a stacked structure having a region satisfying the above formula (1) in the insulating film.

[0214] The apparatus for N 2 O plasma treatment is not particularly limited, and for example, PE-CVD or the like can be used.

[0215] For example, N2O plasma treatment is preferably performed by introducing N2O gas in a range of 100 to 10000 Pa and performing plasma treatment in a range of 5 to 500 W output for 10 to 1000 seconds.

[0216] When a region satisfying the above formula (1) is formed in the insulating film by N 2 O plasma treatment, it is preferable not to perform heat treatment (annealing) on ​​the crystalline oxide semiconductor film before forming the insulating film after the plasma oxidation treatment.

[0217] By directly forming an insulating film on the plasma-treated surface of the crystalline oxide semiconductor film without subjecting the crystalline oxide semiconductor film to plasma oxidation treatment using N2O to heat treatment (annealing), a stacked structure having a region satisfying the above formula (1) can be stably formed in the insulating film.

[0218] In addition, when a region satisfying the above-mentioned formula (1) is formed in the insulating film by N 2 O plasma treatment, the film may not be formed with respect to the crystalline oxide semiconductor film as described above.

[0219] In addition, when a region satisfying the above formula (1) is formed in the insulating film by N2O plasma treatment, it is not necessary to perform heat treatment (annealing) of the insulating film from the viewpoint of forming the region satisfying the above formula (1) in the insulating film.

[0220] [Insulating film forming step]

[0221] The insulating film may be a film formed by the surface treatment process or a film formed on the film formed by the surface treatment process. The film formed by the surface treatment process and the insulating film formed on the film function as the gate insulating film 24 in the TFT.

[0222] (Film formation of insulating film)

[0223] The insulating film forming method is not particularly limited. Examples of the production method include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, sol-gel method, coating method, atomized CVD, etc. In addition, as a gas type for PE-CVD, tetraethoxysilane (TEOS) can be used in addition to silane (SiH4).

[0224] When the insulating film is formed by sputtering, for example, a compound containing silicon (Si) (such as SiO2, SiN2) can be used as a sputtering target.x As the sputtering gas, similar to the film formation of the above-mentioned oxide thin film, it is preferred to use one or more gases selected from the group consisting of argon and oxygen that are substantially free of impurity gases as the sputtering gas.

[0225] The appropriate ranges of the ratio of the impurity gas in the sputtering gas and the purity of the high-purity argon and high-purity oxygen in the sputtering gas are the same as those in the above-mentioned film formation of the oxide thin film.

[0226] The gas introduced during sputtering film formation (sputtering gas) is not particularly limited, and examples thereof include argon, nitrogen, oxygen, water, hydrogen, or a mixed gas containing two or more of these gases.

[0227] As an example, the oxygen partial pressure in the mixed gas when using argon and oxygen is preferably greater than 0 volume % and less than 50 volume %, and more preferably greater than 0 volume % and less than 40 volume %. By changing the oxygen partial pressure, the atomic ratio of silicon (Si) contained in the insulating film relative to all atoms can be adjusted. The oxygen partial pressure can be appropriately selected as needed.

[0228] (Heat treatment of insulating film)

[0229] After forming the insulating film, heat treatment (annealing) is performed. By performing heat treatment (annealing) after forming the insulating film, a region satisfying the above-mentioned formula (1) can be stably formed in the insulating film.

[0230] In addition, by performing heat treatment (annealing treatment) after the formation of the insulating film, hydrogen contained in the insulating film diffuses into the crystalline oxide semiconductor film, and crystal defects existing on the surface of the crystalline oxide semiconductor film are terminated with hydroxyl groups, resulting in a crystalline oxide semiconductor film with few electron traps and good conductive properties.

[0231] The temperature of the heat treatment after the insulating film is formed is preferably 250° C. to 500° C., more preferably 280° C. to 470° C., and further preferably 300° C. to 450° C.

[0232] When the heat treatment temperature after the insulating film is formed is within the above range, a region satisfying the above formula (1) can be stably formed in the insulating film.

[0233] The heating time in the heat treatment step after the insulating film is formed is preferably 0.1 hour to 5 hours, more preferably 0.3 hour to 3 hours, and even more preferably 0.5 hour to 2 hours.

[0234] When the heating time in the heat treatment step after the formation of the insulating film is 0.1 hours or longer, a region satisfying the above-mentioned formula (1) can be stably formed in the insulating film.

[0235] When the heating time in the heat treatment step after the insulating film is formed is 5 hours or less, excellent economic efficiency is achieved.

[0236] The temperature increase rate in the heat treatment step after the insulating film is formed is preferably 2° C. / minute to 40° C. / minute, more preferably 3° C. / minute to 20° C. / minute.

[0237] When the temperature increase rate in the heat treatment step after the formation of the insulating film is within the above range, a region satisfying the above formula (1) can be stably formed in the insulating film.

[0238] The method for determining the temperature increase rate in the heat treatment step after the insulating film is formed is the same as the method for determining the temperature increase rate in the heat treatment step of the oxide film described above.

[0239] The heat treatment step after forming the insulating film is preferably performed in an atmosphere with a humidity of 10% or more at 25° C. By setting the humidity in the atmosphere to be 10% or more during the heat treatment step, a region satisfying the above formula (1) can be stably formed in the insulating film.

[0240] The above-mentioned insulating film forming step and insulating film heat treatment step may be performed only once or multiple times. In this case, the film thickness of the film formed in each film forming step may be the same or different.

[0241] 3. Thin Film Transistor (TFT)

[0242] The TFT of this embodiment includes the above-mentioned stacked structure of the present invention.

[0243] In one embodiment, the TFT has a buffer layer, a channel layer stacked on the buffer layer, a source electrode and a drain electrode respectively connected to the channel layer, and a gate electrode stacked on the channel layer via a gate insulating film, the channel layer is a crystalline oxide semiconductor film included in the stacked structure of the present invention, and the gate insulating film is an insulating film included in the stacked structure of the present invention.

[0244] In the following Figure 3 and Figure 4 , the following structure is shown: the two end sides of the channel layer, that is, the vicinity of the region connecting the source electrode and the drain electrode is the low resistance region A of the crystalline oxide semiconductor film, and the region in contact with the lower surface of the gate insulating film is the high resistance region B.

[0245] That is, a configuration in which a gate insulating film is formed in the high resistance region B, and a source electrode and a drain electrode are formed in the low resistance region A is shown.

[0246] As the structure of the TFT of this embodiment, for example, a conventionally known structure can be adopted.

[0247] The TFT of this embodiment can be manufactured by using the manufacturing method of the stacked structure described above. That is, a manufacturing method having a crystalline oxide semiconductor film forming step and an insulating film forming step, the crystalline oxide semiconductor film forming step including: using a sputtering target, using one or more gases selected from the group consisting of argon, nitrogen, hydrogen, water and oxygen that are substantially free of impurity gases as a sputtering gas, and forming an oxide thin film by sputtering (sometimes referred to as an oxide thin film forming step); and a step of heat treating the oxide thin film (sometimes referred to as an oxide thin film heat treatment step), the insulating film forming step including: for example, using a sputtering target mainly composed of silicon to form an insulating film by sputtering on a crystalline oxide semiconductor film (sometimes referred to as an insulating film forming step); and a step of heat treating the insulating film (sometimes referred to as an insulating film heat treatment step). The conditions of each film forming step and heat treatment step are as described above. The source electrode, drain electrode, gate electrode and gate insulating film can be formed by known materials and formation methods.

[0248] In the stacked structure of one embodiment, the crystalline oxide semiconductor film has high mobility and excellent stability. By using the stacked structure having such a crystalline oxide semiconductor film as a channel layer of a TFT, high mobility and high reliability with suppressed variation in threshold voltage (Vth) can be obtained.

[0249] In this specification, the mobility when Vd=20V is applied is defined as the saturation mobility. Specifically, the calculation can be performed by generating a transfer characteristic Id-Vg graph when Vd=20V is applied, calculating the transconductance (Gm) at each Vg, and finding the mobility using the equation in the saturation region.

[0250] In the following description, current Id is the current between the source electrode and the drain electrode, voltage Vd is the voltage applied between the source electrode and the drain electrode (drain voltage), and voltage Vg is the voltage applied between the source electrode and the gate electrode (gate voltage).

[0251] The shape of the thin film transistor of this embodiment is not particularly limited, and is preferably a top-gate transistor, a back-channel etched transistor, an etch-stop transistor, etc. In addition, these transistors may be self-aligned.

[0252] In one embodiment, a top-gate transistor is preferred.

[0253] Hereinafter, the embodiments will be described with reference to the accompanying drawings, etc. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and various changes can be made to the plans and details without departing from the gist and scope thereof. Therefore, the present invention is not limited to the following descriptions of the embodiments and is not interpreted.

[0254] In the drawings, the size, thickness of the layer, and the region are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the size, thickness of the layer, and the region shown in the drawings. In addition, the drawings are diagrams schematically showing ideal examples, and the present invention is not limited to the shapes and values ​​shown in the drawings.

[0255] Figure 3 This is a schematic cross-sectional view of an example of a TFT according to this embodiment.

[0256] TFT50 is a top-gate TFT having a substrate 21 , a buffer layer 22 , a channel layer (crystalline oxide semiconductor film) 11 , an ITO layer 23 , a gate insulating film (insulating film) 24 , a gate electrode 25 , an interlayer insulating film 26 , a source electrode 27 , a drain electrode 28 and a protective film 29 .

[0257] The TFT 50 has a structure in which a substrate 21, a buffer layer 22, and a channel layer (crystalline oxide semiconductor film) 11 are stacked in this order. The channel layer 11 has a high resistance region 11B in the central portion, and a gate insulating film 24 (insulating film) and a gate electrode 25 are stacked in this order on the high resistance region 11B. The gate insulating film 24 is an insulating film that blocks conduction between the gate electrode 25 and the crystalline oxide semiconductor film 11.

[0258] On both sides of the high resistance region 11B are the low resistance regions 11A-1 and 11A-2 of the channel layer 11. The low resistance regions 11A-1, 11A-2 and the gate electrode 25 are covered with an ITO layer 23 and an interlayer insulating film 26. The ITO layer 23 is used to form the low resistance region of the channel layer 11.

[0259] Specifically, the low resistance regions 11A-1 and 11A-2 are formed by reducing the resistance of the target portion of the channel layer 11 by heat treatment (annealing) in the presence of the ITO layer 23. The region without the ITO layer 23 becomes the high resistance region B.

[0260] The source electrode 27 and the drain electrode 28 are connected to the low resistance regions 11A-1 and 11A-2 respectively through contact holes provided in the ITO layer 23 and the interlayer insulating film 26. The source electrode 27 and the drain electrode 28 are conductive terminals for allowing source current and drain current to flow through the channel layer 11.

[0261] A protective film 29 is provided so as to cover the interlayer insulating film 26 , the source electrode 27 , the drain electrode 28 and other TFT constituent layers.

[0262] The TFT of this embodiment can be improved by a known structure.

[0263] For example, although in Figure 3 Although not shown in the figure, in TFT50, a layer may be provided between substrate 21 and buffer layer 22 as shown in FIG. Figure 4 The light shielding layer 31 may be formed as shown, or may be formed as an intermediate layer of the buffer layer 22 in which a plurality of layers are stacked.

[0264] Figure 4 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0265] TFT51 has the same structure as TFT50 except that a light shielding layer 31 is provided between substrate 21 and buffer layer 22. Light shielding layer 31 is formed to suppress malfunction of TFT caused by light. Light shielding layer may be connected to source electrode 27 or gate electrode 25.

[0266] In addition, Figure 3 In the embodiment, the two end sides of the channel layer 11, that is, the areas near the areas connected to the source electrode 27 and the drain electrode 28, are set as the low resistance areas 11A of the crystalline oxide semiconductor film, and the areas in contact with the lower surface of the gate insulating film 24 are set as the high resistance areas 11B. Such a configuration example is shown as an example of the TFT of the present invention, but the TFT of the present invention is not limited to this configuration. That is, the TFT of the present invention can also use a crystalline oxide semiconductor film with a uniform resistance value in the surface direction as the channel layer 11. In this case, it can be as follows Figure 5 As shown, the ITO layer 23 is not formed.

[0267] Figure 5 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0268] TFT52 has the same structure as TFT50 except that the channel layer (crystalline oxide semiconductor film) 11 is a layer without a resistance boundary (the channel layer (crystalline oxide semiconductor film) 11 is not divided into a low resistance region 11A and a high resistance region 11B) and the ITO layer 23 is not provided.

[0269] In this embodiment, when the TFT is a small TFT, the crystalline oxide semiconductor film as a channel layer for the source electrode and the drain electrode has a channel length (L length; in Figure 3 In the contact region between the channel layer 11 and the gate insulating layer 24, the length in the direction of the source electrode 27-drain electrode 28) is 1 μm or more and 50 μm or less, and the channel width (W length; in Figure 3 In the embodiment, the length of the channel layer 11 in the contact region with the gate insulating layer 24 in the direction perpendicular to the source electrode 27 - drain electrode 28 direction) is greater than or equal to 1 μm and less than or equal to 80 μm.

[0270] The TFT of this embodiment can be improved by a known structure.

[0271] The material forming the substrate is not particularly limited, and any commonly used material can be selected. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SIO (Silicon In Insulator) substrates can also be used, and substrates obtained by providing semiconductor elements on these substrates can also be used as substrates.

[0272] In addition, a flexible substrate can be used as a substrate. In addition, as a method of providing a TFT on a flexible substrate, in addition to a method of directly manufacturing the TFT on the flexible substrate, there is also a method of manufacturing the TFT on a non-flexible substrate, peeling off the TFT, and providing it on the flexible substrate. In this case, a peeling layer can be provided between the non-flexible substrate and the TFT.

[0273] The buffer layer 22 may be composed of a single layer or may be composed of two or more layers stacked together. In addition, a metal layer may be provided between the buffer layer 22 and the substrate 21 .

[0274] Among them, it is preferred that the channel layer 11 and the buffer layer 22 are as follows Figure 3 Directly connected as shown.

[0275] The material forming the buffer layer is not particularly limited, and any commonly used material can be selected, and a laminated film can be used as the buffer layer. For example, SiO2, SiN x , silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, AlN. In addition, the oxidation number of each material may also be changed.

[0276] The light shielding layer 31 may be connected to the source electrode 27 and may also be connected to the gate electrode 25 .

[0277] The material forming the light shielding layer is not particularly limited, and any commonly used material can be selected. Specifically, metal electrodes such as Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, and W, and metal electrodes composed of alloys containing two or more of these metals can be cited. In addition, stacked electrodes of two or more layers can also be used.

[0278] exist Figure 4In the embodiment, a second buffer layer may be provided between the light shielding layer 31 and the substrate 21. The material forming the second buffer layer is not particularly limited, and any commonly used material can be selected, and a laminated film can be used as the second buffer layer. As the material of the second buffer layer, for example, SiO2, SiN x , silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, AlN. In addition, the oxidation number of each material may also be changed.

[0279] As a material for forming the gate insulating film, the materials described as the material of the insulating film can be used.

[0280] The materials forming the drain electrode, the source electrode and the gate electrode are not particularly limited, and any commonly used materials can be selected. Specifically, transparent electrodes such as ITO, IZO, ZnO, SnO2, metal electrodes such as Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, W, or metal electrodes composed of alloys containing two or more of these metals can be cited. In addition, stacked electrodes of more than two layers can also be used.

[0281] The material forming each interlayer insulating film is not particularly limited, and any commonly used material can be selected, and a stacked film can be used as the interlayer insulating film. For example, SiO2, SiN x , silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, AlN. In addition, the oxidation number of each material may also be changed.

[0282] Regardless of the structure of the TFT, it is preferred to provide a protective film on the drain electrode, the source electrode, and the conductive region. By providing the protective film, it is easy to improve the durability even when the TFT is driven for a long time.

[0283] The method for producing the insulating film of the buffer layer, gate insulating film, interlayer insulating film, and protective film is not particularly limited. Examples of the production method include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, sol-gel method, coating method, atomized CVD, etc. In addition, as a gas type for PE-CVD, tetraethoxysilane (TEOS) can be used in addition to silane (SiH4).

[0284] For example, when formed by PE-CVD, it sometimes becomes a process based on high temperature. In addition, the protective film or insulating film often contains impurity gas just after film formation, and it is preferably subjected to heat treatment (annealing treatment). By removing the impurity gas by heat treatment, a stable protective film or insulating film is formed, and a TFT with high durability is easily formed.

[0285] The saturation mobility of the TFT is preferably 10.0 cm 2 / V·s or more, more preferably 20.0cm 2 / V·s or more.

[0286] By setting the saturation mobility of the TFT to 10.0 cm 2 / V·s or above, it is possible to achieve high-definition, high-frame-rate, and large-area displays.

[0287] The saturation mobility of the TFT is obtained from the transfer characteristics when a drain voltage of 20 V is applied. The method for measuring the saturation mobility of the TFT is described in detail in the examples.

[0288] The threshold voltage (Vth) is preferably -3.0V to 3.0V, more preferably -2.0V to 2.0V, and even more preferably -1.0V to 1.0V. If the threshold voltage (Vth) is -3.0V to 3.0V, a Vth correction circuit can be installed in the TFT to correct Vth = 0V. When the TFT obtained in this way is installed in a panel, the display can be driven without causing uneven brightness and screen burn-in.

[0289] The threshold voltage (Vth) can be calculated from the transfer characteristic graph with Id=10 -9 A is defined by Vg.

[0290] The on-off ratio is preferably 10 6 More than 10 7 More than 10 8 If the on-off ratio is 10 6 If the on-off ratio is 10 8If the on-off ratio can be 10 10 Above and make the shutdown current 10 -12 A or less, a display element having excellent low power consumption and capable of being driven at a low frequency of about 1 Hz can be provided.

[0291] The on-off ratio was obtained by determining the ratio [on-current value / off-current value] by setting the value of Id when Vd=10V and Vg=-10V as the off-current value and the value of Id when Vd=10V and Vg=20V as the on-current value.

[0292] The shutdown current value is preferably 10 -10 A or less, more preferably 10 -11 A or less, more preferably 10 -12 A or less. If the cut-off current value is 10 -10 A or less, it is possible to drive an organic EL with a large contrast. In addition, when used for a transfer transistor or a reset transistor of a CMOS image sensor, it is possible to extend the image retention time or improve the sensitivity.

[0293] The TFT according to this embodiment can be suitably used in electronic devices such as solar cells, liquid crystal elements, display elements such as organic electroluminescent elements and inorganic electroluminescent elements, power semiconductor elements, and touch panels.

[0294] The thin film transistor of this embodiment can also be applied to various integrated circuits such as field effect transistors (MOSFET, MESFET), logic circuits, storage circuits, and differential amplifier circuits, and can be applied to electronic equipment, electrical equipment, vehicles, or power machines, etc. Furthermore, in addition to field effect transistors, the thin film transistor involved in this embodiment can also be applied to static induction transistors and Schottky barrier transistors.

[0295] The thin film transistor according to this embodiment can be suitably used in display devices such as portable or vehicle-mounted display devices, solid-state imaging devices, etc. Furthermore, the thin film transistor according to this embodiment can also be suitably used as a transistor for a flat panel detector for an X-ray image sensor for medical use.

[0296] Furthermore, the crystalline oxide semiconductor film according to this embodiment can also be applied to a Schottky diode, a resistance variable memory, and a resistor element.

[0297] Example

[0298] Hereinafter, the present invention will be specifically described based on Examples. However, the present invention is not limited to the Examples.

[0299] [Fabrication of small TFTs with self-aligned top-gate structure]

[0300] Example 1

[0301] Produced through the following processes Figure 6 The thin film transistor (TFT) 53 shown in FIG. 5 is provided with the same Figure 3 The TFT 50 shown has the same structure.

[0302] (1) Formation of buffer layer 22

[0303] Using a SiO2 sputtering target, a SiO2 layer with a thickness of 300 nm was formed on a 4-inch diameter alkali-free glass substrate 21 (EAGLE XG manufactured by Corning Incorporated) by sputtering. x The sputtering conditions are as follows.

[0304] Substrate temperature: 25°C

[0305] Ultimate pressure: 8.5×10 -5 Pa

[0306] Atmosphere gas: Ar

[0307] Sputtering pressure (total pressure): 0.4Pa

[0308] Input voltage: RF300W

[0309] Distance between S (substrate) and T (target): 70 mm

[0310] (2) Formation of oxide film

[0311] Next, a channel layer was formed by sputtering using an oxide sputtering target obtained from a raw material mixture having a charge composition ratio shown in Table 1-1. The metal composition ratio (unit: at %) in the oxide sputtering target is shown in Table 1-1.

[0312] The film formation conditions during sputtering and the thickness of the channel layer are shown in Table 1-1. The sputtering conditions other than those described in Table 1-1 are as follows.

[0313] Substrate temperature: 25°C

[0314] Ultimate pressure: 1.0×10 -4 Pa

[0315] Atmosphere gas: a mixture of Ar and H2O

[0316] Sputtering pressure (total pressure): 0.5Pa

[0317] Input voltage: DC300W

[0318] Distance between S (substrate) and T (target): 70 mm

[0319] (3) Formation of channel layer 11

[0320] Next, the oxide thin film is patterned into an island shape by photolithography to form a channel layer 11. First, a film of photoresist is formed on the oxide thin film. As a photoresist, AZ1500 (manufactured by Anzhi Electronic Materials Co., Ltd.) is used. Exposure is performed through a photomask having a pattern of 50 μm in width and 20 μm in length. After exposure, development is performed with tetramethylammonium hydroxide (TMAH). After development, the oxide thin film is etched with oxalic acid (ITO-06N manufactured by Kanto Chemical). After etching, the photoresist is peeled off to obtain a substrate with a patterned oxide thin film (channel layer 11).

[0321] (4) Annealing

[0322] Next, the substrate with the channel layer 11 formed thereon was placed in a furnace, heated to 350°C at 10°C / min in the atmosphere, and then kept at that temperature for 1 hour. After being kept at 350°C for 1 hour, the substrate was naturally cooled, and after the temperature inside the furnace returned to room temperature, the substrate was taken out of the furnace.

[0323] (5) Surface treatment

[0324] Next, the surface of the channel layer 11 is treated by the following method.

[0325] First, a SiO2 sputtering target was used to sputter to form a 10 nm thick SiO x The sputtering conditions are as follows.

[0326] Substrate temperature: 25°C

[0327] Ultimate pressure: 8.5×10 -5 Pa

[0328] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 30%)

[0329] Sputtering pressure (total pressure): 0.4Pa

[0330] Input voltage: RF300W

[0331] Distance between S (substrate) and T (target): 70 mm

[0332] The above SiO x The SiO layer (processing film) with a thickness of 100 nm formed in the "(7) Formation of the gate insulating film 24" described later. x The layers are integrated and function as a gate insulating film 24 of the TFT.

[0333] The SiO formed by sputtering xThe thickness of the layer is shown in the "Film Thickness" column of "Surface Treatment" in Table 1-1.

[0334] (6) Annealing after surface treatment

[0335] Next, the surface treated substrate was placed in a furnace, heated to 400°C at 10°C / min in the atmosphere, and then kept at that temperature for 1 hour. After being kept at 400°C for 1 hour, the substrate was naturally cooled. After the temperature in the furnace returned to room temperature, the substrate was taken out of the furnace.

[0336] (7) Formation of Gate Insulating Film 24

[0337] Next, a SiO2 sputtering target was used to form a 100 nm thick SiO x The sputtering conditions are as follows.

[0338] Substrate temperature: 25°C

[0339] Ultimate pressure: 8.5×10 -5 Pa

[0340] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 30%)

[0341] Sputtering pressure (total pressure): 0.4Pa

[0342] Input voltage: RF300W

[0343] Distance between S (substrate) and T (target): 70 mm

[0344] Thus, the SiO film formed in this step is formed. x layer (thickness 100nm), and the SiO x The layers (thickness 10 nm) are integrated to form the gate insulating film 24. Thus, the total thickness of the gate insulating film 24 becomes 110 nm.

[0345] (8) Annealing of Gate Insulation Film 24

[0346] Next, the substrate with the gate insulating film 24 formed is placed in a furnace, and the temperature is raised to 400°C at 10°C / min in the atmosphere, and then maintained for 1 hour. After the temperature in the furnace is maintained at 400°C for 1 hour, it is naturally cooled. After the temperature in the furnace returns to room temperature, the substrate is taken out of the furnace.

[0347] (9) Formation of Gate Electrode 25

[0348] Next, a Mo film with a thickness of 150 nm was formed using a sputtering target of Mo. The sputtering conditions were as follows.

[0349] Substrate temperature: 25°C

[0350] Ultimate pressure: 8.5×10 -5 Pa

[0351] Atmosphere gas: Ar

[0352] Sputtering pressure (total pressure): 0.4Pa

[0353] Input voltage: DC100W

[0354] Distance between S (substrate) and T (target): 70 mm

[0355] (10) Patterning of the Gate Electrode 25 and the Gate Insulation Film 24

[0356] Next, the Mo film and the gate insulating film 24 are patterned into an island shape by photolithography. First, a film of photoresist is formed on the channel layer. As a photoresist, AZ1500 (manufactured by Anzhi Electronic Materials Co., Ltd.) is used. Exposure is performed through a photomask having a pattern. After exposure, development is performed with tetramethylammonium hydroxide (TMAH). After development, the Mo film is etched with PAN (a mixed acid of phosphoric acid, nitric acid and acetic acid) to form a gate electrode 25.

[0357] Next, the gate insulating film 24 is etched using buffered hydrofluoric acid (BHF) and patterned into an island shape.

[0358] Next, after the photoresist was peeled off, the region where the channel layer 11 was exposed was etched to a thickness of 10 nm using oxalic acid (ITO-06N manufactured by Kanto Chemical), and then cleaned.

[0359] The size of the portion of the obtained gate electrode layer 25 and gate insulating film 24 overlapping with the channel layer 11 was 10 μm in width×28 μm in height.

[0360] (11) Low resistance treatment

[0361] The low resistance region A (11A-1, 11A-2) is formed in the channel layer 11 by self-alignment using the gate electrode 25. Using an ITO sputtering target, a 2 nm thick ITO layer 23 is formed. The sputtering conditions are as follows.

[0362] Substrate temperature: 25°C

[0363] Ultimate pressure: 8.5×10 -5 Pa

[0364] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 2%)

[0365] Sputtering pressure (total pressure): 0.4Pa

[0366] Input voltage: DC50W

[0367] Distance between S (substrate) and T (target): 70 mm

[0368] Next, the substrate after the low resistance treatment was placed in a furnace, heated to 350°C at 10°C / min in the atmosphere, and then kept for 1 hour for annealing. After being kept at 350°C for 1 hour, the substrate was naturally cooled. After the temperature in the furnace returned to room temperature, the substrate was taken out of the furnace.

[0369] (12) Formation of Interlayer Insulation Film 26

[0370] Next, a SiO2 sputtering target was used to sputter to form a 150 nm thick SiO x The sputtering conditions are as follows.

[0371] Substrate temperature: 25°C

[0372] Ultimate pressure: 8.5×10 -5 Pa

[0373] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 30%)

[0374] Sputtering pressure (total pressure): 0.4Pa

[0375] Input voltage: RF100W

[0376] Distance between S (substrate) and T (target): 70 mm

[0377] (13) Formation of Contact Holes in Interlayer Insulation Film 26

[0378] The substrate with the interlayer insulating film 26 formed thereon was exposed to light through a photomask using photoresist AZ1500 (manufactured by AZ Electronic Materials Co., Ltd.) and then developed using tetramethylammonium hydroxide (TMAH). After development, a contact hole of 12 μm in width and 18 μm in height was formed using buffered hydrofluoric acid (BHF).

[0379] (14) Formation of Source Electrode 27 and Drain Electrode 28

[0380] The source electrode 27 and the drain electrode 28 were patterned by a lift-off process using the image reversal resist AZ5214 and a photomask. The image reversal resist AZ5214 was exposed through a photomask, and the entire surface was exposed after a reverse baking process, and developed with TMAH. For the substrate with the patterned resist, a Mo layer with a thickness of 150 nm was formed under the following sputtering conditions.

[0381] Substrate temperature: 25°C

[0382] Ultimate pressure: 8.5×10 -5 Pa

[0383] Atmosphere gas: Ar

[0384] Sputtering pressure (total pressure): 0.4Pa

[0385] Input voltage: DC100W

[0386] Distance between S (substrate) and T (target): 70 mm

[0387] Then, the substrate on which the Mo layer was formed was peeled off in acetone, thereby patterning the source electrode 27 and the drain electrode 28 .

[0388] (15) Final annealing

[0389] Finally, annealing was performed at 300°C for 1 hour in a N2 atmosphere, thereby obtaining a self-aligned top-gate structured small TFT.

[0390] Tables 1-1 to 1-3 and 2 show the outline of the TFT production conditions.

[0391] Example 2

[0392] A TFT was produced in the same manner as in Example 1, except that the thickness of the channel layer formed in "(2) Formation of an oxide thin film" was changed as shown in Table 1-1.

[0393] Embodiments 3 to 5

[0394] The SiO film formed in "(5) Surface Treatment" x A TFT was produced in the same manner as in Example 1, except that the thickness of the layer (process film) was changed as shown in Table 1-1.

[0395] Example 6

[0396] A TFT was produced in the same manner as in Example 1, except that "(5) surface treatment" was performed by chemical vapor deposition (CVD) instead of sputtering.

[0397] The chemical vapor deposition (CVD) treatment was performed by the following method.

[0398] First, the substrate after the "(4) annealing" was placed in a plasma CVD device, the substrate was kept at 350°C, and SiH4 was introduced at a pressure of 110 Pa in a ratio of 2 sccm, N2O was 100 sccm, and N2 was 120 sccm to form a SiO layer with a thickness of 10 nm. x layer.

[0399] Example 7

[0400] In "(5) Surface treatment", SiN xA SiN layer with a thickness of 10 nm was formed in the same manner as in Example 1 except that a sputtering target of SiO2 was used instead of a sputtering target of SiO2. x The other steps were carried out in the same manner as in Example 1 to produce a TFT.

[0401] Example 8

[0402] In "(5) Surface Treatment", except that a sputtering target of Al2O3 was used instead of a sputtering target of SiO2, a 10 nm thick Al2O3 layer was formed in the same manner as in Example 1. The other steps were carried out in the same manner as in Example 1 to produce a TFT.

[0403] Example 9

[0404] In "(5) Surface treatment (film formation treatment)" of Example 1, plasma oxidation treatment using N2O using a PE-CVD device was performed instead of film formation using sputtering, and the subsequent "(6) Annealing after surface treatment" was not performed. The TFT was manufactured in the same manner as in Example 1. The plasma oxidation treatment using N2O was carried out at room temperature with N2O introduced at a gas pressure of 133 Pa, under the conditions of a power of 50 W and a treatment time of 1 minute.

[0405] In addition, in Table 1-2, the description of "Film formation without surface treatment" in the "Film thickness" column of "Surface treatment" in Example 9 means that no film was formed in the plasma oxidation treatment using N2O.

[0406] In Example 9, the SiO2 film having a thickness of 100 nm formed in "(7) Formation of the gate insulating film 24" is x The layer constitutes the gate insulating film 24 .

[0407] Example 10

[0408] In "(2) Formation of oxide thin film", the composition ratio of the sputtering target used in forming the channel layer is changed as shown in Table 1-2, and the oxygen partial pressure and water partial pressure of the film-forming atmosphere gas during the formation of the channel layer are changed as shown in Table 1-2. Except for this, the TFT is manufactured in the same manner as in Example 1.

[0409] Embodiment 11

[0410] In “(2) Formation of an oxide thin film”, a channel layer was formed in the same manner as in Example 10, except that the composition ratio of the sputtering target used for forming the channel layer was changed as shown in Table 1-2.

[0411] In addition, in "(5) Surface treatment", the O2 flow rate of the film forming atmosphere gas during the film forming treatment was changed from 30% to 1% of the H2O flow rate of the film forming atmosphere gas. Except for this, a SiO3 layer (treated film) with a thickness of 10 nm was formed in the same manner as in Example 1.

[0412] The other steps were carried out in the same manner as in Example 1 to produce a TFT.

[0413] Embodiments 12 to 16

[0414] In "(2) Formation of oxide thin film", the composition ratio of the sputtering target used in forming the channel layer is changed as shown in Table 1-2, and the oxygen partial pressure and water partial pressure of the film-forming atmosphere gas during the formation of the channel layer are changed as shown in Table 1-2. Except for this, the TFT is manufactured in the same manner as in Example 1.

[0415] Comparative Example 1

[0416] A TFT was produced in the same manner as in Example 1 except that "(5) surface treatment" and "(6) annealing after surface treatment" were not performed.

[0417] Comparative Example 2

[0418] TFTs were fabricated in the same manner as in Example 1, except that the thickness of the SiO2 layer (treatment film) formed in "(5) Surface treatment" was changed as shown in Table 1-3.

[0419] Comparative Example 3

[0420] A TFT was produced in the same manner as in Example 1 except that "(6) annealing after surface treatment" was not performed.

[0421] Comparative Example 4

[0422] A TFT was produced in the same manner as in Example 9 except that after performing “(5) surface treatment”, “(6) post-surface treatment annealing” was performed in the same manner as in Example 1.

[0423] In Comparative Example 4, the SiO 2 layer having a thickness of 100 nm formed in “(7) Formation of Gate Insulating Film 24 ” constitutes the gate insulating film 24 .

[0424] The TFTs obtained in Examples and Comparative Examples were evaluated as follows. The results are shown in Tables 1-1 to 1-3.

[0425] (A) Evaluation of the stacked structure of TFT

[0426] (1) A / B measurement (EDX test)

[0427] The average value of A / B represented by the following formula (1) in the stacked structure of the gate insulating film and the channel layer (crystalline oxide semiconductor film) was measured using TEM-EDX (Transmission electron microscopy-Energy Dispersive X-ray Spectroscopy).

[0428] 1.25≤(average value of A / B)≤1.75 (1)

[0429] A in formula (1) is the number of oxygen atoms. B in formula (1) is the number of detectable cationic atoms that are bonded to oxygen atoms. Cationic atoms are cationic atom species contained in the stacked structure of the gate insulating film and the channel layer (crystalline oxide semiconductor film) at 1 at % or more.

[0430] The average value of A / B in the stacked structure was measured using TEM-EDX as follows.

[0431] First, the TFTs obtained in each embodiment and comparative example were processed by focused ion beam: FIB (Focused Ion Beam) at an acceleration voltage of 20 to 30 kV using a composite beam processing and observation device (manufactured by JEOL Ltd., “JIB-4700F”). Then, a focused ion beam processing and observation device (FIB) (manufactured by Hitachi High-Technologies Corporation, “FB-2100”) was used at an acceleration voltage of 40 kV to obtain thin film samples for cross-sectional TEM observation by a microsampling method.

[0432] The thin film sample for cross-sectional TEM observation is prepared as a thin film having a stacked structure with film thickness regions of approximately equal thickness on the gate insulating film side and the channel layer side centered at the interface between the gate insulating film and the channel layer, and is prepared in such a way that the thin film samples of all embodiments and comparative examples have the same processed thickness (approximately 70 nm).

[0433] Next, cross-sectional TEM observation was performed on the thin film sample for cross-sectional TEM observation, and EDX analysis was performed on the field of view including a film thickness region of about 130 nm on the gate insulating film side and the channel layer side, centered at the interface between the gate insulating film and the channel layer (refer to Figure 2 ).

[0434] The EDX analysis was performed using an energy dispersive X-ray analyzer (manufactured by JEOL Ltd., “JED-2300T”) under the following conditions.

[0435] Accelerating voltage: 200 kV

[0436] Measurement mode: STEM mode

[0437] Spot diameter: 0.16nm

[0438] Measuring interval: 1nm

[0439] EDX analysis is performed as follows: cation atoms and oxygen atoms bonded to oxygen atoms are selected as elements to be detected (detectable elements), and line analysis is performed on a range of about 130 nm centered on the interface between the gate insulating film and the channel layer in the stacking direction.

[0440] Specifically, In, Ga, Si, Al, and Mo are selected as the cation atom that exists by bonding to the oxygen atom.

[0441] For the EDX spectrum intensity obtained by EDX line analysis, the exclusive software of the energy dispersive X-ray analyzer (manufactured by JEOL Ltd., “JED-2300T”) automatically calculates the at% of A (oxygen atom) and the at% of B (detectable cation atom existing in combination with the oxygen atom) at each measurement point using the initial setting values, thereby calculating the A / B of each measurement point represented by the above formula (1).

[0442] The average value of A / B is calculated by arithmetically averaging the A / B values ​​obtained at the respective measurement locations in the above-mentioned EDX line analysis with respect to a predetermined film thickness range.

[0443] In addition, for the channel layer (crystalline oxide semiconductor film) region in the TFT, the above-mentioned EDX line analysis is performed on all cations contained in the stacked structure, and the region where the In concentration shows the maximum value in the cation concentration of each cation (the concentration of each cation relative to all detectable atoms contained in the channel layer) is taken as the channel layer (crystalline oxide semiconductor film) region.

[0444] Figure 7 2 shows EDX spectra of thin film samples for cross-sectional TEM observation of Example 1 and Comparative Example 1 obtained by EDX line analysis. Figure 7 The horizontal axis shows the depth position in the stacking direction of the stacking structure, and the vertical axis shows A / B.

[0445] (B) Evaluation of TFT performance

[0446] The obtained TFT was measured at room temperature in a light-shielded environment (in a shielded box) using a semiconductor parameter analyzer ("B1500" manufactured by Agilent Technologies). In addition, a drain voltage (Vd) was applied at 20 V. For Vd application, the gate voltage (Vg) was varied from -5 V to 20 V in 0.1 V steps to measure the current value Id, thereby obtaining Id-Vg characteristics.

[0447] Various parameters calculated from the Id-Vg characteristics are shown in Tables 1-1 to 1-3. The calculation method of each parameter is as follows.

[0448] (a) Maximum value of saturation mobility

[0449] For the maximum value of the saturation mobility when Vd = 20 V is applied, a graph of the Id-Vg characteristics is prepared, the transconductance (Gm) at each Vg is calculated, and the saturation mobility (μ sat ). Specifically, Gm is calculated by the following mathematical formula (c1).

[0450] [Number 1]

[0451]

[0452] Furthermore, μ is calculated by the following formula (c) in the saturation region. sat .

[0453] μ sat =(2·Gm·L) / (W·Ci)…(c)

[0454] In the formula (c), L is the channel length (L length), and W is the channel width (W length).

[0455] Furthermore, according to each Vg~μ sat Calculate μ when Vg = 0 to 20 V sat The maximum value of .

[0456] (b) Reliability of self-aligned small TFT (exposure test)

[0457] The reliability of the TFT was evaluated by a stress test, in which a negative bias heating light irradiation stress test (NBITS) was performed.

[0458] In NBITS, Vg=-20V was applied at 50°C while irradiating light of 4500 nit from the interlayer insulating film 26 side using LED light, and the threshold voltage (Vth) after 10,000 seconds was compared with that before the test, and the difference was defined as ΔVth.

[0459] [Table 1-1]

[0460]

[0461] [Table 1-2]

[0462]

[0463] [Table 1-3]

[0464]

[0465] *) In the "average value of A / B", A is the number of oxygen atoms bonded to cation atoms, and B is the number of cation atoms bonded to oxygen atoms. The cation atoms are cation atom species contained in the stacked structure at 1 at % or more.

[0466] [Table 2]

[0467]

[0468] As shown in Tables 1-1 to 1-2, the TFTs of Examples 1 to 8 and Examples 10 to 16 were prepared by performing surface treatment on the channel layer by sputtering or CVD film formation, performing annealing after the surface treatment, and then forming a gate insulating film and annealing. The TFTs of Examples 1 to 8 and Examples 10 to 16 showed a 30 cm 2 The good mobility is above / Vs, and the optical reliability (NBTIS) ΔVth[V] is suppressed to a low value, thereby obtaining high reliability.

[0469] As shown in Table 1-2, the TFT of Example 9 in which the channel layer is subjected to N2O plasma oxidation treatment (surface treatment of the channel layer) and then the gate insulating film is formed without annealing treatment shows a 30 cm 2 The good mobility is above / Vs, and the optical reliability (NBTIS) ΔVth[V] is suppressed to a low value, thereby obtaining high reliability.

[0470] Industrial Applicability

[0471] The crystalline oxide thin film of the present invention can be suitably used as a component of a thin film transistor, such as a channel layer. In addition, the thin film transistor of the present invention can be used in electronic circuits used in electrical equipment, electronic equipment, vehicles, and power machines.

[0472] The above embodiments and / or examples of the present invention have been described in some detail, but those skilled in the art can easily make many changes to these illustrative embodiments and / or examples without departing from the new teachings and effects of the present invention. Therefore, these many changes are included in the scope of the present invention.

[0473] The contents of all the documents described in this specification and the applications serving as the basis for the priority claim based on the Paris Convention of the present application are cited.

Claims

1. A stacked structure comprising a crystalline oxide semiconductor film having In as a main component and an insulating film stacked to form an interface with the crystalline oxide semiconductor film, characterized in that: The insulating film having a film thickness from the interface to a distance substantially equal to the film thickness of the crystalline oxide semiconductor film has a region satisfying the following formula (1): 1.25≤(average value of A / B)≤1.75 (1), In the formula, A is the number of oxygen atoms, and B is the number of cation atoms bonded to the oxygen atoms, wherein the cation atoms are cation atoms species contained in the stacked structure at 1 at % or more.

2. The stacked structure according to claim 1, characterized in that The crystalline oxide semiconductor film has a region satisfying the formula (1).

3. The laminate structure according to claim 1 or 2, characterized in that: The insulating film is any one of an oxide film mainly composed of silicon (Si), a nitride film mainly composed of silicon (Si), or an oxynitride film mainly composed of silicon (Si).

4. The laminate structure according to any one of claims 1 to 3, characterized in that: The insulating film is an oxide film containing silicon (Si) as a main component.

5. The laminate structure according to any one of claims 1 to 4, characterized in that: The crystalline oxide semiconductor film further contains Ga.

6. The laminate structure according to any one of claims 1 to 5, characterized in that: The crystalline oxide semiconductor film further contains one or more additional elements selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm, and Yb.

7. The laminate structure according to any one of claims 1 to 6, wherein: The atomic ratio of In to all metal elements contained in the crystalline oxide semiconductor film ([In] / ([In]+[all metal elements other than In])×100) is 62 at % or more.

8. The laminate structure according to any one of claims 5 to 7, wherein: The atomic ratio of Ga to all metal elements contained in the crystalline oxide semiconductor film ([Ga] / ([Ga]+[all metal elements other than Ga])×100) is 30 at % or less.

9. The laminate structure according to any one of claims 6 to 8, characterized in that: The atomic ratio of the total amount of the additive elements to all metal elements contained in the crystalline oxide semiconductor film ([total amount of additive elements] / ([total amount of additive elements]+[all metal elements other than additive elements])×100) is 10 at % or less.

10. The laminate structure according to any one of claims 1 to 9, wherein: The carrier concentration of the crystalline oxide semiconductor film is 1×10 18 cm -3 the following.

11. The laminate structure according to any one of claims 1 to 10, characterized in that: The crystalline oxide semiconductor film includes crystal grains of a bixbyite structure.

12. A thin film transistor comprising the stacked structure according to any one of claims 1 to 11, characterized in that: have: Channel layer; a source electrode and a drain electrode respectively connected to the channel layer; a gate electrode stacked on the channel layer via a gate insulating film, The channel layer is a crystalline oxide semiconductor film in the stacked structure, The gate insulating film is an insulating film in the stacked structure.

13. The thin film transistor according to claim 12, wherein: It is a top-gate transistor.

14. A semiconductor device, characterized in that: The laminate structure according to any one of claims 1 to 11 is used.

15. A diode, a thin film transistor, a MOSFET or a MESFET, characterized in that: The semiconductor element according to claim 14 is used.

16. An electronic circuit, characterized in that: A diode, a thin film transistor, a MOSFET or a MESFET comprising the diode, the thin film transistor, the MOSFET or the MESFET as claimed in claim 15.

17. An electrical device, electronic device, vehicle or power machine, characterized in that: An electronic circuit comprising the electronic circuit of claim 16.

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