Display device

Abstract

A display device according to an embodiment may include: a substrate including a light emitting area and a non-light emitting area; a plurality of light emitting elements disposed on the substrate; a first electrode and a second electrode spaced apart from each other and electrically connected to the plurality of light emitting elements; a cap layer disposed on the first electrode and the second electrode; and a color conversion layer disposed on the cap layer. Here, the cap layer may include a plurality of sub-insulating layers, each of which includes a first layer and a second layer stacked in this order. The first layer and the second layer may have different refractive indices.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices are being continuously conducted. Summary of the invention

[0003] Technical issues

[0004] An object of the present disclosure is to provide a display device capable of improving reliability.

[0005] Technical Solution

[0006] A display device according to an embodiment may include: a substrate including an emission region and a non-emission region; a plurality of light-emitting elements disposed on the substrate; a first electrode and a second electrode disposed to be spaced apart from each other and electrically connected to the plurality of light-emitting elements; a cap layer disposed on the first electrode and the second electrode; and a color conversion layer disposed on the cap layer. The cap layer may include a plurality of sub-insulating layers, each of the plurality of sub-insulating layers including a first layer and a second layer stacked in sequence. The first layer and the second layer may have different refractive indices.

[0007] In an embodiment, the first layer may be a first inorganic layer having a first refractive index, and the second layer may be a second inorganic layer having a second refractive index.

[0008] In an embodiment, the first refractive index may be less than the second refractive index.The first inorganic layer may include silicon oxide, and the second inorganic layer may include silicon nitride.

[0009] In an implementation, each of the plurality of sub-insulating layers may further include a third layer stacked on the second layer. The third layer may be a third inorganic layer having a third refractive index.

[0010] In an embodiment, the third refractive index may be different from the second refractive index.

[0011] In an embodiment, the second refractive index may be less than the first refractive index.The first inorganic layer may include silicon nitride, and the second inorganic layer may include silicon oxide.

[0012] In an embodiment, the cover layer may transmit light within a predetermined wavelength range.

[0013] In an embodiment, the color conversion layer may include color conversion particles that convert light emitted from the plurality of light emitting elements into light of different wavelengths.

[0014] In an embodiment, the display device may further include a first insulating layer disposed between the substrate and the plurality of light emitting elements, a second insulating layer disposed on each of the plurality of light emitting elements, and a third insulating layer disposed on the first electrode.

[0015] In an embodiment, the capping layer may have a thickness less than or equal to about 2 μm.

[0016] In an implementation, the display device may further include an additional insulating layer disposed between the first and second electrodes and the capping layer.

[0017] In an implementation, the additional insulating layer may include an organic layer.

[0018] In an implementation, the additional insulating layer may have a thickness in the range of 1.0 μm to 1.3 μm.

[0019] In an implementation, the additional insulating layer may include an inorganic layer.

[0020] In an embodiment, the display device may further include: a first alignment electrode and a second alignment electrode, which are positioned between the substrate and the first insulating layer and are spaced apart from each other; a first dam, which is disposed in the non-emitting area and includes an opening corresponding to the emitting area; a second dam, which is positioned on the first dam in the non-emitting area and surrounds the color conversion layer; and a color filter, which is disposed on the color conversion layer.

[0021] In an implementation, the first electrode may be electrically connected to the first alignment electrode, and the second electrode may be electrically connected to the second alignment electrode.

[0022] In an embodiment, the display device may further include: a pixel circuit layer disposed between the substrate and the plurality of light emitting elements and including at least one transistor electrically connected to the plurality of light emitting elements.

[0023] A display device according to another embodiment may include: a plurality of light emitting elements disposed on a substrate; a first electrode and a second electrode disposed to be spaced apart from each other and electrically connected to the plurality of light emitting elements; a cover pattern disposed on the first electrode to cover the first electrode; and a color conversion layer disposed on the cover pattern. The cover pattern may include a plurality of sub-insulating layers and an opening, each of the plurality of sub-insulating layers including a first layer and a second layer stacked in sequence. The first layer and the second layer may have different refractive indices. The opening of the cover pattern may expose the second electrode.

[0024] In an implementation, the color conversion layer may be directly disposed on the capping pattern and the second electrode, and the capping pattern is not disposed on the second electrode.

[0025] In an embodiment, the cover pattern may selectively transmit light within a predetermined wavelength range.

[0026] Technical Effects

[0027] In a display device according to an embodiment, a cover layer having a distributed Bragg reflector structure may be provided between a light emitting element and a color conversion layer (or QD layer) to reflect light traveling toward a rear surface of the color conversion layer in a front surface direction. Thus, the brightness of a pixel may be increased by increasing the light output efficiency of the pixel.

[0028] In addition, according to an embodiment, a cap layer may be provided between the light emitting element and the color conversion layer to ensure a distance between the light emitting element and the color conversion layer. Therefore, the reliability of the display device may be improved by preventing degradation of the color conversion layer.

[0029] The effects according to the embodiments of the present disclosure are not limited to the contents shown above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic perspective view showing a light emitting element according to an embodiment.

[0031] Figure 2 yes Figure 1 Schematic cross-sectional view of a light-emitting element.

[0032] Figure 3 is a schematic plan view showing a display device according to an embodiment.

[0033] Figure 4 It is shown Figure 3 A schematic circuit diagram of the electrical connection relationship between components included in each of the pixels shown in FIG.

[0034] Figure 5 It is schematically shown Figure 3 A plan view of the pixel shown in FIG.

[0035] Figure 6 It is along Figure 5 A schematic cross-sectional view taken along line I-I'.

[0036] Figure 7 It is along Figure 5 A schematic cross-sectional view taken along line II-II'.

[0037] Figure 8 It is along Figure 5 A cross-sectional view taken along line III-III'.

[0038] Fig. 9 and Fig.10 It is shown Figure 7 Schematic enlargement of the EA part.

[0039] Fig.11 and Fig.12 A pixel according to an embodiment is schematically shown and is similar to Figure 5 A schematic cross-sectional view corresponding to line II to II'. DETAILED DESCRIPTION

[0040] The present disclosure can be modified in various ways and have various forms. Therefore, specific embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed, and the present disclosure includes all modifications, equivalents and substitutions within the spirit and technical scope of the present disclosure.

[0041] When describing each of the accompanying drawings, similar reference numerals are used for similar components. In the accompanying drawings, for the clarity of the present disclosure, the size of the structure is enlarged from the actual size. The terms "first", "second", etc. can be used to describe various components, but these components should not be limited by these terms. These terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component.

[0042] It should be understood that in this application, the terms "including", "having", etc. are used to specify the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification, but do not exclude the possibility of pre-existence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof. In addition, the case where a part of a layer, film, region, plate, etc. is referred to as being "on" another part includes not only the case where the part is "directly" "on" another part, but also includes the case where there is another part between the part and the other part. In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly" "below" another part, but also includes the case where there is another part between the part and the other part.

[0043] In the present application, when a component (e.g., a "first component") is operably or communicably coupled to / operably or communicably coupled to another component (e.g., a "second component") or is operably or communicably "connected to" another component (e.g., a "second component"), it should be understood that the component can be directly connected to the other component or can be connected to the other component through another component (e.g., a "third component"). On the contrary, when a component (e.g., a "first component") is "directly coupled to" / "directly coupled to" another component (e.g., a "second component") or is "directly connected to" another component (e.g., a "second component"), it can be understood that there is no other component (e.g., a "third component") between the component and the other component.

[0044] Hereinafter, preferred embodiments of the present disclosure and other contents necessary for those skilled in the art to understand the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, a singular expression includes a plural expression unless the context clearly indicates otherwise.

[0045] Figure 1 is a schematic perspective view showing a light emitting element LD according to an embodiment, and Figure 2 yes Figure 1 Schematic cross-sectional view of a light emitting element LD.

[0046] refer to Figure 1 and Figure 2 , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as a light emitting stack (or stacking pattern) in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked. In an embodiment, the type and / or shape of the light emitting element LD is not limited to Figure 1 and Figure 2 The embodiment shown in .

[0047] The light emitting element LD may be provided in a shape extending in one direction. When the extending direction of the light emitting element LD is referred to as a length direction, the light emitting element LD may include a first end EP1 and a second end EP2 facing each other along the length direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be positioned at the first end EP1 of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be positioned at the second end EP2 of the light emitting element LD. For example, the second semiconductor layer 13 may be positioned at the first end EP1 of the light emitting element LD, and the first semiconductor layer 11 may be provided at the second end EP2 of the light emitting element LD.

[0048] The light emitting element LD can be arranged in various shapes. Figure 1 As shown in , the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape that is long in the length direction (or has an aspect ratio greater than 1). As another example, the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape that is short in the length direction (or has an aspect ratio less than 1). As yet another example, the light emitting element LD may have a rod-like shape, a rod-like shape, or a column-like shape having an aspect ratio of 1.

[0049] For example, the light emitting element LD may include a light emitting diode (LED) manufactured to be extremely small to have a diameter D and / or a length L of approximately nanometer level (or nanometer) to micrometer level (or micrometer).

[0050] When the light emitting element LD is long in the length direction (ie, the aspect ratio is greater than 1), the diameter D of the light emitting element LD may be about 0.5 μm to 6 μm, and the length L of the light emitting element LD may be about 1 μm to 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto. The size of the light emitting element LD may be changed to meet the required conditions (or design conditions) of the lighting device or the self-luminous display device to which the light emitting element LD is applied.

[0051] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the material configuring the first semiconductor layer 11 is not limited thereto, and other various materials may configure the first semiconductor layer 11.

[0052] The active layer 12 (or emission layer) may be disposed (or located) on the first semiconductor layer 11, and may be formed as a single quantum well structure or a multi-quantum well structure. For example, when the active layer 12 is formed as a multi-quantum well structure, in the active layer 12, a barrier layer (not shown), a strain enhancement layer, and a well layer may be periodically and repeatedly stacked as a unit. However, the structure of the active layer 12 is not limited to the above-described embodiment.

[0053] The active layer 12 may emit light of a wavelength of 400 nm to 900 nm, and a double heterostructure may be used. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12 along the length direction of the light emitting element LD. For example, the cladding layer may be formed of AlGaN or InAlGaN. According to an embodiment, materials such as AlGaN or InAlGaN may be used to form the active layer 12, and various other materials may configure the active layer 12. The active layer 12 may include a first surface contacting the first semiconductor layer 11 and a second surface contacting the second semiconductor layer 13.

[0054] When an electric field of a predetermined voltage or more is applied to both ends of the light emitting element LD, the light emitting element LD emits light while electron-hole pairs are recombined in the active layer 12. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source (or light emitting source) of various light emitting devices (including pixels of a display device).

[0055] The second semiconductor layer 13 may be disposed on (or located on) the second surface of the active layer 12, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, or Ba. However, the material configuring the second semiconductor layer 13 is not limited thereto, and other various materials may configure the second semiconductor layer 13.

[0056] In an embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the length direction of the light emitting element LD. For example, the first semiconductor layer 11 may have a thickness relatively thicker than that of the second semiconductor layer 13 along the length direction of the light emitting element LD.

[0057] exist Figure 1 and Figure 2, although the first semiconductor layer 11 and the second semiconductor layer 13 are shown as being configured by one layer, the present disclosure is not limited thereto. In an embodiment, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one or more layers, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain release layer disposed between semiconductor layers having different lattice structures and used as a buffer for reducing the lattice constant difference. The TSBR layer may be configured by a p-type semiconductor layer such as p-GaInP, p-AlInP, and p-AlGaInP, but is not limited thereto.

[0058] According to an embodiment, in addition to the above-mentioned first semiconductor layer 11, active layer 12, and second semiconductor layer 13, the light emitting element LD may further include a contact electrode (hereinafter referred to as a "first contact electrode") disposed on the second semiconductor layer 13. In addition, according to another embodiment, the light emitting element LD may further include another contact electrode (hereinafter referred to as a "second contact electrode") disposed at one end of the first semiconductor layer 11.

[0059] Each of the first contact electrode and the second contact electrode may be an ohmic contact electrode, but is not limited thereto. According to an embodiment, the first contact electrode and the second contact electrode may be Schottky contact electrodes. The first contact electrode and the second contact electrode may include a conductive material. For example, the first contact electrode and the second contact electrode may include an opaque metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), its oxide, its alloy, etc., alone or in combination, but is not limited thereto. According to an embodiment, the first contact electrode and the second contact electrode may also include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). Zinc oxide (ZnO x ) can be zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0060] The materials included in the first contact electrode and the second contact electrode may be the same as or different from each other. The first contact electrode and the second contact electrode may be substantially transparent or translucent. Therefore, the light generated by the light emitting element LD may pass through each of the first contact electrode and the second contact electrode and may be emitted to the outside of the light emitting element LD. According to an embodiment, when the light generated by the light emitting element LD does not pass through the first contact electrode and the second contact electrode and is emitted to the outside of the light emitting element LD through an area other than both ends of the light emitting element LD, the first contact electrode and the second contact electrode may include an opaque metal.

[0061] In an embodiment, the light emitting element LD may further include an insulating film 14. However, according to an embodiment, the insulating film 14 may be omitted and may be provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0062] The insulating film 14 can prevent an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating film 14 can reduce or minimize surface defects of the light emitting element LD to improve the life and light emitting efficiency of the light emitting element LD. In addition, when a plurality of light emitting elements LD are closely arranged, the insulating film 14 can prevent an undesirable short circuit that may occur between the light emitting elements LD. When the active layer 12 can prevent a short circuit with an external conductive material, the presence or absence of the insulating film 14 is not limited.

[0063] The insulating film 14 may be provided in a form that completely surrounds the outer peripheral surface of the light emitting stack including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

[0064] In the above-described embodiment, the insulating film 14 completely surrounds the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but the present disclosure is not limited thereto. According to an embodiment, when the light emitting element LD includes a first contact electrode, the insulating film 14 may completely surround the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first contact electrode. In addition, according to another embodiment, the insulating film 14 may not completely surround the outer peripheral surface of the first contact electrode, or may surround only a portion of the outer peripheral surface of the first contact electrode and may not surround the rest of the outer peripheral surface of the first contact electrode. In addition, according to an embodiment, when the first contact electrode is provided at the first end EP1 of the light emitting element LD and the second contact electrode is provided at the second end EP2 of the light emitting element LD, the insulating film 14 may expose at least one region of each of the first contact electrode and the second contact electrode.

[0065] The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium oxide (TiO x ), hafnium oxide (HfO x ), titanium strontium oxide (SrTiO x ), cobalt oxide (Co x O y )、MgO、ZnOx ), ruthenium oxide (RuO x ), nickel oxide (NiO), tungsten oxide (WO x ), tantalum oxide (TaO x ), gadolinium oxide (GdO x ), zirconium oxide (ZrO x ), gallium oxide (GaO x ), vanadium oxide (V x O y )、ZnO:Al、ZnO:B、In x O y :H, niobium oxide (Nb x O y ), magnesium fluoride (MgF x ), aluminum fluoride (AlF x ), new aluminum-based (Alucone) polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN x ), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN) and vanadium nitride (VN), but the present disclosure is not limited thereto, and various materials with insulating properties can be used as the material of the insulating film 14.

[0066] The insulating film 14 may be provided in the form of a single layer, or may be provided in the form of a multilayer including a double layer. For example, when the insulating film 14 is formed of a double layer including a first layer and a second layer stacked in sequence, the first layer and the second layer may be formed of different materials (or substances) and may be formed in different processes. According to an embodiment, the first layer and the second layer may be formed by a continuous process by including the same material.

[0067] According to an embodiment, the light-emitting element LD may be implemented with a light-emitting pattern of a core-shell structure. In this case, the above-mentioned first semiconductor layer 11 may be positioned in the core (e.g., the middle (or center) of the light-emitting element LD), the active layer 12 may be arranged and / or formed in a form surrounding the outer peripheral surface of the first semiconductor layer 11, and the second semiconductor layer 13 may be arranged and / or formed in a form surrounding the outer peripheral surface of the active layer 12. In addition, the light-emitting element LD may further include a contact electrode (not shown) surrounding at least one side of the second semiconductor layer 13. In addition, according to an embodiment, the light-emitting element LD may further include an insulating film 14, which is arranged on the outer peripheral surface of the light-emitting pattern of the core-shell structure and includes a transparent insulating material. The light-emitting element LD implemented with the light-emitting pattern of the core-shell structure can be manufactured by a growth method.

[0068] The light-emitting unit (or light-emitting device) including the above-mentioned light-emitting element LD can be used as a light source (or light source) of various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light-emitting elements LD are mixed in a fluid solution (or solvent) and provided to each pixel area (for example, the emission area of ​​each pixel or the emission area of ​​each sub-pixel), each of the light-emitting elements LD can be subjected to surface treatment so that the light-emitting element LD can be uniformly sprayed without unevenly agglomerating in the solution.

[0069] The light-emitting unit (or light-emitting device) including the above-mentioned light-emitting element LD can be used in various types of electronic devices (including display devices) that require a light source. For example, when a plurality of light-emitting elements LD are provided in a pixel region of each pixel of a display panel, the light-emitting element LD can be used as a light source for each pixel. However, the application field of the light-emitting element LD is not limited to the above-mentioned example. For example, the light-emitting element LD can be used in other types of electronic devices such as lighting devices that require a light source.

[0070] Figure 3 is a schematic plan view showing a display device DD according to an embodiment.

[0071] exist Figure 3 , for convenience, the structure of the display device DD, for example, the display panel DP included in the display device DD, is schematically illustrated based on a display area DA displaying an image.

[0072] When the display device DD is an electronic device whose display surface is applied to at least one surface (such as a smart phone, TV, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, medical device, camera or wearable device), the present disclosure can be applied to the display device DD.

[0073] refer to Figures 1 to 3 According to a method of driving the light emitting element LD, the display device DD may be classified into a passive matrix type display device and an active matrix type display device. For example, when the display device DD is implemented as an active matrix type display device, each of the pixels PXL may include a driving transistor that controls the amount of current supplied to the light emitting element LD, a switching transistor that transmits a data signal to the driving transistor, and the like.

[0074] The display panel DP (or the display device DD) may include a substrate SUB and pixels PXL disposed on the substrate SUB. Each pixel PXL may include at least one light emitting element LD.

[0075] The substrate SUB may include a display area DA and a non-display area NDA.

[0076] The display area DA may be an area where pixels PXL displaying an image are disposed. The non-display area NDA may be an area where a driver for driving each pixel PXL and a plurality of lines electrically connecting each pixel PXL and the driver are disposed.

[0077] The non-display area NDA may be positioned adjacent to the display area DA. The non-display area NDA may be disposed on at least one side of the display area DA. For example, the non-display area NDA may surround the periphery (or edge) of the display area DA. Lines electrically connected to each pixel PXL and a driver electrically connected to the lines and driving the pixel PXL may be disposed in the non-display area NDA.

[0078] The line may electrically connect the driver and each pixel PXL. The line may include a fan-out line electrically connected to a signal line (e.g., a scan line, a data line, etc.) that provides a signal to the pixel PXL and is electrically connected to each pixel PXL. In addition, according to an embodiment, the line may include a fan-out line electrically connected to a signal line (e.g., a control line, a sensing line, etc.) connected to each pixel PXL to compensate for changes in the electrical characteristics of each pixel PXL in real time. In addition, the line may include a fan-out line electrically connected to a power line that provides a predetermined voltage to each pixel PXL and is electrically connected to each pixel PXL.

[0079] The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0080] The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0081] The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0082] One area of ​​the substrate SUB may be set as a display area DA, and thus the pixels PXL may be set. The remaining area of ​​the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area and a non-display area NDA arranged around the display area DA (or arranged to be adjacent to the display area DA), and each pixel PXL is arranged in the pixel area.

[0083] Each of the pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment, the pixels PXL may be arranged in a stripe arrangement structure or the like in the display area DA, but is not limited thereto.

[0084] Each of the pixels PXL may include a pixel circuit layer (refer to Figure 6 "PCL") and display component layer (reference Figure 6 “DPL”).

[0085] In the pixel circuit layer, a pixel circuit (refer to Figure 4 "PXC"). For example, each transistor may have a structure in which a semiconductor layer, a gate electrode, a first terminal, and a second terminal are stacked in sequence with an insulating layer interposed therebetween. The semiconductor layer may include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, an organic semiconductor, and / or an oxide semiconductor. The gate electrode, the first terminal (or source region), and the second terminal (or drain region) may include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but are not limited thereto. In addition, the pixel circuit layer may include at least one or more insulating layers.

[0086] The display element layer may be disposed on the pixel circuit layer. An emission component including a light emitting element LD that emits light (refer to Figure 4 The “EMU” of the display element layer DPL may be positioned in the display element layer DPL. A first alignment electrode (or a first alignment line) and a second alignment electrode (or a second alignment line) spaced apart from each other may be disposed in the light emitting unit. The light emitting element LD may be disposed between the first alignment electrode and the second alignment electrode. Figures 5 to 10 The configuration of each pixel PXL is described.

[0087] Each pixel PXL may include at least one light emitting element LD driven by corresponding scan signals and data signals. The light emitting element LD may have a size as small as nanometers (or nanometers) to micrometers (or micrometers), and may be connected in parallel with adjacently disposed light emitting elements, but the present disclosure is not limited thereto. The light emitting element LD may configure the light source of each pixel PXL.

[0088] Figure 4 It is shown Figure 3 Schematic circuit diagram of the electrical connection relationship between components included in each of the pixels PXL shown in FIG.

[0089] For example, Figure 4The electrical connection relationship between components included in the pixel PXL which can be applied to the active matrix type display device according to the embodiment is shown. However, the connection relationship between the components of each pixel PXL is not limited thereto.

[0090] refer to Figures 1 to 4 , the pixel PXL may include an emission component EMU (or an emission unit) that generates light of brightness corresponding to the data signal. In addition, the pixel PXL may include a pixel circuit PXC for driving the emission component EMU.

[0091] According to an embodiment, the emission component EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2, the first power line PL1 being electrically connected to a first driving power source VDD and being applied with a voltage of the first driving power source VDD, and the second power line PL2 being electrically connected to a second driving power source VSS and being applied with a voltage of the second driving power source VSS. For example, the emission component EMU may include a first electrode PE1 (or a first pixel electrode) electrically connected to the first driving power source VDD through a pixel circuit PXC and a first power line PL1, a second electrode PE2 (or a second pixel electrode) electrically connected to the second driving power source VSS through a second power line PL2, and light emitting elements LD electrically connected in parallel in the same direction between the first electrode PE1 and the second electrode PE2. In an embodiment, the first electrode PE1 may be an anode, and the second electrode PE2 may be a cathode.

[0092] Each of the light emitting elements LD included in the emission component EMU may include an end (or a first end EP1) electrically connected to a first driving power source VDD through a first electrode PE1 and another end (or a second end EP2) electrically connected to a second driving power source VSS through a second electrode PE2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. At this time, during the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage of the light emitting element LD or higher.

[0093] As described above, the respective light emitting elements LD electrically connected in parallel in the same direction (eg, forward direction) between the first electrode PE1 and the second electrode PE2 to which voltages of different power sources are supplied may configure corresponding effective light sources.

[0094] The light emitting element LD of the emission component EMU can emit light having a brightness corresponding to the driving current provided by the corresponding pixel circuit PXC. For example, during each frame period, a driving current corresponding to the grayscale value of the corresponding frame data of the pixel circuit PXC can be provided to the emission component EMU. The driving current provided to the emission component EMU can be divided and flow to each of the light emitting elements LD. Therefore, each of the light emitting elements LD can emit light having a brightness corresponding to the current flowing through the light emitting element LD, and thus the emission component EMU can emit light having a brightness corresponding to the driving current.

[0095] An embodiment is described in which both ends EP1 and EP2 of the light-emitting element LD are electrically connected in the same direction between the first driving power source VDD and the second driving power source VSS, but the present disclosure is not limited thereto. According to an embodiment, in addition to the light-emitting element LD configuring each effective light source, the emission component EMU may also include at least one invalid light source, for example, a reverse light-emitting element LDr. The reverse light-emitting element LDr may be electrically connected in parallel between the first electrode PE1 and the second electrode PE2 together with the light-emitting element LD configuring the effective light source, and may be electrically connected between the first electrode PE1 and the second electrode PE2 in a direction opposite to that of the light-emitting element LD. Even if a predetermined driving voltage (for example, a driving voltage in the forward direction) is applied between the first electrode PE1 and the second electrode PE2, the reverse light-emitting element LDr remains in an inactive state, and therefore current substantially does not flow through the reverse light-emitting element LDr.

[0096] The pixel circuit PXC of the pixel PXL may be electrically connected to the scan line Si and the data line Dj. In addition, the pixel circuit PXC of the pixel PXL may be electrically connected to the control line CLi and the sensing line SENj. For example, when the pixel PXL is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj, the i-th control line CLi, and the j-th sensing line SENj of the display area DA.

[0097] The pixel circuit PXC may include first, second and third transistors T1, T2 and T3 and a storage capacitor Cst.

[0098] The first transistor T1 may be a driving transistor for controlling a driving current applied to the emission component EMU, and may be electrically connected between the first driving power supply VDD and the emission component EMU. For example, the first terminal of the first transistor T1 may be electrically connected to the first driving power supply VDD through the first power line PL1, the second terminal of the first transistor T1 may be electrically connected to the second node N2, and the gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied from the first driving power supply VDD to the emission component EMU through the second node N2 according to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, but the present disclosure is not limited thereto. According to an embodiment, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0099] The second transistor T2 may be a switching transistor that selects the pixel PXL in response to the scan signal and activates the pixel PXL, and may be electrically connected between the data line Dj and the first node N1. The first terminal of the second transistor T2 may be electrically connected to the data line Dj, the second terminal of the second transistor T2 may be electrically connected to the first node N1, and the gate electrode of the second transistor T2 may be electrically connected to the scan line Si. The first terminal and the second terminal of the second transistor T2 may be different terminals. For example, when the first terminal is a drain electrode, the second terminal may be a source electrode.

[0100] When a scan signal of a gate-on voltage (e.g., a high level voltage) is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj and the first node N1. The first node N1 may be a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are electrically connected, and the second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0101] The third transistor T3 may electrically connect the first transistor T1 to the sensing line SENj to obtain a sensing signal through the sensing line SENj, and detect the characteristics of the pixel PXL including the threshold voltage of the first transistor T1, etc. using the sensing signal. Information about the characteristics of the pixel PXL may be used to convert image data, so that characteristic deviations between the pixels PXL may be compensated. The second terminal of the third transistor T3 may be electrically connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 may be electrically connected to the sensing line SENj, and the gate electrode of the third transistor T3 may be electrically connected to the control line CLi. In addition, the first terminal of the third transistor T3 may be electrically connected to an initialization power supply. The third transistor T3 may be an initialization transistor capable of initializing the second node N2, and may be turned on when a sensing control signal is provided from the control line CLi to transmit the voltage of the initialization power supply to the second node N2. Therefore, the second storage electrode electrically connected to the second node N2 of the storage capacitor Cst may be initialized.

[0102] The storage capacitor Cst may include a first storage electrode (or lower electrode) and a second storage electrode (or upper electrode). The first storage electrode of the storage capacitor Cst may be electrically connected to the first node N1, and the second storage electrode of the storage capacitor Cst may be electrically connected to the second node N2. The storage capacitor Cst is charged with a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a voltage difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0103] exist Figure 4 In the embodiment, all parallel electrical connections in the light emitting elements LD of the emission component EMU are disclosed, but the present disclosure is not limited thereto. According to the embodiment, the emission component EMU can be configured to include at least one series stage (or stage), which includes a plurality of light emitting elements LD electrically connected in parallel to each other. For example, the emission component EMU can be configured as a series / parallel hybrid structure.

[0104] exist Figure 4 In the embodiment, all of the first transistor T1, the second transistor T2, and the third transistor T3 included in the pixel circuit PXC are N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a P-type transistor. In addition, Figure 4 In the embodiment, an emission component EMU is disclosed in which it is electrically connected between the pixel circuit PXC and the second driving power source VSS, but the emission component EMU may be electrically connected between the first driving power source VDD and the pixel circuit PXC.

[0105] The structure of the pixel circuit PXC may be variously changed and implemented. For example, the pixel circuit PXC may further include a transistor for initializing the first node N1 and / or a transistor for controlling the emission time of the light emitting element LD, or other circuit elements such as a boost capacitor for boosting the voltage of the first node N1.

[0106] In the following embodiments, for ease of description, the horizontal direction (or X-axis direction) on the plane is represented as a first direction DR1, the vertical direction (or Y-axis direction) on the plane is represented as a second direction DR2, and the vertical direction of the plane is represented as a third direction DR3.

[0107] Figure 5 It is schematically shown Figure 3 A plan view of a pixel PXL is shown in FIG.

[0108] exist Figure 5 , for the sake of convenience, a transistor electrically connected to the light emitting element LD and a signal line electrically connected to the transistor are omitted.

[0109] In the following embodiments, not only Figure 5 The components in the pixel PXL shown in FIG. 1 and the region in which the components are disposed (or located) are collectively referred to as the pixel PXL.

[0110] refer to Figures 1 to 5 The pixel PXL may be positioned in a pixel area PXA disposed (or provided) on a substrate SUB. The pixel area PXA may include an emission area EMA and a non-emission area NEA.

[0111] The pixel PXL may include a first bank BNK1 positioned in the non-emission area NEA and a light emitting element LD positioned in the emission area EMA.

[0112] The first bank BNK1 may be a structure that defines (or partitions) a pixel region (or emission area EMA) of each of the pixels PXL adjacent to each other, and may be, for example, a pixel defining layer.

[0113] In an embodiment, the first bank BNK1 may be a pixel defining layer or a dam structure that defines each emission region EMA to which the light emitting element LD is to be provided in a process of providing (or inputting) the light emitting element LD to the pixel PXL. For example, the emission region EMA of the pixel PXL may be separated by the first bank BNK1, and thus a mixed solution (e.g., ink) including a desired amount and / or type of the light emitting element LD may be provided (or injected) to the emission region EMA. According to an embodiment, the first bank BNK1 may be a pixel defining layer or a dam structure that is finally defined in providing the color conversion layer (refer to FIG. 1 ) to the pixel PXL. Figure 6In the process of manufacturing a color conversion layer (“CCL”), a pixel defining layer for each emission area EMA of a color conversion layer CCL is to be provided.

[0114] According to an embodiment, the first bank BNK1 may be configured to include at least one light blocking material and / or reflective material (or scattering material) to prevent a light leakage defect in which light (or light) leaks between the pixel PXL and the pixel PXL adjacent thereto. According to an embodiment, the first bank BNK1 may include a transparent material (or substance). The transparent material may include, for example, a polyamide resin, a polyimide resin, etc., but is not limited thereto. According to another embodiment, a material layer may be separately provided and / or formed on the first bank BNK1 to further improve the efficiency of light emitted from the pixel PXL.

[0115] The first bank BNK1 may include at least one opening OP exposing a configuration positioned below the first bank BNK1 in the pixel area PXA. For example, the first bank BNK1 may include a first opening OP1 and a second opening OP2 exposing a configuration positioned below the first bank BNK1 in the pixel area PXA. In an embodiment, the emission area EMA of the pixel PXL and the first opening OP1 of the first bank BNK1 may correspond to each other.

[0116] In the pixel area PXA, the second opening OP2 may be positioned to be spaced apart from the first opening OP1, and may be positioned adjacent to one side (e.g., the upper side) of the pixel area PXA in a plan view. In an embodiment, the second opening OP2 may be an electrode separation region in which at least one alignment electrode ALE is separated from at least one alignment electrode ALE provided to the pixel PXL adjacent in the second direction DR2, but is not limited thereto.

[0117] The pixel PXL may include an alignment electrode ALE, an electrode PE disposed at least in the emission area EMA, a light emitting element LD electrically connected to the electrode PE, and a bank pattern BNP disposed at a position corresponding to the electrode PE. For example, the pixel PXL may include a first alignment electrode ALE1 and a second alignment electrode ALE2, a light emitting element LD, a first bank pattern BNP1 and a second bank pattern BNP2, and a first electrode PE1 and a second electrode PE2 disposed at least in the emission area EMA. The number, shape, size, arrangement structure, etc. of each of the electrodes PE and / or the alignment electrodes ALE may be variously changed according to the structure of the pixel PXL (e.g., the emission component EMU).

[0118] In an embodiment, the bank pattern BNP, the alignment electrode ALE, the light emitting element LD, and the electrode PE may be sequentially arranged based on one surface of the substrate SUB on which the pixel PXL is arranged, but is not limited thereto. According to an embodiment, the position and shape order of the electrode patterns configuring the pixel PXL (or the emission element EMU) may be variously changed. Figures 6 to 10 The stack structure of the pixel PXL is described.

[0119] The bank patterns BNP may be provided at least in the emission area EMA and may be spaced apart from each other in the first direction DR1 in the emission area EMA, and each of the bank patterns BNP may extend along the second direction DR2. The bank patterns BNP may include first and second bank patterns BNP1 and BNP2 arranged to be spaced apart from each other in the first direction DR1.

[0120] Each bank pattern BNP (also referred to as a “wall pattern”, “protrusion pattern”, “support pattern” or “wall structure”) may have a uniform width in the emission area EMA. For example, when viewed in a plan view, each of the first bank pattern BNP1 and the second bank pattern BNP2 may have a rod shape having a predetermined width along a direction in which each of the first bank pattern BNP1 and the second bank pattern BNP2 extends in the emission area EMA, but is not limited thereto.

[0121] The dam pattern BNP can support each of the first alignment electrode ALE1 and the second alignment electrode ALE2 to change the surface profile (or shape) of each of the first alignment electrode ALE1 and the second alignment electrode ALE2, thereby guiding the light emitted from the light emitting element LD to the image display direction (or front surface direction) of the display device DD.

[0122] The bank patterns BNP may have the same or different widths. For example, the first bank pattern BNP1 and the second bank pattern BNP2 may have the same width or different widths in the first direction DR1 at least in the emission area EMA.

[0123] Each of the first bank pattern BNP1 and the second bank pattern BNP2 may partially overlap at least one alignment electrode ALE in the emission area EMA. For example, the first bank pattern BNP1 may be positioned below the first alignment electrode ALE1 so as to overlap with a region of the first alignment electrode ALE1, and the second bank pattern BNP2 may be positioned below the second alignment electrode ALE2 so as to overlap with a region of the second alignment electrode ALE2. The bank pattern BNP may be a structure that, together with the alignment electrode ALE, precisely defines (or defines) the alignment position of the light emitting element LD in the emission area EMA of the pixel PXL.

[0124] Since the bank pattern BNP is disposed under one region of each of the alignment electrodes ALE in the emission area EMA, one region of each of the alignment electrodes ALE may protrude upwardly from the pixel PXL in the region where the bank pattern BNP is formed. Therefore, the bank pattern BNP as a wall structure may be formed around the light emitting element LD. For example, the wall structure may be formed in the emission area EMA to face the first end EP1 and the second end EP2 of the light emitting element LD.

[0125] In an embodiment, when the bank pattern BNP and / or the alignment electrode ALE include a reflective material, a reflective wall structure may be formed around the light emitting element LD. Therefore, since the light emitted from the light emitting element LD is directed to the upper direction of the pixel PXL (e.g., the image display direction of the display device DD), the light output efficiency of the pixel PXL may be improved.

[0126] The alignment electrodes ALE may be positioned at least in the emission area EMA and may be spaced apart from each other along the first direction DR1 in the emission area EMA, and each of the alignment electrodes ALE may extend in the second direction DR2. The alignment electrodes ALE may include first and second alignment electrodes ALE1 and ALE2 arranged to be spaced apart from each other in the first direction DR1.

[0127] During the manufacturing process of the pixel PXL (or the display device DD), after the light emitting element LD is provided and aligned in the pixel area PXA, at least one of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be separated from the other electrode (e.g., the alignment electrode ALE provided to each of the adjacent pixels PXL adjacent in the second direction DR2) in the second opening OP2 (or the electrode separation region) of the first bank BNK1. For example, one end of the first alignment electrode ALE1 may be separated from the first alignment electrode ALE1 of the pixel PXL positioned on the upper side of the corresponding pixel PXL in the second direction DR2 in the second opening OP2.

[0128] The first alignment electrode ALE1 may be electrically connected to the reference electrode through the first contact portion CNT1 Figure 4 The first contact portion CNT1 may be formed by removing a portion of at least one insulating layer positioned between the first alignment electrode ALE1 and the pixel circuit PXC, and a portion of the configuration of the pixel circuit PXC may be exposed by the first contact portion CNT1. The second alignment electrode ALE2 may be electrically connected to the reference electrode PXC through the second contact portion CNT2. Figure 4The second power line PL2 (or the second driving power source VSS) is described. The second contact portion CNT2 may be formed by removing a portion of at least one insulating layer positioned between the first alignment electrode ALE1 and the second power line PL2, and a portion of the second power line PL2 may be exposed by the second contact portion CNT2.

[0129] In an embodiment, the first and second contact portions CNT1 and CNT2 may be positioned in the non-emission area NEA to overlap the first bank BNK1. However, the present disclosure is not limited thereto, and according to an embodiment, the first and second contact portions CNT1 and CNT2 may be positioned in the emission area EMA or in the second opening OP2 of the first bank BNK1.

[0130] The first alignment electrode ALE1 may be electrically connected to the first electrode PE1 through the first contact hole CH1 in the second opening OP2 of the first bank BNK1. The second alignment electrode ALE2 may be electrically connected to the second electrode PE2 through the second contact hole CH2 in the second opening OP2 of the first bank BNK1.

[0131] In the alignment step of the light emitting element LD, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may receive a predetermined signal (or a predetermined alignment signal) from an alignment pad (not shown) positioned in the non-display area NDA. For example, the first alignment electrode ALE1 may receive a first alignment signal (or a first alignment voltage) from the first alignment pad, and the second alignment electrode ALE2 may receive a second alignment signal (or a second alignment voltage) from the second alignment pad. The above-mentioned first alignment signal and the second alignment signal may be signals having a voltage difference and / or a phase difference to the extent that the light emitting element LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. At least one of the first alignment signal and the second alignment signal may be an AC signal, but is not limited thereto.

[0132] Each of the alignment electrodes ALE may be arranged in a rod shape (or a "|" shape) having a constant width along the second direction DR2, but is not limited thereto. According to an embodiment, each of the alignment electrodes ALE may or may not have a bent portion in the second opening OP2 as an electrode separation region of the non-emission area NEA and / or the first bank BNK1. The shape and / or size of each of the alignment electrodes ALE in the remaining regions except the emission region EMA is not particularly limited, and various changes may be made.

[0133] At least two to tens of light emitting elements LD may be aligned and / or disposed in the emission area EMA (or pixel area PXA), but the number of light emitting elements LD is not limited thereto. According to an embodiment, the number of light emitting elements LD aligned and / or disposed in the emission area EMA (or pixel area PXA) may be variously changed.

[0134] Each of the light emitting elements LD may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2. When viewed in a plan view, each of the light emitting elements LD may include a first end EP1 and a second end EP2 positioned at both ends (or facing each other) in a length direction thereof (e.g., in the first direction DR1). In an embodiment, the second semiconductor layer (refer to FIG. 1 ) including a p-type semiconductor layer Figure 1 13) may be positioned at the first end EP1 (or the p-type end), and may include a first semiconductor layer (reference Figure 1 '11') can be positioned at the second end EP2 (or the n-type end).

[0135] The light emitting elements LD may be arranged to be spaced apart from each other and may be aligned substantially parallel to each other. The distance at which the light emitting elements LD are spaced apart is not particularly limited. According to an embodiment, a plurality of light emitting elements LD may be arranged adjacent to each other to form a group, and a plurality of other light emitting elements LD may form a group in a state where the plurality of other light emitting elements LD are spaced apart from each other by a constant distance, may have a non-uniform density, and may be aligned in one direction.

[0136] The light emitting element LD may be input (or provided) to the pixel area PXA (or the emission area EMA) by an inkjet printing method, a slit coating method, or other various methods. For example, the light emitting element LD may be mixed with a volatile solvent and input (or provided) to the pixel area PXA by an inkjet printing method, a slit coating method, or the like. In the case where an alignment signal corresponding to each of the first alignment electrode ALE1 and the second alignment electrode ALE2 is applied, an electric field may be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2. Therefore, the light emitting element LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. By volatilizing the solvent after aligning the light emitting element LD or removing the solvent by another method, the light emitting element LD may be stably aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0137] The electrode PE (or pixel electrode) may be disposed at least in the emission area EMA, and each of the electrodes PE (or pixel electrodes) may be disposed at a position corresponding to at least one alignment electrode ALE and a light emitting element LD. For example, each electrode PE may be formed on each alignment electrode ALE and a corresponding light emitting element LD to overlap with each alignment electrode ALE and a corresponding light emitting element LD, and may be electrically connected to at least the light emitting element LD.

[0138] The electrode PE may include a first electrode PE1 and a second electrode PE2 disposed to be spaced apart from each other.

[0139] The first electrode PE1 ("first pixel electrode" or "anode") may be formed on the first alignment electrode ALE1 and the first end EP1 of each of the light emitting elements LD to be electrically connected to the first end EP1 of each of the light emitting elements LD. In addition, the first electrode PE1 may directly contact the first alignment electrode ALE1 through the first contact hole CH1 at least in the non-emission area NEA (for example, in the second opening OP2 of the first bank BNK1 as an electrode separation area) to be electrically and / or physically connected to the first alignment electrode ALE1. The first contact hole CH1 may be formed by removing a portion of at least one insulating layer positioned between the first electrode PE1 and the first alignment electrode ALE1, and a portion of the first alignment electrode ALE1 may be exposed by the first contact hole CH1. The first contact hole CH1 as a connection point (or contact point) between the first electrode PE1 and the first alignment electrode ALE1 is positioned in the second opening OP2 of the first bank BNK1 as an electrode separation area of ​​the non-emission area NEA, but the present disclosure is not limited thereto. According to an embodiment, the connection point (or contact point) between the first electrode PE1 and the first alignment electrode ALE1 may be positioned in the emission area EMA of the pixel PXL.

[0140] The pixel circuit PXC, the first alignment electrode ALE1, and the first electrode PE1 may be electrically connected to each other through the first contact portion CNT1 and the first contact hole CH1.

[0141] In the above-described embodiment, the first alignment electrode ALE1 and the first electrode PE1 are directly contacted through the first contact hole CH1 to be connected, but the present disclosure is not limited thereto. According to an embodiment, in order to prevent defects due to the material properties of the first alignment electrode ALE1, the first electrode PE1 may not directly contact the first alignment electrode ALE1, and may directly contact the pixel circuit PXC to be electrically connected to the pixel circuit PXC.

[0142] The first electrode PE1 may have a rod shape extending in the second direction DR2, but is not limited thereto. According to an embodiment, the shape of the first electrode PE1 may be variously changed within a range in which the first electrode PE1 is stably electrically and / or physically connected to the first end EP1 of the light emitting element LD1. In addition, the shape of the first electrode PE1 may be variously changed in consideration of the arrangement, connection relationship, etc. with the first alignment electrode ALE1 disposed thereunder.

[0143] The second electrode PE2 ("second pixel electrode" or "cathode") may be formed on the second end EP2 of each of the second alignment electrode ALE2 and the light emitting element LD to be electrically connected to the second end EP2 of each of the light emitting elements LD. In addition, the second electrode PE2 may directly contact the second alignment electrode ALE2 through the second contact hole CH2 to be electrically and / or physically connected to the second alignment electrode ALE2. The second contact hole CH2 may be formed by removing a portion of at least one insulating layer positioned between the second electrode PE2 and the second alignment electrode ALE2, and a portion of the second alignment electrode ALE2 may be exposed by the second contact hole CH2. According to an embodiment, the second contact hole CH2, which is a connection point (or contact point) between the second electrode PE2 and the second alignment electrode ALE2, may be positioned in the second opening OP2 of the electrode separation region of the first bank BNK1 as the non-emission region NEA, but the present disclosure is not limited thereto. According to an embodiment, the connection point (or contact point) between the second electrode PE2 and the second alignment electrode ALE2 may be positioned in the emission region EMA of the pixel PXL.

[0144] The second power line PL2 , the second alignment electrode ALE2 , and the second electrode PE2 may be electrically connected to each other through the second contact portion CNT2 and the second contact hole CH2 .

[0145] In the above-described embodiment, the second alignment electrode ALE2 and the second electrode PE2 are directly contacted through the second contact hole CH2 to be connected, but the present disclosure is not limited thereto. According to an embodiment, in order to prevent defects due to the material properties of the second alignment electrode ALE2, the second electrode PE2 may not directly contact the second alignment electrode ALE2, and may directly contact the second power line PL2 to be electrically connected to the second power line PL2.

[0146] The second electrode PE2 may have a rod shape extending in the second direction DR2, but is not limited thereto. According to an embodiment, the shape of the second electrode PE2 may be variously changed within the range that the second electrode PE2 is stably electrically and / or physically connected to the second end EP2 of the light emitting element LD. In addition, the shape of the second electrode PE2 may be variously changed in consideration of the arrangement, connection relationship, etc. with the second alignment electrode ALE2 disposed thereunder.

[0147] In the following, reference Figures 6 to 10 The stack structure of the pixel PXL according to the above-described embodiment is described.

[0148] Figure 6 It is along Figure 5 A schematic cross-sectional view taken along line I to I' of FIG. Figure 7 It is along Figure 5 A schematic cross-sectional view taken along line II to II', Figure 8 It is along Figure 5 A cross-sectional view taken along line III to III', and Fig. 9 and Fig.10 It is shown Figure 7 Schematic enlargement of the EA part.

[0149] Fig.10 Shows Fig. 9 A modified embodiment of the embodiment regarding the cover layer CVL, etc.

[0150] exist Figures 6 to 10 In the embodiment, the stack structure of the pixel PXL is simplified, such as illustrating each electrode as a single-layer electrode and illustrating each insulating layer as only a single-layer insulating layer, but is not limited thereto.

[0151] To avoid Figures 6 to 10 The overlapping description of the implementation method of the embodiment mainly describes the points different from the above-mentioned implementation method.

[0152] refer to Figures 1 to 10 , the pixel PXL may include a substrate SUB, a pixel circuit layer PCL and a display element layer DPL.

[0153] The pixel circuit layer PCL and the display element layer DPL may be arranged to overlap each other in a third direction DR3 on one surface of the substrate SUB. For example, the display area DA of the substrate SUB may include a pixel circuit layer PCL arranged on one surface of the substrate SUB and a display element layer DPL arranged on the pixel circuit layer PCL. However, the relative positions of the pixel circuit layer PCL and the display element layer DPL on the substrate SUB may vary depending on the implementation. When the pixel circuit layer PCL and the display element layer DPL are separated and overlap as separate layers, each layout space for forming the pixel circuit PXC and the emission component EMU in each layer can be fully ensured.

[0154] The substrate SUB may include a transparent insulating material to transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0155] In each pixel region PXA of the pixel circuit layer PCL, a circuit element (e.g., transistor T) configuring the pixel circuit PXC of the corresponding pixel PXL and a predetermined signal line electrically connected to the circuit element may be provided. In addition, in each pixel region PXA of the display element layer DPL, an alignment electrode ALE, a light emitting element LD, and / or an electrode PE configuring the emission element EMU of the corresponding pixel PXL may be provided.

[0156] In addition to the circuit elements and the signal lines, the pixel circuit layer PCL may include at least one insulating layer. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and a via layer VIA sequentially stacked on the substrate SUB along the third direction DR3.

[0157] The buffer layer BFL may be completely disposed on the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into transistors included in the pixel circuit PXC. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). The buffer layer BFL may be set as a single layer, but may also be set as a multilayer of at least two layers. When the buffer layer BFL is set as a multilayer, each layer may be formed of the same material or may be formed of different materials. Depending on the material of the substrate SUB, process conditions, etc., the buffer layer BFL may be omitted.

[0158] The gate insulating layer GI may be completely disposed on the buffer layer BFL. The gate insulating layer GI may include the same material as the above-described buffer layer BFL, or may include a suitable material from among the materials exemplified as the configuration material of the buffer layer BFL (or a material selected from among the materials exemplified as the configuration material of the buffer layer BFL). For example, the gate insulating layer GI may be an inorganic insulating layer including an inorganic material.

[0159] The interlayer insulating layer ILD may be completely disposed and / or formed on the gate insulating layer GI. The interlayer insulating layer ILD may include the same material as the buffer layer BFL, or may include suitable one or more materials from among the materials exemplified as the configuration materials of the buffer layer BFL (or one or more materials selected from among the materials exemplified as the configuration materials of the buffer layer BFL).

[0160] The passivation layer PSV may be completely disposed and / or formed on the interlayer insulating layer ILD. The passivation layer PSV may include the same material as the buffer layer BFL, or may include one or more suitable materials from among the materials exemplified as the configuration materials of the buffer layer BFL (or one or more materials selected from among the materials exemplified as the configuration materials of the buffer layer BFL).

[0161] The via layer VIA may be completely disposed and / or formed on the passivation layer PSV. The via layer VIA may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x The organic insulating layer may include, for example, at least one of acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0162] In an embodiment, the via layer VIA may be used as a planarization layer for alleviating a step difference generated by the configuration of the pixel circuit PXC positioned below the via layer VIA in the pixel circuit layer PCL.

[0163] The pixel circuit layer PCL may include at least one conductive layer disposed between the above-mentioned insulating layers. For example, the pixel circuit layer PCL may include a first conductive layer disposed between the substrate SUB and the buffer layer BFL, a second conductive layer disposed on the gate insulating layer GI, a third conductive layer disposed on the interlayer insulating layer ILD, and a fourth conductive layer disposed on the passivation layer PSV. However, the insulating layer and the conductive layer are not limited to the above-mentioned embodiments, and according to an embodiment, another insulating layer and another conductive layer other than the insulating layer and the conductive layer may be disposed in the pixel circuit layer PCL.

[0164] The first conductive layer may be formed as a single layer including copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), or an alloy thereof alone or as a single layer including a mixture of these materials, or may be formed as a double layer or multilayer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low resistance material to reduce line resistance. Each of the second to fourth conductive layers may include the same material as the first conductive layer, or may include suitable one or more materials from the configuration materials exemplified as the first conductive layer, but is not limited thereto.

[0165] The pixel circuit PXC provided in the pixel circuit layer PCL may include at least one transistor T. For example, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 electrically connected to the first transistor T1. However, the present disclosure is not limited thereto, and the pixel circuit PXC may further include a circuit element that performs another function in addition to the first transistor T1 and the second transistor T2. The first transistor T1 may have a Figure 4 The first transistor T1 has the same configuration as described above, and the second transistor T2 may have the same configuration as described above. Figure 4 In the following embodiments, when the first transistor T1 and the second transistor T2 are collectively referred to, the first transistor T1 and the second transistor T2 are referred to as transistors T.

[0166] The transistor T may include a semiconductor pattern and a gate electrode GE overlapping at least a portion of the semiconductor pattern in the third direction DR3. The semiconductor pattern may include a channel region ACT, a first contact region SE, and a second contact region DE. The first contact region SE may be a source region, and the second contact region DE may be a drain region.

[0167] The gate electrode GE may be disposed and / or formed on the gate insulating layer GI to correspond to the channel region ACT of the semiconductor pattern. For example, the gate electrode GE may be a second conductive layer positioned between the gate insulating layer GI and the interlayer insulating layer ILD. The gate electrode GE may be disposed on the gate insulating layer GI to overlap with the channel region ACT of the semiconductor pattern.

[0168] The semiconductor pattern may be disposed and / or formed on the buffer layer BFL. The channel region ACT, the first contact region SE, and the second contact region DE may be semiconductor patterns formed of polycrystalline silicon or amorphous silicon, an oxide semiconductor, or the like. The channel region ACT, the first contact region SE, and the second contact region DE may be formed of a semiconductor layer that is not doped with impurities or is doped with impurities. For example, the first contact region SE and the second contact region DE may be formed of a semiconductor layer that is not doped with impurities, and the channel region ACT may be formed of a semiconductor layer that is not doped with impurities. As the impurity, for example, an n-type impurity may be used, but is not limited thereto.

[0169] The channel region ACT may overlap the gate electrode GE of the corresponding transistor T in the third direction DR3. For example, the channel region ACT of the first transistor T1 may overlap the gate electrode GE of the first transistor T1, and the channel region ACT of the second transistor T2 may overlap the gate electrode GE of the second transistor T2.

[0170] The first contact region SE of the first transistor T1 may be connected to (or in contact with) one end of the channel region ACT of the first transistor T1. In addition, the first contact region SE of the first transistor T1 may be connected to the bridge pattern BRP through the first connection member TE1.

[0171] The first connection member TE1 may be disposed and / or formed on the interlayer insulating layer ILD. For example, the first connection member TE1 may be formed of a third conductive layer. One end of the first connection member TE1 may be electrically connected and / or physically connected to the first contact region SE of the first transistor T1 through a contact hole that sequentially passes through the interlayer insulating layer ILD and the gate insulating layer GI. In addition, the other end of the first connection member TE1 may be electrically connected and / or physically connected to the bridge pattern BRP through a contact hole that passes through the passivation layer PSV positioned on the interlayer insulating layer ILD.

[0172] The bridge pattern BRP may be disposed and / or formed on the passivation layer PSV. For example, the bridge pattern BRP may be formed by a fourth conductive layer. One end of the bridge pattern BRP may be connected to the first contact region SE of the first transistor T1 through the first connection member TE1. In addition, the other end of the bridge pattern BRP may be electrically connected and / or physically connected to the lower metal layer BML through a contact hole that sequentially passes through the passivation layer PSV, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL. The lower metal layer BML and the first contact region SE of the first transistor T1 may be electrically connected to each other through the bridge pattern BRP and the first connection member TE1.

[0173] According to an embodiment, the bridge pattern BRP may be electrically connected to a partial configuration of the display element layer DPL, for example, the first alignment electrode ALE1 , through a contact hole passing through the via layer VIA.

[0174] The lower metal layer BML may be a first conductive layer disposed on the substrate SUB. The lower metal layer BML may be electrically connected to the first transistor T1 to extend a driving range of a predetermined voltage provided to the gate electrode GE of the first transistor T1. For example, the lower metal layer BML may be electrically connected to the first contact region SE of the first transistor T1 to stabilize the channel region ACT of the first transistor T1. In addition, since the lower metal layer BML is electrically connected to the first contact region SE of the first transistor T1, floating of the lower metal layer BML may be prevented.

[0175] The second contact region DE of the first transistor T1 may be connected to (or in contact with) the other end of the channel region ACT of the first transistor T1. In addition, the second contact region DE of the first transistor T1 may be connected to (or in contact with) the second connection member TE2.

[0176] The second connection member TE2 may be disposed and / or formed on the interlayer insulating layer ILD. For example, the second connection member TE2 may be a third conductive layer. One end of the second connection member TE2 may be electrically and / or physically connected to the second contact region DE of the first transistor T1 through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0177] The first contact region SE of the second transistor T2 may be connected to one end of the channel region ACT of the second transistor T2 (or in contact with one end of the channel region ACT of the second transistor T2). In addition, although not directly shown in the drawings, the first contact region SE of the second transistor T2 may be electrically connected to the gate electrode GE of the first transistor T1. For example, the first contact region SE of the second transistor T2 may be electrically connected to the gate electrode GE of the first transistor T1 through another first connection member TE1. The another first connection member TE1 may be disposed and / or formed on the interlayer insulating layer ILD. For example, the another first connection member TE1 may be formed by a third conductive layer.

[0178] The second contact region DE of the second transistor T2 may be connected to the other end of the channel region ACT of the second transistor T2 (or in contact with the other end of the channel region ACT of the second transistor T2). In addition, although not directly shown in the drawings, the second contact region DE of the second transistor T2 may be electrically connected to the data line Dj. For example, the second contact region DE of the second transistor T2 may be electrically connected to the data line Dj through another second connection member TE2. The another second connection member TE2 may be disposed and / or formed on the interlayer insulating layer ILD. For example, the another second connection member TE2 may be formed by a third conductive layer.

[0179] In the above-described embodiment, the case where the transistor T is a thin film transistor having a top gate structure is described as an example, but the present disclosure is not limited thereto, and the structure of the transistor T may be variously changed.

[0180] A passivation layer PSV may be disposed and / or formed on the transistor T and the first and second connection members TE1 and TE2 .

[0181] The pixel circuit layer PCL may include a predetermined power line disposed and / or formed on the passivation layer PSV. For example, the pixel circuit layer PCL may include a second power line PL2 disposed on the passivation layer PSV. The second power line PL2 may be formed by a fourth conductive layer. A voltage of a second driving power source VSS may be applied to the second power line PL2. Figures 6 to 10 Although not directly shown, the pixel circuit layer PCL may also include a reference Figure 4The first power line PL1 is described. The first power line PL1 may be formed in the same process as the second power line PL2 and disposed on the same layer as the second power line PL2, or may be formed in a process different from that of the second power line PL2 and disposed on a layer different from that of the second power line PL2. However, the present disclosure is not limited thereto.

[0182] The via layer VIA may be disposed and / or formed on the bridge pattern BRP and the second power line PL2. The via layer VIA may be partially opened to include a first contact portion CNT1 exposing a portion of the bridge pattern BRP and a second contact portion CNT2 exposing a portion of the second power line PL2.

[0183] The display element layer DPL may be disposed and / or formed on the via layer VIA.

[0184] The display element layer DPL may include a bank pattern BNP, an alignment electrode ALE, a first bank BNK1, a light emitting element LD, and an electrode PE.

[0185] The bank pattern BNP may be positioned on the via layer VIA. For example, the bank pattern BNP may protrude in the third direction DR3 on one surface of the via layer VIA. Therefore, a region of the alignment electrode ALE disposed on the bank pattern BNP may protrude in the third direction DR3 (or the thickness direction of the substrate SUB).

[0186] The bank pattern BNP may include an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to an embodiment, the bank pattern BNP may include a single-layer organic insulating layer and / or a single-layer organic insulating layer, but is not limited thereto. According to an embodiment, the bank pattern BNP may be provided in the form of a multilayer in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the material of the bank pattern BNP is not limited to the above-mentioned embodiment, and according to an embodiment, the bank pattern BNP may include a conductive material (or substance).

[0187] The bank pattern BNP may include a first bank pattern BNP1 and a second bank pattern BNP2. The first bank pattern BNP1 may be positioned under the first alignment electrode ALE1 at least in the emission area EMA and overlap the first alignment electrode ALE1 in the third direction DR3, and the second bank pattern BNP2 may be positioned under the second alignment electrode ALE2 at least in the emission area EMA and overlap the second alignment electrode ALE2 in the third direction DR3.

[0188] The embankment pattern BNP may have a cross section of a trapezoidal shape whose width narrows from the surface (e.g., upper surface) of the through hole layer VIA along the third direction DR3 toward the upper part, but is not limited thereto. According to an embodiment, the embankment pattern BNP may have a cross section of a semi-elliptical shape, a semicircular shape (or a hemispherical shape), etc. whose width narrows from the surface of the through hole layer VIA along the third direction DR3 toward the upper part. When observed in a cross section, the shape of the embankment pattern BNP is not limited to the above-mentioned embodiment, and various changes can be made within the range that the efficiency of light emitted from each of the light-emitting elements LD can be improved. In addition, according to an embodiment, at least one of the embankment patterns BNP may be omitted, or the position of at least one of the embankment patterns BNP may be changed.

[0189] The bank pattern BNP may be used as a reflective member. For example, the bank pattern BNP may be used together with the alignment electrode ALE disposed thereon to guide light emitted from each light emitting element LD to an image display direction of the display device DD to improve light output efficiency of the pixel PXL.

[0190] The alignment electrode ALE may be positioned on the bank pattern BNP.

[0191] The alignment electrodes ALE may be disposed on the same plane and may have the same thickness in the third direction DR3. The alignment electrodes ALE may be simultaneously formed in the same process.

[0192] The alignment electrode ALE may be formed of a material having reflectivity so as to allow light emitted from the light emitting element LD to travel in the image display direction (or the front surface direction) of the display device DD. For example, the alignment electrode ALE may be formed of a conductive material (or substance). The conductive material may include an opaque metal suitable for reflecting light emitted from the light emitting element LD in the image display direction of the display device DD. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) and alloys thereof. However, the material of the alignment electrode ALE is not limited to the above-mentioned embodiments. According to an embodiment, the alignment electrode ALE may include a transparent conductive material (or substance). The transparent conductive material (or substance) may include metals such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x), conductive oxides such as indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO), conductive polymers such as poly (3,4-ethylenedioxythiophene) (PEDOT), etc. When the alignment electrode ALE includes a transparent conductive material (or substance), a separate conductive layer formed of an opaque metal for reflecting light emitted from the light emitting element LD in the image display direction of the display device DD may be added. However, the material of the alignment electrode ALE is not limited to the above materials.

[0193] Each of the alignment electrodes ALE may be arranged and / or formed as a single layer, but is not limited thereto. According to an embodiment, each of the alignment electrodes ALE may be arranged and / or formed as a multilayer in which at least two or more of metals, alloys, conductive oxides, and conductive polymers are stacked. Each of the alignment electrodes ALE may be formed as a multilayer of at least two layers so as to minimize the distortion caused by signal delay when transmitting a signal (or voltage) to both ends (e.g., the first end EP1 and the second end EP2) of each of the light emitting elements LD. For example, each of the alignment electrodes ALE may be formed as a multilayer, which selectively further includes at least one reflective electrode layer, at least one transparent electrode layer arranged on and / or below the reflective electrode layer, and at least one conductive covering layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0194] As described above, when the alignment electrode ALE is formed of a conductive material having reflectivity, light emitted from both ends (eg, the first end EP1 and the second end EP2 ) of each of the light emitting elements LD may further proceed in the image display direction of the display device DD.

[0195] The first alignment electrode ALE1 may be electrically connected to the first transistor T1 of the pixel circuit layer PCL through the first contact portion CNT1 , and the second alignment electrode ALE2 may be electrically connected to the second power line PL2 of the pixel circuit layer PCL through the second contact portion CNT2 .

[0196] A first insulating layer INS1 may be disposed and / or formed on the alignment electrode ALE.

[0197] The first insulating layer INS1 may be disposed on the alignment electrode ALE and the via layer VIA. The first insulating layer INS1 may be partially opened at least in the non-emission area NEA to expose the configuration positioned thereunder. For example, the first insulating layer INS1 may be partially opened to include a first contact hole CH1 and a second contact hole CH2, the first contact hole CH1 exposing a portion of the first alignment electrode ALE1 by removing at least one region in the non-emission area NEA, and the second contact hole CH2 exposing a portion of the second alignment electrode ALE2 by removing at least another region in the non-emission area NEA. At least the non-emission area NEA may be the second opening OP2 of the first embankment BNK1 as an electrode separation area, but is not limited thereto.

[0198] The first insulating layer INS1 may be formed of an inorganic insulating layer (which is formed of an inorganic material). For example, the first insulating layer INS1 may be formed of an inorganic insulating layer suitable for protecting the light emitting element LD from the pixel circuit layer PCL. For example, the first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) of metal oxides. The first insulating layer INS1 may have a profile (or surface) corresponding to the profile of the configuration positioned thereunder. In this case, there may be an empty gap (or separation space) between each of the light emitting elements LD and the first insulating layer INS1. According to an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer (formed of an organic material).

[0199] The first insulating layer INS1 may be provided as a single layer or multiple layers. When the first insulating layer INS1 is provided as multiple layers, the first insulating layer INS1 may be provided as a distributed Bragg reflector (DBR) structure in which first and second inorganic layers having different refractive indices are alternately stacked.

[0200] The first insulating layer INS1 may be disposed entirely throughout the emission area EMA and the non-emission area NEA of each pixel PXL, but is not limited thereto. According to an embodiment, the first insulating layer INS1 may be positioned only in a specific area (eg, the emission area EMA) of each pixel PXL.

[0201] The first bank BNK1 may be disposed on the first insulating layer INS1.

[0202] The first bank BNK1 may be disposed on the first insulating layer INS1 at least in the non-emission area NEA, but is not limited thereto. The first bank BNK1 may configure a pixel defining layer formed between adjacent pixels PXL so as to partition (or define) the emission area EMA of the corresponding pixel PXL around the emission area EMA of each pixel PXL. The first bank BNK1 may be a dam structure that prevents a solution (or ink) in which the light emitting element LD is mixed from flowing into the emission area EMA of an adjacent pixel PXL or controls so that a certain amount of solution is provided to each emission area EMA.

[0203] The first bank BNK1 and the bank pattern BNP may be formed in different processes and disposed on different layers, but are not limited thereto. According to an embodiment, the first bank BNK1 and the bank pattern BNP may be formed in different processes and disposed on the same layer, or may be formed in the same process and disposed on the same layer.

[0204] The light emitting element LD may be provided and aligned in the emission area EMA of the pixel PXL in which the first insulating layer INS1 and the first bank BNK1 are formed. For example, the light emitting element LD may be provided (or input) to the emission area EMA by an inkjet printing method or the like, and the light emitting element LD may be aligned between the alignment electrodes ALE by an electric field formed by a predetermined signal (or alignment signal) applied to each of the alignment electrodes ALE. For example, the light emitting element LD may be aligned on the first insulating layer INS1 between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0205] A second insulating layer INS2 (or insulating pattern) may be disposed on each of the light emitting elements LD. The second insulating layer INS2 may be positioned on the light emitting element LD and may partially cover an outer peripheral surface (or surface) of each of the light emitting elements LD to expose the first end EP1 and the second end EP2 of each of the light emitting elements LD.

[0206] The second insulating layer INS2 may include an organic insulating layer or an inorganic insulating layer including an inorganic material. For example, the second insulating layer INS2 may include an inorganic insulating layer suitable for protecting the active layer 12 of each of the light emitting elements LD from external oxygen and moisture. However, the present disclosure is not limited thereto, and the second insulating layer INS2 may be formed of an organic insulating layer including an organic material according to design conditions of a display device DD (or display panel DP) to which the light emitting element LD is applied, etc. The second insulating layer INS2 may be configured as a single layer or a multilayer.

[0207] When there is a gap between the first insulating layer INS1 and the light emitting element LD before forming the second insulating layer INS2 , the gap may be filled with the second insulating layer INS2 in a process of forming the second insulating layer INS2 .

[0208] By forming the second insulating layer INS2 on the aligned light emitting element LD in the emission area EMA of each pixel PXL, the light emitting element LD may be prevented from being separated from the aligned position.

[0209] The electrode PE may be formed on both ends of the light emitting element LD not covered by the second insulating layer INS2 , for example, on the first end EP1 and the second end EP2 . The electrode PE may include a first electrode PE1 and a second electrode PE2 .

[0210] At least in the emission area EMA, the first electrode PE1 may be disposed on the first insulating layer INS1 on the first alignment electrode ALE1 and the first end EP1 of each of the light emitting elements LD. The first electrode PE1 may be connected to the first alignment electrode ALE1 through a first contact hole CH1 of the first insulating layer INS1. The second electrode PE2 may be connected to the second alignment electrode ALE2 through a second contact hole CH2 of the first insulating layer INS1.

[0211] The first electrode PE1 may be directly disposed on the first end EP1 of the light emitting element LD to contact the first end EP1 of the light emitting element LD. The second electrode PE2 may be directly disposed on the second end EP2 of the light emitting element LD to contact the second end EP2 of the light emitting element LD. The first electrode PE1 and the second electrode PE2 may be formed in different processes.

[0212] The third insulating layer INS3 may be disposed on the first electrode PE1, and the second electrode PE2 may be disposed on the third insulating layer INS3.

[0213] The third insulating layer INS3 may be positioned on the first electrode PE1 to cover the first electrode PE1 (or so as not to expose the first electrode PE1 to the outside), thereby preventing corrosion of the first electrode PE1, etc. The third insulating layer INS3 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. For example, the third insulating layer INS3 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) is at least one of metal oxides, but is not limited thereto. The third insulating layer INS3 may be formed as a single layer or a multi-layer.

[0214] As described above, when the third insulating layer INS3 is disposed between the first electrode PE1 and the second electrode PE2, since the first electrode PE1 and the second electrode PE2 can be stably separated by the third insulating layer INS3, electrical stability between the first end EP1 and the second end EP2 of the light emitting element LD can be ensured.

[0215] Each of the electrodes PE may be formed of various transparent conductive materials. For example, each of the electrodes PE may include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), and zinc tin oxide (ZTO) or gallium tin oxide (GTO), and may be implemented as substantially transparent or translucent to meet a predetermined transmittance. Therefore, light emitted from the first end EP1 and the second end EP2 of the light emitting element LD may pass through the electrode PE and may be emitted to the outside of the display device DD (or display panel DP).

[0216] In an implementation, a capping layer CVL may be disposed on the electrode PE and the third insulating layer INS3 .

[0217] The cover layer CVL may be a fourth insulating layer INS4 that flattens the upper surface of the display element layer DPL while protecting the electrode PE. In addition, the cover layer CVL may change the path of light lost in the light (or light) emitted from the color conversion layer CCL to the front surface direction (or the image display direction of the display device DD) using a refractive index difference, thereby increasing the front surface light output brightness. The cover layer CVL may reuse light (e.g., blue-based light) that has not interacted with the color conversion layer CCL to interact with the color conversion layer CCL, thereby increasing the light output brightness of the color conversion layer CCL.

[0218] In an embodiment, the cover layer CVL may be configured to selectively reflect light within a specific wavelength range. The cover layer CVL may be configured to allow light of a first wavelength to pass through the light traveling in the rear surface direction of the color conversion layer CCL, and to reflect light of a wavelength different from the first wavelength. For example, the cover layer CVL may allow blue-based light traveling from the color conversion layer CCL in the rear surface direction of the color conversion layer CCL (e.g., in the direction of the light emitting element LD) to pass through, and reflect green-based light and / or red-based light other than the blue-based light to the color conversion layer CCL.

[0219] The cap layer CVL may include at least one or more sub-insulating layers, and the sub-insulating layers include a first layer FL and a second layer SL which are sequentially stacked and have different refractive indices. For example, the cap layer CVL may include a first sub-insulating layer SINS1, a second sub-insulating layer SINS2, a third sub-insulating layer SINS3, and a fourth sub-insulating layer SINS4. Fig. 9 Each of the first sub-insulating layer SINS1, the second sub-insulating layer SINS2, the third sub-insulating layer SINS3, and the fourth sub-insulating layer SINS4 may include a first layer FL and a second layer SL sequentially stacked along the third direction DR3.

[0220] The first layer FL may include a first inorganic layer having a first refractive index, and the second layer SL may include a second inorganic layer having a second refractive index different from the first refractive index. The first refractive index may be smaller than the second refractive index. In this case, the first layer FL may include silicon oxide (SiO x ) and the second layer SL may be a first inorganic layer including silicon nitride (SiN x ) of the second inorganic layer. For example, the first layer FL may be a silicon oxide (SiO x ) and the second layer SL may be a first inorganic layer including silicon nitride (SiN x ) of the second inorganic layer. The first layer FL may have about The thickness of the second layer SL may be about The thickness may be, but is not limited thereto.

[0221] The cap layer CVL may include a DBR structure in which a first layer FL having a first refractive index and a second layer SL having a second refractive index are alternately and repeatedly stacked. For example, the cap layer CVL may include at least one sub-insulating layer in which a first layer FL having a first refractive index and a second layer SL having a second refractive index are stacked.

[0222] According to an embodiment, the first refractive index may be higher than the second refractive index. In this case, the first layer FL may include silicon nitride (SiN x ), and the second layer SL may be a first inorganic layer including silicon oxide (SiO x )'s second inorganic layer.

[0223] In the above-mentioned embodiment, the cap layer CVL includes at least one or more sub-insulating layers sequentially stacked and including a first layer FL and a second layer SL having different refractive indices, but is not limited thereto. According to an embodiment, the cap layer CVL may include at least one or more sub-insulating layers SINS1, SINS2, and SINS3, the at least one or more sub-insulating layers SINS1, SINS2, and SINS3 including a first layer FL, a second layer SL, and a third layer TL having a refractive index different from that of adjacent layers, such as Fig.10For example, the capping layer CVL may include a first sub-insulating layer SINS1, a second sub-insulating layer SINS2, and a third sub-insulating layer SINS3 sequentially stacked on the electrode PE2 along the third direction DR3.

[0224] The first layer FL may include a first inorganic layer having a first refractive index, the second layer SL may include a second inorganic layer having a second refractive index different from the first refractive index, and the third layer TL may include a third inorganic layer having a third refractive index different from the second refractive index. The third refractive index may be the same as the first refractive index, but is not limited thereto.

[0225] When the first refractive index and the third refractive index are less than the second refractive index, the first layer FL may include silicon oxide (SiO x ) of the first inorganic layer, the second layer SL may be a silicon nitride (SiN x ), and the third layer TL may be a second inorganic layer including silicon oxide (SiO x ) of the third inorganic layer.

[0226] According to an embodiment, when the first refractive index and the third refractive index are higher than the second refractive index, the first layer FL may include silicon nitride (SiN x ) of the first inorganic layer, the second layer SL may be a silicon oxide (SiO x ), and the third layer TL may be a second inorganic layer including silicon nitride (SiN x ) of the third inorganic layer.

[0227] Fig.10 The cap layer CVL shown in the figure may have a structure in which a first layer FL having a first refractive index, a second layer SL having a second refractive index, and a third layer TL having a third refractive index are alternately and repeatedly stacked. For example, the cap layer CVL may include at least one sub-insulating layer configured by stacking a first layer FL having a first refractive index, a second layer SL having a second refractive index, and a third layer TL having a third refractive index.

[0228] The above-mentioned cover layer CVL can transmit a portion of the light traveling in the rear surface direction of the color conversion layer CCL and reflect the rest. As described above, since the first layer FL and the second layer SL having different refractive indices are alternately stacked to configure the cover layer CVL, a refractive index difference can be repeatedly formed in the cover layer CVL, and thus the light incident on the cover layer CVL can have different transmittances according to its incident angle. For example, the reflectivity of the light reflected from the cover layer CVL can be adjusted by adjusting the material, thickness and / or number of layers included in the stacked first layer FL and second layer SL. For example, in order to optimally increase the reflectivity of the light incident on the cover layer CVL, the thickness of the first layer FL and the second layer SL can be adjusted according to the wavelength and refractive index of the light. In the case where the refractive index of the stacked layer (inorganic layer) is n and the wavelength of the light to be reflected is λ, when a low refractive layer (or high refractive layer) and a high refractive layer (or low refractive layer) with a thickness of λ / 4n are alternately stacked, light in a specific wavelength (λ) region can be effectively reflected.

[0229] In an embodiment, the cover layer CVL may have a first thickness d1 in the third direction DR3. The first thickness d1 may be about 2 μm. The first thickness d1 may be a separation distance between the light emitting element LD and the color conversion layer CCL.

[0230] The color conversion layer CCL and the second bank BNK2 may be positioned on the capping layer CVL. The color conversion layer CCL may be positioned on the capping layer CVL in the emission area EMA of the pixel PXL, and the second bank BNK2 may be positioned on the capping layer CVL in the non-emission area NEA of the corresponding pixel PXL.

[0231] The second bank BNK2 may be disposed in the non-emission area NEA and / or formed on the capping layer CVL on the first bank BNK1. The second bank BNK2 may be a dam structure surrounding the emission area EMA of the pixel PXL and defining the emission area EMA by defining a position where the color conversion layer CCL is to be provided.

[0232] The second bank BNK2 may include a light blocking material. For example, the second bank BNK2 may be a black matrix. According to an embodiment, the second bank BNK2 may be configured to include at least one light blocking material and / or a reflective material so as to allow light emitted from the color conversion layer CCL to travel in an image display direction of the display device DD, thereby improving light output efficiency of the color conversion layer CCL.

[0233] The color conversion layer CCL may be formed on the capping layer CVL of each pixel PXL in the emission area EMA surrounded by the second bank BNK2 .

[0234] The color conversion layer CCL may include color conversion particles QD corresponding to a specific color. For example, the color conversion layer CCL may include color conversion particles QD that convert light of a first color emitted from the light emitting element LD into light of a second color (or a specific color) different from the first color.

[0235] When the pixel PXL is a red pixel (or a red sub-pixel), the color conversion layer CCL of the pixel PXL may include color conversion particles QD of red quantum dots that convert the first color light emitted from the light emitting element LD into the second color light (or red light).

[0236] When the pixel PXL is a green pixel (or a green sub-pixel), the color conversion layer CCL of the pixel PXL may include color conversion particles QD of green quantum dots that convert the first color light emitted from the light emitting element LD into the second color light (or green light).

[0237] When the pixel PXL is a blue pixel (or a blue sub-pixel), the color conversion layer CCL of the pixel PXL may include color conversion particles QD of blue quantum dots that convert light of a first color emitted from the light-emitting element LD into light of a second color (e.g., blue light). When the pixel PXL is a blue pixel (or a blue sub-pixel), according to an embodiment, a light scattering layer including light scattering particles SCT (or a scatterer) may be provided instead of the color conversion layer CCL including the color conversion particles QD. For example, when the light-emitting element LD emits blue-based light, the pixel PXL may include a light scattering layer including light scattering particles SCT. According to an embodiment, the above-mentioned light scattering layer may be omitted. When the pixel PXL is a blue pixel (or a blue sub-pixel), according to another embodiment, a transparent polymer may be provided instead of the color conversion layer CCL.

[0238] The upper substrate U_SUB may be disposed on the color conversion layer CCL and the second bank BNK2. The upper substrate U_SUB may be coupled to the display element layer DPL through the intermediate layer CTL and the like.

[0239] The intermediate layer CTL may be a transparent adhesive layer (or adhesive layer) for enhancing the adhesion between the display element layer DPL and the upper substrate U_SUB, such as an optically transparent adhesive layer, but is not limited thereto. According to an embodiment, the intermediate layer CTL may be a refractive index conversion layer for increasing the light output brightness of the pixel PXL by converting the angle of light emitted from the color conversion layer CCL and traveling toward the upper substrate U_SUB. According to an embodiment, the intermediate layer CTL may include a filler formed of an insulating material having insulating properties and adhesive properties.

[0240] The upper substrate U_SUB may include a base layer BSL, a color filter layer CFL, and a cover layer CPL.

[0241] The base layer BSL may be a rigid substrate or a flexible substrate, and its material or property is not particularly limited. The base layer BSL may be formed of the same material as the substrate SUB, or may be formed of a material different from that of the substrate SUB.

[0242] The color filter layer CFL may be disposed on one surface of the base layer BSL to face the display element layer DPL. The color filter layer CFL may include a color filter corresponding to each pixel PXL. For example, the color filter layer CFL may include a first color filter CF1 disposed on the color conversion layer CCL of one pixel PXL (hereinafter referred to as the "first pixel"), a second color filter CF2 disposed on the color conversion layer of an adjacent pixel adjacent to the first pixel PXL (hereinafter referred to as the "second pixel"), and a third color filter CF3 disposed on the color conversion layer of an adjacent pixel adjacent to the second pixel (hereinafter referred to as the "third pixel").

[0243] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to overlap each other in the non-emission area NEA in the third direction DR3, and may be used as a light blocking member for blocking light interference between adjacent pixels PXL. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a color filter material that selectively transmits light of a color converted and emitted from a corresponding color conversion layer. For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter, but is not limited thereto.

[0244] The cover layer CPL may be disposed on the color filter layer CFL. The cover layer CPL may be positioned on the color filter layer CFL to cover the color filter layer CFL, thereby protecting the color filter layer CFL. The cover layer CPL may be an inorganic layer including an inorganic material or an organic layer including an organic material.

[0245] According to the above-described embodiment, a cover layer CVL in which a first layer FL having a first refractive index and a second layer SL having a second refractive index are alternately and repeatedly stacked may be provided between the electrodes PE1 and PE2 and the color conversion layer CCL. Therefore, by utilizing the refractive index difference between the first layer FL and the second layer SL, light traveling in the rear surface direction of the color conversion layer CCL may be reflected to interact with the color conversion layer CCL. Therefore, the loss of light may be minimized, thereby improving the light output efficiency of the pixel PXL.

[0246] In addition, according to the above embodiment, since the cover layer CVL having the first thickness d1 is provided between the light emitting element LD and the color conversion layer CCL, the distance between the light emitting element LD and the color conversion layer CCL can be ensured. Therefore, the phenomenon that the color conversion layer CCL is deteriorated due to the heat emitted from the light emitting element LD can be prevented, and thus the reliability of the pixel PXL can be improved.

[0247] Fig.11 and Fig.12 A pixel PXL according to an embodiment is schematically shown and is similar to Figure 5 A schematic cross-sectional view corresponding to line II-II'.

[0248] about Fig.11 and Fig.12 The implementation method of the present invention mainly describes the points that are different from the above-mentioned implementation methods to avoid overlapping descriptions.

[0249] refer to Figures 1 to 5 and Fig.11 , the display element layer DPL of the pixel PXL may include an additional insulating layer ADINS.

[0250] The additional insulating layer ADINS may be a fifth insulating layer INS5 disposed between the electrode PE and the cover layer CVL. The additional insulating layer ADINS may include an organic layer. In this case, the additional insulating layer ADINS may be a planarization layer for alleviating the step difference caused by the configuration positioned thereunder (e.g., the electrode PE, the third insulating layer INS3, and the first bank BNK1). When the additional insulating layer ADINS is formed of an organic layer, the cover layer CVL positioned thereon may have a relatively flat surface. In this case, the reflectivity of the light reflected from the cover layer CVL to the color conversion layer CCL may be further improved.

[0251] The additional insulating layer ADINS may have a second thickness d2 in the third direction DR3. The second thickness d2 may be less than the reference Figures 6 to 10 The capping layer CVL has a first thickness d1 and a second thickness d2, for example, in the range of 1.0 μm to 1.3 μm, but is not limited thereto.

[0252] The additional insulating layer ADINS may have a refractive index similar to that of the color conversion layer CCL and may have a refractive index lower than that of the capping layer CVL. In an embodiment, the additional insulating layer ADINS may have a refractive index lower than that of the reference layer CVL. Fig. 9 The refractive index of the layer with a higher refractive index in the first layer FL and the second layer SL of the cap layer CVL is described as lower than that of the second layer SL. For example, when the second layer SL has a higher refractive index than the first layer FL, the additional insulating layer ADINS may have a lower refractive index than the second layer SL.

[0253] Since the additional insulating layer ADINS having a low refractive index is disposed under the cover layer CVL, light loss due to total reflection that may occur at the interface between the additional insulating layer ADINS, the cover layer CVL, and the color conversion layer CCL can be prevented. Therefore, the amount of light traveling to the upper portion of the color conversion layer CCL can be increased, and thus the light output efficiency of the pixel PXL can be improved.

[0254] In addition, since the additional insulating layer ADINS is disposed under the cover layer CVL, a gap between the light emitting element LD and the color conversion layer CCL may be further secured to prevent degradation of the color conversion layer CCL.

[0255] According to an embodiment, the additional insulating layer ADINS may include an inorganic layer. In this case, the additional insulating layer ADINS may be designed to have a thickness equal to or greater than the thickness (or diameter) of the light emitting element LD, for example, 0.6 μm or greater, so as to prevent total reflection of light emitted from the side surface of the light emitting element LD.

[0256] refer to Figures 1 to 5 and Fig.12 , the display element layer DPL of the pixel PXL may include a cap pattern CVP disposed between the electrode PE and the color conversion layer CCL.

[0257] The cap pattern CVP may be disposed on the third insulating layer INS3 on the first electrode PE1 at least in the emission area EMA. The cap pattern CVP may include at least one or more sub-insulating layers including first layers sequentially stacked and having different refractive indices (refer to Fig. 9 "FL") and the second layer (reference Fig. 9 SL in the text box).

[0258] In reference Figures 6 to 10 After the described cap layer CVL is formed on the second electrode PE2, a portion of the cap layer CVL is removed by a photolithography process using a mask, and the cap pattern CVP may be partially opened. The cap pattern CVP may cover the third insulating layer INS3 on the first electrode PE1 and expose the second electrode PE2. For example, the cap pattern CVP may include an opening, and the opening of the cap pattern CVP may expose the second electrode PE2. The color conversion layer CCL may be directly disposed on the cap pattern CVP and the exposed second electrode PE2.

[0259] Since the cap pattern CVP is disposed only on the third insulating layer INS3 on the first electrode PE1 , a moving path of total reflection that may occur within the cap pattern CVP may be reduced, thereby minimizing a loss of light incident on the cap pattern CVP.

[0260] Although the present disclosure has been described with reference to the above preferred embodiments, those skilled in the art or those having common knowledge in the art will appreciate that various modifications and changes may be made to the present disclosure without departing from the spirit and technical field of the present disclosure described in the appended claims.

[0261] Therefore, the technical scope of the present disclosure should not be limited to the contents described in the detailed description of this specification, but should be defined by the claims.

Claims

1. A display device, comprising: A substrate including an emitting region and a non-emitting region; A plurality of light emitting elements are arranged on the substrate; A first electrode and a second electrode are disposed to be spaced apart from each other and electrically connected to the plurality of light emitting elements; A cover layer, disposed on the first electrode and the second electrode; as well as A color conversion layer is disposed on the cover layer, The cap layer includes a plurality of sub-insulating layers, each of the plurality of sub-insulating layers includes a first layer and a second layer stacked in sequence, and The first layer and the second layer have different refractive indices.

2. The display device according to claim 1, wherein: The first layer is a first inorganic layer having a first refractive index, and the second layer is a second inorganic layer having a second refractive index.

3. The display device according to claim 2, wherein: The first refractive index is less than the second refractive index, and The first inorganic layer includes silicon oxide, and the second inorganic layer includes silicon nitride.

4. The display device according to claim 3, wherein: Each of the plurality of sub-insulating layers further includes a third layer stacked on the second layer, and The third layer is a third inorganic layer having a third refractive index.

5. The display device according to claim 4, wherein: The third refractive index is different from the second refractive index.

6. The display device according to claim 2, wherein: The second refractive index is less than the first refractive index, and The first inorganic layer includes silicon nitride, and the second inorganic layer includes silicon oxide.

7. The display device according to claim 3, wherein: The cover layer transmits light within a predetermined wavelength range.

8. The display device according to claim 1, wherein: The color conversion layer includes color conversion particles that convert light emitted from the plurality of light emitting elements into light of different wavelengths.

9. The display device according to claim 7, further comprising: A first insulating layer is provided between the substrate and the plurality of light emitting elements; a second insulating layer disposed on each of the plurality of light emitting elements; as well as The third insulating layer is arranged on the first electrode.

10. The display device according to claim 9, wherein: The thickness of the cover layer is less than or equal to 2 μm.

11. The display device according to claim 9, further comprising: An additional insulating layer is disposed between the first electrode, the second electrode and the cover layer.

12. The display device according to claim 11, wherein: The additional insulating layer includes an organic layer.

13. The display device according to claim 12, wherein: The additional insulating layer has a thickness in the range of 1.0 μm to 1.3 μm.

14. The display device according to claim 11, wherein: The additional insulating layer includes an inorganic layer.

15. The display device according to claim 9, further comprising: a first alignment electrode and a second alignment electrode positioned between the substrate and the first insulating layer and spaced apart from each other; a first bank disposed in the non-emitting region and including an opening corresponding to the emitting region; a second bank positioned on the first bank in the non-emissive region and surrounding the color conversion layer; as well as A color filter is disposed on the color conversion layer.

16. The display device according to claim 15, wherein: The first electrode is electrically connected to the first alignment electrode, and the second electrode is electrically connected to the second alignment electrode.

17. The display device according to claim 1, further comprising: The pixel circuit layer is disposed between the substrate and the plurality of light emitting elements and includes at least one transistor electrically connected to the plurality of light emitting elements.

18. A display device comprising: substrate; A plurality of light emitting elements are arranged on the substrate; A first electrode and a second electrode are disposed to be spaced apart from each other and electrically connected to the plurality of light emitting elements; a cover pattern, disposed on the first electrode to cover the first electrode; as well as A color conversion layer is disposed on the cover pattern, wherein the cover pattern comprises: a plurality of sub-insulating layers, each of the plurality of sub-insulating layers comprising a first layer and a second layer stacked in sequence; and Open your mouth, The first layer and the second layer have different refractive indices, and The opening of the capping pattern exposes the second electrode.

19. The display device according to claim 18, wherein: The color conversion layer is directly disposed on the cover pattern and the second electrode, and The capping pattern is not disposed on the second electrode.

20. The display device according to claim 18, wherein: The cover pattern selectively transmits light within a predetermined wavelength range.

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