Analog front-end circuit for capacitance detection and current calibration method

Abstract

The invention belongs to the field of circuits, and particularly relates to an analog front-end circuit for capacitance detection and a current calibration method, the analog front-end circuit comprises a driving circuit, a to-be-detected capacitor, a chip signal input and output interface circuit, a current amplification circuit or charge amplification circuit, an integrating circuit and an analog-to-digital converter which are connected in sequence; the leakage current measurement and calibration controller is used for receiving a signal of the analog-to-digital converter and outputting a control signal for calibrating the leakage current to the current calibration circuit; the output end of the current calibration circuit is connected with the input end of the integrating circuit, and the current calibration circuit is used for adjusting the output of the current calibration circuit to calibrate the magnitude of the current input into the integrating circuit when receiving the control signal for calibrating the leakage current. According to the application, the leakage current measurement and calibration controller is arranged at the output end of the integrating circuit, the leakage current of the analog front-end circuit is measured, and the control signal is output to adjust the output of the current calibration circuit, so that the magnitude of the current input into the integrating circuit is calibrated, and errors caused by imbalance of the leakage current and the current of the amplifying circuit can be compensated.

Description

Technical Field

[0001] The present application belongs to the field of circuits, and in particular relates to an analog front-end circuit for capacitance detection and a current calibration method. Background Art

[0002] The analog front-end circuit of capacitance detection usually includes a capacitor to be tested, a chip signal input and output interface circuit, a current amplifier circuit or a charge amplifier circuit and an integration circuit. The electrostatic discharge circuit in the chip signal input and output interface circuit may generate leakage current, and the amplifier circuit may generate output current imbalance, which will cause output errors of the integrator. In order to reduce the impact of these errors, the prior art usually resets the integrator at a time to reset the output voltage to a reference voltage, resulting in the detection circuit having to frequently insert reset time intervals during detection, affecting the speed of the detection circuit. Summary of the invention

[0003] The embodiments of the present application provide an analog front-end circuit and a current calibration method for capacitance detection, which can solve the problem of output error of the integrator and slow detection circuit speed caused by frequent resetting of the integrator to a certain extent.

[0004] According to a first aspect of an embodiment of the present application, an analog front-end circuit for capacitance detection is provided, the analog front-end circuit comprising: a driving circuit, a capacitor to be measured, a chip signal input and output interface circuit, a current amplifier circuit or a charge amplifier circuit, an integration circuit, an analog-to-digital converter, a leakage current measurement and calibration controller, and a current calibration circuit; the output end of the driving circuit is connected to the input end of the capacitor to be measured; the output end of the capacitor to be measured is connected to the input end of the chip signal input and output interface circuit, the output end of the chip signal input and output interface circuit is connected to the input end of the current amplifier circuit or the charge amplifier circuit, the output end of the current amplifier circuit or the charge amplifier circuit is connected to the input end of the integration circuit, and the output end of the integration circuit is connected to the analog-to-digital converter; wherein the leakage current measurement and calibration controller is used to receive a signal from the analog-to-digital converter and output a control signal for calibrating the leakage current to the current calibration circuit; the output end of the current calibration circuit is connected to the input end of the integration circuit, and is used to adjust the output of the current calibration circuit to calibrate the current input to the integration circuit when receiving the control signal for calibrating the leakage current.

[0005] In some embodiments, the current calibration circuit includes a current source and a current sink, the current source is used to increase the input current of the integration circuit, and the current sink is used to reduce the input current of the integration circuit.

[0006] In some embodiments, the chip signal input and output interface circuit includes an electrostatic discharge circuit.

[0007] According to a second aspect of an embodiment of the present application, a current calibration method is provided, which is applied to an analog front-end circuit as described above, and the method includes: controlling a driving circuit to output a driving signal with a constant voltage or frequency within a preset range; controlling the chip signal input / output interface circuit and the current amplification circuit or the method circuit to be in a disconnected state, and controlling the plate of the capacitor to be measured to be reset and controlling the integration circuit to be reset; controlling the chip signal input / output interface circuit and the current amplification circuit or the charge method circuit to remain in a disconnected state or switch to a conductive state; obtaining a first electrical signal value of the output of the integration circuit measured by the analog-to-digital converter at a first time; obtaining a second electrical signal value of the output of the integration circuit measured by the analog-to-digital converter at a second time; the second time is a time after a preset time after the first time shown; comparing the absolute difference between the second electrical signal value and the first electrical signal value and the size of a first threshold; if the absolute difference is greater than or equal to the first threshold, adjusting the output current of the current calibration circuit to calibrate the error caused by leakage current.

[0008] In some embodiments, after comparing the absolute difference between the second electrical signal value and the first electrical signal value and the first threshold value, the method further includes: if the absolute difference is smaller than the first threshold value, maintaining the output current of the current calibration circuit unchanged.

[0009] In some embodiments, adjusting the output current of the current calibration circuit to calibrate the error caused by leakage current includes: comparing the magnitude of the second electrical signal value with the first electrical signal value; if the second electrical signal value is greater than the first electrical signal value, reducing the current of the current source of the current calibration circuit and / or increasing the current of the current sink of the current calibration circuit.

[0010] In some embodiments, adjusting the output current of the current calibration circuit to calibrate the error caused by the leakage current includes: comparing the magnitude of the second electrical signal value with the first electrical signal value; if the second electrical signal value is smaller than the first electrical signal value, then increasing the current of the current source of the current calibration circuit and / or reducing the current of the current sink of the current calibration circuit.

[0011] In some embodiments, after adjusting the output current of the current calibration circuit to calibrate the error caused by the leakage current, the method further includes: repeating the current calibration method until the absolute difference is less than the first threshold.

[0012] In some embodiments, the controlling the plate of the capacitor to be measured to reset includes:

[0013] The output end of the chip signal input / output interface circuit is controlled to be connected to a reference voltage source, and then the output end of the chip signal input / output interface circuit is controlled to be disconnected from the reference voltage source.

[0014] In some embodiments, controlling the integration circuit to reset includes: controlling the output end and the input end of the integration circuit to be directly connected through a wire, and then controlling the output end and the input end of the integration circuit to be directly connected through a wire to switch to a disconnected state.

[0015] Based on the technical solution proposed in this application, by setting a leakage current measurement and calibration controller at the output end of the integration circuit, measuring the leakage current of the analog front-end circuit and outputting a control signal to adjust the output of the current calibration circuit, the current magnitude of the input integration circuit is calibrated, and the error caused by the leakage current of the interface circuit and the current imbalance of the amplifier circuit can be compensated. Compared with the prior art that requires frequent timing to reset the output voltage of the integration circuit, this technical solution can compensate for the current error and increase the working speed of the detection circuit.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 It is a circuit diagram of an analog front-end circuit shown in the prior art;

[0019] Figure 2 It is a diagram of an output error of an integration circuit caused by leakage current of an analog front-end circuit shown in the prior art;

[0020] Figure 3 is a circuit diagram of an analog front-end circuit according to an embodiment of the present application;

[0021] Figure 4 is a circuit diagram of an analog front-end circuit according to an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a current calibration method according to an embodiment of the present application;

[0023] Figure 6 is a timing diagram of a current calibration method according to an embodiment of the present application;

[0024] Figure 7 is a schematic diagram of a current calibration method according to another embodiment of the present application;

[0025] Figure 8 is a timing diagram of a current calibration method according to another embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0028] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0029] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0030] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0031] Before describing the solution of the present application in detail, the terms involved in the present application are explained as follows:

[0032] The analog front end (AFE) is a crucial component of electronic devices, mainly responsible for converting real-world analog signals into digital signals that can be processed by digital systems. It is located at the front end of the signal processing chain, and performs preliminary processing and conversion on the input analog signals to provide data for subsequent digital signal processing.

[0033] The driving circuit is used to provide a driving voltage.

[0034] Chip signal input and output interface circuit (chip IO circuit), chip IO (Input / Output) refers to the input and output interface on the chip, which is used to transmit signals with external devices. IO can be different signal types, such as digital signals, analog signals, high-frequency signals, etc. The interface circuit usually contains an electrostatic discharge circuit.

[0035] An electrostatic discharge circuit (ESD circuit) is a circuit used to protect electronic equipment from damage caused by electrostatic discharge (ESD for short).

[0036] The current amplifier circuit is used to amplify the current signal.

[0037] An integrator circuit is used to convert the time integral of the input signal into an output voltage.

[0038] Analog-to-digital converter, or ADC for short, is an electronic component that converts analog signals into digital signals.

[0039] The capacitance detection circuit in the prior art is usually as follows Figure 1 As shown, it includes a driving circuit TX, a capacitor to be measured Cm, a chip IO circuit, a current amplifier circuit C2I, an integration circuit, and an analog-to-digital converter SAR-ADC, etc. The driving circuit is used to provide a driving voltage, the output end of the driving circuit is connected to the input end of the capacitor to be measured Cm, the output end of Cm is connected to the input end of the chip IO circuit, the chip IO circuit includes an ESD circuit, the output end of the chip IO circuit is connected to the input end of the current amplifier circuit I2, the output end of the current amplifier circuit I2 is connected to the input end of the integration circuit, and the output end of the integration circuit is connected to the analog-to-digital converter SAR-ADC.

[0040] In such Figure 1 In the circuit shown, the ESD circuit (part A101 and part A102) is getting bigger and bigger, which leads to a larger leakage current. Especially at high temperature, the leakage current may reach 1uA. The current is transmitted to the integrator by C2I, causing the error of the output voltage. Figure 2As shown in the figure, the upward slope and the downward slope are leakage currents with different current directions. As the detection time increases, the error voltage becomes larger and larger and may even cause the integrator output to saturate. In addition, the current amplifier circuit C2I also has an output current offset. This offset is superimposed on the IO leakage current, further exacerbating the output error of the integration circuit. In order to reduce the impact of these errors, the usual practice is to reset the integration circuit at a fixed time to reset the output voltage to VREF, that is, the PHI2RST switch is turned on, resulting in the detection circuit having to insert a reset time interval during detection, which affects the speed of the detection circuit.

[0041] In order to solve this technical problem, the technical solution of this application is proposed. Figure 3 , Figure 3 The invention is a circuit diagram of an analog front-end circuit according to an embodiment of the present application, wherein the analog front-end circuit comprises: a driving circuit TX, a capacitor to be measured Cm, a chip IO circuit, a current amplifier circuit C2I, an integration circuit, an analog-to-digital converter SAR-ADC, a leakage current measurement and calibration controller, and a current calibration circuit; the output end of the driving circuit TX is connected to the input end of the capacitor to be measured Cm; the output end of the capacitor to be measured Cm is connected to the input end of the chip IO circuit, the output end of the chip signal IO circuit is connected to the current amplifier circuit C2I, the output end of the current amplifier circuit C2I is connected to the input end of the integration circuit, and the output end of the integration circuit is connected to the analog-to-digital converter SAR-ADC; wherein the leakage current measurement and calibration controller is used to receive a signal from the analog-to-digital converter SAR-ADC and output a control signal for calibrating the leakage current to the current calibration circuit; the output end of the current calibration circuit is connected to the input end of the integration circuit, and is used to adjust the output of the current calibration circuit to calibrate the current magnitude of the input integration circuit when receiving the control signal for calibrating the leakage current.

[0042] By setting a leakage current measurement and calibration controller at the output end of the integration circuit, measuring the leakage current of the analog front-end circuit and outputting a control signal to adjust the output of the current calibration circuit, the current magnitude of the input integration circuit is calibrated, and the error caused by the leakage current and the current imbalance of the amplifier circuit can be compensated. Compared with the prior art that requires frequent timing reset of the output voltage of the integration circuit, this technical solution can compensate for the current error and increase the working speed of the detection circuit.

[0043] In some embodiments, the leakage current measurement and calibration controller is one controller; in another embodiment, the leakage current measurement and calibration controller is formed by combining two or more controllers.

[0044] In some embodiments of the present application, the current calibration circuit includes a current source A121 and a current sink A122. The current source A121 is used to increase the input current of the integration circuit, and the current sink A122 is used to reduce the input current of the integration circuit. By adjusting the current source A121 and / or the current sink A122, the error caused by the leakage current can be offset.

[0045] In some embodiments of the present application, the chip IO circuit includes an electrostatic discharge circuit ESD for protecting electronic devices from damage caused by electrostatic discharge.

[0046] In some embodiments of the present application, the ADC is a SAR-ADC, and in other embodiments, the ADC is other types of ADC such as Sigma-delta.

[0047] Figure 4 FIG. 1 is a circuit diagram of an analog front-end circuit according to another embodiment of the present application, which is similar to FIG. Figure 3 The difference of the circuit diagram shown is that the current amplifier circuit C2I is replaced by a charge amplifier circuit CA, that is, the output end of the chip signal IO circuit is connected to the charge amplifier circuit CA, and the output end of the charge amplifier circuit CA is connected to the input end of the integration circuit. The charge amplifier circuit CA is used to amplify the charge signal.

[0048] According to a second aspect of an embodiment of the present application, a current calibration method is provided, which is applied to the analog front-end circuit as described above. Figure 5 As shown, including:

[0049] Control the driving circuit TX to output a driving signal with a constant voltage or frequency within a preset range;

[0050] The control chip IO circuit is disconnected from the current amplifier circuit C2I or the charge amplifier circuit CA, and the plate of the capacitor Cm to be measured is reset and the integration circuit is reset;

[0051] The control chip IO circuit and the current amplifier circuit or the charge amplifier circuit CA are in a conducting state;

[0052] Obtaining a first electrical signal value Vout,t1 of the output of the integration circuit measured by the analog-to-digital converter SAR-ADC at a first time t1;

[0053] Obtaining a second electrical signal value Vout,t2 of the output of the integration circuit measured by the analog-to-digital converter SAR-ADC at a second time t2; the second time t2 is a time after a preset time after the first time t1 shown;

[0054] Compare the absolute difference between the second electrical signal value Vout, t2 and the first electrical signal value Vout, t1 with a first threshold value;

[0055] If the absolute difference is greater than or equal to the first threshold, the output current of the current calibration circuit is adjusted to calibrate the error caused by the leakage current.

[0056] In some embodiments of the present application, the preset range of frequency is preferably 100K-500K Hz.

[0057] In some embodiments of the present application, after comparing the absolute difference between the second electrical signal value Vout, t2 and the first electrical signal value Vout, t1 with the first threshold, if the absolute difference is smaller than the first threshold, the output current of the current calibration circuit is kept unchanged.

[0058] In some embodiments of the present application, adjusting the output current of the current calibration circuit to calibrate the error caused by the leakage current includes the following steps:

[0059] Comparing the second electrical signal value Vout, t2 with the first electrical signal value Vout, t1;

[0060] If the second electrical signal value Vout, t2 is greater than the first electrical signal value Vout, t1, the current of the current source of the current calibration circuit is reduced and / or the current of the current sink of the current calibration circuit is increased. The value of adjusting the current of the calibration circuit is related to the polarity of the amplifier circuit. When the second electrical signal value Vout, t2 is greater than the first electrical signal value Vout, t1, it indicates that the amplifier circuits are connected with the same polarity, and it is necessary to reduce the current of the current source of the current calibration circuit and / or increase the current of the current sink of the current calibration circuit.

[0061] If the second electrical signal value Vout, t2 is less than the first electrical signal value Vout, t1, the current of the current source of the current calibration circuit is increased and / or the current of the current sink of the current calibration circuit is reduced. The value of the current of the calibration circuit is adjusted to be related to the polarity of the amplifier circuit. When the second electrical signal value Vout, t2 is less than the first electrical signal value Vout, t1, it indicates that the polarity of the amplifier circuit connection is opposite, and it is necessary to increase the current of the current source of the current calibration circuit and / or reduce the current of the current sink of the current calibration circuit.

[0062] In some embodiments of the present application, after adjusting the output current of the current calibration circuit to calibrate the error caused by the leakage current, the current calibration method is repeated until the absolute difference is less than the first threshold.

[0063] In some embodiments of the present application, the plate of the capacitor Cm to be measured is controlled to be reset, including: the output end of the control chip IO circuit is connected to the reference voltage source VREF, so that the plate voltage of the capacitor Cm to be measured is reset to the same as VREF, and then the output end of the control chip IO circuit is disconnected from the reference voltage source VREF; Figure 3The switch S1 shown is first controlled to be turned on, and then controlled to be turned off.

[0064] In some embodiments of the present application, controlling the integration circuit to reset includes: controlling the output end and the input end of the integration circuit to be directly connected through a wire, so that the output voltage of the integration circuit is reset to the same as the reference voltage source VREF, and then controlling the output end and the input end of the integration circuit to be directly connected and switched to a disconnected state; Figure 3 The switch S3 shown is first controlled to be turned on, and then controlled to be turned off.

[0065] In some embodiments of the present application, Figure 3 As shown, in the chip IO circuit and the current amplifier circuit C2I ( Figure 4 A switch S2 is provided between the charge amplifier circuit CA) and the chip IO circuit and the current amplifier circuit C2I ( Figure 4 The charge amplifier circuit CA) is disconnected, and S2 is controlled to be turned on, so that the chip IO circuit and the current amplifier circuit C2I ( Figure 4 The charge amplifier circuit CA) is in the on state.

[0066] In some embodiments of the present application, Figure 5 As shown, the above-mentioned current calibration method can be stored in a register, and when starting the current calibration, the register can be configured to enter the calibration mode.

[0067] In some embodiments of the present application, Figure 5 The training sequence of the current calibration method shown is as follows: Figure 6 As shown, at the beginning, switches S1, S2, and S3 are in the off state; first, S1 and S3 are turned on, and S2 is in the off state; then S1 and S3 are disconnected, and then S2 is turned on; when S1 and S3 are continuously disconnected and S2 is continuously turned on, the ADC collects two signals Vout, t1 and Vout, t2 at time t1 and t2 respectively.

[0068] The above calibration method can compensate for the integrator output voltage error caused by IO circuit leakage and current amplifier current offset, thereby avoiding the need to frequently reset the integrator output voltage in the prior art, which affects the speed of the detection circuit.

[0069] According to a third aspect of an embodiment of the present application, a current calibration method is provided, which is applied to the analog front-end circuit as described above. Figure 7 As shown, including:

[0070] include:

[0071] Control the driving circuit TX to output a driving signal with a constant voltage or frequency within a preset range;

[0072] The control chip IO circuit is disconnected from the current amplifier circuit C2I or the charge amplifier circuit CA, and the plate of the capacitor Cm to be measured is reset and the integration circuit is reset;

[0073] The control chip IO circuit and the current amplifier circuit C2I or the charge amplifier circuit CA remain disconnected;

[0074] Obtaining a first electrical signal value Vout,t1 of the output of the integration circuit measured by the analog-to-digital converter SAR-ADC at a first time t1;

[0075] Obtaining a second electrical signal value Vout,t2 of the output of the integration circuit measured by the analog-to-digital converter SAR-ADC at a second time t2; the second time t2 is a time after a preset time after the first time t1 shown;

[0076] Compare the absolute difference between the second electrical signal value Vout, t2 and the first electrical signal value Vout, t1 with a first threshold value;

[0077] If the absolute difference is greater than or equal to the first threshold, the output current of the current calibration circuit is adjusted to calibrate the error caused by the leakage current.

[0078] In some embodiments of the present application, after comparing the absolute difference between the second electrical signal value Vout, t2 and the first electrical signal value Vout, t1 with the first threshold, if the absolute difference is smaller than the first threshold, the output current of the current calibration circuit is kept unchanged.

[0079] The above calibration method is similar to Figure 5 The only difference is that the control chip IO circuit and the current amplifier circuit C2I or the charge amplifier circuit CA are always kept disconnected, that is, S2 is always kept disconnected, so when measuring the second electrical signal value Vout, t2 and the first electrical signal value Vout, t1, it is not connected to the chip IO circuit. Therefore, this method can only compensate for the output voltage error of the integration circuit caused by the current offset of the current amplifier circuit C2I.

[0080] In some embodiments of the present application, the preset range of frequency is preferably 100K-500KHz.

[0081] In some embodiments of the present application, Figure 8 The training sequence of the current calibration method shown is as follows: Figure 8As shown, at the beginning, switches S1, S2, and S3 are in the off state; first, S1 and S3 are turned on, and S2 is in the off state; then S1 and S3 are disconnected; when S1 and S3 are continuously disconnected and S2 is continuously disconnected, ADC collects two signals Vout, t1 and Vout, t2 at time t1 and t2 respectively.

[0082] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope and spirit of the present application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. In addition, each functional unit may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0084] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the claims of the present application.

Claims

1. An analog front-end circuit for capacitance detection, characterized in that: The analog front-end circuit includes: a driving circuit, a capacitor to be measured, a chip signal input and output interface circuit, a current amplifier circuit or a charge amplifier circuit, an integration circuit, an analog-to-digital converter, a leakage current measurement and calibration controller, and a current calibration circuit; the output end of the driving circuit is connected to the input end of the capacitor to be measured; the output end of the capacitor to be measured is connected to the input end of the chip signal input and output interface circuit, the output end of the chip signal input and output interface circuit is connected to the input end of the current amplifier circuit or the charge amplifier circuit, the output end of the current amplifier circuit or the charge amplifier circuit is connected to the input end of the integration circuit, and the output end of the integration circuit is connected to the analog-to-digital converter; wherein, The leakage current measurement and calibration controller is used to receive the signal of the analog-to-digital converter and output a control signal for calibrating the leakage current to the current calibration circuit; The output end of the current calibration circuit is connected to the input end of the integration circuit, and is used to adjust the output of the current calibration circuit to calibrate the current input to the integration circuit when receiving the control signal for calibrating the leakage current.

2. The analog front-end circuit according to claim 1, characterized in that: The current calibration circuit includes a current source and a current sink, wherein the current source is used to increase the input current of the integration circuit, and the current sink is used to reduce the input current of the integration circuit.

3. The analog front-end circuit according to claim 1, characterized in that: The chip signal input and output interface circuit includes an electrostatic discharge circuit.

4. A current calibration method, characterized in that: The method is applied to the analog front-end circuit according to any one of claims 1 to 3, and the method comprises: Control the drive circuit to output a drive signal with a constant voltage or frequency within a preset range; Control the chip signal input / output interface circuit and the current amplification circuit or the method circuit to be in a disconnected state, and control the plate of the capacitor to be measured to be reset and control the integration circuit to be reset; Controlling the chip signal input / output interface circuit and the current amplification circuit or the charge method circuit to maintain a disconnected state or switch to a conductive state; Obtaining a first electrical signal value of the output of the integration circuit measured by the analog-to-digital converter at a first time; Obtain a second electrical signal value of the output of the integration circuit measured by the analog-to-digital converter at a second time; the second time is a time after a preset time after the first time shown; comparing an absolute difference between the second electrical signal value and the first electrical signal value with a first threshold; If the absolute difference is greater than or equal to the first threshold, the output current of the current calibration circuit is adjusted to calibrate the error caused by the leakage current.

5. The method according to claim 4, characterized in that After comparing the absolute difference between the second electrical signal value and the first electrical signal value and the first threshold, the method further includes: If the absolute difference is smaller than the first threshold, the output current of the current calibration circuit is kept unchanged.

6. The method according to claim 4, characterized in that The step of adjusting the output current of the current calibration circuit to calibrate the error caused by the leakage current comprises: Comparing the second electrical signal value with the first electrical signal value; If the value of the second electrical signal is greater than the value of the first electrical signal, the current of the current source of the current calibration circuit is reduced and / or the current of the current sink of the current calibration circuit is increased.

7. The method according to claim 4, characterized in that The step of adjusting the output current of the current calibration circuit to calibrate the error caused by the leakage current comprises: Comparing the second electrical signal value with the first electrical signal value; If the second electrical signal value is smaller than the first electrical signal value, the current of the current source of the current calibration circuit is increased and / or the current of the current sink of the current calibration circuit is decreased.

8. The method according to claim 4, characterized in that After adjusting the output current of the current calibration circuit to calibrate the error caused by the leakage current, the method further includes: The current calibration method is repeated until the absolute difference is less than the first threshold.

9. The method according to claim 4, characterized in that The controlling the plate of the capacitor to be tested to reset comprises: The output end of the chip signal input / output interface circuit is controlled to be connected to a reference voltage source, and then the output end of the chip signal input / output interface circuit is controlled to be disconnected from the reference voltage source.

10. The method according to claim 4, characterized in that The controlling the integration circuit to reset comprises: The output end and the input end of the integration circuit are controlled to be directly connected through a wire, and then the wires of the output end and the input end of the integration circuit are controlled to be directly connected and switched to a disconnected state.

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