Method and device for testing packaging level of MOS (Metal Oxide Semiconductor) transistor
By testing MOS transistors in the test environment corresponding to multiple environmental parameter sets, the problem of inaccurate testing in a single environment state in the prior art is solved, and the accuracy and reliability of the test results are improved.
Patent Information
- Application Number
- CN202411569477.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-02-14
AI Technical Summary
The prior art tests MOS transistors in a single environment state, but fails to fully consider their environmental conditions in specific application scenarios, resulting in inaccurate set of test parameters information.
By obtaining the test text of the MOS transistor to be tested, including the environmental parameter information and test logic of its application scenario, multiple environmental parameter sets are generated, and tested in each test environment to obtain the test parameter information set, and finally determine whether the MOS transistor is qualified. .
It improves the accuracy and reliability of test results and effectively reduces the probability of failure of the product after it is put on the market.
Smart Images
Figure CN119438842A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a packaging-level testing method and device for MOS transistors. Background Art
[0002] With the continuous advancement of electronic technology and the popularization of integrated circuit applications, MOS transistors, as key basic components, have occupied an important position in modern electronic products. Their excellent performance makes them widely used in various electronic devices, such as computers, mobile electronic devices, communication equipment, and power management equipment. Therefore, it is very important to test MOS transistors to ensure the quality and stability of MOS transistors.
[0003] However, the prior art usually tests MOS transistors under a single environmental state, without fully considering the impact of environmental conditions of MOS transistors in specific application scenarios on the performance of MOS transistors, which can easily lead to inaccurate test parameter information sets. Summary of the invention
[0004] The present application provides a packaging-level testing method and device for a MOS transistor to solve the problems raised by the above-mentioned background technology.
[0005] In a first aspect, the present application provides a package-level testing method for a MOS transistor, comprising: Acquire a test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of an application scenario of the MOS transistor to be tested; generating a plurality of environmental parameter sets based on the environmental parameter information; Testing the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested; Whether the MOS transistor to be tested is qualified is determined based on the test parameter information set.
[0006] In a possible implementation, the environmental parameter information includes parameter threshold ranges of multiple environmental parameters, and generating multiple environmental parameter sets based on the environmental parameter information includes: For each of the environmental parameters, determining a minimum value of a parameter threshold range of the environmental parameter as a first target parameter value of the environmental parameter, and determining a maximum value of the parameter threshold range of the environmental parameter as a second target parameter value of the environmental parameter; A Cartesian product operation is performed on the first target parameter value and the second target parameter value corresponding to each of the environmental parameters to obtain the multiple environmental parameter sets.
[0007] In a possible implementation, the MOS transistor to be tested is tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested, including: For each of the environmental parameter sets, a test environment of the MOS transistor to be tested is set based on the environmental parameter set, and the MOS transistor to be tested is tested in the test environment based on the test logic to obtain test parameter information corresponding to the environmental parameter set, and an association relationship between the environmental parameter set and the test parameter information is established; The various association relationships are integrated to obtain the test parameter information set.
[0008] In a possible implementation, the testing the MOS transistor to be tested based on the test logic in the test environment to obtain the test parameter information corresponding to the environment parameter set includes: Applying gate voltages to the MOS transistor to be tested in sequence from an initial voltage value to a maximum voltage value in a preset voltage step, and obtaining a first drain current corresponding to each gate voltage; Applying gate voltages to the MOS transistors to be tested in sequence from the maximum voltage value to the initial voltage value in a preset voltage step reduction, and obtaining a second drain current corresponding to each gate voltage; wherein the voltage step reduction is consistent with a value corresponding to the voltage step; Drawing a first relationship curve between the gate voltage and the first drain current based on the first drain current corresponding to each of the gate voltages, and drawing a second relationship curve between the gate voltage and the second drain current based on the second drain current corresponding to each of the gate voltages; wherein the horizontal axis of the first relationship curve is the gate voltage, and the vertical axis is the first drain current, and the horizontal axis of the second relationship curve is the gate voltage, and the vertical axis is the second drain current; The first relationship curve is analyzed based on a preset elbow analysis algorithm to obtain a first voltage threshold, and the second relationship curve is analyzed based on the elbow analysis algorithm to obtain a second voltage threshold; the first voltage threshold and the second voltage threshold constitute the test parameter information.
[0009] In a possible implementation, judging whether the MOS transistor to be tested is qualified based on the test parameter information set includes: For each of the environmental parameter sets, determining a voltage threshold deviation index of the MOS transistor to be tested in the test environment corresponding to the environmental parameter set based on the test parameter information corresponding to the environmental parameter set and a preset voltage threshold; Respectively comparing each of the voltage threshold deviation indexes with a preset voltage threshold deviation index; If each of the voltage threshold deviation indexes is not greater than the preset voltage threshold deviation index, it is determined that the MOS transistor to be tested is qualified; The step of determining the voltage threshold deviation index of the MOS transistor to be tested in the test environment corresponding to the environmental parameter set based on the test parameter information corresponding to the environmental parameter set and the preset voltage threshold comprises: Obtaining a first absolute value of a difference between a first voltage threshold and a second voltage threshold corresponding to the environmental parameter set, obtaining a second absolute value of a difference between the first voltage threshold and a preset voltage threshold, and obtaining a third absolute value of a difference between the second voltage threshold and the preset voltage threshold; comparing the second absolute value to a third absolute value; If the second absolute value is greater than the third absolute value, calculating a ratio between the second absolute value and the preset voltage threshold, and determining a product of the ratio and the first absolute value as the voltage threshold deviation index; If the third absolute value is greater than the second absolute value, a ratio between the third absolute value and the preset voltage threshold is calculated, and a product of the ratio and the first absolute value is determined as the voltage threshold deviation index.
[0010] In a second aspect, the present application provides a package-level testing device for a MOS transistor, comprising: An acquisition module, used for acquiring a test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of an application scenario of the MOS transistor to be tested; A generating module, used for generating a plurality of environmental parameter sets based on the environmental parameter information; A testing module, used to test the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets, to obtain a test parameter information set of the MOS transistor to be tested; A judgment module is used to judge whether the MOS transistor to be tested is qualified based on the test parameter information set.
[0011] In a possible implementation, the environmental parameter information includes parameter threshold ranges of multiple environmental parameters, and the generating module includes: a determining unit, configured to determine, for each of the environmental parameters, a minimum value of a parameter threshold range of the environmental parameter as a first target parameter value of the environmental parameter, and a maximum value of the parameter threshold range of the environmental parameter as a second target parameter value of the environmental parameter; The calculation unit is used to perform a Cartesian product operation on the first target parameter value and the second target parameter value corresponding to each of the environmental parameters to obtain the multiple environmental parameter sets.
[0012] In a possible implementation, the test module includes: A testing unit, for setting a test environment for the MOS transistor to be tested based on the environmental parameter set for each of the environmental parameter sets, and testing the MOS transistor to be tested based on the test logic in the test environment, obtaining test parameter information corresponding to the environmental parameter set, and establishing an association relationship between the environmental parameter set and the test parameter information; The integration unit is used to integrate each of the association relationships to obtain the test parameter information set.
[0013] The present application provides a packaging-level testing method and device for MOS transistors, wherein the method includes: obtaining a test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of the application scenario of the MOS transistor to be tested; generating multiple environmental parameter sets based on the environmental parameter information; testing the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested; and judging whether the MOS transistor to be tested is qualified based on the test parameter information set. The method generates multiple environmental parameter sets based on environmental parameter information, and tests the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested, and judging whether the MOS transistor to be tested is qualified based on the test parameter information set, thereby improving the accuracy and reliability of the test results and being able to effectively reduce the probability of failure of the product after it is put on the market. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.
[0015] Figure 1 A schematic diagram of a flow chart of a packaging level testing method for a MOS transistor provided in an embodiment of the present application; Figure 2 A schematic block diagram of the structure of a package-level test device for a MOS transistor provided in an embodiment of the present application; Figure 3 A schematic block diagram of the structure of a terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0017] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change based on actual conditions.
[0018] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.
[0019] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0020] With the continuous advancement of electronic technology and the popularization of integrated circuit applications, MOS transistors, as key basic components, have occupied an important position in modern electronic products. Their excellent performance makes them widely used in various electronic devices, such as computers, mobile electronic devices, communication equipment, and power management equipment. Therefore, it is very important to test MOS transistors to ensure the quality and stability of MOS transistors.
[0021] However, the prior art usually tests MOS transistors under a single environmental state, without fully considering the impact of environmental conditions on the performance of MOS transistors in specific application scenarios, which easily leads to inaccurate test parameter information sets. To this end, the present application provides a packaging-level test method and device for MOS transistors to solve the above problems.
[0022] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0023] See also Figure 1 , Figure 1 A schematic diagram of a process flow of a packaging level test method for a MOS transistor provided in an embodiment of the present application is shown in FIG. Figure 1As shown, the packaging-level testing method for a MOS transistor provided in an embodiment of the present application includes steps S1 to S4.
[0024] Step S1, obtaining a test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of an application scenario of the MOS transistor to be tested.
[0025] Step S2: Generate multiple environmental parameter sets based on the environmental parameter information.
[0026] Step S3: testing the MOS transistor to be tested based on the test logic in the test environments corresponding to the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested.
[0027] Step S4: judging whether the MOS transistor to be tested is qualified based on the test parameter information set.
[0028] In this embodiment, an automated testing device is used to test the MOS transistor to be tested. The manipulator of the automated testing device connects the gate, source and drain of the MOS transistor to be tested to the test pins of a test position. The test position is arranged in a closed shell. An environmental state regulating device is arranged in the closed shell. The environmental state regulating device is used to adjust the environmental state in the closed shell.
[0029] As described in the above step S1, the test text of the MOS transistor to be tested is obtained. Specifically, the scanning device of the automated test equipment scans the two-dimensional code set on the MOS transistor to be tested to obtain the transistor identification of the MOS transistor to be tested, and the central processor of the automated test equipment obtains the test text in the database according to the identification code, and the database stores the corresponding relationship between the test text and the transistor identification.
[0030] As described in steps S2 to S3 above, in order to improve the accuracy of the test parameter information set of the MOS transistor to be tested, the influence of the environmental parameter information of the application scenario of the MOS transistor to be tested on the MOS transistor to be tested is fully considered, a plurality of environmental parameter sets are generated based on the environmental parameter information, and the MOS transistor to be tested is tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain the test parameter information set of the MOS transistor to be tested.
[0031] Specifically, the environmental parameter information includes parameter threshold ranges of multiple environmental parameters, and generating multiple environmental parameter sets based on the environmental parameter information includes: for each of the environmental parameters, determining that the minimum value of the parameter threshold range of the environmental parameter is the first target parameter value of the environmental parameter, and determining the maximum value of the parameter threshold range of the environmental parameter is the second target parameter value of the environmental parameter; performing Cartesian product operations on the first target parameter value and the second target parameter value corresponding to each of the environmental parameters to obtain the multiple environmental parameter sets. Among them, the environmental parameters include but are not limited to temperature, humidity, and magnetic field strength. The Cartesian product refers to the set of all possible ordered pairs in two or two sets. Exemplarily, the environmental parameter information includes the parameter threshold range of temperature [5°C, 40°C], the parameter threshold range of humidity [15%, 60%], and the parameter threshold range of magnetic field strength [0.015T, 2T]. The set corresponding to temperature is (5°C, 40°C), the set corresponding to humidity is (15%, 60%), and the set corresponding to magnetic field strength is (0.015T, 2T). Cartesian product operations are performed on the three sets of (5°C, 40°C), (15%, 60%) and (0.015T, 2T), and 8 environmental parameter sets are obtained, namely (5°C, 15%, 0.015T), (5°C, 15%, 2T), (5°C, 60%, 0.015T), (5°C, 60%, 2T), (40°C, 15%, 0.015T), (40°C, 15%, 2T), (40°C, 60%, 0.015T), (40°C, 60%, 2T). It can be understood that the above method of generating multiple environmental parameter sets based on the environmental parameter information can ensure that the subsequent test environment covers various extreme environmental conditions of the MOS transistor to be tested in actual application scenarios, which helps to improve the accuracy of the test parameter information set.
[0032] Specifically, the MOS transistor to be tested is tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain the test parameter information set of the MOS transistor to be tested, including: for each of the environmental parameter sets, the test environment of the MOS transistor to be tested is set based on the environmental parameter set, and the MOS transistor to be tested is tested based on the test logic in the test environment to obtain the test parameter information corresponding to the environmental parameter set, and an association relationship between the environmental parameter set and the test parameter information is constructed; and each of the association relationships is integrated to obtain the test parameter information set. In this embodiment, the central controller of the automated test equipment controls the environmental state adjustment device to adjust the environmental state in the closed shell based on the environmental parameter set to provide the MOS transistor to be tested with a test environment matching the environmental parameter set.
[0033] The MOS transistor to be tested is tested based on the test logic in the test environment to obtain the test parameter information corresponding to the environmental parameter set, including: applying gate voltage to the MOS transistor to be tested in sequence from an initial voltage value to a maximum voltage value with a preset voltage step, and obtaining a first drain current corresponding to each gate voltage; applying gate voltage to the MOS transistor to be tested in sequence from the maximum voltage value to the initial voltage value with a preset voltage step reduction, and obtaining a second drain current corresponding to each gate voltage; wherein the voltage step reduction is consistent with the value corresponding to the voltage step; drawing a first relationship curve between the gate voltage and the first drain current based on the first drain current corresponding to each gate voltage, and obtaining a first drain current corresponding to each gate voltage based on the first drain current corresponding to each gate voltage. The second drain current corresponding to the gate voltage draws a second relationship curve between the gate voltage and the second drain current, wherein the horizontal axis of the first relationship curve is the gate voltage and the vertical axis is the first drain current, and the horizontal axis of the second relationship curve is the gate voltage and the vertical axis is the second drain current; the first relationship curve is analyzed based on a preset elbow analysis algorithm to obtain a first target point where the first drain current begins to increase significantly, and the voltage value corresponding to the first target point is determined to be a first voltage threshold, and the second relationship curve is analyzed based on the elbow analysis algorithm to obtain a second target point where the second drain current begins to increase significantly, and the voltage value corresponding to the second target point is determined to be a second voltage threshold; the first voltage threshold and the second voltage threshold constitute the test parameter information. In the existing method, when testing a MOS transistor, usually only the first voltage threshold is obtained, and whether the MOS transistor is qualified is judged based on the first voltage threshold, while the method provided in this embodiment obtains the first voltage threshold and the second voltage threshold corresponding to the environmental parameter set for each of the environmental parameter sets, thereby improving the diversity of the test parameters and helping to improve the accuracy of the test results.
[0034] As described in the above step S4, whether the MOS transistor to be tested is qualified is determined based on the test parameter information set.
[0035] Specifically, judging whether the MOS transistor to be tested is qualified based on the test parameter information set comprises the following steps: For each of the environmental parameter sets, determining a voltage threshold deviation index of the MOS transistor to be tested in the test environment corresponding to the environmental parameter set based on the test parameter information corresponding to the environmental parameter set and a preset voltage threshold; Respectively comparing each of the voltage threshold deviation indexes with a preset voltage threshold deviation index; If any of the voltage threshold deviation indexes is greater than the preset voltage threshold deviation index, it is determined that the MOS transistor to be tested is unqualified; If each of the voltage threshold deviation indexes is not greater than the preset voltage threshold deviation index, it is determined that the MOS transistor to be tested is qualified; The step of determining the voltage threshold deviation index of the MOS transistor to be tested in the test environment corresponding to the environmental parameter set based on the test parameter information corresponding to the environmental parameter set and the preset voltage threshold comprises: Obtaining a first absolute value of a difference between a first voltage threshold and a second voltage threshold corresponding to the environmental parameter set, obtaining a second absolute value of a difference between the first voltage threshold and a preset voltage threshold, and obtaining a third absolute value of a difference between the second voltage threshold and the preset voltage threshold; comparing the second absolute value to a third absolute value; If the second absolute value is greater than the third absolute value, calculating a ratio between the second absolute value and the preset voltage threshold, and determining the product of the ratio and the first absolute value as the voltage threshold deviation index; specifically, dividing the second absolute value by the preset voltage threshold to obtain the ratio; If the third absolute value is greater than the second absolute value, calculate the ratio between the third absolute value and the preset voltage threshold, and determine the product of the ratio and the first absolute value as the voltage threshold deviation index; specifically, divide the third absolute value by the preset voltage threshold to obtain the ratio.
[0036] The method provided in this embodiment generates multiple environmental parameter sets based on environmental parameter information, and tests the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested, and determines whether the MOS transistor to be tested is qualified based on the test parameter information set, thereby improving the accuracy and reliability of the test results and being able to effectively reduce the probability of failure of the product after it is put on the market.
[0037] See also Figure 2 , Figure 2 The schematic block diagram of the structure of the MOS transistor package level test device 100 provided in the embodiment of the present application is as follows: Figure 2 As shown, a package-level test device 100 for a MOS transistor comprises: The acquisition module 110 is used to acquire the test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of the application scenario of the MOS transistor to be tested.
[0038] The generating module 120 is used to generate a plurality of environmental parameter sets based on the environmental parameter information.
[0039] The testing module 130 is used to test the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested.
[0040] The judgment module 140 is used to judge whether the MOS transistor to be tested is qualified based on the test parameter information set.
[0041] In some embodiments, the environmental parameter information includes parameter threshold ranges of multiple environmental parameters, and the generating module includes: a determining unit, configured to determine, for each of the environmental parameters, a minimum value of a parameter threshold range of the environmental parameter as a first target parameter value of the environmental parameter, and a maximum value of the parameter threshold range of the environmental parameter as a second target parameter value of the environmental parameter; The calculation unit is used to perform a Cartesian product operation on the first target parameter value and the second target parameter value corresponding to each of the environmental parameters to obtain the multiple environmental parameter sets.
[0042] In some embodiments, the test module comprises: A testing unit, for setting a test environment for the MOS transistor to be tested based on the environmental parameter set for each of the environmental parameter sets, and testing the MOS transistor to be tested based on the test logic in the test environment, obtaining test parameter information corresponding to the environmental parameter set, and establishing an association relationship between the environmental parameter set and the test parameter information; The integration unit is used to integrate each of the association relationships to obtain the test parameter information set.
[0043] It should be noted that technicians in the relevant technical field can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described devices, modules and units can refer to the corresponding processes in the aforementioned MOS transistor packaging level testing method embodiment, and will not be repeated here.
[0044] The terminal device 200 provided in the above embodiment can be implemented in the form of a computer program. The computer program can be Figure 3 The system is run on the terminal device 200 shown.
[0045] See also Figure 3 , Figure 3 The present invention provides a schematic block diagram of the structure of a terminal device 200 according to an embodiment of the present application. The terminal device 200 includes a processor 201 and a memory 202. The processor 201 and the memory 202 are connected via a device bus 203, wherein the memory 202 may include a non-volatile storage medium and an internal memory.
[0046] The non-volatile storage medium can store a computer program. The computer program includes program instructions, and when the program instructions are executed by the processor 201, the processor 201 can execute any of the above-mentioned package-level testing methods for MOS transistors.
[0047] The processor 201 is used to provide computing and control capabilities to support the operation of the entire terminal device 200.
[0048] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor 201, the processor 201 can execute any of the above-mentioned package-level testing methods for MOS transistors.
[0049] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the terminal device 200 involved in the scheme of the present application. The specific terminal device 200 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.
[0050] It should be understood that the processor 201 may be a central processing unit (CPU), and the processor 201 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0051] In some embodiments, the processor 201 is used to run a computer program stored in the memory to implement the following steps: Acquire a test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of an application scenario of the MOS transistor to be tested; generating a plurality of environmental parameter sets based on the environmental parameter information; Testing the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested; Whether the MOS transistor to be tested is qualified is determined based on the test parameter information set.
[0052] It should be noted that technicians in the relevant field can clearly understand that for the convenience and simplicity of description, the specific working process of the terminal device 200 described above can refer to the corresponding process of the aforementioned MOS transistor packaging level testing method, and will not be repeated here.
[0053] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by one or more processors, the one or more processors implement the packaging-level testing method of the MOS transistor provided in the embodiment of the present application.
[0054] The computer-readable storage medium may be an internal storage unit of the terminal device 200 in the aforementioned embodiment, such as a hard disk or memory of the terminal device 200. The computer-readable storage medium may also be an external storage device of the terminal device 200, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped with the terminal device 200.
[0055] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A packaging level testing method for a MOS transistor, characterized in that: include: Acquire a test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of an application scenario of the MOS transistor to be tested; generating a plurality of environmental parameter sets based on the environmental parameter information; Testing the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested; Whether the MOS transistor to be tested is qualified is determined based on the test parameter information set.
2. The packaging level testing method of MOS transistor according to claim 1, characterized in that: The environmental parameter information includes parameter threshold ranges of multiple environmental parameters, and the generating of multiple environmental parameter sets based on the environmental parameter information includes: For each of the environmental parameters, determining a minimum value of a parameter threshold range of the environmental parameter as a first target parameter value of the environmental parameter, and determining a maximum value of the parameter threshold range of the environmental parameter as a second target parameter value of the environmental parameter; A Cartesian product operation is performed on the first target parameter value and the second target parameter value corresponding to each of the environmental parameters to obtain the multiple environmental parameter sets.
3. The packaging level testing method of MOS transistor according to claim 1, characterized in that: The MOS transistor to be tested is tested based on the test logic in the test environment corresponding to each of the environmental parameter sets to obtain a test parameter information set of the MOS transistor to be tested, including: For each of the environmental parameter sets, a test environment of the MOS transistor to be tested is set based on the environmental parameter set, and the MOS transistor to be tested is tested in the test environment based on the test logic to obtain test parameter information corresponding to the environmental parameter set, and an association relationship between the environmental parameter set and the test parameter information is established; The various association relationships are integrated to obtain the test parameter information set.
4. The packaging level testing method of MOS transistor according to claim 3, characterized in that: The testing the MOS transistor to be tested based on the test logic in the test environment to obtain the test parameter information corresponding to the environment parameter set includes: Applying gate voltages to the MOS transistor to be tested in sequence from an initial voltage value to a maximum voltage value in a preset voltage step, and obtaining a first drain current corresponding to each gate voltage; Applying gate voltages to the MOS transistors to be tested in sequence from the maximum voltage value to the initial voltage value in a preset voltage step reduction, and obtaining a second drain current corresponding to each gate voltage; wherein the voltage step reduction is consistent with a value corresponding to the voltage step; A first relationship curve between the gate voltage and the first drain current is drawn based on the first drain current corresponding to each of the gate voltages, and a second relationship curve between the gate voltage and the second drain current is drawn based on the second drain current corresponding to each of the gate voltages; wherein the horizontal axis of the first relationship curve is the gate voltage and the vertical axis is the first drain current, and the horizontal axis of the second relationship curve is the gate voltage and the vertical axis is the second drain current; The first relationship curve is analyzed based on a preset elbow analysis algorithm to obtain a first voltage threshold, and the second relationship curve is analyzed based on the elbow analysis algorithm to obtain a second voltage threshold; the first voltage threshold and the second voltage threshold constitute the test parameter information.
5. The packaging level testing method of MOS transistor according to claim 4, characterized in that: The determining whether the MOS transistor to be tested is qualified based on the test parameter information set includes: For each of the environmental parameter sets, determining a voltage threshold deviation index of the MOS transistor to be tested in the test environment corresponding to the environmental parameter set based on the test parameter information corresponding to the environmental parameter set and a preset voltage threshold; Respectively comparing each of the voltage threshold deviation indexes with a preset voltage threshold deviation index; If each of the voltage threshold deviation indexes is not greater than the preset voltage threshold deviation index, it is determined that the MOS transistor to be tested is qualified; The step of determining the voltage threshold deviation index of the MOS transistor to be tested in the test environment corresponding to the environmental parameter set based on the test parameter information corresponding to the environmental parameter set and the preset voltage threshold comprises: Obtaining a first absolute value of a difference between a first voltage threshold and a second voltage threshold corresponding to the environmental parameter set, obtaining a second absolute value of a difference between the first voltage threshold and a preset voltage threshold, and obtaining a third absolute value of a difference between the second voltage threshold and the preset voltage threshold; comparing the second absolute value to a third absolute value; If the second absolute value is greater than the third absolute value, calculating a ratio between the second absolute value and the preset voltage threshold, and determining a product of the ratio and the first absolute value as the voltage threshold deviation index; If the third absolute value is greater than the second absolute value, a ratio between the third absolute value and the preset voltage threshold is calculated, and a product of the ratio and the first absolute value is determined as the voltage threshold deviation index.
6. A packaging level test device for MOS transistors, characterized in that: include: An acquisition module, used for acquiring a test text of the MOS transistor to be tested; wherein the test text includes environmental parameter information and test logic of an application scenario of the MOS transistor to be tested; A generating module, used for generating a plurality of environmental parameter sets based on the environmental parameter information; A testing module, used to test the MOS transistor to be tested based on the test logic in the test environment corresponding to each of the environmental parameter sets, to obtain a test parameter information set of the MOS transistor to be tested; A judgment module is used to judge whether the MOS transistor to be tested is qualified based on the test parameter information set.
7. The transistor packaging level testing device according to claim 6, characterized in that: The environmental parameter information includes parameter threshold ranges of multiple environmental parameters, and the generating module includes: a determining unit, configured to determine, for each of the environmental parameters, a minimum value of a parameter threshold range of the environmental parameter as a first target parameter value of the environmental parameter, and a maximum value of the parameter threshold range of the environmental parameter as a second target parameter value of the environmental parameter; The calculation unit is used to perform a Cartesian product operation on the first target parameter value and the second target parameter value corresponding to each of the environmental parameters to obtain the multiple environmental parameter sets.
8. The transistor packaging level testing device according to claim 6, characterized in that: The test module comprises: A testing unit, for setting a test environment for the MOS transistor to be tested based on the environmental parameter set for each of the environmental parameter sets, and testing the MOS transistor to be tested based on the test logic in the test environment, obtaining test parameter information corresponding to the environmental parameter set, and establishing an association relationship between the environmental parameter set and the test parameter information; The integration unit is used to integrate each of the association relationships to obtain the test parameter information set.