CAF failure positioning analysis method and device
By designing test boards with specific structures and half-processing methods, the problem of difficult to quickly locate CAF failure points in PCB in the prior art is solved, and the CAF failure positioning and efficiency improvement from hole to copper is achieved.
Patent Information
- Application Number
- CN202411531822.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-14
AI Technical Summary
The prior art is difficult to quickly locate CAF failure points in PCBs, especially in hole-to-copper testing.
By designing a test board, including the first test outer layer, multiple test inner layers, test holes, communication holes and isolation pads, the test inner layer is divided into modules by using a half-processing method, and the target test is determined in combination with resistance value testing. layer and test hole.
The CAF failure positioning from hole to copper is achieved, the testing efficiency is improved, and the location of the CAF phenomenon can be quickly identified and analyzed.
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Figure CN119438860A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of CAF testing technology, and in particular to a CAF failure location analysis method and device. Background Art
[0002] Conductive Anodic Fi lament (CAF) refers to the leakage behavior of copper and copper salts that occurs when copper ions migrate from the anode (high voltage) along the micro-crack channels between the glass fibers to the cathode (low voltage) inside the PCB. When the PCB is energized and works in a high temperature and high humidity environment, serious CAF may grow along the resin or glass fiber interface between the two insulated conductors. This phenomenon will eventually lead to poor insulation of the PCB or even short circuit failure.
[0003] At present, most of the tests for PCB CAF are hole-to-hole tests, and hole-to-copper tests are rare. In addition, when a test fails, the failure point cannot be quickly located. Therefore, how to provide a hole-to-copper CAF failure location analysis method has become a technical problem that needs to be solved urgently. Summary of the invention
[0004] The main purpose of the embodiments of the present application is to provide a CAF failure location analysis method and device, aiming to achieve CAF failure location from hole to copper.
[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes a CAF failure location analysis method, which is applied to a test board, wherein the test board comprises: a first test outer layer, multiple test inner layers, a test hole, a connecting hole and an isolation pad, wherein the test hole penetrates the first test outer layer and the multiple test inner layers, and the connecting hole penetrates the first test outer layer and the multiple test inner layers; the connecting hole comprises a first connecting sub-hole and multiple second connecting sub-holes, wherein the first connecting sub-hole on the first test outer layer is connected to the corresponding test hole, and the second connecting sub-hole on the test inner layer is connected to the corresponding test inner layer; the isolation pad is arranged on the test inner layer, and the isolation pad is used to isolate the test hole arranged on the test inner layer from the corresponding test inner layer;
[0006] The method comprises:
[0007] Processing the plurality of test inner layers in half to obtain a first test module and a second test module;
[0008] A target test layer is determined from the first test module or the second test module according to the resistance value between the first test module and the first test outer layer and the resistance value between the second test module and the first test outer layer.
[0009] In some embodiments, the plurality of test holes on the first test outer layer are divided into a plurality of test groups, the hole parameters of the plurality of test holes are different, the plurality of test holes in each test group are connected in sequence, and the plurality of test groups are respectively connected to the first connected sub-holes;
[0010] The method further comprises:
[0011] Divide the plurality of test groups into halves to obtain a third test module and a fourth test module;
[0012] A target test hole is determined from the third test module or the fourth test module according to the resistance value of the third test module and the target test layer and the resistance value of the fourth test module and the target test layer.
[0013] In some embodiments, the third test module includes a test group, the fourth test module includes a test group, and determining the target test hole from the third test module and the fourth test module according to the resistance value between the third test module and the target test layer and the resistance value between the fourth test module and the target test layer includes:
[0014] If the resistance of the third test module is determined to be abnormal according to the resistance of the third test module and the target test layer and the resistance of the fourth test module and the target test layer, the test holes corresponding to the third test module are processed in half to obtain a first hole group and a second hole group;
[0015] The target test hole is determined from the first hole group or the second hole group according to the resistance value of the first hole group and the target test layer and the resistance value of the second hole group and the target test layer.
[0016] In some embodiments, each test inner layer is provided with an isolation piece, and the corresponding test hole and the second communicating sub-hole are provided in the isolation piece.
[0017] In some embodiments, the test board further includes a second test outer layer; wherein the test hole penetrates the second test outer layer, and the connecting hole penetrates the second test outer layer.
[0018] In some embodiments, the test holes are distributed in a matrix.
[0019] To achieve the above-mentioned purpose, the second aspect of the embodiment of the present application proposes a CAF failure location analysis device, the device is applied to a test board, the test board comprises: a first test outer layer, multiple test inner layers, a test hole, a connecting hole and an isolation pad, the test hole penetrates the first test outer layer and the multiple test inner layers, the connecting hole penetrates the first test outer layer and the multiple test inner layers; the connecting hole comprises a first connecting sub-hole and multiple second connecting sub-holes, the first connecting sub-hole on the first test outer layer is connected to the corresponding test hole, and the second connecting sub-hole on the test inner layer is connected to the corresponding test inner layer; the isolation pad is arranged on the test inner layer, and the isolation pad is used to isolate the test hole arranged on the test inner layer from the corresponding test inner layer;
[0020] The device comprises:
[0021] A half-division module, used for processing the plurality of test inner layers in half to obtain a first test module and a second test module;
[0022] The resistance test module is used to determine a target test layer from the first test module and the second test module according to the resistance between the first test module and the first test outer layer and the resistance between the second test module and the first test outer layer.
[0023] The data CAF failure location analysis method and device proposed in the present application are provided with a test board including a first test outer layer, multiple test inner layers, test holes, connecting holes and isolation pads, and the multiple test inner layers of the test board are processed in half to obtain a first test module and a second test module. Through the resistance value of the first test module and the first test outer layer, and the resistance value of the second test module and the test outer layer, the target test layer can be determined from the first test module or the second test module. It can be seen that the embodiment of the present application can quickly locate the CAF phenomenon in the target test layer and the test hole on the first test outer layer based on the half-processing, that is, the CAF failure location from hole to copper is realized. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a schematic diagram of a first test outer layer provided in an embodiment of the present application;
[0025] FIG. 2A to FIG. 2D is a schematic diagram of the test inner layer provided in an embodiment of the present application;
[0026] Figure 2E This is a schematic diagram of inner layer failure testing provided by an embodiment of the present application;
[0027] Figure 2F It is a failure diagram in practical application provided by the embodiment of the present application;
[0028] Figure 3 is a schematic diagram of a second test outer layer provided in an embodiment of the present application;
[0029] Figure 4 is a flow chart of a CAF failure location analysis method provided in an embodiment of the present application;
[0030] Figure 5 is a schematic diagram of determining a third test module and a fourth test module provided in an embodiment of the present application;
[0031] Figure 6 is a flow chart of another embodiment of the CAF failure location analysis method provided in an embodiment of the present application;
[0032] Figure 7 yes Figure 6 Flowchart of step S602 in FIG.
[0033] Figure 8 is a schematic diagram of determining a first hole group and a second hole group provided in an embodiment of the present application;
[0034] 9A to 9D It is a schematic diagram of the implementation of the CAF failure location analysis method provided in the embodiment of the present application;
[0035] Fig.10 It is a schematic diagram of the structure of a CAF failure location analysis device provided in an embodiment of the present application.
[0036] Figure markings: first test outer layer 101, test inner layer 102, test hole 103, first connected sub-hole 104, second connected sub-hole 105, test group 106, third test module 107, fourth test module 108, first hole group 109, second hole group 110, isolation piece 111, second test outer layer 112, target test hole 113, isolation pad 114, failure point 115. DETAILED DESCRIPTION
[0037] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0038] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0040] At present, Conductive Anodic Fi lament (CAF) refers to the leakage behavior of copper and copper salts that occurs when copper ions migrate from the anode (high voltage) along the micro-crack channels between glass fibers to the cathode (low voltage) inside the PCB. When the PCB is working under high temperature and high humidity, serious CAF may grow along the interface of resin or glass fiber between two insulated conductors. This phenomenon will eventually lead to poor insulation of the PCB or even short circuit failure.
[0041] In the related art, most of the tests for PCB CAF are hole-to-hole tests.
[0042] Based on this, an embodiment of the present application provides a CAF failure location analysis method, aiming to implement hole-to-copper CAF testing.
[0043] The CAF failure location analysis method and device provided in the embodiments of the present application are specifically described through the following embodiments. First, the CAF failure location analysis method in the embodiments of the present application is described.
[0044] Reference Figure 1 , FIG. 2A to FIG. 2E, the CAF failure location analysis method provided in the embodiment of the present application can be applied to a test board. The test board may refer to a PCB for CAF testing. The test board includes a first test outer layer 101, multiple test inner layers 102, a test hole 103, a connecting hole and an isolation pad 114. The test hole 103 penetrates the first test outer layer 101 and multiple test inner layers 102, and the connecting hole penetrates the first test outer layer 101 and multiple test inner layers 102. The connecting hole includes a first connecting sub-hole 104 and multiple second connecting sub-holes 105. The first connecting sub-hole 104 on the first test outer layer 101 is connected to the corresponding test hole 103, and the second connecting sub-hole 105 on the test inner layer 102 is connected to the corresponding test inner layer 102. The isolation pad 114 is set on the test inner layer 102, and the isolation pad 114 is used to isolate the test hole 103 set on the test inner layer 102 from the corresponding test inner layer 102. Specifically, the test board is designed as a multi-layer board, and the test board may include a test outer layer and multiple test inner layers 102. The test hole 103 and the connecting hole can both be designed as through holes, that is, the test hole 103 and the connecting hole can pass through all layers of the test board. Each test hole 103 arranged on the test inner layer 102 is circumferentially provided with an isolation pad 114. The isolation pad 114 has an insulating property and can isolate the test hole 103 from the test inner layer 102, that is, the test hole 103 arranged on the test inner layer 102 is not conductive with the corresponding test inner layer 102. The isolation pad 114 can make the test hole 103 an independent test network. It can be understood that the size of the isolation pad 114 can be adaptively set according to the distance from the hole wall to the copper, and a gap needs to be designed around the test pattern of the test inner layer 102. It can be understood that, on each test inner layer 102, except for the second connecting sub-hole 105 corresponding to the test inner layer 102, which has no isolation pad 114 on the circumference, the remaining second connecting sub-holes 105 are also provided with isolation pads 114 on the circumference, that is, the second connecting sub-hole 105 can be connected with the corresponding test inner layer 102.
[0045] The test hole 103 may refer to a hole for performing a hole-to-copper CAF test, and the connecting hole may refer to a hole for connecting the test hole 103 to the first test outer layer 101. In this way, according to the first test outer layer 101 and the test inner layer 102, the connecting hole can be divided into a first connecting sub-hole 104 and a second connecting sub-hole 105. Among them, the first connecting sub-hole 104 is used to connect with the test hole 103 on the first test outer layer 101, and the second connecting sub-hole 105 is used to connect with the corresponding test inner layer 102. That is, through the second connecting sub-hole 105, the area where the corresponding test hole 103 is located can be connected to the first test outer layer 101. It can be understood that the number of test holes 103 and second connecting sub-holes 105 can be adaptively set according to actual needs. For example, when only a CAF test is required for a hole with a fixed aperture and / or a fixed hole wall to copper spacing, the number of test holes 103 can be set to one. When CAF tests are required for holes with different apertures and / or different hole wall to copper spacings, the number of test holes 103 can be set to multiple. The number of the second connecting sub-holes 105 may correspond to the number of the test inner layers 102. It is understandable that when there are multiple test holes 103, the multiple test holes 103 may be distributed in a matrix, or the multiple test holes 103 may be adaptively arranged according to actual needs, which is not specifically limited in the embodiment of the present application.
[0046] In a specific embodiment, the test board may include four test inner layers 102, and the number of the second connecting sub-holes 105 may be 4. That is, the test board includes a first test outer layer L1, a test inner layer L2, a test inner layer L3, a test inner layer L4, and a test inner layer L5. Figure 2A As shown in FIG. 1 , it is a schematic diagram of the arrangement of the test hole 103 and the second connecting sub-hole 105 on the test inner layer L2. Figure 2B As shown in FIG. 1 , it is a schematic diagram of the arrangement of the test hole 103 and the second connecting sub-hole 105 on the test inner layer L3. Figure 2C As shown in FIG. 1 , it is a schematic diagram of the arrangement of the test hole 103 and the second connecting sub-hole 105 on the test inner layer L4. Figure 2D , which is a schematic diagram of the arrangement of the test hole 103 and the second connecting sub-hole 105 on the test inner layer L5.
[0047] Refer to 2A to Figure 2D In some embodiments, an isolation member 111 is provided on each test inner layer 102 , and a corresponding test hole 103 and a second connecting sub-hole 105 are provided in the isolation member 111 , so that the area where the test hole 103 is located can be isolated from other areas of the test inner layer 102 .
[0048] Reference Figure 3In some embodiments, the test board may further include a second test outer layer, that is, the test board may sequentially include a first test outer layer, a plurality of test inner layers, and a second test outer layer from top to bottom. Similarly, the test hole 103 and the connecting hole may both penetrate the second test outer layer 112.
[0049] Reference Figure 4 The CAF failure location analysis method provided in the embodiment of the present application may include but is not limited to steps S401 to S402.
[0050] Step S401, splitting and processing multiple test inner layers into halves to obtain a first test module and a second test module;
[0051] Step S402 , determining a target test layer from the first test module or the second test module according to the resistance value between the first test module and the first test outer layer and the resistance value between the second test module and the first test outer layer.
[0052] In step S401 of some embodiments, the half-processing may refer to dividing multiple test inner layers 102 into two test modules for CAF failure location. For example, the half-processing may obtain a first test module and a second test module. Among them, the first test module may include a test inner layer L2 and a test inner layer L3, and the second test module may include a test inner layer L4 and a test inner layer L5. It can be understood that the number of test inner layers included in the first test module and the second test may be the same or different, and this embodiment of the present application is not specifically limited. For example, when it is determined that there is a high probability of a CAF phenomenon between a certain test inner layer 102 (such as a test inner layer L2) and a test hole 103, the test inner layer 102 (such as a test inner layer L2) can be used alone as a first test module, and the remaining test inner layers 102 (such as test inner layers L3, test inner layers L4 and test inner layers L5) can be used as second test modules. When the probability of CAF between each test inner layer 102 and the test hole 103 cannot be determined, the number of test inner layers 102 included in the first test module and the second test module can be made as equal as possible to improve the efficiency of CAF failure location.
[0053] In step S402 of some embodiments, a resistance test is performed on the first test module and the first test outer layer 101, and a resistance test is performed on the second test module and the first test outer layer 101. The resistance value with a problem among the two resistance values is determined, and the target test layer is determined from the test module corresponding to the problematic resistance value. It is understandable that the target test layer may refer to the test inner layer 102 having a CAF phenomenon between the test hole 103. It is understandable that when the CAF phenomenon occurs, a conductive path may be formed between two conductors that were originally designed to be insulated, thereby causing the resistance between the two conductors to decrease. Therefore, the resistance value with a reduced resistance value can be confirmed as a problematic resistance value. Figure 2E and Figure 2E As shown, when the CAF phenomenon occurs, a failure site 115 (ie, a conductive path) for connecting the test hole 103 and the test inner layer 102 is generated in the isolation pad 114 .
[0054] It can be understood that when the number of test holes 103 is one, and the first test module and the second test module both include only one test inner layer 102, such as when the test board only includes two test inner layers, test inner layer L2 and test inner layer L3, assuming that the first test module includes the test inner layer L2 and the second test module includes the test inner layer L3, through the method described in the above embodiment, it can be determined that there is a CAF phenomenon between the test hole 103 and the test inner layer L2, or it can be determined that there is a CAF phenomenon between the test hole 103 and the test inner layer L3, thereby realizing the hole-to-copper CAF failure positioning.
[0055] It is understandable that when the number of test holes 103 is one, and both the first test module and the second test module include multiple test inner layers 102, the test module corresponding to the problematic resistance value can be further processed in half to determine the target test layer. Similarly, when the number of test holes 103 is multiple, the test holes 103 can also be processed in half to determine the test holes 103 with CAF phenomenon. The following specifically describes the situation when the number of test holes 103 is multiple.
[0056] Reference Figure 5 In some embodiments, the plurality of test holes 103 on the first test outer layer 101 are divided into a plurality of test groups 106, the hole parameters of the plurality of test holes 103 are different, the plurality of test holes 103 in each test group 106 are connected in sequence, and the plurality of test groups 106 are respectively connected to the first connected sub-holes 104. For example, Figure 5 As shown, five test groups can be obtained by division. Hole parameters can refer to parameters that can characterize hole characteristics, such as hole parameters can include hole diameter and hole wall to copper spacing, etc. In this way, multiple test holes 103 can be divided according to hole parameters. For example, test holes 103 with the same hole diameter but different hole wall to copper spacing are divided into a test group 106. Alternatively, the hole parameters of all test holes 103 are different, and they are divided according to the setting position of the test holes 103. The embodiment of the present application does not specifically limit the method for dividing the test holes 103. Multiple test holes 103 in the same test group 106 are connected in series, and all test groups 106 are respectively connected to the first connected sub-hole 104.
[0057] Reference Figure 6 In some embodiments, the method provided in the embodiments of the present application may also include but is not limited to steps S601 to S602.
[0058] Step S601, dividing the multiple test groups into halves to obtain a third test module and a fourth test module;
[0059] Step S602 , determining a target test hole from the third test module or the fourth test module according to the resistance value between the third test module and the target test layer and the resistance value between the fourth test module and the target test layer.
[0060] In step S601 of some embodiments, the half-processing may refer to dividing multiple test groups 106 into two test modules for CAF testing. For example, the half-processing may obtain a third test module 107 and a fourth test module 108. The number of test groups 106 included in the third test module 107 and the fourth test module 108 may be the same or different, and this embodiment of the present application does not specifically limit this. It can be understood that the method for determining the number of test groups 106 included in the third test module 107 and the fourth test module 108 is similar to the method for determining the number of test inner layers 102 included in the first test module and the second test module.
[0061] In step S602 of some embodiments, a resistance test is performed on the third test module 107 and the target test layer, and a resistance test is performed on the fourth test module 108 and the target test layer. The problematic resistance value among the two resistance values is determined, and the target test hole is determined from the test module corresponding to the problematic resistance value. For example, the test module corresponding to the problematic resistance value is the third test module 107. Assuming that the third test module 107 includes a test group 106, and the test group 106 includes a test hole 103, the test hole 103 is the target test hole. In other words, there is a CAF phenomenon between the test hole 103 and the target test layer. It is understandable that when the third test module 107 includes multiple test holes 103, such as when the third test module 107 includes multiple test groups 106, each test group 106 includes multiple test holes 103; or, such as when the third test module 107 includes one test group 106, one test group 106 includes multiple test holes 103, the multiple test holes 103 in the third test module 107 can also be processed in half to screen out the target test holes from the multiple test holes 103 in the third test module 107. This situation is described as follows.
[0062] Reference Figure 7 and Figure 8 In some embodiments, assuming that the third test module 107 includes a test group 106 and the fourth test module 108 includes a test group 106, step S602 may include but is not limited to steps S701 to S702.
[0063] Step S701, if the resistance of the third test module is determined to be abnormal according to the resistance of the third test module and the target test layer, and the resistance of the fourth test module and the target test layer, the test holes corresponding to the third test module are processed in half to obtain a first hole group and a second hole group;
[0064] Step S702 , determining a target test hole from the first hole group or the second hole group according to the resistance value between the first hole group and the target test layer and the resistance value between the second hole group and the target test layer.
[0065] In step S701 of some embodiments, when there is a decrease in resistance, it can be determined that the resistance is abnormal. For example, when it is determined that the resistance of the third test module 107 is abnormal, the test holes 103 included in the third test module 107 can be processed in half to obtain the first hole group 109 and the second hole group 110. It can be understood that the number of test holes 103 included in the first hole group 109 and the second hole group 110 can be the same or different, and this embodiment of the application does not specifically limit this.
[0066] In step S702 of some embodiments, a resistance test is performed on the first hole group 109 and the target test layer, and a resistance test is performed on the second hole group 110 and the target test layer. The problematic resistance value of the two resistance values is determined, and the target test hole is determined from the hole group corresponding to the problematic resistance value. For example, if the problematic hole group is the first hole group 109, the first hole group 109 is further processed in half to determine the target test hole from the first hole group.
[0067] Reference 9A to 9D In a specific embodiment, when a CAF failure occurs, such as Fig.9A As shown, on the first test outer layer 101, the communication path between the second communication sub-hole corresponding to the test inner layer L3 and the second communication sub-hole corresponding to the test inner layer L4 is disconnected, so that the test inner layer L2 and the test inner layer L3 are used as the first test module, and the test inner layer L4 and the test inner layer L5 are used as the second test module. Fig. 9B As shown, if it is determined that there is an abnormality in the resistance value between the first test module and the first test outer layer 101, on the first test outer layer 101, the connecting path between the second connecting sub-hole corresponding to the test inner layer L2 and the second connecting sub-hole corresponding to the test inner layer L3 is disconnected, so as to use the test inner layer L2 as a test module and the test inner layer L3 as a test module. If it is determined that there is an abnormality in the resistance value between the test inner layer L2 and the first test outer layer 101, the test inner layer L2 is used as the target test layer. If it is determined that there is an abnormality in the resistance value between the test inner layer L3 and the first test outer layer 101, the test inner layer L3 is used as the target test layer. As follows, take the test inner layer L2 as the target test layer as an example. As Fig. 9CAs shown, the multiple test groups on the first test outer layer 101 are processed in half to obtain the third test module 107 and the fourth test module 108, and the connection path between the third test module 107 and the fourth test module 108 is disconnected. If it is determined that the resistance between the fourth test module 108 and the test inner layer L2 is abnormal, such as Fig.9D As shown, the communication path between the test group A and the test group B in the fourth test module 108 is disconnected. If it is determined that the resistance between the test group A and the test inner layer L2 is abnormal, the test holes in the test group A are processed in half until the target test hole 113 is determined from the test group A.
[0068] It is understandable that when it is determined that there is a CAF phenomenon between the test inner layer L2 and the target test hole 113, a slicer can be used to take the target test hole 113. The slices are cut and ground to the test inner layer L2, so that the CAF phenomenon can be analyzed, providing data support for the subsequent evaluation and improvement of the CAF resistance of the PCB and the design of the PCB.
[0069] The CAF failure location analysis method provided in the embodiment of the present application first processes multiple test inner layers in half to determine the target test layer. Then, multiple test holes on the first test outer layer are processed in half to determine the target test hole, so that it can be determined that there is a CAF phenomenon between the target test hole and the target test layer, that is, the hole-to-copper CAF failure location is achieved. Moreover, the half-processing method can improve the failure location efficiency of CAF. It can be understood that the above method can be understood as first determining the failure layer and then determining the failure hole. According to actual needs, it can also be set to first determine the failure hole and then determine the failure layer, which will not be described in detail in the embodiment of the present application. Figure 2F As shown, the failure location 115 is usually in the shape of a thin line, and it is generally difficult to determine it through a microscope. Through the method of first determining the layer and then determining the hole, or the method of first determining the hole and then determining the layer in the embodiment of the present application, it is possible to locate the failure location, thereby determining the failure location 115 from the failure location, thereby improving the failure location efficiency of CAF. In addition, since the embodiment of the present application can locate the failure location, the failure location can be analyzed to determine the cause of CAF, thereby reducing the subsequent occurrence of CAF.
[0070] Reference Fig.10The embodiment of the present application also provides a CAF failure location analysis device, which is applied to a test board, the test board comprising: a first test outer layer, multiple test inner layers, a test hole, a connecting hole and an isolation pad, the test hole runs through the first test outer layer and the multiple test inner layers, the connecting hole runs through the first test outer layer and the multiple test inner layers; the connecting hole comprises a first connecting sub-hole and multiple second connecting sub-holes, the first connecting sub-hole on the first test outer layer is connected to the corresponding test hole, and the second connecting sub-hole on the test inner layer is connected to the corresponding test inner layer; the isolation pad is arranged on the test inner layer, and the isolation pad is used to isolate the test hole arranged on the test inner layer from the corresponding test inner layer;
[0071] The device includes:
[0072] A half-division module 1001 is used to process multiple test inner layers in half to obtain a first test module and a second test module;
[0073] The resistance test module 1002 is used to determine a target test layer from the first test module and the second test module according to the resistance between the first test module and the first test outer layer and the resistance between the second test module and the first test outer layer.
[0074] The specific implementation of the CAF failure location analysis device is substantially the same as the specific implementation of the corresponding CAF failure location analysis method described above, and will not be described in detail herein.
[0075] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0076] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.
[0077] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0078] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.
[0079] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0080] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0081] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0082] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0083] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0084] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.
[0085] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.
Claims
1. A CAF failure location analysis method, characterized in that: The method is applied to a test board, which comprises: a first test outer layer, a plurality of test inner layers, a test hole, a connecting hole and an isolation pad, wherein the test hole penetrates the first test outer layer and the plurality of test inner layers, and the connecting hole penetrates the first test outer layer and the plurality of test inner layers; the connecting hole comprises a first connecting sub-hole and a plurality of second connecting sub-holes, the first connecting sub-hole on the first test outer layer is connected to the corresponding test hole, and the second connecting sub-hole on the test inner layer is connected to the corresponding test inner layer; the isolation pad is arranged on the test inner layer, and the isolation pad is used to isolate the test hole arranged on the test inner layer from the corresponding test inner layer; The method comprises: Processing the plurality of test inner layers in half to obtain a first test module and a second test module; A target test layer is determined from the first test module or the second test module according to the resistance value between the first test module and the first test outer layer and the resistance value between the second test module and the first test outer layer.
2. The method according to claim 1, characterized in that Dividing the multiple test holes on the first test outer layer into multiple test groups, the multiple test holes have different hole parameters, the multiple test holes in each test group are connected in sequence, and the multiple test groups are respectively connected to the first connected sub-holes; The method further comprises: Divide the plurality of test groups into halves to obtain a third test module and a fourth test module; A target test hole is determined from the third test module or the fourth test module according to the resistance value of the third test module and the target test layer and the resistance value of the fourth test module and the target test layer.
3. The method according to claim 2, characterized in that The third test module includes a test group, the fourth test module includes a test group, and determining a target test hole from the third test module and the fourth test module according to a resistance value between the third test module and the target test layer and a resistance value between the fourth test module and the target test layer, comprises: If the resistance of the third test module is determined to be abnormal according to the resistance of the third test module and the target test layer and the resistance of the fourth test module and the target test layer, the test holes corresponding to the third test module are processed in half to obtain a first hole group and a second hole group; The target test hole is determined from the first hole group or the second hole group according to the resistance value between the first hole group and the target test layer and the resistance value between the second hole group and the target test layer.
4. The method according to claim 2, characterized in that: Each test inner layer is provided with an isolating piece, and the corresponding test hole and the second communicating sub-hole are provided in the isolating piece.
5. The method according to claim 1, characterized in that The test board further includes a second test outer layer; wherein the test hole penetrates the second test outer layer, and the connecting hole penetrates the second test outer layer.
6. The method according to claim 1, characterized in that The test holes are distributed in a matrix.
7. A CAF failure location analysis device, characterized in that: The device is applied to a test board, which includes: a first test outer layer, multiple test inner layers, a test hole, a connecting hole and a through hole, wherein the test hole penetrates the first test outer layer and the multiple test inner layers, and the connecting hole penetrates the first test outer layer and the multiple test inner layers; the connecting hole includes a first connecting sub-hole and multiple second connecting sub-holes, the first connecting sub-hole on the first test outer layer is connected to the corresponding test hole, and the second connecting sub-hole on the test inner layer is connected to the corresponding test inner layer; the isolation pad is arranged on the test inner layer, and the isolation pad is used to isolate the test hole arranged on the test inner layer from the corresponding test inner layer; The device comprises: A half-division module, used for processing the plurality of test inner layers in half to obtain a first test module and a second test module; The resistance test module is used to determine a target test layer from the first test module and the second test module according to the resistance between the first test module and the first test outer layer and the resistance between the second test module and the first test outer layer.