Layout defect correction method and system and mask

Abstract

The invention provides a layout defect correction method and system and a mask, and belongs to the field of semiconductors. The layout defect correction method comprises the following steps: providing a layout; and screening out the target graph which exists in the first area and the second area at the same time. And obtaining a transition area of the target graph based on the dense graph and the isolated graph. And performing extension processing on the line ends of the two graphs adjacent to the target graph along the direction parallel to the target graph to form an extended graph so as to convert the graph in the transition area from an isolated graph to a dense graph. According to the method, the transition area where defects are prone to occurring in the target pattern is screened out, the two adjacent patterns of the target pattern are subjected to extension processing, and therefore isolated patterns in the transition area can be converted into dense patterns, process windows of the target pattern can be increased, the problem that current cannot be transmitted smoothly in a metal layer can be solved, and the yield of the target pattern is improved. And the yield of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and system for correcting layout defects, and a mask. Background Art

[0002] In the chip, the conductive properties of the metal layer can realize energy transmission between various components. The metal layer of the chip can also share the load of high-frequency current and improve the operating stability of the chip. The metal layer is very sensitive to process changes at the transition point of pattern density, so it is often the place where defects appear.

[0003] Although the metal layer will make changes to the process dimensions based on the original layout to improve the process window of the graphics, the contour of the turning point is still a hot spot that needs attention. If the contour is not as expected, the current in the metal layer cannot be transmitted smoothly, affecting the chip yield.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a method and system for correcting layout defects, and a mask plate to solve the problem that the graphic structure contour of the existing layout is not as expected, the current in the metal layer cannot be transmitted smoothly, affecting the chip yield.

[0006] In order to solve the above technical problems, the present invention provides a method for correcting layout defects, comprising:

[0007] Providing a layout, and obtaining dense graphics and isolated graphics of the layout;

[0008] Determine a first region having a first spacing and a second region having a second spacing in the layout, wherein the first spacing is greater than the second spacing;

[0009] Filtering out target graphics that exist in both the first area and the second area;

[0010] Based on the dense graphics and the isolated graphics, acquiring a transition area of ​​the target graphics;

[0011] Extending the line ends of two graphics adjacent to the target graphic in a direction parallel to the target graphic to form an extended graphic, so as to convert the graphic in the transition area from an isolated graphic to a dense graphic, wherein the line ends of the two graphics extend in opposite directions;

[0012] Perform OPC correction on the layout after extension processing.

[0013] Preferably, the determining of the first area having the first spacing and the second area having the second spacing in the layout comprises:

[0014] Set the spacing value between adjacent graphics;

[0015] The area in which the spacing value between each two adjacent graphics in the layout is greater than the set spacing value is defined as the first area, and the area which is less than the set spacing value is defined as the second area.

[0016] Preferably, the acquiring the transition area of ​​the target graphic based on the dense graphics and the isolated graphics comprises:

[0017] The region where a dense pattern changes to an isolated pattern and vice versa is defined as a transition region.

[0018] Preferably, before extending the line ends of two graphics adjacent to the target graphics in a direction parallel to the target graphics, the layout defect correction method further includes:

[0019] Two graphics adjacent to the target graphic are projected in a direction parallel to the target graphic to form a projection area, and the line ends of the two graphics extend in opposite directions.

[0020] Preferably, the length of the line ends of two graphics adjacent to the target graphic being extended in a direction parallel to the target graphic is 3 to 5 times the minimum value of the line width of the graphics in the layout.

[0021] Preferably, after extending the line ends of two graphics adjacent to the target graphics in a direction parallel to the target graphics, the layout defect correction method further comprises:

[0022] At the turning point between the extended area and the target figure, a sudden step is set on the target figure.

[0023] Preferably, a plurality of steps are provided.

[0024] Preferably, there are two steps.

[0025] Based on the same inventive concept, the present invention also provides a system for correcting layout defects, comprising:

[0026] An acquisition module, used for providing a layout and acquiring dense graphics and isolated graphics of the layout;

[0027] A judgment module is used to judge a first area with a first spacing and a second area with a second spacing in the layout, wherein the first spacing is greater than the second spacing; filter out a target graphic that exists in both the first area and the second area; and obtain a transition area of ​​the target graphic based on the dense graphics and the isolated graphics;

[0028] The processing module is used to extend the line ends of two graphics adjacent to the target graphics in a direction parallel to the target graphics to form an extended graphics, so as to convert the graphics in the transition area from isolated graphics to dense graphics, wherein the line ends of the two graphics extend in opposite directions; and perform OPC correction on the layout after the extension processing.

[0029] Based on the same inventive concept, the present invention also provides a mask, comprising:

[0030] The above-mentioned method for correcting layout defects is used to correct the layout of the mask.

[0031] Compared with the prior art, the layout defect correction method of the present invention has the following advantages:

[0032] The present invention selects target graphics that are prone to defects, selects transition areas in the target graphics that are prone to defects, and extends two adjacent graphics of the target graphics, thereby converting isolated graphics in the transition area into dense graphics. Therefore, the process window of the target graphics can be increased, and the abnormal contour formed by the graphic structure in the transition area can be avoided. The problem that the current cannot be smoothly transmitted in the metal layer can be avoided, and the yield of the chip can be improved.

[0033] The system and mask for correcting layout defects provided by the present invention and the method for correcting layout defects provided by the present invention belong to the same inventive concept. Therefore, the system and mask for correcting layout defects provided by the present invention at least have all the advantages of the method for correcting layout defects provided by the present invention. The layout corrected by the system for correcting layout defects and the layout corrected by the method for correcting layout defects provided by the present invention can both increase the process window of the target graphic, avoid the problem of current not being able to be transmitted smoothly in the metal layer, and improve the yield of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of an ideal contour structure obtained from an original layout in one embodiment;

[0035] Figure 2 It is a schematic structural diagram of an outline formed after a size change is performed on a graphic of an original layout in one embodiment;

[0036] Figure 3 is a flow chart of a method for correcting layout defects in one embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of a structure for screening a target layout in one embodiment of the present invention;

[0038] Figure 5 is a schematic diagram of a structure for obtaining a transition area in a layout in one embodiment of the present invention;

[0039] Figure 6 is a schematic structural diagram of two graphics adjacent to a target graphic after projection processing is performed in one embodiment of the present invention;

[0040] Figure 7 is a schematic structural diagram of an embodiment of the present invention after two graphics adjacent to a target graphic are extended;

[0041] Figure 8 is a schematic structural diagram of setting a sudden change step in a target pattern in one embodiment of the present invention;

[0042] Fig. 9 In one embodiment of the present invention, Figure 3 A schematic diagram of the structure of the outline formed after the layout is corrected by the provided layout defect correction method;

[0043] Fig.10 It is a schematic diagram of a process window structure formed by a layout before extension processing is performed in one embodiment of the present invention;

[0044] Fig.11 It is a schematic diagram of a process window structure formed by a layout after extension processing in one embodiment of the present invention;

[0045] In the figure,

[0046] 10-metal layer; 20-through hole;

[0047] 30-contour; 100-target shape;

[0048] 200-first graphic; 210-first line end;

[0049] 300 - second graphic; 310 - second line end;

[0050] 400-Extended graphics. DETAILED DESCRIPTION

[0051] In order to make the purpose, advantages and features of the present invention clearer, the method and system for correcting the layout defects and the mask of the present invention are further described in detail below in combination with the drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also be slightly simplified. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or the part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0053] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0054] Ginseng Figure 1 and Figure 2As shown, in the chip interconnection process, it is necessary to form a layout on a mask plate to form a graphic structure that meets the process requirements and perform a photolithography process, so that the electrical connection between various components can be achieved through the conductive properties of the metal layer 10 (Metal Layer). The layout includes multiple graphic layers, such as the metal layer 10, and a through-hole layer with through holes 20. Among them, for the metal layer 10, especially under a process close to the photolithography limit, the process window is often poor in the transition area between dense / isolated graphics. Figure 1 In the layout, the pattern structure of the metal layer 10, in an ideal case, the profile 30 formed in the photoresist layer is consistent with the pattern structure of the metal layer 10. However, due to optical reasons during the exposure process or chemical reactions of the photoresist, there is a deviation between the pattern structure formed in the photoresist and the pattern structure on the mask, especially for the patterns in some specific areas, in the areas where dense patterns change to isolated patterns and isolated patterns change to dense patterns, such as Figure 2 In the area a, the profile 30 formed is not as expected, and the metal layer 10 will have the problem of current not being able to be transmitted smoothly, which affects the yield of the chip.

[0055] The core idea of ​​the present invention is to provide a method and system for correcting layout defects, and a mask plate, which can solve the technical problem that the graphic structure contour 30 in the layout is not as expected, the current in the metal layer cannot be transmitted smoothly, and the chip yield is affected.

[0056] In order to realize the above idea, the present invention provides a method for correcting layout defects. Figures 3 to 11 A specific implementation of a layout defect correction method disclosed herein includes the following steps S1 to S8.

[0057] Step S1: providing a layout, and obtaining dense graphics and isolated graphics of the layout.

[0058] Specifically, refer to Figure 3 and Figure 5 As shown, a layout is provided, the layout having regions m1 and m2 where dense patterns are located and a region m3 where isolated patterns are located. The dense patterns and isolated patterns of the layout are obtained through the original designed layout.

[0059] Step S2: Determine a first region having a first spacing and a second region having a second spacing in the layout, wherein the first spacing is greater than the second spacing.

[0060] Specifically, refer to Figure 3 and Figure 4 As shown, determining a first region having a first spacing and a second region having a second spacing in the layout includes:

[0061] First, set the spacing value between adjacent graphics. Set the spacing value between two adjacent graphics in the layout. The set spacing value can be a specific numerical value or a threshold value. The set spacing value can be Figure 4 d1 in Figure 4 , or d2, or it can also be dx, where d2 < dx < d1. Or it can be the threshold value d2 to d1. Engineers can set the spacing value between adjacent graphics according to the actual design requirements of the layout.

[0062] Next, define the area where the spacing value between every two adjacent graphics in the layout is greater than the set spacing value as the first area, and define the area where it is less than the set spacing value as the second area. Taking the set spacing value between adjacent graphics as dx as an example. Define the area where the spacing value between every two adjacent graphics in the layout is greater than dx as the first area, and define the area where the spacing value between every two adjacent graphics in the layout is less than dx as the second area. Select the first area and the second area through a script. It should be noted that selecting the first area and the second area through a script is a prior art, and those skilled in the art are already familiar with the operation of this script.

[0063] Step S3: Screen out the target graphic 100 that exists in both the first area and the second area.

[0064] Specifically, refer to Figures 3 to 6 As shown, screen out the target graphic 100 that is in both the first area and the second area. For the target graphic 100, the spacing between the target graphic 100 and the graphic on one side of it is d1 and d2 respectively, and the spacing between the target graphic 100 and the graphic on the other side of it is also d1 and d2, where d2 < dx < d1. Through the above screening conditions, the target graphic 100 in the layout where the contour 30 is likely to be not as expected can be screened out.

[0065] Step S4: Based on the dense graphics and isolated graphics, obtain the transition area of the target graphic 100.

[0066] Specifically, refer to Figures 3 to 7 As shown, the dense graphics and isolated graphics can be screened out through Step S1. As Figure 5 the areas where the dashed boxes m1 and m2 are located in Figure 5 are dense graphics. Figure 5 The area where the dashed box m3 is located in Figure 5 is the isolated graphic area. Define the area where the dense graphics change to isolated graphics and the isolated graphics change to dense graphics as the transition area. By obtaining the transition area, the position where the graphics in the layout are likely to have defects can be further narrowed down.

[0067] Furthermore, the area where the dense graphics change to isolated graphics and the isolated graphics change to dense graphics can be marked. By making marks, it is convenient to optimize the areas where defects are likely to occur in the layout when making the layout.

[0068] Step S5: Project the two graphics adjacent to the target graphic 100 in a direction parallel to the target graphic 100 to form a projection area to confirm the lengths of the line ends of the two graphics extending in opposite directions.

[0069] Specifically, refer to Figures 3 to 6 As shown, two graphics adjacent to the target graphic 100 are defined as the first graphic 200 and the second graphic 300, respectively. Projection processing is performed in a direction parallel to the target graphic 100 to form a projection area m4 to confirm the extension length of the first line end 210 of the first graphic 200 and the second line end 310 of the second graphic 300. The extension length of the line end is the distance extended in the direction parallel to the target graphic 100. Since projection processing is performed only on the transition area where the dense graphic changes to the isolated graphic and the isolated graphic changes to the dense graphic, the projection processing directions of the first line end 210 and the second line end 310 are opposite.

[0070] Step S6: Based on the projection area, the line ends of two graphics adjacent to the target graphic 100 are extended in a direction parallel to the target graphic 100 to form an extended area, so as to convert the graphics in the transition area from isolated graphics to dense graphics.

[0071] Specifically, refer to Figures 3 to 7 As shown, the first line end 210 and the second line end 310 are extended to form an extended area, and the length of the extension is equal to the length of the projection area. After the extension process, an extended pattern 400 is formed at the line ends of the first pattern 200 and the second pattern 300. Figure 7 As can be seen from the figure, the two extended patterns 400 are respectively located in the area where the dense pattern is located. Therefore, by extending the first pattern 200 and the second pattern 300, the pattern in the transition area can be converted from an isolated pattern to a dense pattern. Thus, the process window of the target pattern 100 can be increased, the profile 30 formed by the pattern structure in the transition area can be prevented from being abnormal, the problem of the metal layer 10 not being able to transmit current smoothly can be avoided, and the yield of the chip can be improved.

[0072] Furthermore, the line ends of two graphics adjacent to the target graphic 100 are extended in a direction parallel to the target graphic 100 by a length of 3 to 5 times the minimum line width of the graphics in the layout. Among them, the length of the projection area m4 formed by the first line end 210 is d3, and the length of the extended graphic 400 formed by the first line end 210 is d3. The length of the projection area m4 formed by the second line end 310 is d4, and the length of the extended graphic 400 formed by the second line end is d4. Figure 6The line widths of the various graphics in the layout are w1, w2, w3, w4, and w5 respectively, so the length of the extended graphic 400 is 3 to 5 times min{w1, w2, w3, w4, w5}. It should be noted that the lengths d3 and d4 of the two extended graphics 400 may be equal or unequal. As long as the extended graphic 400 satisfies the minimum value of 3 to 5 times the line width of the graphics in the layout. By setting the extended length to 3 to 5 times the minimum line width of the graphics in the layout, the process window of the target graphic 100 in the transition area can be effectively improved.

[0073] After this step, the layout can be directly corrected by OPC. However, in order to make the layout have a better process window, the layout is also processed through the following process steps, and then the subsequent process steps such as changing the process size and OPC correction are carried out.

[0074] Step S7: at the turning point between the extension area m4 and the target pattern 100, a sudden step is provided on the target pattern 100.

[0075] Specifically, refer to Figures 3 to 9 As shown, in order to further improve the process window of the target pattern 100, at the position where the extension region m4 and the target pattern 100 turn (ie, Figure 8 and Fig. 9 In the area where the circle m5 is located), a sudden step is set, so that the target pattern 100 is formed as follows Fig. 9 When the contour 30 in the figure is formed, a smooth curve is formed at the position of the sudden step, so that the layout can have a better process window. It should be noted that the sudden step can be one or more, and the engineer can set it according to the actual process requirements. In this embodiment, it is preferred that two steps are set.

[0076] Step S8: Perform OPC correction on the layout after setting steps on the target pattern 100.

[0077] Specifically, refer to Figure 1 As shown. The layout after the above processing is subjected to subsequent processes, such as OPC correction of the layout. Before OPC correction, the layout can also be processed to change the process size. It should be noted that the technology of changing the process size of the layout and OPC correction is a prior art, and those skilled in the art are already familiar with the specific process, which will not be repeated here.

[0078] Table 1 is a comparison of process parameters for the graphics in the layout with and without extension processing

[0079] condition iDOF NILS Unextended layout 0.123 1.12 Layout after extension processing 0.296 1.9

[0080] It can be seen from Table 1 that after the layout is extended, the dense graphics in the original process are transformed into isolated graphics, and the values ​​of the process parameters iDOF and NILS at the transformation of isolated graphics to dense graphics are increased, so there is a better process window. Fig.10 and Fig.11 As shown, Fig.10 It is a schematic diagram of the process window structure formed by the layout before the extension process is performed in one embodiment of the present invention. Fig.11 FIG. 1 is a schematic diagram of a process window structure formed by a layout after extension processing in one embodiment of the present invention. Fig.10 and Fig.11 It can be seen that after the extension process, the transition area in the layout has a larger process window.

[0081] To realize the above idea, this embodiment also discloses a system for correcting layout defects, including: an acquisition module, used to provide a layout, and obtain dense graphics and isolated graphics of the layout. A judgment module, used to judge a first area with a first spacing and a second area with a second spacing in the layout, wherein the first spacing is greater than the second spacing; screen out a target graphic 100 that exists in both the first area and the second area; based on the dense graphics and the isolated graphics, obtain the transition area of ​​the target graphic 100. A processing module, used to extend the line ends of two graphics adjacent to the target graphic 100 in a direction parallel to the target graphic 100 to form an extended graphic 400, so as to convert the graphics in the transition area from an isolated graphic to a dense graphic, wherein the line ends of the two graphics extend in opposite directions; and perform OPC correction on the layout after the extension processing.

[0082] The layout defect correction system provided in this embodiment and the layout defect correction method provided in this embodiment belong to the same inventive concept. Therefore, the layout defect correction system provided in this embodiment can increase the process window of the target graphic 100 by correcting the layout through the layout defect correction system, and can avoid the problem that the current cannot be transmitted smoothly in the metal layer 10, thereby improving the yield of the chip.

[0083] To realize the above idea, this embodiment also discloses a mask plate, including using the above-mentioned method for correcting layout defects to correct the layout of the mask plate.

[0084] The mask provided in this embodiment and the method for correcting layout defects provided in this embodiment belong to the same inventive concept. Therefore, the mask provided in this embodiment and the layout corrected by the method for correcting layout defects provided in this embodiment can increase the process window of the target graphic 100, avoid the problem that the current cannot be smoothly transmitted in the metal layer 10, and improve the yield of the chip.

[0085] In summary, the above embodiments provide detailed descriptions of the method and system for correcting layout defects and different configurations of masks. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above implementations. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the scope of protection of the claims.

Claims

1. A method for correcting layout defects, characterized in that: include: Providing a layout, and obtaining dense graphics and isolated graphics of the layout; Determine a first region having a first spacing and a second region having a second spacing in the layout, wherein the first spacing is greater than the second spacing; Filtering out target graphics that exist in both the first area and the second area; Based on the dense graphics and the isolated graphics, acquiring a transition area of ​​the target graphics; Extending the line ends of two graphics adjacent to the target graphic in a direction parallel to the target graphic to form an extended graphic, so as to convert the graphic in the transition area from an isolated graphic to a dense graphic, wherein the line ends of the two graphics extend in opposite directions; Perform OPC correction on the layout after extension processing.

2. The method for correcting layout defects according to claim 1, characterized in that: The determining of a first region having a first spacing and a second region having a second spacing in the layout comprises: Set the spacing value between adjacent graphics; The area in which the spacing value between each two adjacent graphics in the layout is greater than the set spacing value is defined as the first area, and the area which is less than the set spacing value is defined as the second area.

3. The method for correcting layout defects according to claim 1, characterized in that: The step of acquiring the transition region of the target graphic based on the dense graphic and the isolated graphic comprises: The region where a dense pattern changes to an isolated pattern and vice versa is defined as a transition region.

4. The method for correcting layout defects according to claim 1, characterized in that: Before extending the line ends of two graphics adjacent to the target graphics in a direction parallel to the target graphics, the layout defect correction method further includes: Two graphics adjacent to the target graphic are projected in a direction parallel to the target graphic to form a projection area, and the line ends of the two graphics extend in opposite directions.

5. The method for correcting layout defects according to claim 1, characterized in that: The length of the line ends of the two graphics adjacent to the target graphic being extended in a direction parallel to the target graphic is 3 to 5 times the minimum value of the line width of the graphics in the layout.

6. The method for correcting layout defects according to claim 1, characterized in that: After extending the line ends of two graphics adjacent to the target graphics in a direction parallel to the target graphics, the layout defect correction method further includes: At the turning point between the extended area and the target figure, a sudden step is set on the target figure.

7. The method for correcting layout defects according to claim 6, characterized in that: A plurality of steps are provided.

8. The method for correcting layout defects according to claim 6, characterized in that: There are two steps.

9. A layout defect correction system, characterized in that: include: An acquisition module, used for providing a layout and acquiring dense graphics and isolated graphics of the layout; A judgment module is used to judge a first area with a first spacing and a second area with a second spacing in the layout, wherein the first spacing is greater than the second spacing; filter out a target graphic that exists in both the first area and the second area; and obtain a transition area of ​​the target graphic based on the dense graphics and the isolated graphics; The processing module is used to extend the line ends of two graphics adjacent to the target graphics in a direction parallel to the target graphics to form an extended graphics, so as to convert the graphics in the transition area from isolated graphics to dense graphics, wherein the line ends of the two graphics extend in opposite directions; and perform OPC correction on the layout after the extension processing.

10. A mask, characterized in that: include: The layout of the mask is corrected by using the layout defect correction method described in any one of claims 1 to 8.

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