Memory and control method thereof

Abstract

The invention discloses a memory and a control method thereof. The memory is used for providing corresponding system data for a processor, the memory works in a normal mode or a low-power-consumption mode, and the memory comprises a first working unit which works in the normal mode and comprises a first storage module, and the first storage module provides the system data corresponding to the current function of the processor; and the second working unit works in the normal mode and the low-power-consumption mode and comprises a second storage module, and when the memory starts to be switched from the low-power-consumption mode to the normal mode, the second storage module provides system data corresponding to the preselected function of the processor. By arranging the second storage module which still works normally in the low-power-consumption mode, when the memory is switched to the normal mode from the low-power-consumption mode, the second storage module can provide the system data corresponding to the preselected function without waiting for restarting of other modules, and the response speed when the memory is switched to the normal mode is increased.

Description

Technical Field

[0001] The present invention relates to semiconductor memory technology, and in particular to a memory and a control method thereof. Background Art

[0002] Figure 1 FIG. 1 shows a schematic structural diagram of an electronic system in the prior art. Figure 1 The electronic system shown is a device such as a computer, a mobile phone, a tablet computer, etc., which specifically includes a processor 10 and a memory 20. In order to avoid data loss caused by power failure of the electronic system, a non-volatile memory is usually selected as the memory 20 to provide a data storage area, and the storage capacity and reading speed of the memory directly affect the performance of the electronic system.

[0003] When the electronic system is in standby or hibernation, the memory will switch from normal mode to low power mode to reduce power consumption; when the electronic system wakes up later, the memory will switch from low power mode to normal mode. However, when the memory switches from low power mode to normal mode, it takes a response time of several microseconds to tens of microseconds. During this response time, the memory cannot immediately provide the processor 10 with the required data, which greatly affects the performance of the electronic system. Summary of the invention

[0004] The present application provides a memory and a low power consumption control method thereof, which can improve the response speed of the memory when restoring a normal working state.

[0005] According to one aspect of the present application, a memory is provided for providing corresponding system data to a processor, wherein the memory includes a first working unit and a second working unit, wherein the first working unit provides corresponding specified data in response to a first instruction and enters a low power consumption mode, the specified data is backup data of the system data corresponding to the first instruction, the second working unit receives and stores the specified data in response to the first instruction, and the processor obtains the specified data from the second working unit when the first working unit is not restored to a normal mode.

[0006] Optionally, the first working unit includes a first storage module for storing the system data, and the first storage module is a non-volatile storage module; the second working unit includes a second storage module for storing the specified data, and the second storage module is a volatile storage module.

[0007] Optionally, the first working unit further responds to a second instruction to enter the normal mode, and the processor obtains the system data from the first working unit when the first working unit operates in the normal mode.

[0008] Optionally, the second working unit also includes: an output module, which outputs the system data provided by the first working unit in the normal mode of the first working unit or outputs the specified data provided by the second storage module when the first working unit has not recovered to the normal mode; and a mode switching control module, which provides a selection signal to the first working unit and a write signal to the second storage module in response to the first instruction, the first working unit provides the corresponding specified data according to the selection signal, and the second storage module receives and stores the specified data according to the write signal; or the mode switching control module provides a read signal to the second storage module in response to the second instruction, and the second storage module provides the specified data to the processor according to the read signal when the first working unit has not recovered to the normal mode.

[0009] Optionally, the first working unit further includes: a first control module, which reads a corresponding storage area of ​​the first storage module according to the selection signal to obtain a corresponding analog signal; and an analog module, which is used to sense and process the analog signal to provide the corresponding specified data.

[0010] Optionally, the memory also includes a power supply unit, which includes a first power supply module for supplying power to the first working unit and a second power supply module for supplying power to the second working unit. The mode switching control module also controls the first power supply module to stop supplying power according to the first instruction; or controls the first power supply module to resume supplying power according to the second instruction.

[0011] According to another aspect of the present application, a control method for a memory is provided, the control method being used to control the memory to provide system data to a processor, wherein the control method comprises: enabling a first working unit of the memory to provide corresponding designated data in response to a first instruction and enter a low power consumption mode, the designated data being backup data of the system data corresponding to the first instruction; enabling a second working unit of the memory to receive and store the designated data in response to the first instruction; and enabling the processor to obtain the designated data from the second working unit when the first working unit has not been restored to a normal mode.

[0012] Optionally, the first working unit stores the system data through a non-volatile storage module, and the second working unit stores the designated data through a volatile storage module.

[0013] Optionally, the control method further includes: enabling the first working unit to enter the normal mode in response to a second instruction; and enabling the memory to obtain the system data from the first working unit when the first working unit operates in the normal mode.

[0014] Optionally, the control method further includes: supplying power to the first working unit and the second working unit, stopping supplying power to the first working unit according to the first instruction; and resuming supplying power to the second working unit according to the second instruction.

[0015] According to the memory and control method thereof provided by the present application, the second working unit is set to back up the specified data when the first working unit enters the low power consumption mode, so the processor can obtain the specified data from the second working unit without waiting for the first working unit to recover to the normal mode, thereby improving the response speed of the memory. Moreover, when the memory enters the low power consumption mode, the corresponding specified data is selected according to the first instruction, thereby improving the adaptability of the specified data. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic structural block diagram of an electronic system is shown;

[0018] Figure 2 A schematic structural block diagram of a memory according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic flowchart of a method for controlling a memory according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0021] At the same time, certain words are used in this specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0022] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0023] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0024] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0025] Figure 2 Schematic structural block diagram of the memory of the embodiment of the present application is shown. In the embodiment of the present application, Figure 2 As shown, the memory 100 includes a first working unit 110 , a second working unit 120 and a power supply unit 130 .

[0026] The memory 100 is used to provide corresponding system data to the processor when the processor executes various functions. The memory 100 switches between normal mode and low power mode according to the corresponding switching instructions. In the following, by way of example, the memory 100 switches from normal mode to low power mode when receiving the first instruction; and switches from low power mode to normal mode when receiving the second instruction. In normal mode, the power supply unit 130 supplies power to the first working unit 110 and the second working unit 120; in low power mode, the power supply unit 130 only supplies power to the second working unit 120. That is, when the memory 100 works in normal mode, the first working unit 110 and the second working unit 120 both work in normal mode, and when the memory 100 works in low power mode, the first working unit 110 works in low power mode, and the second working unit 120 works in normal mode.

[0027] The first working unit 110 is used to provide corresponding system data to the processor when the memory 100 works in the normal mode. In addition, the first working unit 110 also responds to the first instruction to provide specified data and enter the low power consumption mode when the memory 100 receives the first instruction. The specified data is the backup data of the system data corresponding to the first instruction.

[0028] Specifically, see Figure 2 The first working unit 110 , for example, includes a first control module 111 , a simulation module 112 and a first storage module 113 .

[0029] The first storage module 113 is used to store system data corresponding to various functions of the processor. When the memory 100 works in normal mode (that is, when the first working unit 100 works in normal mode), the first storage module 113 is read to provide the processor with corresponding system data. In addition, in order to facilitate reading the corresponding system data according to the current function of the processor, the first storage module 113 usually includes multiple storage areas to store system data corresponding to different functions respectively. In an embodiment of the present application, since the system data needs to be stored for a long time, in order to avoid the loss of system data after the memory 100 is powered off, the first storage module 113 selects a non-volatile storage module.

[0030] The first control module 111 is used to control the first storage module 113 to perform operations such as reading, writing, and erasing. Specifically, in the process of the memory 100 providing system data to the processor 120, the first control module 111 reads the corresponding storage area of ​​the first storage module 113 according to the current demand to obtain the corresponding analog signal. For example, when the memory 100 receives the first instruction, the first control module 111 reads the corresponding storage area in the first storage module 113 to obtain the analog signal corresponding to the specified data.

[0031] The simulation module 112 is in communication with the first storage module 113 and is used to sense or process the simulation signal provided by the first storage module to provide corresponding system data.

[0032] The second working unit 120 is used to receive and store the specified data provided by the first working unit 110 in response to the first instruction when the memory 100 receives the first instruction. In addition, when the memory 100 (that is, the first working unit 110) is not restored to the normal mode, the processor obtains the specified data stored in the second working unit 120 from the second working unit 120.

[0033] Specifically, see Figure 2 The second working unit 120 includes an output module 121 , a second storage module 122 and a mode switching control module 123 .

[0034] The mode switching module 123 is used to switch the working mode of the memory 100 according to the switching instruction. Specifically, when receiving the first instruction, the mode switching module 123 provides a selection signal to the first working unit 110 and provides a write signal to the second storage module 122. Among them, the first working unit provides corresponding specified data according to the selection signal; the second storage module 122 receives and stores the specified data according to the write signal. It should be noted that, in some embodiments, the mode switching module 123 can also switch the working mode of the memory 100 according to the working state of the first working unit 110. For example, when the first working unit 110, especially the first storage module 113, does not perform reading, writing or other operations within a certain period of time (first preset time length), it is deemed that the mode switching module 123 has received the first instruction.

[0035] In addition, in some embodiments, the mode switching module 123 is also used to provide a read signal to the second storage module 122 when receiving the second instruction, so that the second storage module 122 directly provides specified data to the processor when the first working unit 110 is not restored to the normal mode, thereby improving the response speed of the memory 100 in the low power consumption mode.

[0036] The second storage module 122 is used for receiving and storing designated data in response to the first instruction when the memory 100 receives the first instruction; and outputting the stored designated data in response to the second instruction when the memory 100 receives the second instruction.

[0037] Since the second storage module 122 essentially only needs to save the specified data in the low power mode, the second storage module 122 can use a volatile storage module to increase the read and write speed, thereby further increasing the response speed of the memory 100 output when switching to the normal mode. In some other embodiments, the second storage module 122 can also use a non-volatile storage module, and this application does not make too many restrictions.

[0038] The output module 121 serves as an output interface of the memory 100, receives system data provided by the first working unit 110 in the normal mode of the first working unit 110 and sends the system data to the processor; or receives specified data provided by the second storage module 122 and sends the specified data to the processor when the first working unit 110 has not been restored to the normal mode.

[0039] The power supply unit 130 supplies power to the memory 100. Specifically, the power supply unit 130 includes a first power supply module 131 for supplying power to the first working unit 110 and a second power supply module 132 for supplying power to the second working unit 120. The mode interface module 123 provides a corresponding control signal to the power supply unit 130 according to the first instruction / the second instruction, so that the first power supply module 131 stops supplying power to the first working unit 110 in response to the first instruction or resumes supplying power to the first working unit 110 in response to the second instruction.

[0040] The memory 100 of the present application is further described below in conjunction with the workflow.

[0041] After the memory 100 is powered on, the first power supply module 131 and the second power supply module 132 respectively supply power to the first working unit 110 and the second working unit 120, and the memory 100 enters the normal mode. The first working unit 110 provides the processor with system data corresponding to the current function of the processor via the output module 121.

[0042] When the mode switching module 123 receives the first instruction, it provides a selection signal to the first control module 111; and provides a write signal to the second storage module 122. When the first control module 111 receives the selection signal, it reads the corresponding storage area of ​​the first storage module 113 according to the selection signal to obtain an analog signal corresponding to the specified data of the first instruction. The analog module 112 senses and processes the analog signal to provide the specified data corresponding to the first instruction to the second working unit 120. After the first working unit 110 outputs the specified data, the first control module 111, the analog module 112 and the first storage module 113 in the first working unit 110 are turned off. The write signal controls the second storage module 122 to receive and store the specified data. The mode switching control module 123 also provides a control signal to the first power supply module 131 for controlling the first power supply module 131 to stop supplying power to the first working unit. In some embodiments, the mode switching control module 123, for example, provides the control signal to the first power supply module 131 after a certain delay (second preset duration) after receiving the first instruction, so as to ensure that the second storage module 122 can receive and store the specified data before the first working unit 110 is powered off; in some embodiments, the mode switching module 123 provides the control signal after detecting that the corresponding specified data is written (or updated) in the second storage module 122, and this application does not impose too many restrictions. Thereafter, the first power supply module stops supplying power to the first working unit, and the memory 100 (i.e., the first working unit 110) enters a low power consumption mode.

[0043] In the low power consumption mode, the second power supply module 132 continues to supply power to the second working unit, and the second working unit 120 operates normally.

[0044] When the mode switching module 123 receives the second instruction, it provides a read signal to the second storage module 122 and simultaneously provides a control signal to the first power supply module 131 to restore the power supply to the first working unit 110. Therefore, when the power supply to the first working unit 110 is restored (that is, when the first working unit 110 has not been restored to the normal mode), the second storage module 122 reads the specified data and provides the specified data to the processor via the output module 121. After power-on, each module of the first working unit 110 restarts, the memory 100 enters the normal mode, and the first storage module 113 continues to provide system data.

[0045] According to the memory provided by the present application, the second working unit is set to back up the specified data when the first working unit enters the low power consumption mode, so the processor can obtain the specified data from the second working unit without waiting for the first working unit to recover to the normal mode, thereby improving the response speed of the memory. Moreover, when the memory enters the low power consumption mode, the corresponding specified data is selected according to the first instruction, thereby improving the adaptability of the specified data.

[0046] Figure 3 A schematic flow chart showing a method for controlling a memory according to an embodiment of the present application is shown. The method for controlling a memory provided in the present application is, for example, applicable to the memory provided in the present application. That is, the memory is used to provide corresponding system data to the processor when the processor executes various functions. The memory switches between normal mode and low power consumption mode according to corresponding switching instructions. In the following, by way of example, the memory switches from normal mode to low power consumption mode when receiving a first instruction; and switches from low power consumption mode to normal mode when receiving a second instruction. The memory includes a first working unit and a second working unit. In normal mode, power is supplied to the first working unit and the second working unit; in low power consumption mode, power is only supplied to the second working unit. That is to say, when the memory operates in normal mode, both the first working unit and the second working unit operate in normal mode. When the memory operates in low power consumption mode, the first working unit operates in low power consumption mode, and the second working unit operates in normal mode. As Figure 3 As shown, the control method includes:

[0047] Step S11, powering on the memory;

[0048] After the memory is powered on, power is supplied to the first working unit and the second working unit of the memory respectively, and the memory enters the normal mode of operation. The processor obtains corresponding system data from the first working unit.

[0049] Specifically, the first working unit includes a first storage module that stores system data corresponding to various functions of the processor. When the memory operates in normal mode (that is, when the first working unit operates in normal mode), the first storage module is read to provide the processor with corresponding system data. In addition, in order to facilitate reading the corresponding system data according to the current function of the processor, the first storage module usually includes a plurality of storage areas to store system data corresponding to different functions respectively. In an embodiment of the present application, since the system data needs to be stored for a long time, in order to avoid the loss of system data after the memory is powered off, the first storage module selects a non-volatile storage module. In addition, it should be noted that the first working unit also includes a control circuit and related analog circuits that work in conjunction with the first storage module so that the first storage module can perform operations such as erase / write / read.

[0050] Step S12, determining whether the memory receives the first instruction;

[0051] The first instruction is used to switch the working mode of the memory from the normal mode to the low power consumption mode. If the memory receives the first instruction, the subsequent steps are continued.

[0052] The present application does not limit the conditions for the memory to switch to the low power mode. For example, in some embodiments, the memory switches modes according to external instructions; in some embodiments, when the first working unit does not perform reading, writing or other operations within a certain period of time (a first preset time length), the memory enters the low power mode.

[0053] Step S13, enabling the first working unit to provide corresponding designated data in response to the first instruction and enter a low power consumption mode;

[0054] The designated data is backup data of the system data corresponding to the first instruction.

[0055] In order to facilitate reading the corresponding system data according to the current function of the processor, the first storage module usually includes multiple storage areas to store system data corresponding to different functions respectively. Therefore, in this step, the first working unit reads the corresponding storage area in the first storage module according to the first instruction to provide the specified data, and enters the low power consumption mode (i.e., shuts down each circuit module in the first working unit) after outputting the specified data.

[0056] Step S14, enabling the second working unit to receive and store the specified data in response to the first instruction;

[0057] Specifically, the second working unit includes a second storage module for receiving and storing the specified data. When the memory 100 receives the first instruction, the second storage module receives and stores the specified data in response to the first instruction.

[0058] Since the second storage module essentially only needs to save the specified data in the low power mode, the second storage module can use a volatile storage module to increase the read and write speed, thereby further increasing the response speed of the memory output when switching to the normal mode. In some other embodiments, the second storage module can also use a non-volatile storage module, and this application does not make too many restrictions.

[0059] Step S15, stop supplying power to the first working unit;

[0060] In some embodiments, the memory, for example, stops supplying power to the first working unit after delaying a certain period of time (a second preset time length) after receiving the first instruction, so as to ensure that the second storage module can receive and store the specified data before the first working unit is powered off; in some embodiments, the memory, for example, stops supplying power to the first working unit after detecting that the corresponding specified data is written (or updated) in the second storage module, and the present application does not impose too many restrictions.

[0061] Step S16, determining whether the memory receives the second instruction;

[0062] The second instruction is used to switch the working mode of the memory from the low power mode to the normal mode. If the memory receives the second instruction, the steps S17 and S18 are continued.

[0063] Step S17, providing the processor with the specified data stored in the second working unit:

[0064] Since the second working unit still works normally in the low power mode, when the memory starts to switch from the low power mode to the normal mode, even if the first working unit does not restore the normal mode, the second storage module can provide the processor with specified data, which greatly shortens the response time of the memory.

[0065] Step S18, restoring power supply to the first working unit:

[0066] When the memory receives the second instruction, it can control the restoration of power supply to the first working unit and restart the working circuits in the first working unit. Thereafter, the memory returns to normal mode, and the first working unit continues to provide corresponding system data to the processor.

[0067] According to the control method of the memory provided by the present application, the second working unit is set to back up the specified data when the first working unit enters the low power consumption mode, so the processor can obtain the specified data from the second working unit without waiting for the first working unit to recover to the normal mode, thereby improving the response speed of the memory. Moreover, when the memory enters the low power consumption mode, the corresponding specified data is selected according to the first instruction, thereby improving the adaptability of the specified data.

[0068] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A memory for providing corresponding system data to a processor, wherein: The memory includes a first working unit and a second working unit, The first working unit provides corresponding designated data in response to the first instruction and enters the low power consumption mode, wherein the designated data is the backup data of the system data corresponding to the first instruction. The second working unit receives and stores the specified data in response to the first instruction, The processor acquires the designated data from the second working unit if the first working unit does not return to a normal mode.

2. The memory according to claim 1, wherein: The first working unit includes a first storage module for storing the system data, and the first storage module is a non-volatile storage module; The second working unit includes a second storage module for storing the designated data, and the second storage module is a volatile storage module.

3. The memory according to claim 2, wherein: The first working unit also enters the normal mode in response to a second instruction, and the processor obtains the system data from the first working unit when the first working unit operates in the normal mode.

4. The memory according to claim 3, wherein: The second working unit also includes: an output module, configured to output the system data provided by the first working unit in a normal mode of the first working unit or to output the specified data provided by the second storage module when the first working unit is not restored to the normal mode; and a mode switching control module, wherein the mode switching control module provides a selection signal to the first working unit and a write signal to the second storage module in response to the first instruction, the first working unit provides the corresponding specified data according to the selection signal, and the second storage module receives and stores the specified data according to the write signal; or The mode switching control module provides a read signal to the second storage module in response to the second instruction, and the second storage module provides the designated data to the processor according to the read signal when the first working unit is not restored to the normal mode.

5. The memory according to claim 4, wherein: The first working unit also includes: A first control module, reading a corresponding storage area of ​​the first storage module according to the selection signal to obtain a corresponding analog signal; and The analog module is used to sense and process the analog signal to provide the corresponding specified data.

6. The memory according to claim 3, wherein: The memory further includes a power supply unit, wherein the power supply unit includes a first power supply module for supplying power to the first working unit and a second power supply module for supplying power to the second working unit. The mode switching control module further controls the first power supply module to stop supplying power according to the first instruction; or controls the first power supply module to resume supplying power according to the second instruction.

7. A memory control method, the control method is used to control the memory to provide system data to a processor, wherein: The control method comprises: enabling a first working unit of the memory to provide corresponding designated data in response to a first instruction and enter a low power consumption mode, wherein the designated data is backup data of the system data corresponding to the first instruction; causing a second working unit of the memory to receive and store the specified data in response to the first instruction; and The processor is caused to obtain the designated data from the second working unit when the first working unit does not return to a normal mode.

8. The control method according to claim 7, wherein: The first working unit stores the system data through a non-volatile storage module, and the second working unit stores the designated data through a volatile storage module.

9. The control method according to claim 8, wherein: The control method further comprises: causing the first working unit to enter the normal mode in response to a second instruction; and The memory is enabled to obtain the system data from the first working unit when the first working unit operates in the normal mode.

10. The control method according to claim 9, wherein: The control method further comprises: supplying power to the first working unit and the second working unit, stopping supplying power to the first working unit according to the first instruction; and The power supply to the second working unit is restored according to the second instruction.

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