Integrated circuit and inter-core communication method thereof
By determining the target inter-core communication unit according to the functional safety level of the processor in the integrated circuit, the problem of abnormal inter-core communication between processors is solved, and the normal progress of inter-core communication and functional safety guarantees are achieved.
Patent Information
- Application Number
- CN202411544999.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-14
AI Technical Summary
In integrated circuits, when intercore communication between processors with higher functional safety levels and processors with lower functional safety levels, intercore communication abnormalities may occur due to different processing capabilities or permissions of processors with different functional safety levels. .
Inter-core communication is performed by determining the functional safety levels of each processor and determining the target inter-core communication unit in the inter-core communication unit corresponding to each processor based on these levels.
Ensure that there will be no abnormality in the communication between processors of different functional safety levels, ensure the normal progress of inter-core communication, and prevent processors of low functional safety levels from being between cores corresponding to processors of high functional safety levels Read data from the communication unit to avoid functional abnormalities.
Smart Images
Figure CN119440877A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an integrated circuit and an inter-core communication method thereof. Background Art
[0002] When an integrated circuit includes multiple processors, the functional safety levels of the multiple processors in the integrated circuit may be different. Usually, an inter-processor communications module (IPCM) corresponding to each processor is provided in the integrated circuit, and processors with different functional safety levels can communicate with each other through the corresponding inter-processor communications module.
[0003] When a processor with a higher functional safety level communicates with a processor with a lower functional safety level, inter-core communication anomalies may occur due to the different processing capabilities or permissions of processors with different functional safety levels. Summary of the invention
[0004] In order to solve the above technical problems, the present disclosure provides an integrated circuit and an inter-core communication method thereof to solve the problem of inter-core communication anomalies occurring when processors with different functional safety levels perform inter-core communication.
[0005] A first aspect of the present disclosure provides an inter-core communication method for an integrated circuit, comprising: a first processor in the integrated circuit determines a second processor that performs inter-core communication with the first processor; the first processor determines a first functional safety level corresponding to the first processor and a second functional safety level corresponding to the second processor; the first processor determines a target inter-core communication unit in a first inter-core communication unit corresponding to the first processor and a second inter-core communication unit corresponding to the second processor based on the first functional safety level and the second functional safety level, and transmits inter-core communication data to the target inter-core communication unit; the second processor reads the inter-core communication data from the target inter-core communication unit.
[0006] The second aspect of the present disclosure provides an integrated circuit, including: a first processor, a second processor, a first inter-core communication unit corresponding to the first processor, and a second inter-core communication unit corresponding to the second processor; the first processor is used to determine the second processor that performs inter-core communication with the first processor, and determine the first functional safety level corresponding to the first processor and the second functional safety level corresponding to the second processor; the first processor is also used to determine a target inter-core communication unit in the first inter-core communication unit and the second inter-core communication unit based on the first functional safety level and the second functional safety level; the first processor is also used to transmit inter-core communication data to the target inter-core communication unit; the second processor is used to read the inter-core communication data from the target inter-core communication unit.
[0007] In a third aspect of the present disclosure, an embodiment proposes an electronic device, comprising: a processor; a memory for storing executable instructions of the processor; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the inter-core communication method of the integrated circuit described in the first aspect above; or, the electronic device comprises the integrated circuit described in the second aspect above.
[0008] In a fourth aspect of the present disclosure, an embodiment proposes a computer program product. When an instruction processor in the computer program product executes, the inter-core communication method of the integrated circuit proposed in the embodiment of the first aspect of the present disclosure is executed.
[0009] The inter-core communication method of the integrated circuit provided by the embodiment of the present disclosure, when inter-core communication is performed between two processors of different functional safety levels in the integrated circuit, by determining the functional safety level corresponding to each processor, and based on the functional safety level corresponding to each processor, determining the target inter-core communication unit in the inter-core communication unit corresponding to each processor, and then performing inter-core communication between the two processors based on the target inter-core communication unit. Therefore, when the present disclosure performs inter-core communication between processors of different functional safety levels, since the target inter-core communication unit can be determined based on the functional safety level of each processor, and the inter-core communication data can be transmitted between processors of different functional safety levels through the target inter-core communication unit, it can ensure that no abnormality occurs when performing inter-core communication between processors of different functional safety levels, thereby ensuring the normal performance of inter-core communication. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1A Schematic diagram of a circuit structure of an integrated circuit provided by an exemplary embodiment of the present disclosure.
[0011] Figure 1B is a schematic diagram of a circuit structure of an integrated circuit provided by another exemplary embodiment of the present disclosure.
[0012] Figure 1C is a circuit structure diagram of an integrated circuit provided by yet another exemplary embodiment of the present disclosure.
[0013] Figure 2 The figure is a flowchart of an inter-core communication method of an integrated circuit provided by an exemplary embodiment of the present disclosure.
[0014] Figure 3 The diagram is a scenario diagram of an inter-core communication method of an integrated circuit provided by an exemplary embodiment of the present disclosure.
[0015] Figure 4 It is a scenario diagram of an inter-core communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure.
[0016] Figure 5 It is a flowchart of an inter-core communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure.
[0017] Figure 6 It is a flowchart of an inter-core communication method of an integrated circuit provided by yet another exemplary embodiment of the present disclosure.
[0018] Figure 7 It is a flowchart of an inter-core communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure.
[0019] Figure 8 It is a flowchart of an inter-core communication method of an integrated circuit provided by another exemplary embodiment of the present disclosure.
[0020] Fig. 9 It is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION
[0021] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.
[0022] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
[0023] Application Overview
[0024] An integrated circuit may include multiple processors. For an integrated circuit with functional safety requirements, the multiple processors included in the integrated circuit may have different functional safety levels. When processors with different functional safety levels in the integrated circuit communicate with each other, the inter-core communication may be performed through the inter-core communication units corresponding to each processor.
[0025] When processors with different functional safety levels communicate between cores, if a processor with a low functional safety level reads data from the inter-core communication unit corresponding to a processor with a high functional safety level, an abnormality in the processor with the low functional safety level may cause a functional abnormality in the inter-core communication unit corresponding to the processor with the high functional safety level or cause a functional safety problem in the inter-core communication unit corresponding to the processor with the high functional safety level, resulting in the processor with the high functional safety level being unable to communicate between cores with other processors.
[0026] Based on the above problems, the inter-core communication method of an integrated circuit provided in the embodiment of the present disclosure, when inter-core communication is performed between processors with different functional safety levels, since the target inter-core communication unit can be determined by the functional safety level of each processor, and the inter-core communication data can be transmitted between processors with different functional safety levels through the target inter-core communication unit, it can be ensured that no abnormalities will occur when inter-core communication is performed between processors with different functional safety levels, thereby ensuring the normal progress of inter-core communication.
[0027] Moreover, when the present invention performs inter-core communication between processors with different functional safety levels, since the target inter-core communication unit is the inter-core communication unit corresponding to the processor with a low functional safety level, the processor with a low functional safety level will not read data in the inter-core communication unit corresponding to the processor with a high functional safety level, so it will not cause abnormalities in the inter-core communication unit corresponding to the processor with a high functional safety level, thereby ensuring that problems with the processor with a low functional safety level will not affect the high functional safety level, so that the processor with a high functional safety level can perform inter-core communication with other processors normally.
[0028] Exemplary Systems
[0029] FIG1 is a schematic diagram of the structure of an integrated circuit provided by an exemplary embodiment of the present disclosure. As shown in FIG1 , the integrated circuit 100 may include a first processor 101, a second processor 102, a first inter-core communication unit 103 corresponding to the first processor 101, and a second inter-core communication unit 104 corresponding to the second processor 102.
[0030] The first processor 101 is used to determine the second processor 102 that performs inter-core communication with the first processor, and determine a first functional safety level corresponding to the first processor 101 and a second functional safety level corresponding to the second processor 102.
[0031] The first processor 101 is also used to determine a target inter-core communication unit in the first inter-core communication unit 103 corresponding to the first processor 101 and the second inter-core communication unit 104 corresponding to the second processor 102 based on the first functional safety level and the second functional safety level; and transmit the inter-core communication data to the target inter-core communication unit.
[0032] The second processor 102 is used to read the inter-core communication data from the target inter-core communication unit.
[0033] Exemplarily, the target inter-core communication unit may be the first inter-core communication unit 103 or the second inter-core communication unit 104 , and the target inter-core communication unit may be the inter-core communication unit corresponding to the processor with a lower functional safety level among the first processor 101 and the second processor 102 .
[0034] In some embodiments, the first processor 101 can determine the high-low relationship between the first functional safety level and the second functional safety level; and based on the high-low relationship, determine the target inter-core communication unit in the first inter-core communication unit 103 corresponding to the first processor 101 and the second inter-core communication unit 103 corresponding to the second processor 102.
[0035] Exemplarily, when the first functional safety level of the first processor 101 is higher than the second functional safety level of the second processor 102 , the second inter-core communication unit 104 corresponding to the second processor 102 is determined as the target inter-core communication unit.
[0036] For example, Figure 1A As shown, taking the first functional safety level of the first processor 101 as an example, which is higher than the second functional safety level of the second processor 102, the first processor 101 determines the second inter-core communication unit 104 corresponding to the second processor 102 as the target inter-core communication unit, and transmits the inter-core communication data to the second inter-core communication unit 104, so that the second processor 102 can read the inter-core communication data from the second inter-core communication unit 104.
[0037] Exemplarily, when the first functional safety level of the first processor 101 is lower than the second functional safety level of the second processor 102 , the first inter-core communication unit 103 corresponding to the first processor 101 is determined as the target inter-core communication unit.
[0038] For example, Figure 1B As shown, taking the first functional safety level of the first processor 101 as an example, which is lower than the second functional safety level of the second processor 102. The first processor 101 determines the first inter-core communication unit 103 as the target inter-core communication unit, and transmits the inter-core communication data to the first inter-core communication unit 103, so that the second processor 102 can read the inter-core communication data from the first inter-core communication unit 103.
[0039] Exemplarily, when the first functional safety level of the first processor 101 is the same as the second functional safety level of the second processor 102, the first inter-core communication unit 103 corresponding to the first processor 101 and the second inter-core communication unit 104 corresponding to the second processor 102 can be the same inter-core communication unit or different inter-core communication units.
[0040] When the first inter-core communication unit 103 corresponding to the first processor 101 and the second inter-core communication unit 104 corresponding to the second processor 102 are different inter-core communication units, the first inter-core communication unit 103 corresponding to the first processor 101 can be determined as the target inter-core communication unit; or, the second inter-core communication unit 104 corresponding to the second processor 102 can also be determined as the target inter-core communication unit.
[0041] When the first inter-core communication unit 103 corresponding to the first processor 101 and the second inter-core communication unit 104 corresponding to the second processor 102 are the same inter-core communication unit, that is, the first inter-core communication unit 103 corresponding to the first processor 101 is the second inter-core communication unit 104 corresponding to the second processor 102, the same inter-core communication unit corresponding to the first processor 101 and the second processor 102 can be determined as the target inter-core communication unit.
[0042] In some embodiments, when the first processor 101 and the second processor 102 perform inter-core communication, the first processor 101 may also transmit a first interrupt signal to the second processor 102 through the first inter-core communication module 103, and the second processor 102 may read the inter-core communication data transmitted by the first processor 101 from the first inter-core communication module 103 based on the first interrupt signal.
[0043] In some embodiments, Figure 1C As shown, the integrated circuit 100 may further include a third processor 105. The first processor 101 is further configured to transmit the second interrupt signal to the third processor 105 through the first inter-core communication unit 103; the third processor 105 is configured to determine that the functional safety level of the third processor 105 is higher than the functional safety level of the first processor 101, and based on the transmission frequency of the second interrupt signal, shield the second interrupt signal.
[0044] For example, Figure 1C As shown, when the first processor 101 with a low functional safety level transmits the second interrupt signal to the third processor 105 with a high functional safety level through the first inter-core communication unit 103, if the third processor 105 with a high functional safety level determines that the transmission frequency of the second interrupt signal is greater than the preset frequency, then the third processor 105 can determine that the first processor 101 initiates an interrupt storm attack, so that the third processor 105 can shield the second interrupt signal.
[0045] In some embodiments, after the third processor 105 masks the second interrupt signal, the third processor 105 may periodically read the inter-core communication data transmitted by the first processor 101 from the first inter-core communication unit 103 .
[0046] The integrated circuit provided by the embodiment of the present disclosure, when performing inter-core communication between two processors of different functional safety levels in the integrated circuit, determines the functional safety level corresponding to each processor, and based on the high-low relationship of the functional safety levels corresponding to each processor, uses the inter-core communication unit corresponding to the processor with the lower functional safety level as the target inter-core communication unit, and then performs inter-core communication between the two processors based on the target inter-core communication unit. Since the present disclosure performs inter-core communication between processors of different functional safety levels based on the inter-core communication unit corresponding to the processor with the low functional safety level, the processor with the low functional safety level will not read data in the inter-core communication unit corresponding to the processor with the high functional safety level, and thus will not cause abnormalities in the inter-core communication unit corresponding to the processor with the high functional safety level. Therefore, the present disclosure can ensure that problems with processors with low functional safety levels will not affect high functional safety levels, so that processors with high functional safety levels can normally perform inter-core communication with other processors.
[0047] Exemplary Methods
[0048] Figure 2 FIG. 1 is a flow chart of an integrated circuit inter-core communication method provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to the integrated circuit shown in FIG. 1 above, or to an electronic device including the integrated circuit shown in FIG. 1 above, such as Figure 2 As shown, the method comprises the following steps:
[0049] Step 201: A first processor in an integrated circuit determines a second processor that performs inter-core communication with the first processor.
[0050] In some embodiments, the integrated circuit may be a system-on-chip, for example, a cabin-driver integrated chip or an intelligent driving chip. The integrated circuit may include multiple processors, which may include a first processor and a second processor. The embodiment of the present disclosure does not limit the number of processors included in the integrated circuit.
[0051] In some embodiments, the first processor and the second processor may be any of the following: a central processing unit, an image processor, a neural network processor, etc. The disclosed embodiment does not limit the types of the first processor and the second processor. For example, the types of the first processor and the second processor may be the same or different.
[0052] Exemplarily, the first processor is a central processing unit, and the second processor is also a central processing unit; the first processor is a central processing unit, and the second processor is an image processor.
[0053] Step 202: The first processor determines a first functional safety level corresponding to the first processor and a second functional safety level corresponding to the second processor.
[0054] In some embodiments, the functional safety level of the processor may be a safety level corresponding to the processor when executing certain functions. In some examples, multiple processors included in the integrated circuit may have different functional safety levels, at least two processors with the same functional safety level in the integrated circuit may correspond to the same inter-core communication unit or may correspond to different inter-core communication units; multiple processors with different functional safety levels in the integrated circuit may correspond to different inter-core communication units.
[0055] For example, multiple processors in an integrated circuit can be grouped according to different functional safety levels. Processors belonging to the same functional safety level can be grouped together. The processors in this group can correspond to the same inter-core communication unit or different inter-core communication units.
[0056] Exemplarily, the functional safety levels of multiple processes in the integrated circuit can be divided into four levels according to the automotive safety integrity level (ASIL) defined by the International Organization for Standardization and the risks associated with the danger: ASIL-A, ASIL-B, ASIL-C, ASIL-D and quality management (QM). Among them, the functional safety level specified by ASIL-D is the highest, and the functional safety levels specified by ASIL-C, ASIL-B, ASIL-B and QM decrease step by step. The disclosed embodiment does not limit the type of functional safety level corresponding to each processor, which is only an exemplary description here.
[0057] like Figure 3 As shown, an integrated circuit includes processor 1, processor 2 ... processor 5 and processor 6 as an example. Processors 1 to 6 are grouped according to different functional levels. The functional safety level of processor 1 and processor 2 is ASIL-D, and processor 1 and processor 2 correspond to the same inter-core communication unit IPCM1; the functional safety level of processor 3 and processor 4 is ASIL-B, and processor 3 and processor 4 correspond to the same inter-core communication unit IPCM2; the functional safety level of processor 5 and processor 6 is QM, and processor 5 and processor 6 correspond to the same inter-core communication unit IPCM3.
[0058] like Figure 4As shown, an integrated circuit includes processor 1, processor 2 ... processor 5 and processor 6 as an example. Processors 1 to 6 are grouped according to different functional levels. The functional safety level of processor 1 and processor 2 is ASIL-D, and processor 1 and processor 2 correspond to the same inter-core communication unit IPCM1; the functional safety level of processor 3 and processor 4 is ASIL-B, and processor 3 and processor 4 correspond to the same inter-core communication unit IPCM2; the functional safety level of processor 5 and processor 6 is QM, and processor 5 and processor 6 correspond to the same inter-core communication unit IPCM3.
[0059] In some embodiments, the first processor may determine a first functional safety level corresponding to the first processor based on functional safety level information of the first processor, and determine a second functional safety level corresponding to the second processor based on functional safety level information of the second processor. The functional safety level information may be a functional safety level identifier.
[0060] In some embodiments, the first functional safety level corresponding to the first processor and the second functional safety level corresponding to the second processor may be the same or different.
[0061] For example, Figure 3 In the integrated circuit shown, taking the first processor as processor 1 and the second processor as processor 5 as an example, the first functional safety level corresponding to the first processor is ASIL-D, and the second functional safety level corresponding to the second processor is QM.
[0062] For example, Figure 4 In the integrated circuit shown, taking the first processor as processor 6 and the second processor as processor 2 as an example, the first functional safety level corresponding to the first processor is QM, and the second functional safety level corresponding to the second processor is ASIL-D.
[0063] Step 203: The first processor determines a target inter-core communication unit among a first inter-core communication unit corresponding to the first processor and a second inter-core communication unit corresponding to the second processor based on the first functional safety level and the second functional safety level, and transmits the inter-core communication data to the target inter-core communication unit.
[0064] The target inter-core communication unit may be an inter-core communication unit corresponding to a processor with a lower functional safety level among the first processor and the second processor, and the target inter-core communication unit may be the first inter-core communication unit or the second inter-core communication unit.
[0065] Exemplarily, when the first functional safety level and the second functional safety level are different, the first inter-core communication unit is different from the second inter-core communication unit, and the target inter-core communication unit can be determined in the first inter-core communication unit and the second inter-core communication unit according to the first functional safety level and the second functional safety level.
[0066] In some embodiments, the first processor may use the first inter-core communication unit as a target inter-core communication unit based on the first functional safety level and the second functional safety level, and transmit the inter-core communication data to the first inter-core communication unit.
[0067] For example, Figure 4 As shown, taking the first processor as processor 6 and the second processor as processor 2 as an example, the first functional safety level corresponding to processor 6 is QM, and the second functional safety level corresponding to processor 2 is ASIL-D. Since the functional safety level of ASIL-D is higher than QM, processor 6 can use the inter-core communication unit IPCM3 corresponding to processor 6 as the target inter-core communication unit and transmit the inter-core communication data to IPCM3.
[0068] In some other embodiments, the first processor may use the second inter-core communication unit as a target inter-core communication unit based on the first functional safety level and the second functional safety level, and transmit the inter-core communication data to the second inter-core communication unit.
[0069] For example, Figure 3 As shown, taking the first processor as processor 1 and the second processor as processor 5 as an example, the first functional safety level corresponding to processor 1 is ASIL-D, and the second functional safety level corresponding to processor 5 can be QM. Since the functional safety level of ASIL-D is higher than QM, processor 1 uses the inter-core communication unit IPCM3 corresponding to processor 5 as the target inter-core communication unit and transmits the inter-core communication data to IPCM3.
[0070] Exemplarily, the inter-core communication data may be data collected by the first processor from various data sources (such as sensors, memory, registers, external devices, etc.) and need to be sent to the second processor. The inter-core communication data may include measurement values, status information, or control instructions, etc.
[0071] In some embodiments, before transmitting the collected data to the target inter-core communication unit, the first processor may process the collected data, such as formatting, encoding, encrypting, etc., and encapsulate the processed data into a specific data packet or message format to obtain inter-core communication data, and then transmit it to the target inter-core communication unit. After the first processor transmits the inter-core communication data to the target inter-core communication unit, the target inter-core communication unit may store the inter-core communication data.
[0072] Step 204: The second processor reads the inter-core communication data from the target inter-core communication unit.
[0073] In some embodiments, the second processor stores address information of a target inter-core communication unit, and can access the target inter-core communication unit corresponding to the address information based on the address information, and read inter-core data from the target inter-core communication unit.
[0074] For example, Figure 3 As shown, taking the first processor as processor 1 and the second processor as processor 5 as an example, the inter-core communication unit IPCM3 corresponding to processor 5 is the target inter-core communication unit, so that processor 5 can read the inter-core communication data from the inter-core communication unit IPCM3.
[0075] For example, Figure 4 As shown, taking the first processor as processor 6 and the second processor as processor 2 as an example, the inter-core communication unit IPCM3 corresponding to processor 6 is used as the target inter-core communication unit, so that processor 2 can read the inter-core communication data from the inter-core communication unit IPCM3.
[0076] Exemplarily, the second processor may also process the read inter-core communication data, for example, the second processor parses, calculates or forwards the inter-core communication data.
[0077] The inter-core communication method of an integrated circuit provided by the embodiment of the present disclosure, when inter-core communication is performed between processors with different functional safety levels, can determine the target inter-core communication unit based on the functional safety level of each processor, and transmit the inter-core communication data between processors with different functional safety levels through the target inter-core communication unit. Therefore, it can be ensured that no abnormalities will occur when inter-core communication is performed between processors with different functional safety levels, thereby ensuring the normal progress of inter-core communication.
[0078] like Figure 5 As shown in the above Figure 2 Based on the illustrated embodiment, step 203 may include the following steps:
[0079] Step 2031: The first processor determines a relationship between the first functional safety level and the second functional safety level.
[0080] In some embodiments, the first processor may compare the first functional safety level and the second functional safety level to determine a higher-lower relationship between the first functional safety level and the second functional safety level.
[0081] Exemplarily, the relationship between the first functional safety level and the second functional safety level may be that the first functional safety level is higher than the second functional safety level; or, the relationship between the first functional safety level and the second functional safety level may be that the first functional safety level is lower than the second functional safety level; or, the relationship between the first functional safety level and the second functional safety level may be that the first functional safety level is the same as the second functional safety level.
[0082] For example, when the first functional safety level is ASIL-A and the second functional safety level is ASIL-D, the first functional safety level is lower than the second functional safety level; when the first functional safety level is ASIL-D and the second functional safety level is QM, the first functional safety level is higher than the second functional safety level; when the first functional safety level is ASIL-D and the second functional safety level is ASIL-D, the first functional safety level is the same as the second functional safety level.
[0083] Step 2032: The first processor determines, based on the high-low relationship, the inter-core communication unit corresponding to the processor with a lower functional safety level among the first inter-core communication unit corresponding to the first processor and the second inter-core communication unit corresponding to the second processor as the target inter-core communication unit.
[0084] In some embodiments, when the relationship between the first functional safety level and the second functional safety level is different, the determined target inter-core communication unit is also different.
[0085] In some examples, in response to the high-low relationship being that the first functional safety level is higher than the second functional safety level, the first processor determines the second inter-core communication unit corresponding to the second processor as the target inter-core communication unit.
[0086] For example, Figure 3 As shown, taking the first processor as processor 1 and the second processor as processor 5 as an example, the first functional safety level corresponding to processor 1 is ASIL-D, and the second functional safety level corresponding to processor 5 is QM; since the first functional safety level ASIL-D is higher than the second functional safety level QM, processor 1 can determine the inter-core communication unit IPCM3 corresponding to processor 5 as the target inter-core communication unit.
[0087] In some examples, in response to the high-low relationship being that the first functional safety level is lower than the second functional safety level, the first processor determines a first inter-core communication unit corresponding to the first processor as a target inter-core communication unit.
[0088] For example, Figure 4As shown, taking the first processor as processor 6 and the second processor as processor 2 as an example, the first functional safety level corresponding to processor 6 is QM, and the second functional safety level corresponding to processor 2 is ASIL-D; since the first functional safety level QM is lower than the second functional safety level ASIL-D, processor 6 can determine its corresponding inter-core communication unit IPCM3 as the target inter-core communication unit.
[0089] It is understandable that both the above Figure 3 The medium and high functional safety level processor sends inter-core communication data to the low functional safety level processor, or Figure 4 Processors with medium and low functional safety levels send inter-core communication data to processors with high functional safety levels. This is based on the inter-core communication units corresponding to the processors with low functional safety levels to perform inter-core communication between the two processors, thereby ensuring that problems with the processors with low functional safety levels will not affect the high functional safety level, so that the processors with high functional safety levels can perform inter-core communication with other processors normally.
[0090] When performing inter-core communication, the target inter-core communication unit can be determined according to the functional safety level of each processor. Therefore, when performing inter-core communication between processors with different functional safety levels, the processor with a low functional safety level will not read data in the inter-core communication unit corresponding to the processor with a high functional safety level, and thus will not cause abnormalities in the inter-core communication unit corresponding to the processor with a high functional safety level, thereby ensuring that problems with the processor with a low functional safety level will not affect the high functional safety level, so that the processor with a high functional safety level can perform inter-core communication with other processors normally.
[0091] In some examples, in response to the high-low relationship that the first functional safety level is the same as the second functional safety level, when the first inter-core communication unit corresponding to the first processor and the second inter-core communication unit corresponding to the second processor are different inter-core communication units, the first processor can determine the first inter-core communication unit corresponding to the first processor or the second inter-core communication unit corresponding to the second processor as the target inter-core communication unit.
[0092] In some examples, in response to the high-low relationship that the first functional safety level is the same as the second functional safety level, when the first inter-core communication unit corresponding to the first processor and the second inter-core communication unit corresponding to the second processor are the same inter-core communication unit, the first processor can determine the inter-core communication units corresponding to the first processor and the second processor as the target inter-core communication unit.
[0093] For example, Figure 3As shown, taking the first processor as processor 1 and the second processor as processor 2 as an example, the first functional safety level corresponding to processor 1 is ASIL-D, and the second functional safety level corresponding to processor 2 is ASIL-D; since the first functional safety level ASIL-D is the same as the second functional safety level ASIL-D, processor 1 can determine the inter-core communication unit IPCM1 corresponding to processor 1 and processor 2 as the target inter-core communication unit.
[0094] Step 2033: The first processor transmits the inter-core communication data to the target inter-core communication unit.
[0095] For example, Figure 3 As shown, taking the first processor as processor 1 and the second processor as processor 5 as an example, the target inter-core communication unit is the inter-core communication unit IPCM3 corresponding to processor 5, so that processor 1 can transmit inter-core communication data to the inter-core communication unit IPCM3.
[0096] For example, Figure 4 As shown, taking the first processor as processor 6 and the second processor as processor 2 as an example, the target inter-core communication unit is the inter-core communication unit IPCM3 corresponding to processor 6, so that processor 6 can transmit inter-core communication data to the inter-core communication unit IPCM3.
[0097] For example, Figure 3 As shown, taking the first processor as processor 1 and the second processor as processor 2 as an example, the target inter-core communication unit is the inter-core communication unit IPCM1 corresponding to processor 1 and processor 2, so that processor 1 transmits the inter-core communication data to the inter-core communication unit IPCM1.
[0098] The inter-core communication method provided by the embodiment of the present disclosure, whether it is a processor with a high functional safety level sending inter-core communication data to a processor with a low functional safety level or a processor with a low functional safety level sending inter-core communication data to a processor with a high functional safety level, is based on the inter-core communication unit corresponding to the processor with a low functional safety level to perform inter-core communication between the two processors. Therefore, the processor with a low functional safety level will not read data in the inter-core communication unit corresponding to the processor with a high functional safety level, thereby not causing an abnormality in the inter-core communication unit corresponding to the processor with a high functional safety level. That is, the present disclosure can ensure that problems with a processor with a low functional safety level will not affect the high functional safety level, so that the processor with a high functional safety level can perform inter-core communication with other processors normally.
[0099] like Figure 6 As shown in the above Figure 5 Based on the illustrated embodiment, step 2033 may include the following steps:
[0100] Step 20331: The first processor transmits the inter-core communication data and the first interrupt signal to the target inter-core communication unit.
[0101] In some embodiments, the first processor first transmits the inter-core communication data to the target inter-core communication unit, and then transmits the first interrupt signal to the target inter-core communication unit after the inter-core communication data transmission is completed (for example, after the last frame of data transmission is completed).
[0102] In some embodiments, the first interrupt signal is used to notify the second processor to read the inter-core communication data from the target inter-core communication unit.
[0103] For example, Figure 3 As shown, taking the first processor as processor 1 and the second processor as processor 5 as an example, the target inter-core communication unit is the inter-core communication unit IPCM3 corresponding to processor 5, and processor 1 can transmit inter-core communication data and a first interrupt signal to the inter-core communication unit IPCM3.
[0104] Accordingly, the above step 204 may include the following steps:
[0105] Step 2041: The second processor reads inter-core communication data from the target inter-core communication unit based on the first interrupt signal transmitted by the target inter-core communication unit.
[0106] In some embodiments, the first interrupt signal includes address information of the target inter-core communication unit. The second processor can determine that the target inter-core communication unit stores inter-core communication data based on the first interrupt signal, and can read the inter-core communication data from the target inter-core communication unit corresponding to the address information.
[0107] For example, Figure 3 As shown, taking the first processor as processor 1 and the second processor as processor 5 as an example, the target inter-core communication unit is the inter-core communication unit IPCM3 corresponding to processor 5, and processor 5 can read the inter-core communication data in IPCM3 based on the first interrupt signal transmitted by the inter-core communication unit IPCM3.
[0108] The inter-core communication method provided by the embodiment of the present disclosure has the following advantages: since the first processor in the integrated circuit can transmit the first interrupt signal while transmitting the inter-core communication data to the target inter-core communication unit, the second processor can quickly read the inter-core communication data from the target inter-core communication unit based on the first interrupt signal transmitted by the target inter-core communication unit, thereby improving the speed at which the second processor reads data, and ensuring the send-and-receive between the sending processor and the receiving processor, thereby improving the inter-core communication efficiency.
[0109] like Figure 7 As shown in the above Figure 2Based on the illustrated embodiment, the inter-core communication method of the integrated circuit provided by the embodiment of the present disclosure may further include the following steps:
[0110] Step 205: The first processor transmits the second interrupt signal to the third processor through the first inter-core communication unit.
[0111] In some embodiments, the second interrupt signal is used to notify the third processor to read the inter-core communication data from the first inter-core communication unit.
[0112] In some embodiments, when inter-core communication is performed between the first processor and the third processor, after the first processor transmits the inter-core communication data to the first inter-core communication unit, the first processor may transmit a second interrupt signal to the third processor through the first inter-core communication unit to notify the third processor that the inter-core communication data is stored in the first inter-core communication unit.
[0113] Step 206 : The third processor determines that the functional safety level of the third processor is higher than the functional safety level of the first processor.
[0114] In some embodiments, the third processor can determine the functional safety level of the third processor based on the functional safety level information of the third processor, and determine the functional safety level of the first processor based on the functional safety level information of the first processor; and compare the functional safety level of the first processor with the functional safety level of the third processor to determine that the functional safety level of the third processor is higher than the functional safety level of the first processor.
[0115] Step 207: The third processor masks the second interrupt signal based on the transmission frequency of the second interrupt signal.
[0116] In some embodiments, when the third processor determines that the transmission frequency of the second interrupt signal is greater than a preset frequency, it is determined that the first processor has initiated an interrupt storm to the third processor, and the third processor can shield the second interrupt signal.
[0117] Exemplarily, when the transmission frequency of the second interrupt signal is greater than a preset frequency, the third processor can prevent the reception of the second interrupt signal by disabling the interrupt pin; alternatively, the third processor can execute a (ClearInterrupt Flag, CLI) instruction, and the interrupt flag of the third processor will be cleared, thereby prohibiting the third processor from responding to the second interrupt signal.
[0118] For example, Figure 4As shown, taking the first processor as processor 6 and the third processor as processor 2 as an example, the first functional safety level corresponding to processor 6 is QM, the second functional safety level corresponding to processor 2 is ASIL-D, and the target inter-core communication unit is IPCM3 corresponding to processor 6. Processor 6 transmits the second interrupt signal to processor 2 through IPCM3. Since the functional safety level of the third processor is higher than the functional safety level of the first processor, when the third processor determines that the transmission frequency of the second interrupt signal is greater than the preset frequency, the second interrupt signal transmitted by processor 6 through IPCM3 can be shielded.
[0119] In the inter-core communication method provided by the embodiment of the present disclosure, the first processor in the integrated circuit can transmit the second interrupt signal to the third processor through the first inter-core communication unit, and when the third processor with a high functional safety level determines that the transmission frequency of the second interrupt signal is greater than the preset frequency, the interrupt signal can be shielded. By shielding the interrupt signal by the third processor, the stability of the integrated circuit can be improved, and the integrated circuit can be prevented from crashing or abnormally occurring due to being unable to handle too many interrupts.
[0120] like Figure 8 As shown in the above Figure 7 Based on the embodiment shown, the following steps may also be included:
[0121] Step 208: The third processor reads the inter-core communication data from the first inter-core communication unit based on a preset cycle.
[0122] In some embodiments, the third processor may access the first inter-core communication unit based on a preset cycle, and upon determining that the first inter-core communication unit stores the inter-core communication data, read the inter-core communication data from the first inter-core communication unit.
[0123] For example, Figure 4 As shown, taking the first processor as processor 6 and the third processor as processor 2 as an example, when the third processor determines that the transmission frequency of the second interrupt signal is greater than the preset frequency, after shielding the second interrupt signal transmitted by processor 6 through IPCM3, processor 2 can read the inter-core communication data from the inter-core communication unit IPCM3 based on the preset period.
[0124] According to the inter-core communication method provided by the embodiment of the present disclosure, when multiple processors of an integrated circuit perform inter-core communication, after the third processor has shielded the interrupt signal causing the interrupt storm, the third processor can read the inter-core communication data from the first inter-core communication unit based on a preset period. Thus, it is ensured that the third processor can still receive the inter-core communication data sent by the first processor by actively accessing the first inter-core communication unit under the premise of preventing being attacked, thereby ensuring the normal execution of the inter-core communication between the first processor and the third processor.
[0125] Exemplary Electronic Devices
[0126] Fig. 9 A structural diagram of an electronic device 11 provided in an embodiment of the present disclosure includes at least one processor 111 and a memory 112 .
[0127] The processor 111 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 11 to perform desired functions.
[0128] The memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 111 may execute one or more computer program instructions to implement the vehicle control method and / or other desired functions of the various embodiments of the present disclosure described above.
[0129] In one example, the electronic device 11 may further include: an input device 113 and an output device 114 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).
[0130] The input device 113 may include various sensors, including but not limited to: a distance sensor for detecting the distance between the target object and the vehicle; an image sensor for collecting information about the vehicle's surrounding environment. In some examples, the input device may also include a pressure sensor for detecting seat pressure, determining whether there is a passenger, and the position of the passenger; a temperature sensor for monitoring the temperature in the cabin; a humidity sensor for monitoring the humidity in the cabin to assist in adjusting the interior environment; an air quality sensor for monitoring the air quality in the vehicle, such as carbon dioxide, volatile organic compounds (VOCs), etc.; a light sensor for detecting the light intensity inside and outside the vehicle; an acceleration sensor for detecting changes in the acceleration of the vehicle; a distance sensor for detecting the distance between the vehicle and other objects; a touch screen sensor for interaction with the vehicle's infotainment system; a biometric sensor, such as fingerprint recognition, facial recognition, etc.; a heart rate monitor for monitoring the driver's heart rate; a sound sensor for voice recognition and interaction to achieve voice control functions; a seat sensor for monitoring the use of the seat, such as whether the seat is occupied and the body shape of the passenger; a wireless communication sensor, such as Bluetooth, Wi-Fi, etc., for connecting with smart devices to achieve data transmission and remote control. In addition to the examples given above, the input device may also include more or fewer sensors, which will not be described in detail here.
[0131] The output device 114 can output various information or signals to other hardware or devices, which may include displays, vehicle audio, seats, windows, steering wheels, etc., as well as communication networks and remote output devices connected thereto, etc. The displays may include a plurality of different display screens such as a driver's display screen, a co-driver's display screen, and a rear display screen, and the vehicle audio may include a plurality of speakers arranged at different positions in the vehicle cabin, and different display screens or speakers may work independently.
[0132] Of course, to simplify, Fig. 9 Only some of the components related to the present disclosure in the electronic device 11 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 11 may also include any other appropriate components.
[0133] Of course, to simplify, Fig. 9 Only some of the components related to the present disclosure in the electronic device 11 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 11 may also include any other appropriate components.
[0134] Exemplary computer program products and computer-readable storage media
[0135] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the inter-core communication method of the integrated circuit of the various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section.
[0136] The computer program product may be written in any combination of one or more programming languages to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0137] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps of the inter-core communication method of the integrated circuit of the various embodiments of the present disclosure described in the above “Exemplary Method” section.
[0138] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.
[0139] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.
[0140] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the present claims and their equivalents, the present disclosure is also intended to include these modifications and variations.
Claims
1. A method for inter-core communication of an integrated circuit, comprising: A first processor in the integrated circuit determines a second processor that performs inter-core communication with the first processor; Determining, by the first processor, a first functional safety level corresponding to the first processor and a second functional safety level corresponding to the second processor; The first processor determines a target inter-core communication unit in a first inter-core communication unit corresponding to the first processor and a second inter-core communication unit corresponding to the second processor based on the first functional safety level and the second functional safety level, and transmits inter-core communication data to the target inter-core communication unit; The second processor reads the inter-core communication data from the target inter-core communication unit.
2. The method according to claim 1, wherein: The first processor determines, based on the first functional safety level and the second functional safety level, a target inter-core communication unit in a first inter-core communication unit corresponding to the first processor and a second inter-core communication unit corresponding to the second processor, including: The first processor determines a higher-lower relationship between the first functional safety level and the second functional safety level; Based on the high-low relationship, the first processor determines, among the first inter-core communication unit corresponding to the first processor and the second inter-core communication unit corresponding to the second processor, that the inter-core communication unit corresponding to the processor with a lower functional safety level is the target inter-core communication unit.
3. The method according to claim 2, wherein: The first processor determines, based on the high-low relationship, that the inter-core communication unit corresponding to the processor with a lower functional safety level is the target inter-core communication unit among the first inter-core communication unit corresponding to the first processor and the second inter-core communication unit corresponding to the second processor, including: In response to the first functional safety level being higher than the second functional safety level, the first processor determines the second inter-core communication unit corresponding to the second processor as the target inter-core communication unit; or, In response to the high-low relationship being that the first functional safety level is lower than the second functional safety level, the first processor determines a first inter-core communication unit corresponding to the first processor as the target inter-core communication unit; In response to the high-low relationship being that the first functional safety level is the same as the second functional safety level, the first processor determines a first inter-core communication unit corresponding to the first processor or a second inter-core communication unit corresponding to the second processor as the target inter-core communication unit.
4. The method according to claim 1, wherein: The first processor transmits the inter-core communication data to the target inter-core communication unit, including: The first processor transmits the inter-core communication data and the first interrupt signal to the target inter-core communication unit; The second processor reads the inter-core communication data from the target inter-core communication unit, including: The second processor reads the inter-core communication data from the target inter-core communication unit based on the first interrupt signal transmitted by the target inter-core communication unit.
5. The method according to any one of claims 1 to 3, further comprising: The first processor transmits the second interrupt signal to the third processor through the first inter-core communication unit; The third processor determines that the functional safety level of the third processor is higher than the functional safety level of the first processor; The third processor masks the second interrupt signal based on the transmission frequency of the second interrupt signal.
6. The method according to claim 5, after the third processor masks the second interrupt signal based on the transmission parameter of the interrupt signal, the method further comprises: The third processor reads the inter-core communication data from the first inter-core communication unit based on a preset cycle.
7. An integrated circuit comprising: A first processor, a second processor, a first inter-core communication unit corresponding to the first processor, and a second inter-core communication unit corresponding to the second processor; The first processor is used to determine the second processor that performs inter-core communication with the first processor, and determine a first functional safety level corresponding to the first processor and a second functional safety level corresponding to the second processor; The first processor is further configured to determine a target inter-core communication unit in the first inter-core communication unit and the second inter-core communication unit based on the first functional safety level and the second functional safety level; The first processor is further configured to transmit the inter-core communication data to the target inter-core communication unit; The second processor is used to read the inter-core communication data from the target inter-core communication unit.
8. The integrated circuit according to claim 7, wherein: The first processor determines a target inter-core communication unit in the first inter-core communication unit and the second inter-core communication unit based on the first functional safety level and the second functional safety level, specifically for: The first processor determines a higher-lower relationship between the first functional safety level and the second functional safety level; Based on the high-low relationship, the first processor determines, among the first inter-core communication unit corresponding to the first processor and the second inter-core communication unit corresponding to the second processor, that the inter-core communication unit corresponding to the processor with a lower functional safety level is the target inter-core communication unit.
9. The integrated circuit according to claim 7, wherein: The integrated circuit further comprises: a third processor, The first processor is further configured to transmit the second interrupt signal to the third processor via the first inter-core communication unit; The third processor is used to determine that a functional safety level of the third processor is higher than a functional safety level of the first processor; and based on the transmission frequency of the interrupt signal, shield the second interrupt signal.
10. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the inter-core communication method of an integrated circuit according to any one of claims 1 to 6.
11. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the inter-core communication method of the integrated circuit according to any one of claims 1 to 6; Alternatively, the electronic device comprises an integrated circuit as claimed in claims 7-9.