Dynamic error correction method suitable for three-dimensional NAND flash memory, controller and storage system

Abstract

The invention discloses a dynamic error correction method suitable for a three-dimensional NAND flash memory, a controller and a storage system, and belongs to the technical field of semiconductor storage, and the method comprises the following steps: a coding stage: carrying out polar code coding on data to be written into the three-dimensional NAND flash memory to obtain a code word sequence with the length of N; in the decoding stage, the LLR value of each bit is calculated for the data with the length of N read from the three-dimensional NAND flash memory; after setting the list length of the SCL decoding algorithm, inputting the N-bit LLR value into the SCL decoding algorithm to realize decoding; the step of setting the list length of the SCL decoding algorithm comprises the following steps: acquiring bit error rates of the SCL decoding algorithm under different list lengths under the current original bit error rate of the three-dimensional NAND flash memory, screening the list length with the bit error rate lower than a preset performance threshold, and setting the list length of the SCL decoding algorithm as the screened minimum length. The method adapts to the error characteristic of the three-dimensional NAND flash memory, and the overhead can be reduced under the condition of ensuring that the error correction requirement is met.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor storage technology, and more specifically, relates to a dynamic error correction method, a controller and a storage system suitable for three-dimensional NAND flash memory. Background Art

[0002] The storage capacity and storage density of flash memory are steadily increasing with the reduction of feature size and the increase of stacking layers. Its excellent storage capacity and performance are the needs of today's big data era and have been widely used in various scenarios: servers, data centers, etc. Large-capacity solid-state drives using 3D NAND flash memory are also rapidly replacing mechanical hard disks in the storage market. However, the improvement of the integration of 3D NAND flash memory arrays still comes at the cost of reduced service life and reliability. On the one hand, from SLC to TLC and then to possible QLC and PLC in the future, multi-level storage cell technology compresses the threshold voltage distribution window of each state, resulting in more states overlapping each other, requiring more reference voltages, and seriously affecting performance and reliability. On the other hand, multi-layer stacking brings more complex interference and differences in the vertical direction. The combination of the two shows different error characteristics from planar NAND flash memory, especially the inter-layer differences unique to the three-dimensional structure, that is, the RBER of different layers is different, and the RBER in different layers changes differently over time.

[0003] The BCH code commonly used in the early days and the LDPC code commonly used now are both common ECC schemes in flash memory. As for polar codes, due to their unique structure, they have become the first constructive coding scheme that can be proven to reach the channel capacity through rigorous mathematical methods. They have good error floor performance and low encoding and decoding complexity, which has also attracted the attention of scholars. There are related works that use polar codes as flash memory ECC (Error Checking and Correction) to study their performance.

[0004] The SC (serial cancellation) decoding algorithm is a classic decoding algorithm for polar codes. The algorithm is based on the recursive coding structure of polar codes and gradually determines the value of each bit by traversing a full binary tree constructed by position information. The SCL (serial cancellation list) decoding algorithm is an improvement on the SC decoding algorithm, which aims to improve the accuracy and efficiency of decoding. The SCL decoding algorithm significantly improves the decoding performance at the expense of a certain complexity by retaining multiple possible decoding paths and selecting the optimal path at each step. The basic idea of ​​the SCL decoding algorithm is to retain not only one optimal path but L optimal paths through a list in each decoding process. These paths are sorted according to the path metric, which is usually calculated based on the log-likelihood ratio (LLR). At each step, the algorithm selects L optimal paths to continue decoding until the preset termination condition is reached. Finally, the path with the highest path metric is selected as the decoding result. The decoding performance and complexity can be flexibly adjusted by adjusting the value of the list length L.

[0005] However, current work on polar code ECC mainly focuses on planar flash memory, and the decoding algorithm is too simple. It often directly uses the existing soft decoding algorithm in the communication field without taking into account the error characteristics unique to three-dimensional NAND flash memory, and cannot effectively balance the decoding performance and decoding overhead. Summary of the invention

[0006] In view of the defects of the prior art and the need for improvement, the present invention provides a dynamic error correction method, a controller and a storage system suitable for three-dimensional NAND flash memory. The purpose is to flexibly adjust the list length of the decoding algorithm in the decoding process according to the error characteristics of the three-dimensional NAND flash memory when using polar code encoding, so as to reduce the overhead as much as possible while ensuring that the error correction requirements are met.

[0007] To achieve the above object, according to one aspect of the present invention, a dynamic error correction method applicable to a three-dimensional NAND flash memory is provided, comprising: an encoding stage and a decoding stage;

[0008] The encoding stage includes: performing polarization code encoding on the data to be written into the three-dimensional NAND flash memory to obtain a code word sequence with a preset length N; N = 2 x , x is a natural number;

[0009] The decoding stage includes: for data of length N read from the three-dimensional NAND flash memory, calculating the LLR value corresponding to each bit to obtain N bits of soft information; after setting the list length of the SCL decoding algorithm, inputting the N bits of soft information into the SCL decoding algorithm to achieve decoding;

[0010] The steps of setting the list length of the SCL decoding algorithm include:

[0011] S1. Determine the current original bit error rate of the three-dimensional NAND flash memory, and obtain the bit error rate of the SCL decoding algorithm under different list lengths under the current original bit error rate, and select the list length with a bit error rate lower than a preset performance threshold to obtain a list length candidate set;

[0012] S2. Set the list length of the SCL decoding algorithm to the minimum length in the list length candidate set.

[0013] Furthermore, between step S1 and step S2, the following steps are also included:

[0014] Obtain the bit error rate of the LDPC decoding algorithm under the current original bit error rate as a reference benchmark;

[0015] Eliminate the list lengths whose corresponding bit error rates are higher than the reference benchmark from the list length candidate set;

[0016] If the list length candidate set is empty, add the preset maximum list length to it.

[0017] Furthermore, the dynamic error correction method applicable to three-dimensional NAND flash memory provided by the present invention further includes: drawing curves of the bit error rate of the LDPC decoding algorithm and the SCL decoding algorithm at different list lengths versus the original bit error rate in the same two-dimensional coordinate system, and obtaining the intersection of the curve corresponding to the LDPC decoding algorithm and the other curves; the abscissa and ordinate of the two-dimensional coordinate system are the original bit error rate and the bit error rate of the decoding algorithm, respectively;

[0018] Taking the original bit error rate corresponding to each intersection point as a boundary, multiple original bit error rate ranges are obtained;

[0019] SCL decoding algorithms with bit error rates lower than those of LDPC decoding algorithms are selected within each original bit error rate range, and the list lengths of the SCL decoding algorithms selected within each original bit error rate range are combined into a preferred length set corresponding to the corresponding original bit error rate range;

[0020] In addition, list lengths whose corresponding bit error rates are higher than the reference benchmark are removed from the list length candidate set, including:

[0021] Determine the original bit error rate range to which the current original bit error rate belongs, and obtain the corresponding preferred length set as the current preferred length set;

[0022] The list lengths in the list length candidate set that do not belong to the current preferred length set are deleted from the list length candidate set.

[0023] Further, the SCL decoding algorithm is set according to the ECC capability requirements, which include decoding delay and decoding capability;

[0024] Moreover, when the ECC capability requirement focuses more on decoding delay, the SCL decoding algorithm is the Fast-SCL algorithm; when the ECC capability requirement focuses more on decoding capability, the SCL decoding algorithm is the CA-SCL algorithm.

[0025] Furthermore, polarization code encoding is performed on the data to be written into the three-dimensional NAND flash memory, including:

[0026] The beta-expansion method is used to evaluate the reliability of each symbol in the N-bit binary symbol sequence after encoding, and the R×N bits with the highest reliability are used as information channels, and the remaining (1-R)×N bits are used as frozen channels; R represents the code rate of the flash memory system where the three-dimensional NAND flash memory is located;

[0027] The data to be written into the three-dimensional NAND flash memory is divided according to R×N to obtain a plurality of data blocks;

[0028] For each data block, fill the R×N symbols into the information channel, fill the known (1-R)×N frozen bits into the frozen channel, and obtain an N-bit binary symbol sequence U={u1, u2, ..., u N}, perform a recursive XOR operation to obtain an N-bit binary symbol sequence Y = {y1, y2, ..., y N};

[0029] The recursive XOR operation consists of the following steps:

[0030] T1, for the binary symbol sequence A = {a1, a2, ..., a M}, if its length M>1, go to step T2; otherwise, end the current binary symbol sequence;

[0031] T2, according to the binary symbol sequence A = {a1, a2, ..., a M} is converted into a binary symbol sequence B = {b1, b2, ..., b M}, the conversion is as follows:

[0032]

[0033] T3, for the binary symbol sequence B = {b1, b2, ..., b M} so that the odd-numbered sign bits and the even-numbered sign bits are located in the first half and the second half respectively;

[0034] T4, dividing the sorted binary symbol sequence B into two binary symbol sequences evenly, and performing a recursive XOR operation on each of the binary symbol sequences obtained by the division;

[0035] in, Represents the exclusive OR operation.

[0036] According to another aspect of the present invention, a dynamic error correction controller for three-dimensional NAND flash memory is provided, comprising a computer-readable storage medium and a processor; the computer-readable storage medium is used to store a computer program, and the processor is used to read the computer program stored in the computer-readable storage medium to execute the above-mentioned dynamic error correction method applicable to three-dimensional NAND flash memory provided by the present invention.

[0037] According to another aspect of the present invention, a storage system is provided, comprising: a three-dimensional NAND flash memory and the above-mentioned dynamic error correction controller applicable to the three-dimensional NAND flash memory provided by the present invention.

[0038] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0039] (1) In the case of polar code encoding of data, the present invention selects the SCL decoding algorithm to decode the data read from the three-dimensional NAND flash memory, which can obtain better decoding performance; before decoding, the list length that can meet the error correction requirement is determined according to the current original bit error rate of the three-dimensional flash memory, and the minimum list length is selected therefrom, thereby adaptively adapting to the error conditions of different layers in the three-dimensional NAND flash memory, reducing the decoding overhead and the decoding delay while ensuring that the error correction requirement is met.

[0040] (2) LDPC (Low-Density Parity-Check) code is an efficient error correction coding scheme, which is widely used in NAND flash memory, mainly for improving the reliability of data storage. Due to its good balance between error correction capability and implementation complexity, LDPC code has become the mainstream choice for many modern storage systems. In the preferred embodiment of the present invention, the decoding performance of LDPC code is used as a reference benchmark, and the list length with decoding performance lower than the reference benchmark is eliminated from the list length that can meet the error correction requirements, so that the SCL decoding algorithm has better decoding performance while meeting the error correction requirements.

[0041] (3) In a further preferred embodiment of the present invention, by plotting the curves of the bit error rate of the LDPC decoding algorithm and the SCL decoding algorithm at different list lengths versus the original bit error rate in the same two-dimensional coordinate system, the intersection of the curve corresponding to the LDPC decoding algorithm and the other curves is obtained. The intersection is used as a criterion for switching the list length, thereby quickly determining the list length that can make the decoding performance of the SCL decoding algorithm better than that of the LDPC decoding algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 Schematic diagram of the existing polar code encoding process;

[0043] Figure 2 Schematic diagram of the existing polar code decoding process; wherein (a), (b), and (c) represent three operations in different decoding processes respectively;

[0044] Figure 3 A schematic diagram of a dynamic error correction method applicable to a three-dimensional NAND flash memory provided by an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of a curve showing the change of the bit error rate with the original bit error rate of the LDPC decoding algorithm and the Fast-SCL decoding algorithm at different list lengths provided in an embodiment of the present invention;

[0046] Figure 5 A schematic diagram of a curve showing the change of the bit error rate of the LDPC decoding algorithm and the CA-SCL decoding algorithm at different list lengths with the original bit error rate provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] In the present invention, the terms "first", "second", etc. (if any) in the present invention and the accompanying drawings are used to distinguish similar objects but not necessarily to describe a specific order or sequence.

[0049] Before explaining the technical solution of the present invention in detail, a conventional polar code encoding and decoding method is briefly introduced.

[0050] In the polar code encoding process, the polar code is used to encode the original information data string to obtain the encoded data string. For example, if the total length of the data is 32, Figure 1 As shown, the reliability of the 32-bit data after encoding is pre-evaluated using the beta-expansion method, and the data is sorted. According to the code rate R required by the storage system where the three-dimensional NAND flash memory is located, R×32 bits are selected as information channels to store information data, and the remaining (1-R)×32 bits are selected as frozen channels to store known frozen bits (usually 0). Then, assuming that the original information symbol is {u1, u2, …, u 32}, first, perform XOR operation on two by two, for example, for u1 and u2, we get: s1 = u1 ⊕ u2, s2 = u2, ⊕ represents XOR operation; then reorder the bits so that the original odd bit symbols are in the first half and the original even bit symbols are in the second half, and after the bit reordering, the information symbols are evenly divided into subsequences {s1, s2, ..., s 16} and {s 17 ,s 18 ,…,s 32}. Recursively perform the above XOR-reorder-segmentation steps for the subsequence until no further segmentation is possible, and you will get {y1, y2, …, y 32}. After encoding, a data string with a length of 32 will also be obtained.

[0051] Traditional decoding methods such as Figure 2 As shown in , the symbol sequence to be decoded is organized into a decoding tree, the leaf nodes of the decoding tree correspond to a single symbol, and the internal nodes are symbol sequences composed of symbols or symbol sequences corresponding to their child nodes; when decoding, starting from the root node of the decoding tree, the initial LLR value of the channel is used as the original information, and the information passed to the left child node is first calculated by the f formula, such as Figure 2 As shown in (a), sgn(·) represents the sign function. When the left subtree obtains the hard decision value through soft information calculation and returns it upward, the soft information of the right child node is calculated through the g formula, as shown in Figure 2 When the right subtree obtains the hard decision value through soft information calculation, a reverse encoding operation is finally performed to restore the hard decision value, as shown in (b) in the figure. Figure 2 As shown in (c) in .

[0052] The SCL (successive cancellation list) decoding algorithm introduces a list based on the above decoding algorithm. When decoding, it starts from the root node of the code tree and searches for paths layer by layer toward the leaf node layer. After each layer is expanded, as many paths as possible are retained (the number of paths retained in each layer is not greater than the list length L), and the L paths with the smallest path metric (PM) are selected and saved in the list, waiting for the expansion of the next layer. When L=1, the SCL decoding algorithm degenerates into the SC decoding algorithm. The longer the list length, the better the decoding performance, but the corresponding storage overhead is greater and the decoding delay is higher.

[0053] Current work on polar code ECC is mainly focused on planar flash memory. When using the SCL decoding algorithm, a fixed list length is often set according to the decoding performance requirements. However, under the same list length, the decoding performance of the SCL decoding algorithm will vary with the original bit error rate (RBER). Due to the difference between layers of three-dimensional NAND flash memory, the RBER of different layers is different, and the RBER in different layers varies over time. The fixed list length may cause the decoding algorithm to fail to meet the error correction requirements in some layers, or require additional overhead in some layers. In response to this technical problem, the present invention provides a dynamic error correction method, controller and storage system suitable for three-dimensional NAND flash memory. The overall concept is to flexibly adjust the list length of the decoding algorithm during the decoding process based on the error characteristics of the three-dimensional NAND flash memory, comprehensively consider the original bit error rate, error correction requirements and decoding overhead, and minimize the overhead while ensuring that the error correction requirements are met.

[0054] The following are examples.

[0055] Embodiment 1:

[0056] A dynamic error correction method suitable for three-dimensional NAND flash memory, such as Figure 3 As shown, it includes: encoding stage and decoding stage;

[0057] The encoding stage includes: performing polarization code encoding on the data to be written into the three-dimensional NAND flash memory to obtain a code word sequence with a preset length N; N = 2 x , x is a natural number;

[0058] The decoding stage includes: for data of length N read from the three-dimensional NAND flash memory, calculating the LLR value corresponding to each bit to obtain N bits of soft information; after setting the list length of the SCL decoding algorithm, inputting the N bits of soft information into the SCL decoding algorithm to achieve decoding;

[0059] The steps of setting the list length of the SCL decoding algorithm include:

[0060] S1. Determine the current original bit error rate of the three-dimensional NAND flash memory, and obtain the bit error rate of the SCL decoding algorithm under different list lengths under the current original bit error rate, and select the list length with a bit error rate lower than a preset performance threshold to obtain a list length candidate set;

[0061] S2. Set the list length of the SCL decoding algorithm to the minimum length in the list length candidate set.

[0062] In this embodiment, the method of encoding data in the encoding stage is the same as the traditional method.

[0063] In practical applications, the specific selected SCL decoding algorithm can be set according to the actual ECC capability requirements, which include decoding delay and decoding capability. In this embodiment, compared with the decoding capability, the ECC capability requirements pay more attention to the decoding delay, and accordingly, the SCL decoding algorithm is the Fast-SCL algorithm to obtain a lower decoding delay. It should be noted that the Fast-SCL decoding algorithm is only an optional SCL decoding algorithm of the present invention and should not be understood as the only limitation of the present invention. In some other embodiments of the present invention, other SCL decoding algorithms with flexible list lengths can also be selected.

[0064] The decoding performance of the Fast-SCL decoding algorithm is different under different list lengths, and the decoding performance of the Fast-SCL decoding algorithm is also different when the RBER is different under the same list length, such as Figure 4 shown.

[0065] In practical applications, the RBER of NAND flash memory is related to the current number of erase / program times and retention time of the flash memory. Currently, there are relevant models for estimating the RBER of NAND flash memory. After obtaining the current number of erase / program times and retention time, the corresponding model is input to obtain the current RBER of the three-dimensional NAND flash memory.

[0066] In this embodiment, when polar code encoding is performed on data, an SCL decoding algorithm is selected to decode data read from a three-dimensional NAND flash memory, so that better decoding performance can be obtained. Before decoding, a list length that can meet error correction requirements is determined according to the current original bit error rate of the three-dimensional flash memory, and the minimum list length is selected therefrom, thereby adaptively adapting to error conditions of different layers in the three-dimensional NAND flash memory, reducing decoding overhead and decoding delay while ensuring that error correction requirements are met.

[0067] LDPC (Low-Density Parity-Check) code is an efficient error correction coding scheme, widely used in NAND flash memory, mainly used to improve the reliability of data storage. Due to its good balance between error correction capability and implementation complexity, LDPC code has become the mainstream choice for many modern storage systems. In order to further improve the decoding performance, as a preferred implementation, this embodiment will also use the decoding performance of the LDPC decoding algorithm as a reference benchmark when setting the list length of the Fast-SCL decoding algorithm, and try to make the set list length enable the Fast-SCL decoding algorithm to obtain better decoding performance than the LDPC decoding algorithm. Accordingly, between step S1 and step S2, it also includes:

[0068] Obtain the bit error rate of the LDPC decoding algorithm under the current original bit error rate as a reference benchmark;

[0069] Eliminate the list lengths whose corresponding bit error rates are higher than the reference benchmark from the list length candidate set;

[0070] If the list length candidate set is empty, add the preset maximum list length to it.

[0071] Based on the above operations, when the list length reaches the preset maximum list length (usually set to 32) and the RBER rises to the maximum error correction capability of the polar code, the performance of the dynamic polar code is not as good as that of the LDPC because the LDPC is in the waterfall region. At this time, the list length is still set to the maximum list length to get as close to the decoding performance of the LDPC as possible.

[0072] In order to quickly determine the relationship between the decoding performance of the Fast-SCL decoding algorithm and the LDPC decoding algorithm under different list lengths, as a preferred implementation, this embodiment further includes: in the same two-dimensional coordinate system, respectively plotting the curves of the bit error rate of the LDPC decoding algorithm and the Fast-SCL decoding algorithm under different list lengths versus the original bit error rate, and obtaining the intersection of the curve corresponding to the LDPC decoding algorithm and the other curves, such as Figure 4 As shown, "FLL" represents fix list length (fixed length); the horizontal axis and the vertical axis of the two-dimensional coordinate system are the original bit error rate (RBER) and the bit error rate (BER) of the decoding algorithm respectively;

[0073] Taking the original bit error rate corresponding to each intersection point as a boundary, multiple original bit error rate ranges are obtained;

[0074] SCL decoding algorithms with bit error rates lower than those of LDPC decoding algorithms are selected within each original bit error rate range, and the list lengths of the SCL decoding algorithms selected within each original bit error rate range are combined into a preferred length set corresponding to the corresponding original bit error rate range;

[0075] In addition, list lengths whose corresponding bit error rates are higher than the reference benchmark are removed from the list length candidate set, including:

[0076] Determine the original bit error rate range to which the current original bit error rate belongs, and obtain the corresponding preferred length set as the current preferred length set;

[0077] The list lengths in the list length candidate set that do not belong to the current preferred length set are deleted from the list length candidate set.

[0078] In this embodiment, the curves of the bit error rate of the LDPC decoding algorithm and the SCL decoding algorithm at different list lengths are plotted in the same two-dimensional coordinate system to change with the original bit error rate, and the intersection of the curve corresponding to the LDPC decoding algorithm and the other curves is obtained. The intersection will be used as the standard for switching the list length. For example, if the current list length is 2 x, when RBER increases to 2 (x-1) The decoding capability of the LDPC code crosses the point where the list length is reduced to 2 (x-1) This shows that 2 (x-1) The decoding capability is sufficient to complete the decoding task.

[0079] Embodiment 2:

[0080] A dynamic error correction method for three-dimensional NAND flash memory. This embodiment is similar to the above-mentioned embodiment 1, except that, in this embodiment, compared with decoding delay, ECC capability requirements focus more on decoding capability, so in this embodiment, the SCL decoding algorithm specifically uses the CA-SCL algorithm to obtain higher decoding capability.

[0081] In this embodiment, the curves of the bit error rate of the LDPC decoding algorithm and the CA-SCL decoding algorithm at different list lengths versus the original bit error rate are plotted in the same two-dimensional coordinate system, and the intersection of the curve corresponding to the LDPC decoding algorithm and the other curves is obtained, such as Figure 5 As shown, “FLL” stands for fix list length.

[0082] In this embodiment, the specific implementation of the remaining steps can refer to the description in the above-mentioned embodiment 1 and will not be repeated here.

[0083] Embodiment 3:

[0084] A dynamic error correction controller for a three-dimensional NAND flash memory includes a computer-readable storage medium and a processor; the computer-readable storage medium is used to store a computer program, and the processor is used to read the computer program stored in the computer-readable storage medium and execute the dynamic error correction method for the three-dimensional NAND flash memory provided in the above-mentioned embodiment 1 or 2.

[0085] Embodiment 4:

[0086] A storage system includes: a three-dimensional NAND flash memory and the dynamic error correction controller provided in the above-mentioned embodiment 3 and applicable to the three-dimensional NAND flash memory.

[0087] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamic error correction method applicable to three-dimensional NAND flash memory, characterized in that: include: Encoding phase and decoding phase; The encoding stage includes: performing polar code encoding on the data to be written into the three-dimensional NAND flash memory to obtain a code word sequence with a preset length N; N=2 x , x is a natural number; The decoding stage includes: for data of length N read from the three-dimensional NAND flash memory, calculating the LLR value corresponding to each bit to obtain N-bit soft information; after setting the list length of the SCL decoding algorithm, inputting the N-bit soft information into the SCL decoding algorithm to implement decoding; The step of setting the list length of the SCL decoding algorithm comprises the following steps: S1, determining the current original bit error rate of the three-dimensional NAND flash memory, and obtaining the bit error rates of the SCL decoding algorithm at different list lengths under the current original bit error rate, and screening out the list lengths with bit error rates lower than a preset performance threshold to obtain a list length candidate set; S2. Setting the list length of the SCL decoding algorithm to the minimum length in the list length candidate set.

2. The dynamic error correction method applicable to a three-dimensional NAND flash memory according to claim 1, characterized in that: The step S1 and the step S2 also include: Obtain the bit error rate of the LDPC decoding algorithm under the current original bit error rate as a reference benchmark; Eliminate, from the list length candidate set, list lengths corresponding to bit error rates higher than the reference benchmark; If the list length candidate set is empty, a preset maximum list length is added thereto.

3. The dynamic error correction method applicable to a three-dimensional NAND flash memory as claimed in claim 2, characterized in that: Also includes: In the same two-dimensional coordinate system, respectively draw the curves of the bit error rate of the LDPC decoding algorithm and the SCL decoding algorithm at different list lengths versus the original bit error rate, and obtain the intersection of the curve corresponding to the LDPC decoding algorithm and the other curves; The horizontal coordinate and the vertical coordinate of the two-dimensional coordinate system are the original bit error rate and the bit error rate of the decoding algorithm respectively; Taking the original bit error rate corresponding to each intersection point as a boundary, multiple original bit error rate ranges are obtained; SCL decoding algorithms with bit error rates lower than those of LDPC decoding algorithms are selected within each original bit error rate range, and the list lengths of the SCL decoding algorithms selected within each original bit error rate range are combined into a preferred length set corresponding to the corresponding original bit error rate range; Furthermore, removing the list length corresponding to the bit error rate higher than the reference benchmark from the list length candidate set includes: Determine the original bit error rate range to which the current original bit error rate belongs, and obtain the corresponding preferred length set as the current preferred length set; The list lengths in the list length candidate set that do not belong to the current preferred length set are deleted from the list length candidate set.

4. The dynamic error correction method applicable to a three-dimensional NAND flash memory according to any one of claims 1 to 3, characterized in that: The SCL decoding algorithm is set according to the ECC capability requirement, and the ECC capability requirement includes decoding delay and decoding capability; Furthermore, when the ECC capability requirement focuses more on decoding delay, the SCL decoding algorithm is a Fast-SCL algorithm; when the ECC capability requirement focuses more on decoding capability, the SCL decoding algorithm is a CA-SCL algorithm.

5. The dynamic error correction method applicable to a three-dimensional NAND flash memory as claimed in claim 1, characterized in that: For data to be written into the three-dimensional NAND flash memory, polar code encoding is performed on it, including: The reliability of each symbol in the N-bit binary symbol sequence after encoding is evaluated by beta-expansion, and the R×N bits with the highest reliability are used as information channels, and the remaining (1-R)×N bits are used as frozen channels; R represents the code rate of the flash memory system where the three-dimensional NAND flash memory is located; Dividing the data to be written into the three-dimensional NAND flash memory according to R×N to obtain a plurality of data blocks; For each data block, fill the R×N symbols into the information channel, fill the known (1-R)×N frozen bits into the frozen channel, and obtain an N-bit binary symbol sequence U={u1, u2, ..., u N }, perform a recursive XOR operation to obtain an N-bit binary symbol sequence Y = {y1, y2, ..., y N }; The recursive XOR operation comprises the following steps: T1, for the binary symbol sequence A = {a1, a2, ..., a M }, if its length M>1, go to step T2; otherwise, end the current binary symbol sequence; T2, according to the binary symbol sequence A = {a1, a2, ..., a M } is converted into a binary symbol sequence B = {b1, b2, ..., b M }, the conversion is as follows: T3, for the binary symbol sequence B = {b1, b2, ..., b M } so that the odd-numbered sign bits and the even-numbered sign bits are located in the first half and the second half respectively; T4, dividing the sorted binary symbol sequence B into two binary symbol sequences evenly, and performing the recursive XOR operation on each of the binary symbol sequences obtained by the division; in, Represents the exclusive OR operation.

6. A dynamic error correction controller for a three-dimensional NAND flash memory, characterized in that: It comprises a computer-readable storage medium and a processor; the computer-readable storage medium is used to store a computer program, and the processor is used to read the computer program stored in the computer-readable storage medium to execute the dynamic error correction method applicable to a three-dimensional NAND flash memory as described in any one of claims 1 to 5.

7. A storage system, characterized in that: include: A three-dimensional NAND flash memory and a dynamic error correction controller applicable to the three-dimensional NAND flash memory as claimed in claim 6.

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