Method and device for realizing high-speed data channel fault tolerance, chip and storage medium

Abstract

The invention discloses a method for realizing high-speed data channel fault tolerance. The method is applied to a network acceleration chip provided with a first data channel and a second data channel. The method at least comprises the following steps: a network acceleration chip performs data interaction with a host through a first data channel; performing anomaly detection on the first data channel, and collecting anomaly configuration information corresponding to the first data channel when detecting that the first data channel is abnormal; according to the abnormal configuration information, determining an IO context environment which needs to recover uncompleted data interaction with the host, and switching the current interaction to a second data channel; and continuing to perform data interaction with the host by using the second data channel according to the determined IO context environment in which data interaction is not completed. The invention further discloses a corresponding device, a chip and a storage medium. By implementing the invention, the fault-tolerant capability and robustness of the network acceleration chip in the key data interaction path can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, chip and storage medium for implementing fault tolerance of a high-speed data channel. Background Art

[0002] In data center applications, Smart Network Interface Card / Data Processing Unit (SMARTNIC / DPU) is usually designed as a complex system on a chip (SoC), including multi-core CPU, dynamic random access memory / static memory (DRAM / SRAM), application specific integrated circuit (ASIC), field programmable gate array (FPGA) and other hardware resources. It also has programmable dedicated acceleration engine and DMA engine and other hardware modules, which can provide acceleration services for specific application scenarios. SMARTNIC / DPU chips have been widely used in virtualization acceleration, network protocol stack, data encryption and decryption, cloud services, machine learning, storage and other fields.

[0003] SMARTNIC / DPU can provide high-speed data channels for offloading I / O-intensive and compute-intensive tasks. In the process of implementing offloading tasks in the high-speed data channel, in order to adapt to the interactive information in different application scenarios, the high-speed data channel needs to determine the corresponding data storage format after negotiation with the host. These data formats may be protocols defined by public specifications for a certain application, including the Non-Volatile Memory express (NVMe) protocol, the Virtual I / ODevice (Virtio) protocol, the XTS-AES encryption algorithm (a high-performance encryption algorithm), and private data formats between users and DPUs.

[0004] During the entire data offloading process, the high-speed data channel connects and communicates with the host through the Peripheral Component Interconnect Express (PCIe) high-speed bus, and obtains the data to be processed from the host. Although ASIC can design high-speed data channels within the DPU to provide higher offloading capabilities, it has some disadvantages, such as insufficient flexibility, poor programmability, and difficulty in flexible definition and configuration of software. In addition, after the design of ASIC is completed, its hardware logic is immutable and difficult to adapt to changes in demand. Therefore, there are great challenges in using ASIC to design efficient and highly reliable data channels for complex application scenarios in data centers.

[0005] In the field of storage and data encryption and decryption where high availability and high reliability are required for data processing, if the high-speed data channel is unavailable or unreliable due to ASIC logic anomalies, it will bring potential risks to the data security of upstream applications. For example, data may be lost due to processing anomalies during the calculation of erasure coding (EC), or the original data cannot be restored due to anomalies in the encryption and decryption process. Therefore, the high-speed data channel used in the prior art has the disadvantages of insufficient fault tolerance and poor robustness. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a method, device, chip and storage medium for realizing fault tolerance of high-speed data channels, which can improve the fault tolerance and robustness of network acceleration chips in key data interaction paths.

[0007] In order to solve the above technical problems, as one aspect of the present invention, a method for realizing fault tolerance of a high-speed data channel is provided, and the method is applied to a network acceleration chip, wherein the network acceleration chip is provided with a first data channel for high-speed data interaction and a second data channel used as a redundant channel; the method at least comprises:

[0008] The network acceleration chip exchanges data with the host through the first data channel;

[0009] Performing anomaly detection on the first data channel, and when detecting that an anomaly occurs in the first data channel, collecting anomaly configuration information corresponding to the first data channel;

[0010] According to the abnormal configuration information, determine the IO context environment of the unfinished data interaction that needs to resume data interaction with the host, and switch the current interaction to the second data channel;

[0011] The second data channel is used to continue data interaction with the host according to the determined IO context environment of the unfinished data interaction.

[0012] The method further includes completing the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host, including:

[0013] In the memory of the network acceleration chip, space resources of the DMA command queue are allocated to the DMA engine, and the DMA engine and DMA queue components in the second data channel are initialized;

[0014] In the memory of the network acceleration chip, space resources for storing metadata are allocated to the IO request context queue;

[0015] The relevant information in the host IO queue is configured in the request context component of the first data channel to complete the initialization; the relevant information in the IO queue includes: the base address, queue depth, initial queue head and initial queue tail of the host IO queue, and the base address information of the corresponding IO request context queue in the host IO queue.

[0016] The performing abnormality detection on the first data channel further includes:

[0017] The abnormality monitoring of the first data channel is started, and when any one of the following three abnormal conditions is met, it is determined that the first data channel is abnormal:

[0018] If the abnormal information stored in the first data channel is found in the metadata in the IO request context queue, it is determined that an abnormality has occurred in the first data channel;

[0019] By establishing a periodic heartbeat keep-alive detection for the first data channel, a heartbeat detection signal is periodically sent to the first data channel, and if the detection condition does not meet the expectation within a predetermined time, it is determined that an abnormality has occurred in the first channel, wherein the heartbeat detection signal is generated based on a state condition in the first data channel;

[0020] When an abnormal message reported by the first data channel through the SPI interrupt is received, it is determined that an abnormality has occurred in the first channel.

[0021] Wherein, when the first data channel is detected to be abnormal, collecting abnormal configuration information corresponding to the first data channel further includes:

[0022] Acquire abnormal host queue configuration information when IO is suspended in the queue context component of the first data channel, wherein the abnormal host queue configuration information includes: a base address of the abnormal host queue, a queue depth, a head / tail cursor base address of the queue, and position information of the first channel accessing the host queue and the first data channel accessing the IO request context queue when abnormal;

[0023] According to the abnormal host queue configuration information, the unprocessed IO request context information of the first data channel is collected in the IO request context queue component of the first data channel, and the metadata information of the unprocessed IO requests is obtained from the IO request context queue.

[0024] Wherein, determining, according to the abnormal configuration information, an IO context environment in which unfinished data interaction needs to be resumed with the host, and switching the current interaction to the second data channel further includes:

[0025] In the second data channel, a DMA command queue is applied for through the DMA engine to establish a context environment for interacting with the host IO request;

[0026] According to the collected context information of the unprocessed IO requests in the first data channel and the corresponding metadata, the uncompleted IO requests are determined and encapsulated into DMA commands, and the IO requests for the uncompleted data interaction are exchanged with the host through the DMA engine in the second data channel;

[0027] The IO context environment of the unfinished data interaction that the second data channel needs to resume data interaction with the host is determined through the IO request context information, and the second data channel is controlled to read and write the IO requests in the host's IO queue according to the determined IO context environment of the unfinished data interaction, and transmit IO data to the host.

[0028] Among them, further include:

[0029] When the network acceleration chip performs data interaction with the host through the first data channel, metadata corresponding to the current interaction is stored in an IO request context queue in the network acceleration chip.

[0030] The network acceleration chip is a DPU chip or a SMARTNIC chip; the first data channel is an ASIC data channel, and the second data channel is a DMA data channel.

[0031] As another aspect of the present invention, a device for realizing fault tolerance of a high-speed data channel is also provided, the device is applied to a network acceleration chip, the network acceleration chip is provided with a first data channel for high-speed data interaction and a second data channel for redundant processing; the device at least comprises:

[0032] A first channel interaction unit, used for the network acceleration chip to interact with the host through the first data channel;

[0033] an abnormality detection unit, configured to perform abnormality detection on the first data channel, and when an abnormality is detected in the first data channel, collect abnormal configuration information corresponding to the first data channel;

[0034] A switching processing unit, configured to determine, according to the abnormal configuration information, an IO context environment in which unfinished data interaction needs to be resumed with the host, and switch the current interaction to a second data channel;

[0035] The second channel interaction unit is used to continue data interaction with the host by using the second data channel according to the determined IO context environment of the unfinished data interaction.

[0036] As another aspect of the present invention, a network acceleration chip is provided, wherein a first data channel for high-speed data interaction and a second data channel for redundant processing are provided in the network acceleration chip, further comprising:

[0037] A fault-tolerant control unit is used to switch the current interaction to the second data channel when an abnormality occurs in the first data channel, and includes:

[0038] A configuration unit, used to complete the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host;

[0039] An error detection unit, used for performing abnormality monitoring on the first data channel;

[0040] A collecting unit, which collects abnormal configuration information corresponding to the first data channel when an abnormality is detected in the first data channel;

[0041] The switching unit is used to determine, according to the abnormal configuration information, an IO context environment in which the unfinished data interaction with the host needs to be resumed, and switch the current interaction to the second data channel.

[0042] Wherein, a queue context component and an IO request context queue component are provided in the first data channel;

[0043] A DMA engine and a DMA queue are arranged in the second data channel.

[0044] Among them, further include:

[0045] When the network acceleration chip performs data interaction with the host through the first data channel, key information of the IO request corresponding to the current interaction and metadata thereof are stored in the IO request context queue in the network acceleration chip.

[0046] The network acceleration chip is a DPU chip or a SMARTNIC chip; the first data channel is an ASIC data channel, and the second data channel is a DMA data channel.

[0047] Correspondingly, another aspect of the present invention further provides a device for implementing high-speed data channel fault tolerance, the device is applied to a network acceleration chip, the network acceleration chip is provided with a first data channel for high-speed data interaction and a second data channel for redundant processing; the device at least comprises:

[0048] A first channel interaction unit, used for the network acceleration chip to interact with the host through the first data channel;

[0049] an abnormality detection unit, configured to perform abnormality detection on the first data channel, and when an abnormality is detected in the first data channel, collect abnormal configuration information corresponding to the first data channel;

[0050] A switching processing unit, configured to determine, according to the abnormal configuration information, an IO context environment in which unfinished data interaction needs to be resumed with the host, and switch the current interaction to a second data channel;

[0051] The second channel interaction unit is used to continue data interaction with the host by using the second data channel according to the determined IO context environment of the unfinished data interaction.

[0052] Accordingly, in another aspect of the present invention, a network acceleration chip is provided, wherein a first data channel for high-speed data interaction and a second data channel for redundant processing are provided, further comprising:

[0053] A fault-tolerant control unit is used to switch the current interaction to the second data channel when an abnormality occurs in the first data channel, and includes:

[0054] A configuration unit, used to complete the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host;

[0055] An error detection unit, used for performing abnormality monitoring on the first data channel;

[0056] A collecting unit, which collects abnormal configuration information corresponding to the first data channel when an abnormality is detected in the first data channel;

[0057] The switching unit is used to determine, according to the abnormal configuration information, an IO context environment in which the unfinished data interaction with the host needs to be resumed, and switch the current interaction to the second data channel.

[0058] Among them, further include:

[0059] A queue context component and an IO request context queue component are deployed in the first data channel;

[0060] A DMA engine and a DMA queue are deployed in the second data channel.

[0061] Accordingly, as another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the aforementioned method are implemented.

[0062] The implementation of the present invention has the following beneficial effects:

[0063] The present invention provides a method, device, chip and storage medium for realizing fault tolerance of high-speed data channels, by deploying a first data channel for high-speed data interaction and a second data channel for redundant processing in a network acceleration chip (such as DPU / SMARTNIC), and setting a fault-tolerant control unit; when the network acceleration chip interacts with the host through the first data channel, an abnormality detection can be performed, and when an abnormality is detected in the first data channel, the abnormal configuration information corresponding to the first data channel is collected, and according to the abnormal configuration information, the IO context environment that needs to restore the unfinished data interaction with the host is determined, and the current interaction is switched to the second data channel, so that the second data channel is used to continue to interact with the host from the determined IO context environment of the unfinished data interaction, so as to ensure the reliability and stability of the system. The present invention can be implemented to improve the fault tolerance and robustness of the SMARTNIC / DPU system through the fault-tolerant mode of software and hardware collaboration in specific application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying creative labor, other drawings obtained based on these drawings still belong to the scope of the present invention.

[0065] Figure 1 A schematic diagram of the main process of an embodiment of a method for realizing fault tolerance of a high-speed data channel provided by the present invention;

[0066] Figure 2 for Figure 1 Schematic diagram of the application environment;

[0067] Figure 3 for Figure 1 A more detailed flow chart of

[0068] Figure 4 A schematic structural diagram of an embodiment of a high-speed data channel fault tolerance device provided by the present invention. DETAILED DESCRIPTION

[0069] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0070] like Figure 1 FIG. 1 is a schematic diagram showing a main flow chart of an embodiment of a method for realizing high-speed data channel fault tolerance provided by the present invention; and FIG. Figure 2 and Figure 3 As shown, in this embodiment, the method is applied to Figure 2 environment architecture.

[0071] like Figure 2 As shown, the network acceleration chip is connected to the host through a PCIe interface, and the network acceleration chip may be, for example, a DPU or a SMARTNIC, in which a first data channel for high-speed data interaction and a second data channel for fault-tolerant processing are provided; in an example of the present invention, the first data channel is an ASIC data channel, and an ASIC may be used to implement data packet processing logic on the first data channel; the second data channel is a DMA data channel, and a fault-tolerant channel logic may be implemented on the second channel based on programmable DMA hardware and in collaboration with a software program;

[0072] More specifically, a queue context component (Queue Context) and an IO request context queue component (IO Request Context Queue) are deployed in the first data channel;

[0073] Among them, the queue context component is generally used to store and manage queue information in the network acceleration chip, which contains the status and configuration parameters of each queue. In the present application, this component acts in the first data channel, and its main function is to provide the second data channel with the exception queue configuration information required for IO context switching during fault-tolerant processing. The abnormal host queue configuration information includes: the base address of the abnormal host queue, the queue depth, the head / tail cursor base address of the queue, and the location information of the first channel accessing the host queue and the location information of the first data channel accessing the IO request context queue during the abnormality.

[0074] The IO request context queue component is used to store metadata of the IO request corresponding to the interaction on the first data channel. The metadata is used to track and identify the data packets or tasks in the queue. Generally, the metadata includes key information of the IO request and its processing status information. For example, in some examples, the metadata may include:

[0075] Identifier of IO request: used to uniquely identify each IO request, usually an ID, sequence number or pointer;

[0076] Type of IO request: indicates the type of IO request, such as read (Read) or write (Write);

[0077] Target device of the IO request: indicates the device or resource that the IO request is to access, such as the address or identifier of a storage device;

[0078] The offset and length of the IO request: indicates the starting position of the IO request on the target device and the length of the data to be transferred;

[0079] Processing status of IO request: records the processing status of IO request on the first data channel, such as whether the transmission has been completed or whether an error has occurred.

[0080] A DMA engine and a DMA queue are deployed in the second data channel, and the second data channel implements a path for accessing IO requests and IO data in the host IO queue.

[0081] Among them, the DMA engine is a programmable DMA (direct memory access) module in the network acceleration chip, which is used to efficiently transfer data between the host memory and the network acceleration chip. The DMA engine is responsible for managing the data transmission process, including starting the transmission, handling transmission errors, interrupt processing, etc. It can be configured and programmed to implement various data transmission modes and protocols to meet different application requirements.

[0082] The DMA queue is used to manage and schedule the data transfer operations of the DMA engine. It maintains the status of the DMA engine, the read and write pointers, and the data packets or tasks to be processed.

[0083] At the same time, an IO request context queue is deployed in the memory of the network acceleration chip, which is used to cache the context information and exception information of each IO request queue reported by the IO request context queue component.

[0084] The network acceleration chip further includes a fault-tolerant control unit, which is used to switch the current interaction to the second data channel when an abnormality occurs in the first data channel. More specifically, the fault-tolerant control unit is the second data channel that completes the control of IO data transmission through a software and hardware collaborative method, and includes the following four sub-units:

[0085] A configuration unit, used to complete the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host;

[0086] An error detection unit, used for performing abnormality monitoring on the first data channel;

[0087] A collecting unit, which collects abnormal configuration information corresponding to the first data channel when an abnormality is detected in the first data channel;

[0088] The switching unit is used to determine, according to the abnormal configuration information, an IO context environment in which the unfinished data interaction with the host needs to be resumed, and switch the current interaction to the second data channel.

[0089] More detailed functional details of the above functional units or components will be described below in conjunction with the process of the method.

[0090] More specifically, please combine Figure 3 As shown, in this embodiment, the method provided by the present invention comprises at least the following steps:

[0091] Step S10, the network acceleration chip exchanges data with the host through the first data channel;

[0092] It can be understood that the following steps are further included before step S10:

[0093] Step S00, completing the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host, including:

[0094] In the memory of the network acceleration chip, space resources of the DMA command queue are allocated to the DMA engine, and the DMA engine and DMA queue components in the second data channel are initialized;

[0095] In the memory of the network acceleration chip, a space resource for storing IO metadata is allocated to the IO request context queue, and the space resource is provided with an area for storing abnormal information of abnormal IO;

[0096] The relevant information in the host IO queue is configured in the request context component of the first data channel to complete the initialization; the relevant information in the IO queue includes: the base address, queue depth, initial queue head and initial queue tail of the host IO queue, and the base address information of the corresponding IO request context queue in the host IO queue.

[0097] Meanwhile, step S10 further includes:

[0098] When the network acceleration chip performs data interaction with the host through the first data channel, metadata of the IO request corresponding to the current interaction is stored in the IO request context queue of the network acceleration chip.

[0099] It is understandable that in the embodiment of the present invention, after the IO request context queue component set in the first data channel takes away the host-side IO request, the host can release the relevant request resources. For example, after the requests in the NVMe SQ (Submission Queue) and packed virtqueue on the host side in the storage offloading scenario are taken away by the first data channel, new requests can be placed in the original position. In order to avoid that some IO requests cannot be recovered after the first channel is abnormal, the first data channel needs to send the metadata of the IO request to the IO request context queue for caching.

[0100] Step S11, performing an abnormality detection on the first data channel, and when an abnormality is detected in the first data channel, collecting abnormal configuration information corresponding to the first data channel; if no abnormality is detected, continuing the monitoring process.

[0101] In the step S11, performing abnormality detection on the first data channel further includes:

[0102] Step S110, start abnormal monitoring of the first data channel, and determine that the first data channel is abnormal when any one of the following three abnormal conditions is met:

[0103] If the abnormal information stored in the first data channel is found in the status information of the metadata in the IO request context queue, it is determined that an abnormality has occurred in the first data channel;

[0104] By establishing a periodic heartbeat keep-alive detection for the first data channel, a heartbeat detection signal is periodically sent to the first data channel. If the detection condition does not meet expectations within a predetermined time (for example, no response to the heartbeat detection signal from the first data channel is received), it is determined that an abnormality has occurred in the first channel, wherein the heartbeat detection signal is generated based on a state condition in the first data channel. Specifically, the heartbeat signal can be a defined signal or flag that reflects the active state of the first channel. The generation of such a heartbeat signal may depend on monitoring certain state conditions, such as the activity count of the channel, the last communication time, etc. It is understandable that in other examples, the detection condition may also be abnormal conditions such as: the head and tail cursors of the host queue accessed in the first data channel remain unchanged for a long time, the first data channel is in a back pressure state for a long time, etc.

[0105] When an abnormal message reported by the first data channel through the SPI interrupt is received, it is determined that an abnormality has occurred in the first channel.

[0106] Meanwhile, in the step S11, when the first data channel is detected to be abnormal, collecting abnormal configuration information corresponding to the first data channel further includes:

[0107] Step S111, obtaining abnormal host queue configuration information when IO is suspended in the queue context component of the first data channel, wherein the abnormal host queue configuration information includes: the base address of the abnormal host IO queue, the queue depth, the head / tail cursor base address of the queue, and the position information of the first channel accessing the host queue and the position information of the first data channel accessing the IO request context queue when abnormal;

[0108] According to the abnormal host queue configuration information, the unprocessed IO request context information of the first data channel is collected in the IO request context queue component of the first data channel, and the metadata information of the unprocessed IO requests is obtained from the IO request context queue.

[0109] It can be understood that, in the embodiment of the present invention, the queue context set in the first channel can provide the second data channel with the exception queue configuration information required for IO context switching during fault tolerance processing.

[0110] Step S12, determining, according to the abnormal configuration information, an IO context environment that needs to resume unfinished data interaction with the host, and switching the current interaction to the second data channel;

[0111] The IO context environment of unfinished data interaction includes two parts. The first part is the IO request of the unfinished data interaction pulled from the host Host to the first data channel. The second data channel needs to complete the first part of the IO request through metadata recovery. The recovery of the first part of the IO request is completed inside the network acceleration chip SoC; the second part is the IO request in the host host queue. The second data channel needs to continue processing from the starting position where the processing was suspended in the host queue.

[0112] In a specific example, the step S12 is specifically: constructing an IO path of the first data channel that is suspended due to an abnormality through the second data channel related components, and switching to the second data channel through the IO context information to continue to interact with the host:

[0113] In the second data channel, a DMA command queue is applied for through the DMA engine to establish a context environment for interacting with the host IO request;

[0114] According to the collected context information of the unprocessed IO requests in the first data channel and the corresponding metadata, the uncompleted IO requests are determined and encapsulated into DMA commands, and the uncompleted IO requests in the SOC are exchanged with the host through the DMA engine in the second data channel;

[0115] The IO context environment in which the second data channel needs to resume unfinished data interaction with the host is determined through the IO request context information. The second data channel reads and writes IO requests in the host's IO queue according to the determined unfinished IO context environment and transmits IO data to the host.

[0116] It is understandable that metadata contains key information and its processing status, which is used to describe and track the status and properties of IO requests. Unfinished host IO requests can be parsed based on metadata, which depends on specific parsing algorithms and context information. Generally, unfinished host IO requests can be determined by checking each metadata item in the IO request context queue and based on the processing status information therein.

[0117] For example, suppose the following two metadata items are stored in the IO request context queue:

[0118] Metadata Item 1:

[0119] Identifier: 1

[0120] Type: Write

[0121] Target device: Storage device A

[0122] Offset: 0

[0123] Length:4096

[0124] Status: Unfinished

[0125] Metadata item 2:

[0126] Identifier: 2

[0127] Type: Read

[0128] Target device: Storage device B

[0129] Offset:8192

[0130] Length:2048

[0131] Status: Complete

[0132] By parsing the processing status information of the metadata items, it can be determined that the IO request corresponding to metadata item 1 is unfinished, while the IO request corresponding to metadata item 2 is completed. Then, relevant processing is performed as needed, such as handing over the unfinished IO request to the second data channel to continue transmitting data.

[0133] In some examples, for an unfinished IO request, when switching to the second data channel, a re-request operation can be performed on the unfinished IO request; in this case, the IO request context information is used to determine that the second data channel needs to resume the IO context environment for unfinished data interaction with the host, and the second data channel reads and writes the IO requests in the host's IO queue according to the determined IO context environment for unfinished data interaction, and transmits IO data to the host.

[0134] In other examples, the completed part of the unfinished IO request can also be determined based on the abnormal host queue configuration information obtained in the queue context component of the first data channel, and then the unfinished data can be continued to be requested. In this case, it is necessary to determine it based on the base address of the abnormal host IO queue, the queue depth, and the head / tail cursor base address of the queue.

[0135] Step S13: using the second data channel to continue data interaction with the host according to the determined IO context environment of the unfinished data interaction.

[0136] In order to have a deeper understanding of the method provided by the present invention, a specific example is provided below for explanation:

[0137] The following introduces an implementation example of fault-tolerant processing in a storage or encryption / decryption scenario using the interaction of the virtio protocol and the NVMe protocol. Other offloading scenarios with higher requirements for data reliability have similar implementation processes, which are not listed here one by one.

[0138] Specifically, for NVMe submission / completion queues (Submission Queue / Completion Queue, SQ / CQ and split / packed Virtqueue fault tolerance processing embodiments, including the following steps:

[0139] Step 1: The fault-tolerant control unit configures the virtqueue information into the queue context component. The information configured for different types of queues differs as follows:

[0140] For a packed virtqueue, it is necessary to configure the descriptor table base address, available ring base address, used ring base address, and queue size information in the queue context component of the first data channel.

[0141] For split vritqueue, the descriptor ring (DescriptorRing) base address and queue size information need to be configured in the queue context component.

[0142] For NVMe SQ / CQ, the SQ / CQ base address and SQ / CQ size information need to be configured in the queue context component.

[0143] Step 2: The fault-tolerant control unit applies for IO request context queue and DMA command queue resources in the SoC memory, and configures the base address and queue depth of the requested related queue into the queue context component of the first data channel.

[0144] Step 3: The host puts an IO request into its IO queue and notifies the network acceleration chip (DPU / SMARTNIC) through the notify / doorbell command that there is an IO request to be processed.

[0145] Step 4: The first data channel takes out the IO request from the IO queue and parses it. When parsing the IO request, the first data channel needs to extract the metadata and store it in the IO request context queue, and then starts to process the actual IO request. The metadata extracted for different types of queues are different as follows:

[0146] Among them, for virtio packed / split vritqueue, its metadata includes the physical address, BD length and BD type information of all data memory segment descriptors (Buffer Descriptor, BD) requested by indirect / chain;

[0147] For NVMe SQ, its metadata includes command identifier (CID), command operation code (OPC), namespace identifier (NSID), data storage location in memory (DPTR), the first logical block address (SLBA) accessed by read and write commands, the number of logical blocks (NLB), data memory segment ID (Buffer Id), and the current queue head pointer (SQ Head Pointer SQHD) of the submission queue in SQ.

[0148] Step 5: The first data channel reads and writes the IO data on the host side by parsing the metadata information of the IO request; if the processing is successful, a response is sent to the host virtqueue / CQ and the process goes to step 3; if an exception is encountered during the processing, the exception is reported and the process goes to step 6;

[0149] Step 6: The fault-tolerant control unit detects abnormal host queue information and collects context information for the abnormal queue. The information collected for different types of queues is different as follows:

[0150] For packed vritqueue, the following information needs to be collected: vq effective head (avail head), vq used tail (used tail), descriptor table base address, effective ring base address, used ring base address and queue size information;

[0151] For the split vritqueue, the following information needs to be collected: device / driver wraparound counter, descriptor ring base address and queue size information, and location information for the first channel accessing the split vritqueue.

[0152] For NVMe, the following information needs to be collected: SQ / CQ base address and SQ / CQ size information, and the location information of the first channel accessing the SQ / CQ.

[0153] Step 7: The fault-tolerant control unit collects the IO request context information and retrieves the metadata of the unfinished IO request in step 4 from the IO request context queue;

[0154] Step 8: The IO context information collected in the previous steps 6-7 will be used to switch the IO context in the second channel. The process of switching the IO context on different types of queues is as follows:

[0155] For split vritqueue, read the unfinished IO requests through the second data channel related components, including the unfinished valid split BDs between the valid head of vq and the used tail of vq and the unfinished metadata in step 7; parse the used BDs according to the virtio split protocol, encapsulate them into DMA commands and put them into the DMA command queue.

[0156] For the packed vritqueue, the second data channel related components scan the merged vq according to the IO context information collected in steps 6-7, and retrieve the unfinished valid merged BD request; parse the used BD according to the virtio merge protocol, and encapsulate it into a DMA command and put it into the DMA command queue.

[0157] For NVMe SQ, the unfinished SQE request is read through the second data channel related components according to the IO context information collected in steps 6-7; the CQE is parsed according to the NVMe protocol, and encapsulated into a DMA command and put into the DMA command queue.

[0158] In this way, the fault-tolerant control unit can dynamically switch IO contexts between queues of different types to optimize IO processing efficiency.

[0159] Step 9: The fault-tolerant control unit uses the second data channel to read the request of vritqueue / SQ according to the virtio / NVMe protocol, parses it, and replies to complete the subsequent data interaction with the host.

[0160] It is understandable that in this embodiment, the host can be interacted with through the first data channel to process and respond to the IO requests in its IO queue. In this process, if an error occurs, the error can be recovered or bypassed through specific context information and fault tolerance strategies, and the second data channel is used to continue to interact with the host, which can ensure the reliability and stability of the system. The method of the present invention can improve the fault tolerance and robustness of the SMARTNIC / DPU system through the fault tolerance mode of software and hardware collaboration in specific application scenarios.

[0161] like Figure 4 As shown, a high-speed data channel fault tolerance device 1 provided by the present invention is shown, and the device is applied to a network acceleration chip, and the network acceleration chip is provided with a first data channel for high-speed data interaction and a second data channel for redundant processing; the device 1 at least includes:

[0162] A first channel interaction unit 10, used for the network acceleration chip to interact with the host through the first data channel;

[0163] The abnormality detection unit 11 is used to perform abnormality detection on the first data channel, and when an abnormality is detected in the first data channel, collect abnormal configuration information corresponding to the first data channel;

[0164] A switching processing unit 12 is used to determine, according to the abnormal configuration information, an IO context environment in which unfinished data interaction needs to be resumed with the host, and switch the current interaction to the second data channel;

[0165] The second channel interaction unit 13 is used to continue data interaction with the host by using the second data channel according to the determined IO context environment of the unfinished data interaction.

[0166] For more details, please refer to and combine the above Figures 1 to 3 The description is not repeated here.

[0167] Accordingly, another aspect of the present invention further provides a network acceleration chip. Figure 2As shown, the network acceleration chip is provided with at least a first data channel for high-speed data interaction and a second data channel for redundant processing, and further includes:

[0168] A fault-tolerant control unit is used to switch the current interaction to the second data channel when an abnormality occurs in the first data channel, and includes:

[0169] A configuration unit, used to complete the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host;

[0170] An error detection unit, used for performing abnormality monitoring on the first data channel;

[0171] A collecting unit, which collects abnormal configuration information corresponding to the first data channel when an abnormality is detected in the first data channel;

[0172] The switching unit is used to determine, according to the abnormal configuration information, an IO context environment in which the unfinished data interaction with the host needs to be resumed, and switch the current interaction to the second data channel.

[0173] Among them, further include:

[0174] A queue context component and an IO request context queue component are deployed in the first data channel;

[0175] A DMA engine and a DMA queue are deployed in the second data channel.

[0176] For more details, please refer to and combine the above Figures 1 to 3 The description is not repeated here.

[0177] Accordingly, as another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the above-mentioned Figures 1 to 3 For more details, please refer to and combine with the above Figures 1 to 3 The description is not repeated here.

[0178] The implementation of the present invention has the following beneficial effects:

[0179] The present invention provides a method, device, chip and storage medium for realizing high-speed data channel fault tolerance, by deploying a first data channel for high-speed data interaction and a second data channel for redundant processing in a network acceleration chip (such as DPU / SMARTNIC), and setting a fault-tolerant control unit; when the network acceleration chip interacts with the host through the first data channel, an abnormality detection can be performed, and when an abnormality is detected in the first data channel, the abnormal configuration information corresponding to the first data channel is collected, and according to the abnormal configuration information, the IO context environment that needs to restore the unfinished data interaction with the host is determined, and the current interaction is switched to the second data channel, so that the second data channel is used to continue to interact with the host according to the determined IO context environment of the unfinished data interaction, so as to ensure the reliability and stability of the system. The present invention can be implemented to improve the fault tolerance and robustness of the SMARTNIC / DPU system through the fault-tolerant mode of software and hardware collaboration in specific application scenarios.

[0180] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0181] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0182] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for implementing high-speed data channel fault tolerance, the method being applied to a network acceleration chip, characterized in that: The network acceleration chip is provided with a first data channel for high-speed data interaction and a second data channel used as a redundant channel; The method at least comprises: The network acceleration chip exchanges data with the host through the first data channel; Performing anomaly detection on the first data channel, and when detecting that an anomaly occurs in the first data channel, collecting anomaly configuration information corresponding to the first data channel; According to the abnormal configuration information, determine the IO context environment that needs to resume the unfinished data interaction with the host, and switch the current interaction to the second data channel; The second data channel is used to continue data interaction with the host according to the determined IO context environment of the unfinished data interaction.

2. The method according to claim 1, characterized in that The method further includes completing the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host, including: In the memory of the network acceleration chip, space resources of the DMA command queue are allocated to the DMA engine, and the DMA engine and DMA queue components in the second data channel are initialized; In the memory of the network acceleration chip, space resources for storing metadata are allocated to the IO request context queue; The relevant information in the host IO queue is configured in the request context component of the first data channel to complete the initialization; the relevant information in the host IO queue includes: the base address, queue depth, initial queue head and initial queue tail of the host IO queue, and the base address information of the corresponding IO request context queue in the host IO queue.

3. The method according to claim 2, characterized in that The performing abnormality detection on the first data channel further includes: The abnormality monitoring of the first data channel is started, and when any one of the following three abnormal conditions is met, it is determined that the first data channel is abnormal: If the abnormal information stored in the first data channel is found in the metadata in the IO request context queue, it is determined that an abnormality has occurred in the first data channel; By establishing a periodic heartbeat keep-alive detection for the first data channel, a heartbeat detection signal is periodically sent to the first data channel, and if the detection condition does not meet the expectation within a predetermined time, it is determined that an abnormality has occurred in the first channel, wherein the heartbeat detection signal is generated based on a state condition in the first data channel; When an abnormal message reported by the first data channel through the SPI interrupt is received, it is determined that an abnormality has occurred in the first channel.

4. The method according to claim 3, characterized in that When detecting that the first data channel is abnormal, collecting abnormal configuration information corresponding to the first data channel further includes: Acquire abnormal host queue configuration information when IO is suspended in the queue context component of the first data channel, wherein the abnormal host queue configuration information includes: a base address of the abnormal host queue, a queue depth, a head / tail cursor base address of the queue, and position information of the first channel accessing the host queue and the first data channel accessing the IO request context queue when abnormal; According to the abnormal host queue configuration information, the unprocessed IO request context information of the first data channel is collected in the IO request context queue component of the first data channel, and the metadata information of the unprocessed IO requests is obtained from the IO request context queue.

5. The method according to claim 3, characterized in that The step of determining, according to the abnormal configuration information, an IO context environment in which unfinished data interaction needs to be resumed with the host, and switching the current interaction to the second data channel further includes: In the second data channel, a DMA command queue is applied for through the DMA engine to establish a context environment for interacting with the host IO request; According to the collected context information of the unprocessed IO requests in the first data channel and the corresponding metadata, the uncompleted IO requests are determined and encapsulated into DMA commands, and the uncompleted IO requests in the SOC are exchanged with the host through the DMA engine in the second data channel; The IO context environment of the unfinished data interaction that the second data channel needs to resume data interaction with the host is determined through the IO request context information, and the second data channel is controlled to read and write the IO requests in the host's IO queue according to the determined IO context environment of the unfinished data interaction, and transmit IO data to the host.

6. The method according to any one of claims 1 to 5, further comprising: When the network acceleration chip performs data interaction with the host through the first data channel, metadata corresponding to the current interaction is stored in the IO request context queue of the network acceleration chip.

7. The method according to claim 6, characterized in that The network acceleration chip is a DPU chip or a SMARTNIC chip; the first data channel is an ASIC data channel, and the second data channel is a DMA data channel.

8. A device for realizing fault tolerance of a high-speed data channel, the device being applied to a network acceleration chip, characterized in that: The network acceleration chip is provided with a first data channel for high-speed data interaction and a second data channel for redundant processing; The device at least comprises: A first channel interaction unit, used for the network acceleration chip to interact with the host through the first data channel; an abnormality detection unit, configured to perform abnormality detection on the first data channel, and when an abnormality is detected in the first data channel, collect abnormal configuration information corresponding to the first data channel; A switching processing unit, configured to determine, according to the abnormal configuration information, an IO context environment in which unfinished data interaction needs to be resumed with the host, and switch the current interaction to a second data channel; The second channel interaction unit is used to continue data interaction with the host by using the second data channel according to the determined IO context environment of the unfinished data interaction.

9. A network acceleration chip, characterized in that: The network acceleration chip is provided with a first data channel for high-speed data interaction and a second data channel for redundant processing, and further comprises: A fault-tolerant control unit is used to switch the current interaction to the second data channel when an abnormality occurs in the first data channel, and includes: A configuration unit, used to complete the initialization configuration of the first data channel and the second data channel according to the IO queue provided by the host; An error detection unit, used for monitoring the first data channel for abnormalities; A collecting unit, which collects abnormal configuration information corresponding to the first data channel when an abnormality is detected in the first data channel; The switching unit is used to determine, according to the abnormal configuration information, an IO context environment in which the unfinished data interaction with the host needs to be resumed, and switch the current interaction to the second data channel.

10. The network acceleration chip according to claim 9, characterized in that: in: A queue context component and an IO request context queue component are provided in the first data channel; A DMA engine and a DMA queue are arranged in the second data channel.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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