Storage consistency verification method and system of on-chip multi-core processor, storage medium and equipment

Abstract

The invention discloses a storage consistency verification method and system of an on-chip multi-core processor, a storage medium and equipment. The method comprises the following steps: obtaining at least one directed acyclic graph based on test memory access excitation randomly generated for a multi-core processor; converting each layer in the directed acyclic graph into a program which can be executed by an on-chip multi-core processor; and executing the program corresponding to each layer in the on-chip multi-core processor, and determining the storage consistency of the on-chip multi-core processor according to the execution result of the program corresponding to each layer. By implementing the embodiment of the invention, the consistency verification test efficiency can be improved, and the efficiency and accuracy of abnormal positioning can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage consistency verification, and in particular to a storage consistency verification method, system, storage medium and device for an on-chip multi-core processor. Background Art

[0002] The multi-core structure on a chip has become the mainstream technology of current high-performance microprocessors. Among them, the storage system is the most complex part of the multi-core processor design on a chip. In order to improve the performance of the storage system, a variety of optimization technologies such as multi-level cache, distributed memory, and write buffer are often used in the design of the multi-core storage system on a chip. These complex designs greatly increase the probability of errors in the storage system. Storage consistency is an important feature of the storage system of the multi-core processor on a chip. It stipulates the correctness of the execution results of parallel programs and defines the order relationship between memory access operations in multiple processors. Together with the instruction set, it constitutes the hardware and software interface of the multi-core processor on a chip. Therefore, the verification of storage consistency is an important part of the verification of the multi-core processor on a chip.

[0003] In the prior art, LCHECK can be used as a storage consistency verification tool for on-chip multi-core processors. All the information required by LCHECK comes from the visible results of the program, and it can be used to verify storage consistency models such as sequential consistency, processor consistency, and weak consistency. However, LCHECK also has some shortcomings. For example, due to the size limitations of its operation window, memory access queue, write cache and other components, and the limited number of operations that overlap the execution time of a memory access operation, when LCHECK verifies storage consistency, the derivation of the order relationship and the detection of loops in the execution graph can be limited to a certain range of operations.

[0004] At the same time, since the LCHECK technology uses random generation of test memory access stimulus, there is no concept of order when generating stimulus. The memory access operation is random in time. It is essentially a stimulus generation method with non-deterministic execution results. This stimulus is a challenge to the correctness check and test efficiency of the test. On the one hand, the correctness check of consistency requires that after the use case is executed, the tool analyzes the relevant timestamps in the log to determine the order of memory access operations issued between different processes, and then checks the consistency of the execution results. The accuracy of the timestamp is affected by the existence of components such as the processor's internal operation window, memory access queue, and write cache. Targeted white box testing is required, and targeted testability design needs to be performed at the submission exit; on the other hand, due to the randomness of the stimulus, loops will inevitably occur, and the invalid stimulus of this part still needs to be eliminated through log analysis, which not only potentially affects the correctness of other stimuli, but also wastes test time and reduces test efficiency; at the same time, due to random uncertainty, the efficiency of problem debugging is also low. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a storage consistency verification method, system, storage medium and device for an on-chip multi-core processor, which can improve the efficiency of consistency verification testing and improve the efficiency and accuracy of abnormality positioning.

[0006] In order to solve the above technical problems, as one aspect of the present invention, a storage consistency verification method for an on-chip multi-core processor is provided, which at least comprises the following steps:

[0007] Based on the randomly generated test memory access stimulus for the multi-core processor, at least one directed acyclic graph is obtained; in the directed acyclic graph, each vertex is a memory access operation of a CPU core in the on-chip multi-core processor on a cache line address, and the directed edge of the directed acyclic graph is a notification event after the memory access operation is completed, and the starting point of the directed edge is the upstream vertex, and the end point of the directed edge is the downstream vertex;

[0008] Convert each layer in the directed acyclic graph into a program executable by the on-chip multi-core processor;

[0009] The program corresponding to each layer is executed in the on-chip multi-core processor, and the storage consistency of the on-chip multi-core processor is determined according to the execution result of the program corresponding to each layer.

[0010] The step of obtaining at least one directed acyclic graph based on the randomly generated test memory access stimulus for the multi-core processor further includes:

[0011] Based on the randomly generated test memory access stimulus for the multi-core processor, a cache line address for concurrent access by multiple CPU cores is randomly generated; an event statistics counter variable is randomly generated; and a CPU core number group for accessing the cache line address is randomly formed, and the CPU core number group includes multiple CPU cores; the number of layers of a directed acyclic graph is randomly formed; each layer randomly forms a corresponding memory access operation, and the memory access operation is one of a read operation, a write operation, a read-modify-write operation or an atomic operation; an exception information recording address of a directed acyclic graph is randomly formed;

[0012] According to the number of layers, the CPU cores involved in each layer and the corresponding memory access operations, a directed acyclic graph is established, and the initial standard value of the event statistics counter variable corresponding to each layer and the result standard value after execution are determined.

[0013] The step of converting each layer in the directed acyclic graph into a program executable by the CPU further includes:

[0014] A program conversion tool or a script tool is used to convert each layer of the directed acyclic graph into a program executable by a CPU core, and the program is imported into the on-chip multi-core processor.

[0015] The step of executing the program corresponding to each layer in the on-chip multi-core processor and determining the storage consistency of the on-chip multi-core processor according to the execution result of the program corresponding to each layer further includes:

[0016] When executing the program corresponding to each layer, check whether the current value of the event statistics counter variable is the same as the initial standard value of the event statistics counter variable of this layer;

[0017] When the two are the same, control at least one CPU core corresponding to the current layer to perform a memory access operation on the cache line address in a memory access mode corresponding to the current layer, and update the value of the event statistics counter variable;

[0018] Check whether the content of the cache line address after the memory access operation of this layer is completed is the same as the standard value of the result of this layer; if they are the same, continue to execute the corresponding program of the lower layer;

[0019] If it is detected that the current value of the event statistics counter variable is different from the initial standard value of this layer, or it is detected that the content in the cache line address after the memory access operation of this layer is completed is different from the standard value of the result of this layer, the corresponding exception will be recorded to the exception information recording address and the current test will be terminated.

[0020] Among them, further include:

[0021] If the programs corresponding to the predetermined number of directed acyclic graphs are all executed successfully, it is determined that the storage consistency of the on-chip multi-core processor meets the requirements;

[0022] If the monitoring detects the presence of abnormal records, it is determined that there is a defect in the storage consistency of the on-chip multi-core processor.

[0023] Correspondingly, another aspect of the present invention further provides a storage consistency verification system for an on-chip multi-core processor, which at least includes:

[0024] A directed acyclic graph generation unit is used to obtain at least one directed acyclic graph based on a randomly generated test memory access stimulus for a multi-core processor; in the directed acyclic graph, each vertex is a memory access operation of a CPU core in the on-chip multi-core processor on a cache line address, and a directed edge of the directed acyclic graph is a notification event after the memory access operation is completed, and the starting point of the directed edge is an upstream vertex, and the end point of the directed edge is a downstream vertex;

[0025] An execution program conversion unit is used to convert each layer in the directed acyclic graph into a program executable by the on-chip multi-core processor;

[0026] The verification processing unit is used to execute the program corresponding to each layer in the on-chip multi-core processor, and determine the storage consistency of the on-chip multi-core processor according to the execution result of the program corresponding to each layer.

[0027] Wherein, the directed acyclic graph generating unit further comprises:

[0028] An ordered stimulus random determination unit is used to randomly generate a cache line address for concurrent access by multiple CPU cores based on a randomly generated test memory access stimulus for a multi-core processor; randomly generate an event statistics counter variable; and randomly form a CPU core number group for accessing the cache line address, wherein the CPU core number group includes multiple CPU cores; randomly form the number of layers of a directed acyclic graph; each layer randomly forms a corresponding memory access operation, wherein the memory access operation is one of a read operation, a write operation, a read-modify-write operation or an atomic operation; and randomly form an exception information recording address of a directed acyclic graph;

[0029] The generating subunit is used to establish a directed acyclic graph according to the number of layers, the CPU cores involved in each layer and the corresponding memory access operations, and determine the initial standard value of the event statistics counter variable corresponding to each layer and the result standard value after execution is completed.

[0030] The execution program conversion unit is specifically used to convert each layer of the directed acyclic graph into a program executable by the CPU core using a program conversion tool or a script tool, and import the program into the on-chip multi-core processor.

[0031] Wherein, the verification processing unit further includes:

[0032] The counter variable detection unit is used to detect whether the current value of the event statistics counter variable is the same as the initial standard value of the event statistics counter variable of this layer when executing the program corresponding to each layer;

[0033] A program execution unit, configured to control at least one CPU core corresponding to the current layer to perform a memory access operation on the cache line address in a memory access mode corresponding to the current layer, and update the value of the event statistics counter variable when the counter variable detection unit detects that the two are the same;

[0034] An execution result detection unit is used to check whether the content in the cache line address after the memory access operation of this layer is completed is the same as the standard value of the result of this layer; if they are the same, the execution of the corresponding program of the lower layer is continued;

[0035] The exception handling unit is used to record the corresponding exception to the exception information recording address and end the current test if the detection result of the counter variable detection unit or the execution result detection unit is abnormal.

[0036] Wherein, the verification processing unit further includes:

[0037] The verification result determination unit is used to determine that the storage consistency of the on-chip multi-core processor meets the requirements if all programs corresponding to a predetermined number of directed acyclic graphs are successfully executed; and to determine that the storage consistency of the on-chip multi-core processor has defects if abnormal records are monitored.

[0038] Accordingly, the present invention also provides a computer-readable storage medium storing executable instructions, which implement the aforementioned method when the executable instructions are executed.

[0039] Correspondingly, the present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the aforementioned method when executing the computer program.

[0040] The implementation of the embodiments of the present invention has the following beneficial effects:

[0041] The present invention provides a storage consistency verification method, system, storage medium and device for a multi-core processor on a chip. By randomly generating a test memory access stimulus, the concept of order is determined when the stimulus is generated, so that the memory access operation is determined in terms of time and execution results. This stimulus is friendly to the correctness check and test efficiency of the test, and can significantly improve the efficiency.

[0042] At the same time, by using the method of the present invention, the correctness check of consistency does not need to adopt white box testing. At the same time, since the program execution result is determined when the stimulus is generated, there is no need to perform offline log analysis, and online real-time inspection can be achieved, and error exception information can be recorded in the memory to facilitate subsequent problem location, thereby greatly improving efficiency; and the stimulus generation method of the present invention adopts a directed acyclic graph, so no loop is generated, which ensures the correctness of the test stimulus, can eliminate the potential negative impact of invalid stimulus on other stimuli, and also greatly improves the test efficiency;

[0043] In addition, the present invention can provide a method for deterministic stimulus generation and online inspection of execution results, which can greatly improve the efficiency of problem locating and effectively avoid the problem that the stimulus continues to be submitted even though the exception has already occurred, thereby destroying the exception site. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying creative labor, other drawings obtained based on these drawings still belong to the scope of the present invention.

[0045] Figure 1A schematic diagram of the main process of an embodiment of a storage consistency verification method for an on-chip multi-core processor provided by the present invention;

[0046] Figure 2 A schematic diagram of a directed acyclic graph according to the present invention;

[0047] Figure 3 A schematic diagram of the structure of an embodiment of a storage consistency verification system for an on-chip multi-core processor provided by the present invention;

[0048] Figure 4 for Figure 3 A schematic diagram of the structure of a directed acyclic graph generation unit in;

[0049] Figure 5 for Figure 3 Schematic diagram of the structure of the verification processing unit. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0051] like Figure 1 FIG. 1 is a schematic diagram showing a main flow chart of an embodiment of a storage consistency verification method for a multi-core processor on a chip provided by the present invention. Figure 2 As shown, in this embodiment, the method at least includes the following steps:

[0052] Step S10, based on the randomly generated test memory access stimulus for the multi-core processor, at least one directed acyclic graph is obtained; in the directed acyclic graph, each vertex is a memory access operation of a CPU core in the on-chip multi-core processor on the cache line address, and the directed edge of the directed acyclic graph is a notification event after the memory access operation is completed, the starting point of the directed edge is the upstream vertex, and the end point of the directed edge is the downstream vertex; it can be understood that in an embodiment of the present invention, a set of stimuli of an ordered relationship is abstracted into a standard producer-consumer model, and a corresponding directed acyclic graph is generated according to the model.

[0053] More specifically, in one example, step S10 further includes:

[0054] Based on the randomly generated test memory access stimulus for the multi-core processor, a cache line address A for concurrent access by multiple CPU cores is randomly generated; an event statistics counter variable B is randomly generated; and a CPU core number group C for accessing the cache line address is randomly formed, and the CPU core number group includes multiple CPU cores; the number of layers D of a directed acyclic graph is randomly formed; each layer randomly forms a corresponding memory access operation, and the memory access operation is one of a read operation, a write operation, a read-modify-write operation or an atomic operation; an exception information recording address E of a directed acyclic graph is randomly formed;

[0055] According to the number of layers, the CPU cores involved in each layer and the corresponding memory access operations, a directed acyclic graph is established, and the initial standard value of the event statistics counter variable corresponding to each layer and the result standard value after execution are determined.

[0056] like Figure 2 As shown, an example of a directed acyclic graph generated in the present invention is shown. In this directed acyclic graph, there are six layers in total. The first layer involves the CPU0 core, and the memory access operation is a write operation; the second layer involves the CPU1 core, the CPU2 core and the CPU3 core, and the memory access operation is a read operation; the third layer involves the CPU1 core, and the memory access operation is a write operation; the fourth layer involves the CPU4 core, and the memory access operation is a RMW operation (i.e., a read-modify-write operation); the fifth layer involves the CPU5 core and the CPU6 core, and the memory access operation is an atomic operation (auomicadd); the sixth layer involves the CPU7 core, and the memory access operation is a read operation.

[0057] Step S11, converting each layer in the directed acyclic graph into a program executable by the on-chip multi-core processor;

[0058] More specifically, in one example, the step S11 further includes: using a program conversion tool or a script tool to convert each layer of the directed acyclic graph into a program executable by a CPU core, and importing the program into the on-chip multi-core processor.

[0059] Step S12, executing the program corresponding to each layer in the on-chip multi-core processor, and determining the storage consistency of the on-chip multi-core processor according to the execution result of the program corresponding to each layer.

[0060] More specifically, in one example, step S11 further includes:

[0061] When executing the program corresponding to each layer, check whether the current value of the event statistics counter variable B is the same as the initial standard value of the event statistics counter variable of this layer;

[0062] When the two are the same, control at least one CPU core corresponding to the current layer to perform a memory access operation on the cache line address in a memory access mode corresponding to the current layer, and update the value of the event statistics counter variable B;

[0063] Check whether the content of the cache line address after the memory access operation of this layer is completed is the same as the standard value of the result of this layer; if they are the same, continue to execute the corresponding program of the lower layer;

[0064] If the current value of the detection event statistics counter variable B is different from the initial standard value of the event statistics counter variable of this layer, or the content in the cache line address after the memory access operation of this layer is completed is different from the standard value of the result of this layer, the corresponding exception will be recorded to the exception information recording address E and the current test will be ended.

[0065] If the programs corresponding to the predetermined number of directed acyclic graphs are all executed successfully, it is determined that the storage consistency of the on-chip multi-core processor meets the requirements;

[0066] If the monitoring detects the presence of abnormal records, it is determined that there is a defect in the storage consistency of the on-chip multi-core processor.

[0067] It is understandable that during the verification operation, if it is monitored that the CPU core receives an abnormal interrupt, the location where the exception occurs can be obtained by checking the log or checking the log after the use case ends.

[0068] For ease of understanding, the following combination Figure 2 The example of the directed acyclic graph in step S12 is explained as follows:

[0069] The first layer is fixed to vertex 0 of the directed acyclic graph. CPU0 is randomly selected from CPU core number group C to perform a write operation on the address. After CPU0 completes the execution, the data at address A is DATA0. Event statistics counter variable B is updated to 1 through atomic add.

[0070] At the second level, if the randomly generated action is a read action, multiple CPU cores can be randomly selected from CPU core number group C. The above figure shows a read action, which randomly generates multiple vertices 1 / 2 / 3 of a directed acyclic graph. When vertex 1 / 2 / 3 checks that event statistics counter variable B is 1, it starts a read operation on address A and can obtain DATA0 in the correct address A. After each core completes execution, it updates event statistics counter variable B to 2 / 3 / 4 through atomic add.

[0071] At the third level, if the randomly generated action is a write operation, only one CPU core can be randomly selected from the CPU core number group C. When vertex 4 checks that the event statistics counter variable B is 4, it starts writing to address A. The data at address A is DATA1. The event statistics counter variable B is updated to 5 through atomic add.

[0072] At the fourth layer, if the randomly generated action is an RMW operation, only one CPU core can be randomly selected from the CPU core number group C. When vertex 5 checks that the event statistics counter variable B is 5, it starts the RMW operation on address A, obtains the data DATA1, and the modified data is DATA2. The event statistics counter variable B is updated to 6 through atomic add.

[0073] At the fifth layer, if the randomly generated action is an atomic operation, multiple CPU cores can be randomly selected from the CPU core number group C. When vertex 6 / 7 checks that the event statistics counter variable B is 6, it starts the atomic add operation on address A, and the acquired data is DATA2 / DATA2+1. The modified data is DATA2+1 / DATA2+2. The event statistics counter variable B is updated to 7 / 8 through atomic add.

[0074] The sixth layer is the last layer. A CPU core is randomly selected from the CPU core number group C. When vertex 8 checks that the event statistics counter variable B is 8, it starts the read operation on address A and can obtain the correct address A's DATA2+2.

[0075] It can be understood that each abstract step in the above-mentioned directed acyclic graph can eventually be converted into a standard program through a program conversion device (or script) of the present invention, which can be run on an on-chip multi-core processor. Through a large number of random directed acyclic graphs, it can eventually be converted into an operating program for each CPU core. Multiple CPU cores can run concurrently, and there are various consistent accesses to the same address. At the same time, since the execution results of each layer are deterministic, the CPU core of each layer can check the data correctness by itself. If there is an exception, it will be recorded at address E, and the exception interrupt will be sent to the main control core (which can be a CPU core independent of the CPU core number group C). The main control core will end the test in time to avoid damaging the abnormal scene.

[0076] like Figure 3 FIG. 1 is a schematic diagram showing the main flow of a storage consistency verification system for a multi-core processor on a chip provided by the present invention. Figure 4 and Figure 5 As shown, in this embodiment, the system 1 at least includes:

[0077] A directed acyclic graph generating unit 10 is used to obtain at least one directed acyclic graph based on a randomly generated test memory access stimulus for a multi-core processor; in the directed acyclic graph, each vertex is a memory access operation of a CPU core in the on-chip multi-core processor on a cache line address, and a directed edge of the directed acyclic graph is a notification event after the memory access operation is completed, and the starting point of the directed edge is an upstream vertex, and the end point of the directed edge is a downstream vertex;

[0078] An execution program conversion unit 11 is used to convert each layer in the directed acyclic graph into a program executable by the on-chip multi-core processor; wherein the execution program conversion unit 11 is specifically used to convert each layer of the directed acyclic graph into a program executable by the CPU core using a program conversion tool or a script tool, and import it into the on-chip multi-core processor;

[0079] The verification processing unit 12 is used to execute the program corresponding to each layer in the on-chip multi-core processor, and determine the storage consistency of the on-chip multi-core processor according to the execution result of the program corresponding to each layer.

[0080] like Figure 4 As shown, the directed acyclic graph generation unit 10 further includes:

[0081] The ordered stimulus random determination unit 100 is used to randomly generate a cache line address A for concurrent access by multiple CPU cores based on a randomly generated test memory access stimulus for a multi-core processor; randomly generate an event statistics counter variable B; and randomly form a CPU core number group C for accessing the cache line address, wherein the CPU core number group includes multiple CPU cores; randomly form the number of layers D of a directed acyclic graph; each layer randomly forms a corresponding memory access operation, wherein the memory access operation is one of a read operation, a write operation, a read-modify-write operation or an atomic operation; and randomly form an exception information recording address E of a directed acyclic graph;

[0082] The generating subunit 101 is used to establish a directed acyclic graph according to the number of layers, the CPU cores involved in each layer and the corresponding memory access operations, and determine the initial standard value of the event statistics counter variable corresponding to each layer and the result standard value after execution.

[0083] like Figure 4 As shown, the verification processing unit 12 further includes:

[0084] The counter variable detection unit 120 is used to detect whether the current value of the event statistics counter variable B is the same as the initial standard value of the event statistics counter variable of this layer when executing the program corresponding to each layer;

[0085] The program execution unit 121 is used to control at least one CPU core corresponding to the current layer to perform a memory access operation on the cache line address in a memory access mode corresponding to the current layer, and update the value of the event statistics counter variable B when the counter variable detection unit detects that the two are the same;

[0086] The execution result detection unit 122 is used to check whether the content in the cache line address after the memory access operation of the current layer is completed is the same as the result standard value of the current layer; if they are the same, the execution of the corresponding program of the lower layer is continued;

[0087] The exception handling unit 123 is used for recording the corresponding exception to the exception information recording address E and ending the current test if the detection result of the counter variable detection unit or the execution result detection unit is abnormal;

[0088] The verification result determination unit 124 is used to determine that the storage consistency of the on-chip multi-core processor meets the requirements if all programs corresponding to a predetermined number of directed acyclic graphs are successfully executed; if abnormal records are monitored, it is determined that the storage consistency of the on-chip multi-core processor has defects.

[0089] For more details, please refer to and combine the above Figure 1 to Figure 2 The description is not repeated here.

[0090] Accordingly, the present invention also provides a computer-readable storage medium storing executable instructions, which, when executed, implement the above-mentioned Figure 1 and Figure 2 For more details, please refer to and combine the above Figure 1 to Figure 2 The description is not repeated here.

[0091] Accordingly, the present invention further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the above-mentioned Figure 1 and Figure 2 For more details, please refer to and combine the above Figure 1 to Figure 2 The description is not repeated here.

[0092] The implementation of the embodiments of the present invention has the following beneficial effects:

[0093] The present invention provides a storage consistency verification method, system, storage medium and device for a multi-core processor on a chip. By randomly generating a test memory access stimulus, the concept of order is determined when the stimulus is generated, so that the memory access operation is determined in terms of time and execution results. This stimulus is friendly to the correctness check and test efficiency of the test, and can significantly improve the efficiency.

[0094] At the same time, by using the method of the present invention, the correctness check of consistency does not need to adopt white box testing. At the same time, since the program execution result is determined when the stimulus is generated, there is no need to perform offline log analysis, and online real-time inspection can be achieved, and error exception information can be recorded in the memory to facilitate subsequent problem location, thereby greatly improving efficiency; and the stimulus generation method of the present invention adopts a directed acyclic graph, so no loop is generated, which ensures the correctness of the test stimulus, can eliminate the potential negative impact of invalid stimulus on other stimuli, and also greatly improves the test efficiency;

[0095] In addition, the present invention can provide a method for deterministic stimulus generation and online inspection of execution results, which can greatly improve the efficiency of problem locating and effectively avoid the problem that the stimulus continues to be submitted even though the exception has already occurred, thereby destroying the exception site.

[0096] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0097] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0098] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A storage consistency verification method for a multi-core processor on a chip, characterized in that: At least the following steps are included: Based on the randomly generated test memory access stimulus for the multi-core processor, at least one directed acyclic graph is obtained; in the directed acyclic graph, each vertex is a memory access operation of a CPU core in the on-chip multi-core processor on a cache line address, and the directed edge of the directed acyclic graph is a notification event after the memory access operation is completed, and the starting point of the directed edge is the upstream vertex, and the end point of the directed edge is the downstream vertex; Convert each layer in the directed acyclic graph into a program executable by the on-chip multi-core processor; The program corresponding to each layer is executed in the on-chip multi-core processor, and the storage consistency of the on-chip multi-core processor is determined according to the execution result of the program corresponding to each layer.

2. The method according to claim 1, characterized in that The step of obtaining at least one directed acyclic graph based on the randomly generated test memory access stimulus for the multi-core processor further includes: Based on the randomly generated test memory access stimulus for the multi-core processor, a cache line address for concurrent access by multiple CPU cores is randomly generated; an event statistics counter variable is randomly generated; and a CPU core number group for accessing the cache line address is randomly formed, and the CPU core number group includes multiple CPU cores; the number of layers of a directed acyclic graph is randomly formed; each layer randomly forms a corresponding memory access operation, and the memory access operation is one of a read operation, a write operation, a read-modify-write operation or an atomic operation; an exception information recording address of a directed acyclic graph is randomly formed; According to the number of layers, the CPU cores involved in each layer and the corresponding memory access operations, a directed acyclic graph is established, and the initial standard value of the event statistics counter variable corresponding to each layer and the result standard value after execution are determined.

3. The method according to claim 2, characterized in that The step of converting each layer in the directed acyclic graph into a program executable by the on-chip multi-core processor further includes: A program conversion tool or a script tool is used to convert each layer of the directed acyclic graph into a program executable by a CPU core, and the program is imported into the on-chip multi-core processor.

4. The method according to claim 2 or 3, characterized in that The step of executing the program corresponding to each layer in the on-chip multi-core processor and determining the storage consistency of the on-chip multi-core processor according to the execution result of the program corresponding to each layer comprises: When executing the program corresponding to each layer, check whether the current value of the event statistics counter variable is the same as the initial standard value of the event statistics counter variable of this layer; When the two are the same, control at least one CPU core corresponding to the current layer to perform a memory access operation on the cache line address in a memory access mode corresponding to the current layer, and update the value of the event statistics counter variable; Check whether the content of the cache line address after the memory access operation of this layer is completed is the same as the standard value of the result of this layer; if they are the same, continue to execute the corresponding program of the lower layer; If it is detected that the current value of the event statistics counter variable is different from the initial standard value of this layer, or it is detected that the content in the cache line address after the memory access operation of this layer is completed is different from the standard value of the result of this layer, the corresponding exception will be recorded to the exception information recording address and the current test will be terminated.

5. The method according to claim 4, characterized in that Further including: If the programs corresponding to the predetermined number of directed acyclic graphs are all executed successfully, it is determined that the storage consistency of the on-chip multi-core processor meets the requirements; If the monitoring detects the presence of abnormal records, it is determined that there is a defect in the storage consistency of the on-chip multi-core processor.

6. A storage consistency verification system for a multi-core processor on a chip, characterized in that: At least the following steps are included: A directed acyclic graph generation unit is used to obtain at least one directed acyclic graph based on a randomly generated test memory access stimulus for a multi-core processor; in the directed acyclic graph, each vertex is a memory access operation of a CPU core in the on-chip multi-core processor on a cache line address, and a directed edge of the directed acyclic graph is a notification event after the memory access operation is completed, and the starting point of the directed edge is an upstream vertex, and the end point of the directed edge is a downstream vertex; An execution program conversion unit is used to convert each layer in the directed acyclic graph into a program executable by the on-chip multi-core processor; The verification processing unit is used to execute the program corresponding to each layer in the on-chip multi-core processor, and determine the storage consistency of the on-chip multi-core processor according to the execution result of the program corresponding to each layer.

7. The system according to claim 6, characterized in that The directed acyclic graph generating unit further comprises: An ordered stimulus random determination unit is used to randomly generate a cache line address for concurrent access by multiple CPU cores based on a randomly generated test memory access stimulus for a multi-core processor; randomly generate an event statistics counter variable; and randomly form a CPU core number group for accessing the cache line address, wherein the CPU core number group includes multiple CPU cores; randomly form the number of layers of a directed acyclic graph; each layer randomly forms a corresponding memory access operation, wherein the memory access operation is one of a read operation, a write operation, a read-modify-write operation or an atomic operation; and randomly form an exception information recording address of a directed acyclic graph; The generating subunit is used to establish a directed acyclic graph according to the number of layers, the CPU cores involved in each layer and the corresponding memory access operations, and determine the initial standard value of the event statistics counter variable corresponding to each layer and the result standard value after execution is completed.

8. The system according to claim 7, characterized in that The execution program conversion unit is specifically used to convert each layer of the directed acyclic graph into a program executable by the CPU core by using a program conversion tool or a script tool, and import the program into the on-chip multi-core processor.

9. The system according to claim 7 or 8, characterized in that The verification processing unit further comprises: The counter variable detection unit is used to detect whether the current value of the event statistics counter variable is the same as the initial standard value of the event statistics counter variable of this layer when executing the program corresponding to each layer; A program execution unit, configured to control at least one CPU core corresponding to the current layer to perform a memory access operation on the cache line address in a memory access mode corresponding to the current layer, and update the value of the event statistics counter variable when the counter variable detection unit detects that the two are the same; An execution result detection unit is used to check whether the content in the cache line address after the memory access operation of this layer is completed is the same as the standard value of the result of this layer; if they are the same, the execution of the corresponding program of the lower layer is continued; The exception handling unit is used to record the corresponding exception to the exception information recording address and end the current test if the detection result of the counter variable detection unit or the execution result detection unit is abnormal.

10. The system according to claim 9, characterized in that The verification processing unit further comprises: The verification result determination unit is used to determine that the storage consistency of the on-chip multi-core processor meets the requirements if all programs corresponding to a predetermined number of directed acyclic graphs are successfully executed; and to determine that the storage consistency of the on-chip multi-core processor has defects if abnormal records are monitored.

11. A computer-readable storage medium storing executable instructions, characterized in that: When the executable instructions are executed, the method according to any one of claims 1 to 5 is implemented.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

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