Data handling method, DMA resource controller, SOC system and terminal equipment

Abstract

The invention discloses a data handling method, a DMA resource controller, an SOC system and a terminal device, and belongs to the technical field of chips, the data handling method is characterized by comprising the following steps: determining a data handling mode of current to-be-handled data according to a data transmission type of the current to-be-handled data in a first memory; the first memory is used for storing data to be conveyed, the second memory is used for storing data to be conveyed, the current data to be conveyed is conveyed to the second memory on the basis of a data conveying mode, and one of the first memory and the second memory is a DMA (direct memory access) module. Data transmission of all types of source data and result data can be realized by using the data handling mode provided by the invention.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and more specifically to a data transport method, a DMA resource controller, a SOC system and a terminal device. Background Art

[0002] Data transmission is essential in the entire DSP chip operation. In the prior art, a DMA controller is usually used for data transmission. For example, the Chinese invention patent with the authorization announcement number CN110399322A provides a data transmission method and a ping-pong DMA architecture, which uses two DMA modules to configure data. When the first DMA module is busy, the second DMA module can also configure the data and perform data operations corresponding to different state types according to different state types of the register. However, the above patent uses two DMA modules, which increases resource consumption.

[0003] In addition, the DMA module in the prior art usually includes multiple sets of DMA_Ports, each set of DMA_Ports is suitable for different transport modes, but the increase in the number of DMA_Ports will also increase resource consumption, so the prior art has shortcomings. Summary of the invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a data transfer method, a DMA resource controller, a SOC system and a terminal device. The present invention proposes a variety of data transfer modes according to the type of data to be transferred and the characteristics of the algorithm, so that all types of source data and result data can use the data transfer mode provided by the present invention to realize data transmission, thereby reducing resource consumption.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides a data transport method, comprising:

[0007] Determining a data transfer mode of the data to be transferred currently in the first memory according to a data transfer type of the data to be transferred currently in the first memory;

[0008] The data to be currently transferred is transferred to a second memory based on the data transfer mode, wherein one of the first memory and the second memory is a DMA module.

[0009] As a further improvement of the present invention, the data transmission type includes one-dimensional data transmission or two-dimensional data transmission, and determining the data transfer mode of the data to be transferred currently in the first memory according to the data transmission type of the data to be transferred currently includes:

[0010] If the data transmission type is one-dimensional data transmission, determining that the data transport mode is a sequential transport mode;

[0011] If the data transmission type is two-dimensional data transmission, the data transport mode is determined to be one of matrix column transport or matrix transposition transport according to a data processing algorithm of the current data to be transported.

[0012] As a further improvement of the present invention, the data transmission type includes one-dimensional data transmission and two-dimensional data transmission, and correspondingly, the data processing algorithm of the current data to be transported is a fast Fourier transform algorithm, and the data transmission mode of the current data to be transported is determined according to the data transmission type of the current data to be transported in the first memory, including:

[0013] If the data to be transported is small point data, determining that the data transport mode is a sequential transport mode;

[0014] If the current data to be transported is large point data, the data transport mode is determined to be a two-dimensional column transport mode and a two-dimensional row transport mode in sequence.

[0015] As a further improvement of the present invention, if the data transfer mode is a sequential transfer mode, transferring the current data to be transferred to the second memory based on the data transfer mode includes:

[0016] Reading data before the set bit in the current data to be transferred as a data unit to be transferred;

[0017] Writing the data unit to be transferred into the storage circular queue;

[0018] The current data to be transferred is updated to the data after removing the data unit to be transferred, and the step of reading the data before the set bit in the current data to be transferred is repeated to obtain the data unit to be transferred again, and the data unit to be transferred is written into the storage circular queue until the current data to be transferred is all written into the second memory.

[0019] As a further improvement of the present invention, if the data transport mode is matrix column transport, and the current data to be transported is a two-dimensional data matrix, the method of transporting the current data to be transported to the second memory based on the data transport mode includes:

[0020] Reading the first row of data that is currently not read in the two-dimensional data matrix;

[0021] Write the currently read row data into the storage queue in column order;

[0022] The two-dimensional data matrix is ​​updated to a matrix after the row data is removed from the two-dimensional data matrix, and the step of reading the first row of row data that is not currently read in the two-dimensional data matrix is ​​repeated, and the row data currently read is written into the storage queue in column order until all the data to be transferred are written into the second memory.

[0023] As a further improvement of the present invention, if the data transport mode is matrix transposition transport, and the current data to be transported is a two-dimensional data matrix, the method of transporting the current data to be transported to the second memory based on the data transport mode includes:

[0024] Divide the current data to be transferred into a plurality of matrix units according to a preset number of rows, with the first row as the starting row, wherein the number of rows of the last matrix unit is less than or equal to the preset number of rows, and the number of rows of the remaining matrix units is equal to the preset number of rows;

[0025] For the matrix units whose number of rows is equal to the preset number of rows, column transport is performed;

[0026] For matrix units whose number of rows is less than the preset number of rows, the length of data carried in each carry beat is reduced, the data length of each write beat of the second memory is synchronously configured, and a corresponding label register is created for the data carried in each carry beat; wherein, if the carry data corresponding to each carry beat is valid through the mask judgment, the number of the corresponding label register is updated.

[0027] As a further improvement of the present invention, the column transfer for the matrix unit whose number of rows is equal to the preset number of rows includes:

[0028] If the total number of rows of the data to be transferred is an odd number, for each two adjacent columns of data, the last data bit of the odd column data and the first data bit of the next corresponding even column data are written into the second memory at the same write beat.

[0029] As a further improvement of the present invention, if the data transfer mode is a sequential transfer mode, transferring the current data to be transferred to the second memory based on the data transfer mode includes:

[0030] The current data to be transferred is sequentially transferred to the second memory based on the same index-address conversion rule as that of the butterfly memory access controller.

[0031] As a further improvement of the present invention, the data transport mode is to sequentially perform a two-dimensional column transport mode and a two-dimensional row transport mode, and the method of transporting the current data to be transported to the second memory based on the data transport mode includes:

[0032] The current data to be transported is transported according to the two-dimensional column transport mode, and after Fourier transform operation is performed, fast Fourier transform intermediate result data is obtained;

[0033] The fast Fourier transform intermediate result data is transferred to the second memory according to the two-dimensional row transfer mode.

[0034] As a further improvement of the present invention, the transferring of the current data to be transferred to the second memory based on the data transfer mode further includes:

[0035] If the data length of the current data to be transferred is not an integer power of 2, the current data to be transferred is padded with zeros to the data length closest to the integer power of 2.

[0036] The present invention provides a DMA resource controller, which is applied to the above data transfer method, including:

[0037] A DMA module, the DMA module comprising a status register;

[0038] A logic control module, used for controlling the jump of a state machine, wherein the state machine is composed of the state register and a combinational logic circuit;

[0039] A data configuration module, used for configuring the DMA module;

[0040] DMA_Port, used for data transmission between the first memory and the second memory.

[0041] As a further improvement of the present invention, the DMA module includes:

[0042] A DMA register unit, used for maintaining a DMA register, wherein the DMA register includes a control register, a configuration register and the status register;

[0043] DMA read and write control unit, used to control the signals of AXI4's read address channel, read data channel, write data channel, write address channel, and write response channel;

[0044] A DMA cache unit, used for caching data read into the DMA module and processed;

[0045] The DMA matrix control unit is used to generate relevant read and write information of two-dimensional transmission and matrix transposition transmission, and send the relevant read and write information to the DMA read and write control module.

[0046] The present invention provides a SOC system, comprising the above-mentioned DMA resource controller.

[0047] The present invention provides a terminal device, comprising the above-mentioned SOC system.

[0048] The present invention proposes a variety of data transfer modes according to the type of data to be transferred and the characteristics of the algorithm, and implements the above transfer modes through a set of DMA_Port, so that the source data and result data of all algorithms can be transmitted by selecting the above transfer modes, avoiding the disadvantage that some algorithms have similar transmission methods but use multiple sets of DMA_Port logic, and reducing resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a schematic diagram of the matrix full column moving mode;

[0050] Figure 2 This is a schematic diagram of the matrix transpose move-in mode;

[0051] Figure 3 This is a schematic diagram of the 16-BANK sequential loading (horizontal) mode;

[0052] Figure 4 This is a schematic diagram of the 32BANK sequential loading (horizontal) mode;

[0053] Figure 5 This is a schematic diagram of the 16-BANK sequential removal (horizontal) mode;

[0054] Figure 6 This is a schematic diagram of the 32BANK sequential removal (horizontal) mode;

[0055] Figure 7 This is a schematic diagram of the FFT small point sequential moving mode;

[0056] Figure 8 This is a schematic diagram of the data collection rules for moving the FFT large points sequentially into the middle column;

[0057] Fig. 9 This is a schematic diagram of the data retrieval rules for FFT large points to be moved into the Bank of China in sequence;

[0058] Fig.10 Design block diagram for DMA resource controller;

[0059] Fig.11 This is the architecture diagram of the DMA module;

[0060] Fig.12 It is the working flow chart of DMA resource controller;

[0061] Fig.13 It is the state jump diagram of the main state machine in the DMA resource controller;

[0062] Fig.14 This is the state jump diagram of the slave state machine in the DMA resource controller. DETAILED DESCRIPTION

[0063] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations of the technical solution of the present invention.

[0064] The term "and / or" in the following text is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0065] The present application provides a data transfer method, including:

[0066] Determining a data transfer mode for the data to be transferred currently according to a data transfer type of the data to be transferred currently in the first memory;

[0067] The data to be currently transferred is transferred to the second memory based on the data transfer mode, wherein one of the first memory and the second memory is a DMA module.

[0068] Specifically, when the data transfer mode is the move-in mode, the first memory is a DMA module and the second memory is an SRAM (static RAM); when the data transfer mode is the move-out mode, the first memory is an SRAM and the second memory is a DMA module.

[0069] The data transfer method provided in this embodiment can accurately determine the data transfer mode according to the data transmission type of the current data to be transferred, thereby improving data transmission efficiency.

[0070] Furthermore, the data transmission type includes one-dimensional data transmission or two-dimensional data transmission.

[0071] If the data transmission type is one-dimensional data transmission, determining that the data transport mode is a sequential transport mode;

[0072] If the data transmission type is two-dimensional data transmission, the data transmission mode is determined to be one of matrix column transmission or matrix transposition transmission according to the data processing algorithm of the current data to be transmitted.

[0073] Furthermore, if the data transfer mode is a sequential transfer mode, the step of transferring the current data to be transferred to the second storage device based on the data transfer mode includes:

[0074] Read the data before the set bit in the current data to be transferred as the data unit to be transferred;

[0075] Write the data unit to be transferred into the storage circular queue;

[0076] The current data to be transferred is updated to the data after the data unit to be transferred is removed, and the step of reading the data before the set bit in the current data to be transferred is repeated to obtain the data unit to be transferred again, and the data unit to be transferred is written into the storage circular queue until all the current data to be transferred is written into the second memory.

[0077] Furthermore, if the data transfer mode is matrix column transfer, and the current data to be transferred is a two-dimensional data matrix, the step of transferring the current data to be transferred to the second memory based on the data transfer mode includes:

[0078] Read the first row of data that is not currently read in the two-dimensional data matrix;

[0079] Write the currently read row data into the storage queue in column order;

[0080] The two-dimensional data matrix is ​​updated to a matrix after the row data is removed from the two-dimensional data matrix, and the step of reading the first row of row data that is not currently read in the two-dimensional data matrix is ​​repeated, and the currently read row data is written into the storage queue in column order until all the data to be transferred is written into the second memory.

[0081] The setting bit is preferably 256 bits, and the storage circular queue is a continuous queue, which can maximize the use of storage space. For example, when the total number of BANKs is 16, data needs to be stored in each BANK in the order of BANK0-BANK16. Only after the data is stored in BANK16, can the data be stored in sequence from BANK0. Different from this, the storage queue does not need to store data in each BANK. For example, when the total number of BANKs is 16, after the currently read row data is written to the storage queue in column order, all BANKs cannot be stored, and some BANKs are still idle. However, when the next write step is performed, data still needs to be stored in sequence starting from BANK0, and there is no need to store it in the idle BANK in the previous step.

[0082] Further, if the data transport mode is matrix transposition transport, and the current data to be transported is a two-dimensional data matrix, the current data to be transported is transported to the second memory based on the data transport mode, including:

[0083] The current data to be transferred is divided into multiple matrix units according to the preset number of rows, with the first row as the starting row, wherein the number of rows of the last matrix unit is less than or equal to the preset number of rows, and the number of rows of the remaining matrix units is equal to the preset number of rows;

[0084] For the matrix cells whose number of rows is equal to the preset number of rows, column transfer is performed;

[0085] For matrix units whose number of rows is less than the preset number of rows, the length of data carried by each carry beat is reduced, the data length of each write beat of the second memory is synchronously configured, and a corresponding label register is created for the data carried by each carry beat; wherein, if the carry data corresponding to each carry beat is valid through the mask judgment, the number of the corresponding label register is updated.

[0086] Exemplarily, when the two-dimensional data matrix has 255 rows and the preset number of rows is 128 rows, the first matrix unit has 128 rows and the second matrix unit has 127 rows. When the first matrix unit is transported, the length of the data transported by each transport beat is 4 64 bits. When the second matrix unit is transported, since the number of rows of the second matrix unit is less than the preset number of rows, the length of the data transported by each transport beat is reduced to 1 64 bit. The transport data corresponding to each transport beat needs to be judged by the mask whether it is valid. If it is valid, the value of the label corresponding to the register number is increased by one, that is, the data transported by the next transport beat is stored in the next register. For example, if the data transported by the current beat is valid and stored in register a, the label value of register a is 1, then the data transported by the next beat is stored in register b when it is valid, and the label value of register b is 2.

[0087] Furthermore, for the matrix units whose number of rows is equal to the preset number of rows, column transfer is performed, including:

[0088] If the total number of rows of data to be transferred is an odd number, for each of two adjacent columns of data, the last data bit of the odd column data and the first data bit of the next corresponding even column data are placed in the same write cycle and written into the second memory.

[0089] The transfer beat is for the first memory, which means moving data out of the first memory, and the write beat is for the second memory, which means moving data moved out of the first memory into the second memory.

[0090] Further, the data transmission type includes one-dimensional data transmission and two-dimensional data transmission. Correspondingly, the data processing algorithm of the current data to be transported is a fast Fourier transform algorithm. According to the data transmission type of the current data to be transported in the first memory, the data transport mode of the current data to be transported is determined, including:

[0091] If the data to be transported is small point data, the data transport mode is determined to be a sequential transport mode;

[0092] If the data to be transported is large point data, the data transport mode is determined to be a two-dimensional column transport mode and a two-dimensional row transport mode in sequence.

[0093] Further, if the data transfer mode is a sequential transfer mode, transferring the current data to be transferred to the second memory based on the data transfer mode includes:

[0094] The current data to be transferred is sequentially transferred to the second memory based on the same index-address conversion rule as the butterfly memory access controller.

[0095] And if the data length of the current data to be transported is not an integer power of 2, the current data to be transported is padded with zeros to the data length closest to the integer power of 2, and then transported.

[0096] Further, if the data transport mode is to sequentially perform a two-dimensional column transport mode and a two-dimensional row transport mode, the current data to be transported is transported to the second memory based on the data transport mode, including:

[0097] The current data to be transported is transported according to the two-dimensional column transport mode, and after Fourier transform operation, the fast Fourier transform intermediate result data is obtained;

[0098] The fast Fourier transform intermediate result data is transferred to the second memory in a two-dimensional row transfer mode.

[0099] It can be seen from the above analysis that this embodiment designs a variety of data transfer modes according to the type of data to be transferred and the processing algorithm. The above transfer modes are introduced in turn with examples below.

[0100] Fine-grained transport mode:

[0101] Fine-grained transport modes include matrix column transport mode, matrix transposition transport mode, sequential transport mode, and sequential transport mode.

[0102] Matrix column transport mode:

[0103] The matrix column transport mode is used for source data transport that requires matrix and other related algorithms. This mode supports the writing of source data with a total of 16 banks and ping-pong split, such as Figure 1 As shown in the figure, when the DMA module reads the source data in two dimensions, it reads and writes 256 bits each time, and each 256-bit data is split into four 64-bit data. Every two numbers form 128 bits and write one bank, that is, bank16 stores the 1st and 2nd columns of the 1st row, bank17 stores the 3rd and 4th columns of data, and so on. Bank23 stores the 15th and 16th columns of data, and the 1st and 2nd columns of the 2nd row are continuously stored in bank16, arranged horizontally in sequence. If the number of columns S is less than 16, the 1st and 2nd columns of the 2nd row are still stored starting from bank16, instead of being continuously stored after the Sth data of the 1st row.

[0104] Matrix transpose import mode:

[0105] The matrix transposition mode is used when the number of matrix data columns in matrix multiplication is less than 16. Due to the small number of columns, the degree of parallelism is low. In order to improve the degree of parallelism, vector multiplication is used to implement matrix multiplication. During the implementation process, the retrieved data needs to be placed in SRAM by column. At this time, SRAM is the second memory, so the DMA module uses transposition transport. Figure 2 As shown in the figure, when a small matrix with 128 rows is moved, the DMA module moves the small matrix by column, each time moving 256 bits of data (i.e., 4 64-bit complex numbers), and sets four registers to store the labels of the four data storage locations. The 16th bit corresponds to the bank where the data should be stored, and the remaining bits correspond to the address where the data should be stored. The data is written into the SRAM through the label change. The following situations are subdivided in this moving process:

[0106] (1) When transferring a small matrix with 128 rows, the DMA module transfers the small matrix by column, transferring 256 bits of data each time (i.e., four 64-bit complex numbers), and sets four registers to store the labels of the four data storage locations. The lower 16 bits correspond to the bank where the data should be stored, and the remaining bits correspond to the address where the data should be stored. The data is written into the SRAM through the label change. The following situations are subdivided in this transfer process:

[0107] Ⅰ: The total number of rows is an odd number:

[0108] In order to increase the speed, the DMA module moves in 4 64-bit data per beat, and the transposition port writes 4 64-bit data to SRAM per beat. Since two of the data sent in one beat need to be written into the same BANK, the 128-bit write mode of the BANK is used. However, when the number of rows is an odd number, the last row of the first column of the last move and the first row of the second column of the first move are data that should be written into the same BANK together in the 128-bit write mode. Similarly, the 128th row of the second column of the first move and the 129th row of the second column of the second move should also be written together. Therefore, when the total number of rows is an odd number, it is divided into two cases:

[0109] a: When DMA moves odd-numbered columns of data, there is no situation where different data are moved at the same time and written into the BANK together. 128-bit data is written into two BANKs in one shot.

[0110] b: When the DMA module moves data in even columns, there are cases where different data are moved at the same time and need to be written into the BANK together. Set up 8 64-bit registers to store the 8 data of the last row of even columns of the previous move, select data according to the column counter and insert it into the current move data (insert 0 for the first move), and write 128-bit data to 3 BANKs in one shot.

[0111] Ⅱ: The total number of rows is an even number:

[0112] There is no special case of odd numbers, and normally 128-bit data is written to two banks in one beat.

[0113] (2) When moving a small matrix that does not have 128 rows at the end, since the DMA module may send invalid data (marked by a mask), a method of writing 64-bit data in one beat is used. By controlling the ack signal to the DMA module, the DMA module transmits a 256-bit data every four beats, and the SRAM write mode is changed to 64-bit write. The four beats process four 64-bit data respectively. If the 64-bit data corresponding to the beat is judged valid by the mask, the set label write enable is pulled high, and the label will be increased by 1. If the data is judged invalid, the label remains unchanged. The label is used to select the bank and address where the data of the beat should be written.

[0114] Sequential handling mode:

[0115] The sequential transport mode includes a sequential move-in mode and a sequential move-out mode. The sequential move-in mode includes a 16-BANK move-in mode and a 32-BANK move-in mode. The sequential move-out mode includes a 16-BANK move-out mode and a 32-BANK move-out mode.

[0116] 16BANK move-in mode:

[0117] The 16BANK import mode is used for the transfer of source data that requires matrix, vector, sorting and other related algorithms. It supports the writing of source data or coefficients with a total of 16 banks and ping-pong split. Figure 3 As shown in the figure, when the source data or coefficients are read sequentially, 256 bits are read and written each time. If the read data is a complex number, each 256-bit data is split into four 64-bit data; if the read data is a real number, each 256-bit data is split into eight 32-bit data. The split data are stored in each bank in turn. Bank0 stores the first and second data, and Bank1 stores the third and fourth data. After 16 data are stored in 8 banks in a table area, the 17th data is stored below the second data in Bank0, and so on.

[0118] 32BANK move-in mode:

[0119] The 32BANK import mode is used for the transfer of source data that requires FIR, correlation and other related algorithms, and supports the writing of source data with a total of 32 banks and ping-pong split. Figure 4As shown, when the source data is read sequentially, 256 bits are read and written each time. If the read data is a complex number, each 256-bit data is split into four 64-bit data; if the read data is a real number, each 256-bit data is split into eight 32-bit data. The split data are stored in each Bank in turn. Bank0 stores the first and second data, and Bank1 stores the third and fourth data. After 32 data are stored in 16 banks in a table area, the 33rd data is stored below the second data in Bank0, and so on.

[0120] 16BANK move-out mode:

[0121] The 16BANK move-out mode is used to move out the result data of matrix, vector, FIR, correlation, sorting and other related algorithms, and supports the move-out of result data with a total number of 16 banks and ping-pong split. Figure 5 As shown, the result data is stored horizontally in the Bank, that is, the result data 0-7 are stored serially at address 0 of 8 Banks, and then the result data 8-15 are stored at address 1 of 8 Banks.

[0122] 32BANK move-out mode:

[0123] The 32BANK export mode is used to export the result data of matrix, Doppler and other related algorithms, and supports the export of result data with a total number of 32 banks and ping-pong split. Figure 6 As shown, the result area is stored horizontally in the Bank, that is, the result data 0-15 are stored serially at address 0 of 16 Banks, and the result data 16-31 are stored at address 1 of 16 Banks.

[0124] Coarse-grained transport mode:

[0125] The coarse-grained transport mode includes an FFT transport-in mode and an FFT transport-out mode. The FFT transport-in mode includes an FFT small point sequential transport-in mode and an FFT large point two-dimensional transport-in mode. The FFT large point two-dimensional transport-in mode includes row transport and column transport.

[0126] FFT small points sequentially move in mode:

[0127] In the case of FFT small points being moved in sequentially, such as Figure 7As shown, the source data is stored sequentially in DDR (Double Data Rate SDRAM, double-rate synchronous dynamic random access memory). When the DMA module reads the source data, the AXI bus is 256 bits, and the DMA_Port writes every 256 bits of data into 4 BANKs in one clock cycle. The source data ping area is BANK0-BANK31. The DMA_Port receives the 256-bit data transmitted sequentially from the DMA module, and fills the input source data that is not an integer power of 2 with zeros as close as possible to an integer power of 2. If it is a case of multiple batches of data, after all the source data are transmitted, the batches are filled with zeros to the nearest integer power of 2. After the zero-filling process, the DMA_Port completes the transmission of 256 bits, i.e., 4 source data, in every 1 clock cycle. The address rule transmitted to the SRAM space is the same index-address conversion rule as the butterfly memory access controller. The source data pong area is BANK32-BANK63. DMA_Port receives the ping-pong signal transmitted from the DMA module. According to the ping-pong signal, the data transmission is jumped to the source data pong area. The data transmission method is exactly the same as that of the source data pong area.

[0128] FFT large point 2D import mode:

[0129] In the two-dimensional transfer of large points in FFT, SRAM cannot cache all the data at once, and a two-dimensional FFT algorithm must be used. At this time, the transmission mode of the DMA module is two-dimensional transmission. In this case, the working state of DMA_Port is similar to simultaneously transferring data of multiple small-point FFTs, and the DMA module performs column transfer and row transfer of two-dimensional FFT in sequence.

[0130] like Figure 8 As shown, taking 512k points as an example, in the column transport stage, the data of 512k points is abstractly divided into a two-dimensional matrix with 4k rows and 128 columns. Since the maximum storage capacity of the ping-pong area is 128k, the large matrix will be divided into 4 small matrices every 32 columns; in the row transport, since the arrangement order of the abstract matrix is ​​the same as the actual DDR address, the DMA module only needs to perform sequential transmission. When carrying out column transport, the DMA module will start the two-dimensional transmission mode and carry out the transport in sequence according to the rows and columns of the divided small matrix. For example, when transmitting the first 4k*32 matrix, the source data of addresses 0-31 are transmitted sequentially, and then jump to the 128th address to transmit the second row of the small matrix. After completing the transmission of the first small matrix, send a ping-pong signal to the butterfly DMA_Port, and then jump to address 32 to start the transmission of the second small matrix, repeat 4 times until all 512k source data are transmitted.

[0131] And in the column transfer phase, DMA_Port transfers 128K data each time, repeats 4 times, and stores it into SRAM as 128 4K-length input sequences; in the row transfer phase, it also transfers 128K data each time, repeats 4 times, but stores it into SRAM as 4k 128-length input sequences.

[0132] FFT small point sequential removal mode:

[0133] In the FFT small point sequential movement, the result data is stored in SRAM. DMA_Port first generates the index in reverse order, and then fetches the data from the corresponding SRAM address according to the index-address conversion rule. DMA_Port fetches 4 64-bit result data per clock cycle and merges every 4 data into 256-bit output.

[0134] FFT large point sequential output mode:

[0135] In the FFT large point two-dimensional output, for the two-dimensional FFT operation, the output of DMA_Port includes the transmission of the column transformation results and the transmission of the row transformation results (final results).

[0136] When processing the result of column transformation, DMA_Port sorts the data in the ping / pong area in batches, then generates indexes in reverse order, and moves them out according to the index-address conversion rules, and repeats multiple times according to the number of large points. The DMA module receives the data and transfers it back to DDR using sequential transmission.

[0137] When processing the row transformation result (final result), DMA_Port first sorts the data in the ping / pong area in batches, then reverses the order, and then generates an index after transposition, and moves it out according to the index-address conversion rule. This is repeated multiple times according to the number of large points. The DMA module receives the data and transfers it back to DDR using sequential transmission.

[0138] This embodiment combines algorithms with similar memory access methods into four modes at a fine granularity. The data transfer function of the fine-grained algorithm required by the protocol can be realized by combining and configuring the four modes. Due to the uniqueness of the in-situ memory access of the FFT algorithm, it requires two transmission modes: sequential transmission and two-dimensional transmission. Both its source data and result data must be guaranteed to be accessed in-situ, and it cannot share the mode with other algorithms. Therefore, the FFT move-in mode and FFT sequential move-out mode are designed for it at a coarse granularity. The source data and result data of all algorithms only need to use the above modes to realize data transmission, which saves resource consumption to the greatest extent.

[0139] like Fig.10 As shown, the embodiment of the present application further provides a DMA resource controller, which is applied to the above data transfer method, including:

[0140] DMA module, the DMA module includes a status register;

[0141] The logic control module is used to control the jump of the state machine, which is composed of a state register and a combinational logic circuit;

[0142] Data configuration module, used to configure DMA module;

[0143] DMA_Port, used for data transmission between the first memory and the second memory.

[0144] In the three-dimensional reconfigurable acceleration core architecture, one of the first memory and the second memory is a DMA module, and the other is an SRAM.

[0145] Among them, DMA_Port supports all the above data handling modes when performing data transmission, avoiding the disadvantage that some algorithms have similar transmission methods but use multiple sets of DMA_Port logic.

[0146] Specifically, Fig.11 As shown, the DMA module also includes:

[0147] A DMA register unit, used for maintaining DMA registers, which include control registers, configuration registers and status registers;

[0148] DMA read and write control unit, including DMA read control unit and DMA write control unit, wherein DMA read control unit is responsible for controlling each signal of AXI4 read address channel and read data channel, DMA read control unit includes read control main module, read address generation module and data input module, main module plays the main control role, read address generation module is responsible for generating relevant address generation of write internal buffer, data input module is responsible for address alignment of input data, data splicing and splitting, etc., DMA write control unit function and structure are similar to DMA read control module, except that it corresponds to write data channel, write address channel and write response channel of AXI4;

[0149] DMA cache unit, including 8 groups of 4kB SRAM, is used to cache the data read into the DMA module and processed, and then read out by the write control module. ;

[0150] The DMA matrix control unit is used to generate relevant read and write information of two-dimensional transmission and matrix transposition transmission, and send the relevant read and write information to the DMA read and write control module.

[0151] Further, the DMA module provided in this embodiment is dedicated to the three-dimensional reconfigurable acceleration core architecture, supports the AXI4 protocol, and is mounted on the AXI bus as the only host in the core, and only interacts with the only slave DDR for data transmission between DDR and SRAM. Therefore, the DMA module only needs one channel, and all cross-clocks are completed by SOC (System on Chip, system-level chip), so there is no need to perform cross-clock domain processing. According to the transmission performance requirements of the three-dimensional reconfigurable acceleration core, it only needs to support the burst transmission mode, and since the data bit width is 256bit, the maximum burst length is 128. Due to the large loopback delay, this DMA module supports a maximum of 16 unfinished operations based on the internal cache size.

[0152] Among them, the three-dimensional reconfigurable acceleration core architecture adopts a static instruction flow control data flow mechanism to schedule internal operations (instruction level), and relies on the CPU to statically implement different configurations (thread level) based on the SSD (static scheduling, static data flow) model. This architecture decouples storage and computing, and is a multi-dimensional reconfigurable technology that realizes spatial dimensions, temporal dimensions, and resource dimensions.

[0153] The DMA module provided in this embodiment adds a DMA matrix control unit, and on the basis of supporting sequential transmission, additionally supports chain transmission, two-dimensional transmission and transposed transmission, thereby improving the transmission and processing efficiency of matrix data.

[0154] Furthermore, the data transfer steps of the DMA resource manager provided in this embodiment are as follows: Fig.12 As shown, the configuration information is first input into the DMA resource manager, and then the logic control module determines the data area and executes the corresponding handling steps according to the determination result.

[0155] Specifically, if the judgment result is source data, the data configuration module obtains a single configuration of the DMA module, and writes the configuration of the DMA module into the register group inside the DMA module through the APB bus, starts the DMA module, and then the DMA module takes data from the DDR and transmits it to the DMA_Port. The DMA_Port completes the placement of the data in the SRAM, completes a single transfer of the source data, and then determines whether the data needs to be transferred again. If necessary, the logic control module continues to determine the data area. If not, the transfer is stopped.

[0156] If the judgment result is result data, the data configuration module obtains the single configuration of the DMA module, and writes the configuration of the DMA module into the register group inside the DMA module through the APB bus, starts the DMA module, and then the DMA module sends a data access request to the DMA_Port to move the data back to the DDR. The DMA_Port accesses the data from the SRAM and supplies it to the DMA module, completing a single transfer of the result data. After that, it is determined whether the data needs to be transferred again. If necessary, the logic control module continues to determine the data area. If not, the transfer is stopped.

[0157] Among them, the configuration modes of the DMA module include master mode and slave mode. In slave mode, the DMA resource manager obtains configuration information by polling the relevant information in the configuration register; in master mode, the DMA resource controller moves the configuration information in the DDR to the configuration register as the configuration information for subsequent use, and calculates according to the relevant information such as the starting address and data length in the configuration information to obtain a single configuration of the DMA.

[0158] Furthermore, when the DMA resource controller performs different working steps, the state machine of the DMA resource controller will enter different states, wherein the state machine includes a master state machine and a slave state machine.

[0159] like Fig.13 As shown, the states of the main state machine can be divided into:

[0160] Idle state (DMA_IDLE): The master state machine is initially in the idle state. When the master state machine is started, the state machine enters the state of preparing to transfer configuration information (DMA_MASTER_READY).

[0161] DMA_MASTER_READY: The DMA resource controller determines the master-slave mode. If it is the master mode, the master state machine starts the configuration information transfer and enters the configuration information transfer state (DMA_MASTER); if it is the slave mode, the master state machine enters the ready state (DMA_READY).

[0162] DMA_MASTER: When a single transfer of configuration information is completed, the master state machine enters the transfer configuration information completion state (DMA_MASTER_FINISH).

[0163] DMA_MASTER_FINISH: If the configuration information still needs to be transferred, the master state machine enters the state of preparing to transfer the configuration information (DMA_MASTER_READY); if the configuration information does not need to be transferred, the master state machine enters the ready state (DMA_READY).

[0164] DMA_READY: When the DMA module is ready to be started for transferring source data, the main state machine enters the preparation state (DMA_SRC1_READY) for transferring the first source data (SRC1).

[0165] DMA_SRC1_READY: The DMA resource controller determines whether SRC1 currently needs to be moved. When SRC1 needs to be moved, the main state machine enters the SRC1 moving state (DMA_SRC1); when SRC1 does not need to be moved, it enters the second source data (SRC2) moving preparation state (DMA_SRC2_READY).

[0166] DMA_SRC1: When the single transfer SRC1 is completed, the main state machine enters the transfer SRC1 completion state (DMA_SRC1_FINISH).

[0167] DMA_SRC1_FINISH: The main state machine enters the SRC2 ready state (DMA_SRC2_READY).

[0168] DMA_SRC2_READY: The DMA resource controller determines whether SRC2 currently needs to be transferred. When SRC2 needs to be transferred, it enters the transfer SRC2 state (DMA_SRC2); when SRC2 does not need to be transferred, it enters the transfer result data (RES) preparation state (DMA_RES_READY).

[0169] DMA_SRC2: When the single transfer SRC2 is completed, the main state machine enters the transfer SRC2 completion state (DMA_SRC2_FINISH).

[0170] DMA_SRC2_FINISH: The main state machine enters the transfer RES ready state (DMA_RES_READY).

[0171] DMA_RES_READY: DMA resource controller determines whether RES needs to be transported currently. When RES needs to be transported and RES transport is not skipped, it enters the transport RES state (DMA_TRANS_RES); when the algorithm type RES does not need to be transported, it enters the transport RES completion state (DMA_RES_FINISH); when RES transport needs to be skipped, it enters the transport SRC1 ready state (DMA_SRC1_READY);

[0172] DMA_TRANS_RES: When the single transfer RES is completed, the main state machine enters the transfer RES completion state (DMA_RES_FINISH).

[0173] DMA_RES_FINISH: If the current mode is slave mode and the slave mode ends, the master state machine enters the idle state (DMA_IDLE); if the master mode or slave mode has not ended and the next ping-pong is required, it enters the transfer SRC1 ready state (DMA_SRC1_READY); if the current mode is master mode and the master mode is completed in one go, and the next transfer is still required, it enters the idle state (DMA_IDLE) and waits for the state machine to start next time.

[0174] When the master state machine enters any of the DMA_MASTER, DMA_SRC1, DMA_SRC2, and DMA_RES transfer states, the slave state machine, also called the data transfer state machine, is triggered. Fig.14 As shown, taking the DMA_MASTER state as an example, the data transfer state machine is described as follows.

[0175] DMA_TRANS_IDLE: The data transfer state machine starts in the idle state. When the configuration data in the configuration register is configured, it enters the configuration calculation state (DMA_CONFIG_CAL).

[0176] DMA_CONFIG_CAL: The data handling state machine is in the configuration calculation state, which is used to calculate a single DMA configuration. When the configuration calculation is completed, it enters the configuration state (DMA_CONFIG).

[0177] DMA_CONFIG: In this state, the DMA controller performs a single DMA transfer configuration on the DMA through the APB bus, and enters the DMA transfer state (DMA_TRANSING) after the configuration is completed.

[0178] DMA_TRANSING: In this state, DMA performs single-configuration data transfer. After the single-configuration transfer is completed, the data transfer state machine enters the transfer completion state (DMA_TRANS_FINISH).

[0179] DMA_TRANS_FINISH: The DMA transfer state machine is in the single transfer completion state, and then returns to the idle state (DMA_TRANS_IDLE) and waits for the next startup.

[0180] From the above description, it can be seen that the DMA resource controller provided in this embodiment supports both master and slave modes to configure the DMA module, and the state machine in the DMA resource controller can match the transport state jump according to the transport requirements of different algorithms to improve the transport efficiency.

[0181] Furthermore, an embodiment of the present application provides a SOC system, including the above-mentioned DMA resource controller.

[0182] Furthermore, an embodiment of the present application provides a terminal device, including the above-mentioned SOC system.

[0183] The embodiments of the present application provide a data transfer method, a DMA resource controller, a SOC system and a terminal device, which adopt the method of summarizing the DMA_Port of each algorithm and designing four fine-grained transfer modes and two coarse-grained transfer modes designed for the FFT algorithm. While saving resource overhead, it improves resource utilization, supports the configuration of the DMA module in both master and slave modes, and matches the jump of the state machine transfer state according to the transfer requirements of different algorithms.

[0184] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0185] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0186] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0187] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0188] The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A data transport method, characterized in that: include: Determining a data transfer mode of the data to be transferred currently in the first memory according to a data transfer type of the data to be transferred currently in the first memory; The data to be currently transferred is transferred to a second memory based on the data transfer mode, wherein one of the first memory and the second memory is a DMA module.

2. A data transport method according to claim 1, characterized in that: The data transmission type includes one-dimensional data transmission or two-dimensional data transmission, and determining the data transfer mode of the data to be transferred currently in the first memory according to the data transmission type of the data to be transferred currently includes: If the data transmission type is one-dimensional data transmission, determining that the data transport mode is a sequential transport mode; If the data transmission type is two-dimensional data transmission, the data transport mode is determined to be one of matrix column transport or matrix transposition transport according to a data processing algorithm of the current data to be transported.

3. A data transport method according to claim 1, characterized in that: The data transmission type includes one-dimensional data transmission and two-dimensional data transmission. Correspondingly, the data processing algorithm of the current data to be transported is a fast Fourier transform algorithm. The data transmission mode of the current data to be transported is determined according to the data transmission type of the current data to be transported in the first memory, including: If the data to be transported is small point data, determining that the data transport mode is a sequential transport mode; If the current data to be transported is large point data, the data transport mode is determined to be a two-dimensional column transport mode and a two-dimensional row transport mode in sequence.

4. A data transport method according to claim 2, characterized in that: If the data transfer mode is a sequential transfer mode, transferring the current data to be transferred to the second memory based on the data transfer mode includes: Reading data before the set bit in the current data to be transferred as a data unit to be transferred; Writing the data unit to be transferred into the storage circular queue; The current data to be transferred is updated to the data after removing the data unit to be transferred, and the step of reading the data before the set bit in the current data to be transferred is repeated to obtain the data unit to be transferred again, and the data unit to be transferred is written into the storage circular queue until the current data to be transferred is all written into the second memory.

5. A data transport method according to claim 2, characterized in that: If the data transport mode is matrix column transport, and the current data to be transported is a two-dimensional data matrix, transporting the current data to be transported to the second memory based on the data transport mode includes: Reading the first row of data that is currently not read in the two-dimensional data matrix; Write the currently read row data into the storage queue in column order; The two-dimensional data matrix is ​​updated to a matrix after the row data is removed from the two-dimensional data matrix, and the step of reading the first row of row data that is not currently read in the two-dimensional data matrix is ​​repeated, and the row data currently read is written into the storage queue in column order until all the data to be transferred are written into the second memory.

6. A data transport method according to claim 2, characterized in that: If the data transport mode is matrix transposition transport, and the current data to be transported is a two-dimensional data matrix, transporting the current data to be transported to the second memory based on the data transport mode includes: Divide the current data to be transferred into a plurality of matrix units according to a preset number of rows, with the first row as the starting row, wherein the number of rows of the last matrix unit is less than or equal to the preset number of rows, and the number of rows of the remaining matrix units is equal to the preset number of rows; For the matrix units whose number of rows is equal to the preset number of rows, column transport is performed; For matrix units whose number of rows is less than the preset number of rows, the length of data carried by each carry beat is reduced, the data length of each write beat of the second memory is synchronously configured, and a corresponding label register is created for the data carried by each carry beat; wherein, if the carry data corresponding to each carry beat is valid through the mask judgment, the number of the corresponding label register is updated.

7. A data transport method according to claim 6, characterized in that: The column transport is performed for the matrix units whose number of rows is equal to the preset number of rows, including: If the total number of rows of the data to be transferred is an odd number, for each two adjacent columns of data, the last data bit of the odd column data and the first data bit of the next corresponding even column data are written into the second memory at the same write beat.

8. A data transport method according to claim 3, characterized in that: If the data transfer mode is a sequential transfer mode, transferring the current data to be transferred to the second memory based on the data transfer mode includes: The current data to be transferred is sequentially transferred to the second memory based on the same index-address conversion rule as that of the butterfly memory access controller.

9. A data transport method according to claim 3, characterized in that: The data transport mode is to sequentially perform a two-dimensional column transport mode and a two-dimensional row transport mode, and the currently to-be-transferred data is transported to the second memory based on the data transport mode, including: The current data to be transported is transported according to the two-dimensional column transport mode, and after Fourier transform operation is performed, fast Fourier transform intermediate result data is obtained; The fast Fourier transform intermediate result data is transferred to the second memory according to the two-dimensional row transfer mode.

10. A data transport method according to claim 8, characterized in that: The method of transferring the current data to be transferred to the second memory based on the data transfer mode further includes: If the data length of the current data to be transferred is not an integer power of 2, the current data to be transferred is padded with zeros to the data length closest to the integer power of 2.

11. A DMA resource controller, applied to a data transfer method according to any one of claims 1 to 9, characterized in that: The DMA resource controller comprises: A DMA module, the DMA module comprising a status register; A logic control module, used for controlling the jump of a state machine, wherein the state machine is composed of the state register and a combinational logic circuit; A data configuration module, used for configuring the DMA module; DMA_Port, used for data transmission between the first memory and the second memory.

12. A DMA resource controller according to claim 11, characterized in that: The DMA module includes: A DMA register unit, used for maintaining a DMA register, wherein the DMA register includes a control register, a configuration register and the status register; DMA read and write control unit, used to control the signals of AXI4's read address channel, read data channel, write data channel, write address channel, and write response channel; A DMA cache unit, used for caching data read into the DMA module and processed; The DMA matrix control unit is used to generate relevant read and write information of two-dimensional transmission and matrix transposition transmission, and send the relevant read and write information to the DMA read and write control module.

13. A SOC system, characterized in that: The SOC system includes a DMA resource controller as described in any one of claims 11-12.

14. A terminal device, characterized in that: The terminal device includes the SOC system as claimed in claim 13.

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