System for reading external chip based on SPI (Serial Peripheral Interface)

Abstract

The invention relates to the technical field of electronics, in particular to a system for reading an external chip based on an SPI (Serial Peripheral Interface), which comprises a parameter configuration module, an external clock input module, an external parameter input module and an SPI signal generation module which are integrated on an FPGA (Field Programmable Gate Array), wherein the parameter configuration module, the external clock input module and the external parameter input module determine the state of a signal line in the SPI signal generation module according to the state of an external chip and the address of to-be-read data in the external chip, further read the to-be-read data from the external chip and transmit the to-be-read data to other external data receiving modules; according to the SPI signal generation module, the receiving and transmitting sequence of high and low levels on each signal line in the SPI signal generation module is flexibly customized, the SPI signal generation module adapts to different address bit widths and receives different data bit widths, and the SPI parameter reading requirements of different external chips can be more widely met.

Description

Technical Field

[0001] The invention belongs to the technical field of electronics, and in particular relates to a system for reading external chips based on SPI. Background Art

[0002] At present, the parameters of image sensors are usually read by SMBus (System Management Bus), SPI (Serial Peripheral Interface) or Uart (Universal Asynchronous Receiver / Transmitter). Among them, the SPI method is widely used. However, the parameter reading method based on the SPI method is usually implemented by the function module provided by the manufacturer inside the core chip. The SPI format signal has four signals, namely the SPI input data signal line (Serial Data Input, SDI), the SPI output data signal line (Serial D-ata Output, SDO), the SPI chip select signal line (Serial Chip Enable, SCE) and the SPI clock signal line (Serial Clock, SCK). The high and low levels of the four signals are used to realize the overall SPI configuration waveform output, thereby realizing the data communication and other functions of the external chip. At present, the traditional methods are based on chips such as DSP, ARM or SoC, and the chip manufacturers provide SPI data reading functions through tape-out or function. Summary of the invention

[0003] In view of this, the invention aims to provide a system for reading external chips based on SPI, which flexibly customizes the high and low levels of each signal line in the SPI signal generation module through the parameter configuration module, external clock input module and external parameter input module integrated on the FPGA, so as to flexibly adjust the data transmission and reception order, adapt to different address bit widths and receive different data bit widths, and can be more widely applicable to the SPI parameter reading requirements of different external chips.

[0004] To achieve the above object, the technical solution created by the present invention is implemented as follows: A system for reading an external chip based on SPI, including: Parameter configuration module, determines the frequency division coefficient, read address width and data return width; The external clock input module outputs the clock count according to the read address width, frequency division coefficient and the external clock from the external chip; An external parameter input module receives a read enable signal and a read address from an external chip, and outputs an address value of data to be read in the external chip according to a read address width; The SPI signal generation module receives and determines the state of the signal line in the SPI signal generation module according to the output of the parameter configuration module, the external clock input module and the external parameter input module, and then reads the data to be read from the external chip and passes the data to be read to other external data receiving modules.

[0005] Furthermore, the parameter configuration module re-divides the frequency of the external clock to obtain a frequency division coefficient, where the frequency division coefficient is a common divisor of the frequency of the external clock.

[0006] Furthermore, in the parameter configuration module, the read address width is determined by the following formula: R=2 W -1; Wherein, W represents the read address width, and R represents the address range of the data to be read in the external chip; The data return width is determined by the following formula: R'=2 W’ -1; Wherein, W' represents the data return width, and R' represents the range of the data to be read.

[0007] Furthermore, in the external clock input module, the continuous clock cycle of the output address in the SPI signal generation module is determined according to the read address width and the division coefficient, and the number of cycles of the continuous clock cycle is the rising edge count of the external clock, and the rising edge count is the clock count; the read address width determines the target value of the rising edge count.

[0008] Furthermore, the SPI signal generation module includes an idle state S0, an SCE transition state S1, a send address state S2, a receive data state S3 and a termination state S4, and the SPI signal generation module includes a signal line SDO, a signal line SDI, a signal line SCE and a signal line SCK.

[0009] Further, when the SPI signal generation module is in the idle state S0, after the SPI signal generation module waits for and receives a read enable signal, the SPI signal generation module enters the SCE transition state S1.

[0010] Further, when the SPI signal generation module is in the SCE transition state S1, the signal line SCE becomes a low level, and then the SPI signal generation module enters the address sending state S2.

[0011] Furthermore, when the SPI signal generation module is in the address sending state S2, the address value is converted into binary data, and the signal line SDO sends the binary address value to the external chip one by one according to the clock count; when the signal line SDO completes the data output, the SPI signal generation module then enters the data receiving state S3.

[0012] Furthermore, when the SPI signal generation module is in the data receiving state S3, the SPI signal generation module collects the level on the signal line SDI at the corresponding moment according to the clock count, and the collected low level is marked as 0, and the high level is 1, and the data is combined into binary code according to the collection order; when the bit width of the collected binary code is equal to the data return width, after collecting the binary code with sufficient data bit width, the SPI signal generation module packages the collected binary code and enters the termination state S4.

[0013] Furthermore, when the SPI signal generation module is in the termination state S4, the packaged data is sent to other external data receiving modules, and the signal line SCE becomes a high level output again. At this time, the SPI signal generation module returns to the S0 state and waits for the next read enable signal.

[0014] Compared with the prior art, the invention can achieve the following beneficial effects: In the system based on SPI reading of external chips created by the present invention, based on external clock input, the rising edge of the external clock is counted through the external clock input module, and the corresponding output binary data waveform is generated according to the parameterized address and data bit width, so as to complete the data transmission; the high and low levels on each signal line in the SPI signal generation module are flexibly customized in cooperation with the external parameter input module, so as to flexibly adjust the data transmission and reception sequence, adapt to different address bit widths and receive different data bit widths, and can be more widely applicable to the SPI parameter reading requirements of different external chips, so as to realize a highly flexible and highly customizable chip reading strategy, which can be generally applicable to various peripheral chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings: Figure 1 A schematic diagram of the structure of a system for reading an external chip based on SPI according to an embodiment of the present invention; Figure 2 A schematic diagram of the state transition of the SPI signal generation module described in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0018] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0019] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0020] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0021] like Figure 1 to Figure 2As shown, the system based on SPI reading external chip described in the embodiment of the invention includes a parameter configuration module, an external clock input module, an external parameter input module and an SPI signal generation module integrated on the FPGA. Among them, the parameter configuration module determines the frequency division coefficient, the read address width and the data return width; the external clock input module outputs the clock count according to the read address width, the frequency division coefficient and the external clock from the external chip; the external parameter input module receives the read enable signal and the read address from the external chip, and outputs the address value of the data to be read in the external chip according to the read address width; the SPI signal generation module receives and determines the state of the signal line in the SPI signal generation module according to the output of the parameter configuration module, the external clock input module and the external parameter input module, and then reads the data to be read from the external chip, and passes the data to be read to other external data receiving modules. In the implementation of the present invention, the system based on SPI reading external chip is implemented on the FPGA by the Verilog hardware description language.

[0022] In the parameter configuration module, the frequency of the external clock is re-divided to obtain a frequency division coefficient, which is a common divisor of the frequency of the external clock. The purpose of frequency division in the embodiment of the present invention is to reduce the SPI clock. Since the external input is a high-frequency clock, if it is driven by a high-frequency clock, it will lead to problems such as increased system energy consumption and excessive count values. Therefore, the high-speed clock must be reduced to a low-speed clock through frequency division. The low-speed clock has a low frequency and a long jump interval, which can effectively reduce system power consumption and reduce count values, and can ensure a more stable operation of the system. Since different external chips have different read address widths and data return widths, and the read address of each external chip is determined by the product manual of the external chip, it is necessary to adaptively configure the read address width and data return width in combination with the address range of the read data of the external chip and the range of the data to be read in the parameter configuration module, that is: The read address width is determined by the following formula: R=2 W -1; Wherein, W represents the read address width, and R represents the address range of the data to be read in the external chip. For example, if the address range of the data to be read in the external chip is R=255, then through 2 8 -1=255 can get the corresponding read address width W as 8; The data return width is determined by the following formula: R'=2 W’ -1; Where W' represents the data return width, and R' represents the range of the data to be read. For example, if the range of the data to be read R'=255, then 2 8 -1=255 can get the corresponding data return width W' as 8.

[0023] In the external clock input module, the continuous clock cycle of the output address in the SPI signal generation module is determined according to the read address width and the division coefficient. The number of cycles of the continuous clock cycle is the rising edge count of the external clock. When a certain count value is reached, the high and low levels will change. The rising edge count is the clock count. The read address width determines the target value of the rising edge count, that is, the read address width is to determine the target value of the count. After determining the value found, the next step will be started.

[0024] The SPI signal generation module realizes state transition through the rising edge and condition of the external clock. Specifically, in the SPI signal generation module, it includes an idle state S0, an SCE jump state S1, a send address state S2, a receive data state S3 and a termination state S4, and the SPI signal generation module includes a signal line SDO, a signal line SDI, a signal line SCE and a signal line SCK.

[0025] First, the SPI signal generation module will be initialized. At this time, the signal line SDO is at a low level, the signal line SDI is in a high-impedance state, and the signal line SCE and the signal line SCK are both at a high level.

[0026] When the SPI signal generation module is in the idle state S0, the SPI signal generation module waits for a read enable signal transmitted by the external parameter input module. After the SPI signal generation module receives the read enable signal, the SPI signal generation module enters the SCE jump state S1.

[0027] When the SPI signal generation module is in the SCE transition state S1, the signal line SCE becomes a low level, and then the SPI signal generation module enters the address sending state S2.

[0028] When the SPI signal generation module is in the address sending state S2, the address value is converted into binary data, and the signal line SDO sends the binary address value to the external chip one by one according to the clock count, that is, the binary address value is sent one by one in order from low to high. When the data is 0, a low level is sent, and when the data is 1, a high level is sent; when the signal line SDO completes data output, the SPI signal generation module enters the data receiving state S3.

[0029] When the SPI signal generation module is in the data receiving state S3, the SPI signal generation module collects the level on the signal line SDI at the corresponding moment according to the clock count, and the collected low level is marked as 0, and the high level is 1, and the data is combined into binary code according to the collection order; when the bit width of the collected binary code is equal to the data return width, after collecting binary codes with sufficient data bit width, the SPI signal generation module packages the collected binary codes and enters the termination state S4.

[0030] When the SPI signal generation module is in the termination state S4, the packaged data is sent to other external data receiving modules, and the signal line SCE becomes a high level output again. At this time, the SPI signal generation module returns to the S0 state and waits for the next read enable signal. At this point, the system based on SPI reading external chips described in the embodiment of the present invention completes the reading and transmission of data.

[0031] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A system for reading external chips based on SPI, characterized in that: Includes integrated on the FPGA: Parameter configuration module, determines the frequency division coefficient, read address width and data return width; An external clock input module outputs a clock count according to the read address width, the frequency division coefficient and an external clock from an external chip; An external parameter input module receives a read enable signal and a read address from the external chip, and outputs an address value of data to be read in the external chip according to the read address width; The SPI signal generation module receives and determines the state of the signal line in the SPI signal generation module according to the outputs of the parameter configuration module, the external clock input module and the external parameter input module, and then reads the data to be read from the external chip and passes the data to be read to other external data receiving modules.

2. The system for reading external chips based on SPI according to claim 1, characterized in that: The parameter configuration module re-divides the frequency of the external clock to obtain the frequency division coefficient, where the frequency division coefficient is a common divisor of the frequency of the external clock.

3. The system for reading external chips based on SPI according to claim 1, characterized in that: In the parameter configuration module, the read address width is determined by the following formula: R=2 W -1； Wherein, W represents the read address width, and R represents the address range of the data to be read in the external chip; The data return width is determined by the following formula: R’=2 W’ -1； Wherein W' represents the data return width, and R' represents the range of the data to be read.

4. The system for reading external chips based on SPI according to claim 1, characterized in that: In the external clock input module, the continuous clock cycle of the output address in the SPI signal generation module is determined according to the read address width and the frequency division coefficient, the number of cycles of the continuous clock cycle is the rising edge count of the external clock, and the rising edge count is the clock count; the read address width determines the target value of the rising edge count.

5. The system for reading external chips based on SPI according to claim 1, characterized in that: The SPI signal generation module includes an idle state S0, an SCE jump state S1, a send address state S2, a receive data state S3 and a termination state S4, and the SPI signal generation module includes a signal line SDO, a signal line SDI, a signal line SCE and a signal line SCK.

6. The system for reading external chips based on SPI according to claim 5, characterized in that: When the SPI signal generating module is in the idle state S0, after the SPI signal generating module waits for and receives the read enable signal, the SPI signal generating module enters the SCE jump state S1.

7. The system for reading external chips based on SPI according to claim 5, characterized in that: When the SPI signal generating module is in the SCE transition state S1, the signal line SCE becomes a low level, and then the SPI signal generating module enters the sending address state S2.

8. The system for reading external chips based on SPI according to claim 7, characterized in that: When the SPI signal generating module is in the sending address state S2, the address value is converted into binary data, and the signal line SDO sends the binary address value to the external chip one by one according to the clock count; when the signal line SDO completes data output, the SPI signal generating module then enters the receiving data state S3.

9. The system for reading external chips based on SPI according to claim 8, characterized in that: When the SPI signal generating module is in the data receiving state S3, the SPI signal generating module collects the level on the signal line SDI at the corresponding moment according to the clock count, and if a low level is collected, it is marked as 0, and if a high level is collected, it is marked as 1, and the data is combined into binary code according to the collection order; when the bit width of the collected binary code is equal to the data return width, after collecting binary codes with sufficient data bit width, the SPI signal generating module packages the collected binary codes and enters the termination state S4.

10. The system for reading external chips based on SPI according to claim 9, characterized in that: When the SPI signal generating module is in the termination state S4, the packaged data is sent to other external data receiving modules, and the signal line SCE becomes a high level output again. At this time, the SPI signal generating module returns to the S0 state and waits for the next read enable signal.

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