Cache consistency verification method, related multi-core processor, storage medium and device
By reading the data of the target core and bus Cache in the verification use case of multi-core processors and performing cache consistency verification based on these data, the problem of incomplete and accurate verification in the prior art is solved, and the accuracy of verification is improved.
Patent Information
- Application Number
- CN202411490931.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-02-14
AI Technical Summary
When verifying the consistency of multi-core processor Cache, the prior art cannot fully and accurately reveal the specific situation of Cache data changes, which can easily lead to missed judgments or misjudgments.
By obtaining and executing verification use cases for multi-core processors, data in all caches of the target core and cache of the bus at a specific moment are read, and cache consistency is verified based on the first data and the second data, and multiple verification conditions are met. Determine cache consistency.
Improves the accuracy of Cache consistency verification, allowing a more comprehensive understanding of data changes in Cache when performing verification use cases, reducing the possibility of missed or misjudgment.
Smart Images
Figure CN119441117A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a cache consistency verification method, a related multi-core processor, a storage medium and a device. Background Art
[0002] In a processor with multiple cores, when multiple cores access shared memory simultaneously, it is necessary to ensure that the data obtained by each core is consistent to avoid calculation errors caused by inconsistent data.
[0003] At present, in order to verify the cache consistency, the commonly used method is to directly compare whether the target data read or written by each core after executing the verification case is consistent, and then determine whether the multi-core processor meets the expected consistency standard. In addition, the cache hit rate and miss rate can be calculated based on the event counts of the caches at all levels of each core recorded by the Performance Monitoring Unit (PMU), thereby obtaining information about the cache usage efficiency.
[0004] However, the target data can only indirectly reflect the consistency state of the cache, and cannot directly reveal the specific changes in the data in the cache when executing the verification case. Since the cache consistency protocol itself is relatively complex, the read and write strategies (such as replacement strategy or write-back / write-through strategy, etc.) adopted are different, and the execution process of specific verification cases is also different. Simply relying on the final target data or statistical information to verify the cache consistency is often not comprehensive and accurate, and it is easy to cause missed judgments or misjudgments. Summary of the invention
[0005] In response to the deficiencies in the prior art, the present application provides a cache consistency verification method, a related multi-core processor, a storage medium and a device. By verifying the cache consistency based on first data and second data, the first data and the second data are the data actually stored in all caches of the corresponding target core and the cache of the bus. The specific circumstances of the data changes in the cache when executing the verification use case can be known, thereby improving the accuracy of the verification.
[0006] To solve the above problems, the present invention provides the following technical solutions:
[0007] In a first aspect, an embodiment of the present application provides a cache consistency verification method, including:
[0008] Acquire and execute verification use cases of a multi-core processor; when executing the verification use cases, read first data in all caches of a first target core of the multi-core processor and caches of a bus at a first verification moment; when executing the verification use cases, read second data in all caches of a second target core of the multi-core processor and caches of a bus at a second verification moment; and verify cache consistency based on the first data and the second data.
[0009] In some embodiments, the cache consistency verification based on the first data and the second data includes: when the target data in the first data and the second data are consistent, determining that the multi-core processor satisfies the first verification condition of the cache consistency verification; when it is determined based on the data identification bits in the first data and the second data that the first data and the second data satisfy a preset cache consistency protocol, determining that the multi-core processor satisfies the second verification condition of the cache consistency verification; when the multi-core processor satisfies the first verification condition and the second verification condition, determining that the multi-core processor passes the cache consistency verification.
[0010] In some embodiments, the method further includes: when executing the verification use case, obtaining the data flow of the target port on the bus; when it is determined that the execution process of the verification use case is the same as the preset execution process based on the first data, the second data and the data flow of the target port, determining that the multi-core processor satisfies the third verification condition of the cache consistency verification; when the multi-core processor satisfies the first verification condition and the second verification condition, determining that the multi-core processor passes the cache consistency verification, including: when the multi-core processor satisfies the first verification condition, the second verification condition and the third verification condition, determining that the multi-core processor passes the cache consistency verification.
[0011] In some embodiments, the method further includes: reading first monitoring data in a performance monitoring module of the first target core and second monitoring data in a performance monitoring module of the second target core, wherein the first monitoring data includes event counts of each level of Cache of the first target core, and the second monitoring data includes event counts of each level of Cache of the second target core; calculating a first hit rate of the first level Cache of the first target core according to the event counts of the first level Cache of the first target core in the first monitoring data; calculating a second hit rate of the first level Cache of the second target core according to the event counts of the first level Cache of the second target core in the second monitoring data; when the first hit rate and the second hit rate are both greater than a first preset value, determining that the multi-core processor satisfies a fourth verification condition for verifying the cache consistency; when the multi-core processor satisfies the first verification condition, the second verification condition, and the third verification condition, determining that the multi-core processor passes the cache consistency verification, including: when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, and the fourth verification condition, determining that the multi-core processor passes the cache consistency verification.
[0012] In some embodiments, the method further includes: calculating the hit rate of each level of cache in the first target core except the first level cache according to the cache event count of each level of the first target core except the first level cache in the first monitoring data; calculating the hit rate of each level of cache in the second target core except the first level cache according to the cache event count of each level of the second target core except the first level cache in the second monitoring data; when the hit rate of each level of cache in the first target core except the first level cache is located in the corresponding preset numerical interval, and the hit rate of each level of cache in the second target core except the first level cache is located in the corresponding preset numerical interval, determining that the multi-core processor satisfies the fifth verification condition of the cache consistency verification; when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition and the fourth verification condition, determining that the multi-core processor passes the cache consistency verification, including: when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition and the fifth verification condition, determining that the multi-core processor passes the cache consistency verification.
[0013] In some embodiments, the bus of the multi-core processor includes multiple ports and a bus performance monitoring module, one of the ports is used to connect to a core or a storage module, and the method also includes: reading third monitoring data of the bus performance monitoring module, the third monitoring data including event counts of multiple target ports of the bus; when the event count of each target port of the bus is a corresponding preset value, determining that the multi-core processor satisfies the sixth verification condition of the cache consistency verification; when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition and the fourth verification condition, determining that the multi-core processor passes the cache consistency verification, including: when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition and the sixth verification condition, determining that the multi-core processor passes the cache consistency verification.
[0014] In some embodiments, the method also includes: when executing the verification use case, reading the third data of all caches of all cores except the first target core at the first verification time; when executing the verification use case, reading the fourth data of all caches of all cores except the second target core at the second verification time; the verification of cache consistency based on the first data and the second data includes: verifying cache consistency based on the first data, the second data, the third data and the fourth data.
[0015] In a second aspect, an embodiment of the present application provides a multi-core processor, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the cache consistency verification method as described in the first aspect.
[0016] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores an executable program, and the executable program is executed by a processor to implement the cache consistency verification method as described in the first aspect.
[0017] In a fourth aspect, an embodiment of the present application provides a cache consistency verification device, the verification device comprising an execution module and a verification module, the execution module being used to obtain and execute verification use cases of a multi-core processor; when executing the verification use cases, first data in all caches of a first target core of the multi-core processor and caches of a bus are read at a first verification moment; when executing the verification use cases, second data in all caches of a second target core of the multi-core processor and caches of a bus are read at a second verification moment; the verification module being used to perform cache consistency verification based on the first data and the second data.
[0018] The present application provides a cache consistency verification method, related multi-core processor, storage medium and device. The present application verifies cache consistency based on first data and second data. The first data and the second data are the data actually stored in all caches of the corresponding target core and the cache of the bus. The specific circumstances of data changes in the cache when executing the verification use case can be known, thereby improving the accuracy of the verification. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a flow chart of the first implementation method of the cache consistency verification method provided in the embodiment of the present application.
[0020] Figure 2 yes Figure 1 Detailed flowchart of step S400.
[0021] Figure 3 It is a flow chart of the second implementation method of the cache consistency verification method provided in the embodiment of the present application.
[0022] Figure 4 It is a flow chart of the third implementation method of the cache consistency verification method provided in the embodiment of the present application.
[0023] Figure 5 It is a flow chart of the fourth implementation method of the cache consistency verification method provided in the embodiment of the present application.
[0024] Figure 6 It is a flowchart of the fifth implementation method of the cache consistency verification method provided in an embodiment of the present application.
[0025] Figure 7 It is a flow chart of the sixth implementation method of the cache consistency verification method provided in the embodiment of the present application.
[0026] Figure 8It is a structural diagram of the first implementation mode of the multi-core processor provided in the embodiment of the present application.
[0027] Fig. 9 It is a structural diagram of a second implementation of a multi-core processor provided in an embodiment of the present application.
[0028] Fig.10 It is a structural block diagram of a computer-readable storage medium provided in an embodiment of the present application.
[0029] Fig.11 It is a structural diagram of a cache consistency verification device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0032] The present application provides a cache consistency verification method, related multi-core processor, storage medium and device. By verifying the cache consistency based on first data and second data, the first data and the second data are the data actually stored in all caches of the corresponding target core and the cache of the bus. The specific situation of the data change in the cache when executing the verification case can be known, thereby improving the accuracy of the verification.
[0033] The cache consistency verification method provided by the present application will be described in detail below with reference to the accompanying drawings.
[0034] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a first implementation method of a cache consistency verification method provided in an embodiment of the present application. Figure 1 As shown, the cache consistency verification method includes: step S100 to step S400.
[0035] Step S100: Acquire and execute verification use cases of the multi-core processor.
[0036] In some embodiments, the multi-core processor includes multiple cores, for example, the number of cores is 2, 3, 4, 5, 10, or 20.
[0037] Optionally, the plurality of cores include a first target core and a second target core different from the first target core.
[0038] In some implementations, multiple verification cases are preset, and one verification case is obtained and executed each time. In this way, the comprehensiveness of the verification can be improved.
[0039] Exemplarily, the verification use case is: a first target core writes target data to a first address, and then a second target core reads the target data at the first address.
[0040] Optionally, the first address refers to an address in the storage module, not an actual storage address of the target data. The target data at the first address in the storage module may not be the latest, and the latest target data at the first address may be stored in a certain Cache.
[0041] Step S200: when executing the verification case, first data in all caches of the first target core of the multi-core processor and the caches of the bus are read at a first verification moment.
[0042] In some embodiments, each core includes at least one Cache (cache memory). Cache is usually used to store frequently accessed data in order to improve the data access speed of the core. Cache Line is the smallest data storage unit in Cache, and one cache line stores one piece of data.
[0043] In some implementations, the data most recently read or written by each core is stored in the core's first-level cache.
[0044] In some implementations, the bus includes a bus cache.
[0045] In some embodiments, when the first target core writes target data to the first address, when the first target core includes multiple levels of cache and the storage space of the first level cache of the first target core is full, the first target core will store a copy of the first old data stored in the first level cache into the second level cache, and write a cache line at the storage address of the first old data, the cache line including the target data and the identifier of the first address. When the storage space of the second level cache is full, the first target core will store a copy of the second old data stored in the second level cache into the third level cache, and then write the first old data at the storage address of the second old data, and the operation when the storage space of the next level cache is full refers to the above description. When the storage space of all caches of the first target core is full, the first target core will store a copy of the old data of the last level cache into the cache of the bus. When the storage space of the cache of the bus is full, a copy of the old data of the cache of the bus is stored in the storage module.
[0046] Exemplarily, the verification use case includes: the first target core reads data at the second address.
[0047] In some embodiments, when the first target core reads data at the second address, it first searches for corresponding data in the cache in the first target core and the cache of the bus according to the second address. If the data is not found, it reads the data at the second address from the storage module through the bus.
[0048] In some implementations, after the first target core reads the data at the second address, the data at the second address is stored in the first-level cache of the first target core.
[0049] It is understandable that different cache consistency protocols specify different data reading and writing strategies (such as replacement strategies or write-back / write-through strategies, etc.). Therefore, according to different cache consistency protocols, the specific execution process of the verification use case is also different. The execution process of the above verification use case is only an example.
[0050] Optionally, the storage module is a DDR (Double Data Rate, double data rate synchronous dynamic random access memory).
[0051] In some implementations, the first verification moment is the moment when the first target core completes an operation when executing the verification case.
[0052] Exemplarily, the first verification time is the time when the first target core completes writing the target data to the first address.
[0053] In some implementations, the first verification moment is a moment before the first target core performs an operation when executing a verification case.
[0054] Exemplarily, the first verification time is the time before the first target core writes the target data to the first address.
[0055] In some implementations, there are multiple first verification moments. Optionally, the first verification moment is the moment before the first target core performs an operation or the moment when an operation is completed when executing the verification case. In this way, the first data can be obtained more comprehensively.
[0056] In some implementations, the multi-core processor further includes a bus and a storage module, each core is connected to the bus, the bus is connected to the storage module, and each core communicates with the storage module via the bus.
[0057] Step S300: when executing the verification case, second data in all caches of the second target core of the multi-core processor and caches of the bus are read at the second verification moment.
[0058] As described above, illustratively, the verification use case is: a first target core writes target data to a first address, and then a second target core reads the target data at the first address.
[0059] In some implementations, the second verification moment is the moment when the second target core completes an operation when executing the verification use case.
[0060] Exemplarily, the second verification time is the time when the second target core completes reading the target data of the first address.
[0061] In some implementations, the second verification moment is the moment before the second target core performs an operation when executing the verification case.
[0062] Exemplarily, the second verification time is the time before the second target core writes the target data to the first address.
[0063] In some implementations, there are multiple second verification moments. Optionally, the second verification moment is the moment before the second target core performs an operation or the moment when an operation is completed when executing the verification case. In this way, the second data can be obtained more comprehensively.
[0064] In some embodiments, when the first target core writes target data to the first address, information indicating that the target data is located in the first target core is stored in the cache of the bus. When the second target core reads the target data at the first address, the second target core first searches for the target data in the cache of the second target core and the cache of the bus according to the first address. When the target data is not found in the cache of the second target core, but information indicating that the target data is located in the first target core is found in the cache of the bus, the second target core reads the target data at the first address from the corresponding cache of the first target core through the bus.
[0065] Step S400: verify cache consistency according to the first data and the second data.
[0066] By verifying the cache consistency based on the first data and the second data, the first data and the second data are the data actually stored in all caches of the corresponding target core and the cache of the bus, the specific circumstances of the data changes in the cache when executing the verification use case can be known, thereby improving the accuracy of the verification.
[0067] See also Figure 2 , Figure 2 yes Figure 1 Detailed flow chart of step S400 in FIG. Figure 2 As shown, in some embodiments, step S400 includes steps S410 to S430.
[0068] Step S410: When the target data in the first data and the second data are consistent, it is determined that the multi-core processor satisfies a first verification condition for cache consistency verification.
[0069] As described above, a cache line is the smallest data storage unit in a cache, and one cache line stores one copy of data. In some implementations, a cache line includes a data identification bit and stored data.
[0070] In some embodiments, the data identification bit includes a data address identification bit and a data status identification bit. The data address identification bit is used to indicate the address corresponding to the stored data. The data status identification bit is used to indicate the state of the stored data. For example, the data status identification bit is used to indicate that the stored data is stored according to a certain preset cache consistency protocol, and can be used to indicate the state of the stored data.
[0071] Exemplarily, the state of the stored data includes a valid state, an invalid state, a new state, or an old state. The valid state indicates that the stored data is valid and can be read. The invalid state indicates that the stored data is invalid. The new state indicates that the stored data is the latest data of the corresponding address. The old state indicates that the stored data is the old data of the corresponding address.
[0072] In some implementations, a data address identification bit corresponding to the first address in the first data is identified, so that the target data actually written by the first target core is obtained in the cache line where the data address identification bit is located.
[0073] In some implementations, a data address identification bit in the second data corresponding to the first address is identified, so that the target data actually read by the second target core is obtained in the cache line where the data address identification bit is located.
[0074] In some implementations, when the target data in the first data and the second data are consistent, it is determined that the multi-core processor satisfies a first verification condition for verifying cache consistency.
[0075] In some embodiments, cache consistency is verified for each core in the multi-core processor, and a verification case is obtained and executed each time. When the target data is consistent after each execution of the verification case, it is determined that the multi-core processor meets the first verification condition of cache consistency verification.
[0076] Step S420: when it is determined according to the data identification bits in the first data and the second data that the first data and the second data satisfy a preset cache consistency protocol, it is determined that the multi-core processor satisfies a second verification condition for cache consistency verification.
[0077] As described above, in some embodiments, the data status flag is used to indicate that the stored data is stored according to a preset cache consistency protocol. According to the data status flag of the data flag in the first data and the second data, it can be determined whether the first data and the second data meet the preset cache consistency protocol.
[0078] In some embodiments, when executing the verification use case, the data state flag in the cache line involved in the execution process will change accordingly. Exemplarily, when the first-level cache of the first target core has stored data of the first address, the data state flag corresponding to the data indicates the old state. When the first target core writes the target data to the first address again, the data state flag corresponding to the target data indicates the new state.
[0079] In some implementations, when the data state identification bits of all data identification bits in the first data and the second data indicate corresponding preset states, it can be further determined that the first data and the second data satisfy a preset cache consistency protocol.
[0080] Optionally, the preset cache consistency protocol is a MESI protocol, an MSI protocol, a MOESI protocol or a MESIF protocol.
[0081] Step S430: When the multi-core processor meets the first verification condition and the second verification condition, it is determined that the multi-core processor passes the cache consistency verification.
[0082] See also Figure 3 , Figure 3 FIG. 2 is a flow chart of a second implementation of the cache consistency verification method provided in the embodiment of the present application. Figure 3 As shown, the cache consistency verification method also includes: step S501 to step S502.
[0083] Step S501: when executing the verification case, obtain the data stream of the target port on the bus.
[0084] In some implementations, the bus of the multi-core processor includes multiple ports and a bus performance monitoring module, and one port is used to connect to one core or one storage module. The target port is a port that sends and / or receives data when executing a verification case.
[0085] Optionally, the number of target ports is multiple.
[0086] Step S502: When it is determined that the execution process of the verification case is the same as the preset execution process according to the first data, the second data and the data flow of the target port, it is determined that the multi-core processor meets the third verification condition of the cache consistency verification.
[0087] As mentioned above, different cache consistency protocols specify different data read and write strategies (such as replacement strategies or write-back / write-through strategies, etc.). Therefore, according to different cache consistency protocols, the specific execution process of the verification use case is also different. For example, when the first target core writes the target data to the first address, the target data can be written only to the first-level cache of the first target core without writing it to the storage module, or the target data can be written to the first-level cache and storage module of the first target core at the same time. When the second target core reads the target data at the first address, it can read only the target data in the first target core, or it can write the target data to the storage module after reading the target data in the first target core.
[0088] If a core wants to write data to a storage module, it must communicate with the storage module through a port on the bus. If a core wants to read data from other cores except the first target core, it must also communicate with other cores through a port on the bus. Therefore, by obtaining the data flow of the target port on the bus, a part of the execution flow of the verification case can be determined.
[0089] In some implementations, when executing the verification case, the data in the first target core and the second target core may change accordingly. For example, the data status flag in the cache line involved in the execution process may change accordingly. Therefore, the execution process of the verification case may be determined based on the first data, the second data, and the data flow of the target port.
[0090] In some implementations, step S420 includes: when the multi-core processor meets the first verification condition, the second verification condition, and the third verification condition, determining that the multi-core processor passes the cache consistency verification.
[0091] The method also includes a way to obtain the data flow of the target port on the bus, which can not only know the specific circumstances of the data changes in the cache when executing the verification case, but also determine the execution process of the verification case, and verify whether the execution process of the verification case is the same as the preset execution process, thereby further improving the accuracy of the verification.
[0092] See also Figure 4 , Figure 4 FIG. 1 is a flow chart of a third implementation of the cache consistency verification method provided in the embodiment of the present application. Figure 4 As shown, the cache consistency verification method also includes: step S503 to step S506.
[0093] Step S503: read the first monitoring data in the performance monitoring module of the first target core and the second monitoring data in the performance monitoring module of the second target core.
[0094] The first monitoring data includes the event count of each level of cache of the first target core, and the second monitoring data includes the event count of each level of cache of the second target core.
[0095] In some embodiments, each core includes a performance monitoring module, which is used to monitor the operation of the cache included in the core and count the events of each level of cache in the core.
[0096] Optionally, the performance monitoring module is a PMU.
[0097] Optionally, the cache events include data writing events and data reading events.
[0098] Step S504: Calculate a first hit rate of the first level cache of the first target core according to the event count of the first level cache of the first target core in the first monitoring data.
[0099] In some implementations, the first target core records event counts of data write events and event counts of data read events executed by the core.
[0100] In some embodiments, the first hit rate of the first level cache of the first target core is obtained by dividing the sum of the event counts of data write events and data read events of the first level cache of the first target core by the sum of the event counts of data write events and data read events executed by the first target core.
[0101] In some implementations, the event count of data write events of the first level cache of the first target core is divided by the event count of data write events executed by the first target core to obtain a first write hit rate of the first level cache of the first target core.
[0102] Optionally, when the operation of the first target core in the verification case only includes data writing operations, the first write hit rate may be used as the first hit rate.
[0103] In some implementations, the event count of data read events of the first level cache of the first target core is divided by the event count of data read events executed by the first target core to obtain a first read hit rate of the first level cache of the first target core.
[0104] Optionally, when the operation of the first target core in the verification case only includes data read operations, the first read hit rate may be used as the first hit rate.
[0105] Step S505: Calculate a second hit rate of the first-level Cache of the second target core according to the event count of the first-level Cache of the second target core in the second monitoring data.
[0106] In some embodiments, the second hit rate of the first level cache of the second target core is obtained by dividing the sum of the event counts of data write events and data read events of the first level cache of the second target core by the sum of the event counts of data write events and data read events executed by the second target core.
[0107] In some implementations, the event count of data write events of the first level cache of the second target core is divided by the event count of data write events executed by the second target core to obtain a second write hit rate of the first level cache of the second target core.
[0108] Optionally, when the operation of the second target core in the verification case only includes data write operations, the second write hit rate may be used as the second hit rate.
[0109] In some implementations, the event count of data read events of the first level cache of the second target core is divided by the event count of data read events executed by the second target core to obtain a second read hit rate of the first level cache of the second target core.
[0110] Optionally, when the operation of the second target core in the verification case only includes data read operations, the second read hit rate may be the second hit rate.
[0111] Step S506: When both the first hit rate and the second hit rate are greater than the first preset value, it is determined that the multi-core processor meets the fourth verification condition of the cache consistency verification.
[0112] In some implementations, a higher hit rate of the first-level cache of a core indicates a lower frequency of the core accessing the storage module, and a faster data access speed.
[0113] In some embodiments, the step of determining that the multi-core processor passes the cache consistency verification when the multi-core processor satisfies the first verification condition, the second verification condition, and the third verification condition includes: determining that the multi-core processor passes the cache consistency verification when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, and the fourth verification condition. In this way, the cache consistency verification can be comprehensively performed in multiple aspects, thereby further improving the accuracy of the verification.
[0114] In some implementations, in the verification of cache consistency, in addition to the verification conditions for the hit rate of the first-level cache of the core, there are also corresponding verification conditions for other caches. For each cache other than the first-level cache, there is a corresponding preset value interval.
[0115] See also Figure 5 , Figure 5 FIG. 4 is a flow chart of a fourth implementation of a cache consistency verification method provided in an embodiment of the present application. Figure 5 As shown, the cache consistency verification method also includes: step S507 to step S509.
[0116] Step S507: Calculate the hit rate of each level of cache in the first target core except the first level of cache according to the cache event count of each level in the first target core except the first level of cache in the first monitoring data.
[0117] Step S508: Calculate the hit rate of each level of cache in the second target core except the first level cache according to the cache event count of each level in the second target core except the first level cache in the second monitoring data.
[0118] The method for calculating the hit rate of each level of cache is described in step S504.
[0119] Step S509: When the hit rate of each level of cache of the first target core except the first level cache is within the corresponding preset value range, and the hit rate of each level of cache of the second target core except the first level cache is within the corresponding preset value range, it is determined that the multi-core processor meets the fifth verification condition of cache consistency verification.
[0120] In some embodiments, the step of determining that the multi-core processor passes the cache consistency verification when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, and the fourth verification condition includes: determining that the multi-core processor passes the cache consistency verification when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition, and the fifth verification condition. In this way, the cache consistency verification can be further comprehensively performed in multiple aspects, thereby further improving the accuracy of the verification.
[0121] In some implementations, the bus of the multi-core processor includes multiple ports and a bus performance monitoring module, and one port is used to connect to one core or one storage module.
[0122] See also Figure 6 , Figure 6 FIG. 5 is a flow chart of a fifth implementation of a cache consistency verification method provided in an embodiment of the present application. Figure 6 As shown, the cache consistency verification method also includes: step S510 to step S511.
[0123] Step S510: Read the third monitoring data of the bus performance monitoring module.
[0124] The third monitoring data includes event counts of multiple target ports of the bus.
[0125] As described above, in some embodiments, a target port is a port that sends or receives data when executing a verification case.
[0126] In some implementations, the event count of the target port includes an event count of a data sending event and an event count of a data receiving event, etc.
[0127] Step S511: when the event count of each target port of the bus is the corresponding preset value, it is determined that the multi-core processor meets the sixth verification condition of the cache consistency verification.
[0128] As described above, if a core wants to write data into a storage module, it must communicate with the storage module through a port on the bus. If a core wants to read data from other cores except the first target core, it must also communicate with other cores through a port on the bus.
[0129] In some implementations, the execution flow of the verification case may be determined based on the first data, the second data, and the data flow of the target port.
[0130] In some implementations, when the event count of each target port of the bus is equal to a corresponding preset value, it can be further verified that the execution flow is the same as the preset execution flow.
[0131] In some embodiments, the step of determining that the multi-core processor passes the cache consistency verification when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, and the fourth verification condition includes: determining that the multi-core processor passes the cache consistency verification when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition, and the sixth verification condition.
[0132] In some implementations, when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition, and the fifth verification condition, the step of determining that the multi-core processor passes the cache consistency verification includes:
[0133] When the multi-core processor meets the first verification condition, the second verification condition, the third verification condition, the fourth verification condition, the fifth verification condition and the sixth verification condition, it is determined that the multi-core processor passes the cache consistency verification. In this way, the cache consistency verification can be further comprehensively performed in multiple aspects, thereby further improving the accuracy of the verification.
[0134] See also Figure 7 , Figure 7 FIG. 6 is a flow chart of a sixth implementation of a cache consistency verification method provided in an embodiment of the present application. Figure 7 As shown, in some implementations, the cache consistency verification method further includes: step S512 to step S513.
[0135] Step S512: when executing the verification use case, the third data of all caches of all cores except the first target core is read at the first verification moment.
[0136] Step S513: when executing the verification case, read the fourth data of all caches of all cores except the second target core at the second verification moment.
[0137] In some implementations, step S400 includes: verifying cache consistency according to the first data, the second data, the third data, and the fourth data.
[0138] In some embodiments, when a core performs a read or write operation, data in caches other than the cache of the core will also be changed accordingly. For example, after the first target core writes target data to the first address, information indicating that the target data is located in the first target core will be stored in the cache of the bus.
[0139] Optionally, the caches in other cores may also store information indicating that the target data is located in the first target core, so that the other cores can read the latest target data at the first address from the first target core.
[0140] In some implementations, when specific data among the first data, the second data, the third data, and the fourth data satisfies a preset cache consistency protocol, it is determined that the multi-core processor satisfies the seventh verification condition of the cache consistency verification.
[0141] In some implementations, when the multi-core processor meets the first verification condition and the seventh verification condition, it is determined that the multi-core processor passes the cache consistency verification.
[0142] In some implementations, when the multi-core processor meets the first verification condition, the second verification condition, and the seventh verification condition, it is determined that the multi-core processor passes the cache consistency verification.
[0143] It is understandable that different cache consistency protocols specify different data read and write strategies. Therefore, according to different cache consistency protocols, when executing the verification case, the data changes of the third data and the fourth data are also different. By verifying the cache consistency according to the first data, the second data, the third data and the fourth data, the specific situation of the data changes in all caches can be known, which can further improve the accuracy of the verification.
[0144] In some implementations, when the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition, the fifth verification condition, the sixth verification condition, and the seventh verification condition, it is determined that the multi-core processor passes the cache consistency verification.
[0145] In summary, the cache consistency verification method provided in the embodiment of the present application has the following advantages:
[0146] 1. By verifying the cache consistency based on the first data and the second data, the first data and the second data are the data actually stored in all caches of the corresponding target core and the cache of the bus, the specific situation of the data change in the cache when executing the verification case can be known, thereby improving the accuracy of the verification.
[0147] 2. The method also includes a way of obtaining the data flow of the target port on the bus, which can not only know the specific circumstances of the data changes in the cache when executing the verification case, but also determine the execution process of the verification case, and verify whether the execution process of the verification case is the same as the preset execution process, thereby further improving the accuracy of the verification.
[0148] 3. By determining whether the multi-core processor passes the cache consistency verification when the multi-core processor meets multiple verification conditions, the cache consistency verification can be comprehensively performed in multiple aspects, thereby further improving the accuracy of the verification.
[0149] 4. By verifying the consistency of the cache according to the first data, the second data, the third data and the fourth data, the specific situation of the data change in all caches can be known, which can further improve the accuracy of the verification.
[0150] The present application also provides a multi-core processor for implementing the cache consistency verification method provided in the present application.
[0151] See also Figure 8 , Figure 8 Schematic diagram of the structure of the first implementation of the multi-core processor provided in the embodiment of the present application. Figure 8 As shown, the multi-core processor 100 includes: one or more processors 101 and a memory 102, Figure 8 A processor 101 is taken as an example.
[0152] In some implementations, the processor 101 and the memory 102 may be connected via a bus or other means. Figure 8 The example of connecting through bus is taken in the following.
[0153] In some embodiments, processor 101 is used to obtain and execute verification use cases of a multi-core processor; when executing the verification use cases, first data in all caches of a first target core of the multi-core processor and caches of a bus are read at a first verification moment; when executing the verification use cases, second data in all caches of a second target core of the multi-core processor and caches of a bus are read at a second verification moment; and cache consistency is verified based on the first data and the second data.
[0154] In some embodiments, the memory 102, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules of the cache consistency verification method in the embodiment of the present application. The processor 101 executes various functional applications and data processing of the multi-core processor 100 by running the non-volatile software programs, instructions and modules stored in the memory 102, that is, the cache consistency verification method of the above method embodiment is implemented.
[0155] In some embodiments, the memory 102 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created according to the use of the multi-core processor 100, etc. In addition, the memory 102 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 102 may optionally include a memory remotely arranged relative to the processor 101, and these remote memories may be connected to the controller via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0156] In some embodiments, one or more modules are stored in the memory 102, and when executed by one or more processors 101, the cache consistency verification method in any of the above method embodiments is executed, for example, the above described Figure 1 The method comprises steps S100 to S400.
[0157] See also Fig. 9 , Fig. 9 Schematic diagram of the structure of the second implementation of the multi-core processor provided in the embodiment of the present application. Figure 1 As shown, in some embodiments, the multi-core processor 100 includes multiple cores and at least one storage module 140, and each core includes at least one Cache. For example, the multi-core processor 100 includes a first target core 110 and a second target core 120, the first target core 110 includes at least a first-level Cache of the first target core 110, and the second target core 120 includes at least a first-level Cache of the second target core 120. One core is also a core processor. Cache and storage modules are both memories.
[0158] In some implementations, the multi-core processor 100 further includes a bus 130 , and the bus 130 includes a cache 131 of the bus 130 .
[0159] In some implementations, the bus 130 further includes a plurality of ports, one port being connected to one core or storage module 140 .
[0160] like Fig. 9 As shown, in some embodiments, the multi-core processor 100 further includes a multi-core processor monitoring module 140, which can be connected to the electronic device. The bus 130 is connected to the multi-core processor monitoring module 140 through a port.
[0161] Optionally, the multi-core processor monitoring module 140 performs cache consistency verification based on the read data.
[0162] Optionally, the multi-core processor monitoring module 140 may send the read data to an electronic device, and the electronic device performs cache consistency verification based on the data.
[0163] In some embodiments, the multi-core processor monitoring module 140 includes a first monitoring submodule. The first monitoring submodule is used to read first data in all caches of a first target core of the multi-core processor and caches of a bus at a first verification time, and read second data in all caches of a second target core of the multi-core processor and caches of a bus at a second verification time when executing a verification case.
[0164] In some embodiments, the multi-core processor monitoring module 140 further includes a second monitoring submodule and a third monitoring submodule. The second monitoring submodule is used to trigger the second monitoring submodule to obtain the data stream of the target port on the bus when the trigger condition is met during the execution of the verification case. The third monitoring submodule is used to obtain the data stream of the target port when receiving the trigger information of the second monitoring submodule.
[0165] Optionally, the trigger condition is: the port sends or receives data.
[0166] In some embodiments, a port includes multiple channels, and the multiple channels include a request channel, a response channel, a sniffing channel, and a data channel. The request channel is used to send a data acquisition request. The response channel is used to send a response to the data acquisition request. The sniffing channel is used to enable the multi-core processor monitoring module to monitor the data flow of other channels of the port. The data channel is used to transmit data.
[0167] In some implementations, the multi-core processor monitoring module 140 obtains the data flow of the port through the sniffing channel, and can obtain the sender information and the receiver information of each piece of data according to the data flow of the request channel and the data flow of the response channel. , and then determine the execution process of the verification case.
[0168] Please refer to Fig.10 , Fig.10The computer-readable storage medium 200 stores a program code 210, which can be called by a processor to execute the cache consistency verification method described in the above method embodiment.
[0169] The computer-readable storage medium 200 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium 200 has a storage space for program codes for executing any method steps in the above-mentioned cache consistency verification method. These program codes may be read from or written to one or more computer program products. The program code may be compressed, for example, in an appropriate form.
[0170] See also Fig.11 , Fig.11 Schematic diagram of the structure of the cache consistency verification device provided by the embodiment of the present application. Fig.11 As shown, the cache consistency verification device 300 includes an execution module 310 and a verification module 320 .
[0171] In some embodiments, the execution module 310 is used to obtain and execute verification use cases of a multi-core processor; when executing the verification use cases, first data in all caches of a first target core of the multi-core processor and caches of a bus are read at a first verification moment; when executing the verification use cases, second data in all caches of a second target core of the multi-core processor and caches of a bus are read at a second verification moment.
[0172] In some implementations, the verification module 320 is used to verify cache consistency based on the first data and the second data.
[0173] In some implementations, the embodiments of the present application further provide a computer program product, including a computer program, which implements the above-mentioned cache consistency verification method when executed by a processor.
[0174] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium 200. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited thereto.
[0175] In summary, the present application provides a method for verifying cache consistency, a related multi-core processor, a storage medium and a device, the method for verifying cache consistency includes: obtaining and executing a verification case of a multi-core processor; when executing the verification case, reading first data in all caches of a first target core of the multi-core processor and caches of a bus at a first verification moment; when executing the verification case, reading second data in all caches of a second target core of the multi-core processor and caches of a bus at a second verification moment; and verifying cache consistency according to the first data and the second data. The present application verifies cache consistency according to the first data and the second data, the first data and the second data are data actually stored in all caches of the corresponding target core and caches of the bus, and can know the specific situation of data changes in the cache when executing the verification case, thereby improving the accuracy of verification.
Claims
1. A cache consistency verification method, characterized in that: include: Acquire and execute verification use cases for multi-core processors; When executing the verification case, at a first verification moment, first data in all caches of a first target core of the multi-core processor and caches of a bus are read; When executing the verification case, at a second verification time, second data in all caches of a second target core of the multi-core processor and caches of a bus are read; Cache consistency is verified based on the first data and the second data.
2. The cache consistency verification method according to claim 1, characterized in that: The verifying cache consistency according to the first data and the second data includes: When the target data in the first data and the second data are consistent, determining that the multi-core processor satisfies a first verification condition for verifying the cache consistency; When it is determined according to the data identification bits in the first data and the second data that the first data and the second data satisfy a preset cache consistency protocol, determining that the multi-core processor satisfies a second verification condition for verifying the cache consistency; When the multi-core processor meets the first verification condition and the second verification condition, it is determined that the multi-core processor passes the cache consistency verification.
3. The cache consistency verification method according to claim 2, characterized in that: The method further comprises: When executing the verification case, obtaining a data stream of a target port on the bus; When it is determined that the execution process of the verification case is the same as the preset execution process according to the first data, the second data and the data flow of the target port, it is determined that the multi-core processor satisfies the third verification condition of the cache consistency verification; When the multi-core processor satisfies the first verification condition and the second verification condition, determining that the multi-core processor passes the cache consistency verification includes: When the multi-core processor meets the first verification condition, the second verification condition and the third verification condition, it is determined that the multi-core processor passes the cache consistency verification.
4. The cache consistency verification method according to claim 3, characterized in that: The method further comprises: Reading first monitoring data in the performance monitoring module of the first target core and second monitoring data in the performance monitoring module of the second target core, wherein the first monitoring data includes event counts of each level of cache of the first target core, and the second monitoring data includes event counts of each level of cache of the second target core; Calculating a first hit rate of the first level Cache of the first target core according to an event count of the first level Cache of the first target core in the first monitoring data; Calculating a second hit rate of the first-level Cache of the second target core according to the event count of the first-level Cache of the second target core in the second monitoring data; When both the first hit rate and the second hit rate are greater than a first preset value, determining that the multi-core processor satisfies a fourth verification condition of the cache consistency verification; When the multi-core processor satisfies the first verification condition, the second verification condition, and the third verification condition, determining that the multi-core processor passes the cache consistency verification includes: When the multi-core processor meets the first verification condition, the second verification condition, the third verification condition and the fourth verification condition, it is determined that the multi-core processor passes the cache consistency verification.
5. The cache consistency verification method according to claim 4, characterized in that: The method further comprises: Calculate the hit rate of each level of cache in the first target core except the first level cache according to the cache event count of each level in the first target core except the first level cache in the first monitoring data; Calculate the hit rate of each level of cache in the second target core except the first level cache according to the cache event count of each level in the second target core except the first level cache in the second monitoring data; When the hit rate of each level of cache of the first target core except the first level cache is within the corresponding preset value interval, and the hit rate of each level of cache of the second target core except the first level cache is within the corresponding preset value interval, it is determined that the multi-core processor meets the fifth verification condition of the cache consistency verification; When the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, and the fourth verification condition, determining that the multi-core processor passes the cache consistency verification includes: When the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition, and the fifth verification condition, it is determined that the multi-core processor passes the cache consistency verification.
6. The cache consistency verification method according to claim 4, characterized in that: The bus of the multi-core processor includes a plurality of ports and a bus performance monitoring module, one of the ports is used to connect to one core or one storage module, and the method further includes: Reading third monitoring data of the bus performance monitoring module, wherein the third monitoring data includes event counts of multiple target ports of the bus; When the event count of each target port of the bus is a corresponding preset value, determining that the multi-core processor satisfies the sixth verification condition of the cache consistency verification; When the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, and the fourth verification condition, determining that the multi-core processor passes the cache consistency verification includes: When the multi-core processor satisfies the first verification condition, the second verification condition, the third verification condition, the fourth verification condition and the sixth verification condition, it is determined that the multi-core processor passes the cache consistency verification.
7. The cache consistency verification method according to claim 1, characterized in that: The method further comprises: When executing the verification use case, reading third data of all caches of all cores except the first target core at the first verification time; When executing the verification case, reading fourth data of all caches of all cores except the second target core at the second verification time; The verifying cache consistency according to the first data and the second data includes: Cache consistency is verified according to the first data, the second data, the third data and the fourth data.
8. A multi-core processor, characterized in that: The multi-core processor comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the cache consistency verification method as described in any one of claims 1 to 7.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores an executable program, and the executable program is executed by a processor to implement the cache consistency verification method according to any one of claims 1 to 7.
10. A cache consistency verification device, characterized in that: The verification device comprises an execution module and a verification module. The execution module is used to obtain and execute a verification case of a multi-core processor; when executing the verification case, first data in all caches of a first target core of the multi-core processor and caches of a bus are read at a first verification time; when executing the verification case, second data in all caches of a second target core of the multi-core processor and caches of a bus are read at a second verification time; The verification module is used to verify cache consistency according to the first data and the second data.