Automatic error positioning method and device, electronic equipment and medium

Abstract

The invention provides an automatic error positioning method and device, electronic equipment and a medium, and relates to the field of data processing, in particular to the field of error recognition and fault positioning. The method comprises the steps of obtaining a first node graph obtained by loading an inference model through a first inference framework, wherein to-be-detected errors exist in the first node graph; obtaining a second node graph obtained by loading the inference model through a second inference framework; and in response to determining that a first node in the first node graph satisfies an error occurrence condition, determining the first node as a node having an error, the first node satisfying the error occurrence condition comprising that for the first node, there is no matched node in the second node graph.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to error identification and fault location, and specifically to an automatic error location method, device, electronic device, computer-readable storage medium, and computer program product. Background Art

[0002] With the continuous development of semiconductor technology, AI acceleration chips based on semiconductor integrated circuits are in a state of flourishing. In order to better demonstrate the reasoning computing power of the chip, different reasoning frameworks will be selected. When performing reasoning calculations on various AI acceleration chips, how to obtain more accurate reasoning results is an urgent problem to be solved.

[0003] The methods described in this section are not necessarily methods that have been previously conceived or employed. Unless otherwise indicated, it should not be assumed that any method described in this section is considered to be prior art simply because it is included in this section. Similarly, unless otherwise indicated, the issues mentioned in this section should not be considered to have been recognized in any prior art. Summary of the invention

[0004] The present disclosure provides an automatic error location method, device, electronic device, computer-readable storage medium, and computer program product.

[0005] According to one aspect of the present disclosure, there is provided an automatic error location method, comprising: obtaining a first node graph obtained by loading an inference model through a first inference framework, wherein an error to be detected exists in the first node graph; obtaining a second node graph obtained by loading the inference model through a second inference framework; and in response to determining that a first node in the first node graph satisfies an error occurrence condition, determining the first node as a node where an error occurs, wherein the first node satisfies the error occurrence condition including that, for the first node, there is no matching node in the second node graph.

[0006] According to another aspect of the present disclosure, there is provided an automatic error location device, comprising: a first node graph obtaining unit, used to obtain a first node graph obtained by loading an inference model through a first inference framework, wherein there is an error to be detected in the first node graph; a second node graph obtaining unit, used to obtain a second node graph obtained by loading the inference model through a second inference framework; and an error node determination unit, used to determine a first node in the first node graph as a node where an error occurs in response to determining that the first node satisfies an error occurrence condition, wherein the first node satisfies the error occurrence condition including that, for the first node, there is no matching node in the second node graph.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform an automatic error location method according to one or more embodiments of the present disclosure.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the automatic error location method according to one or more embodiments of the present disclosure.

[0009] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the computer program implements the automatic error location method according to one or more embodiments of the present disclosure.

[0010] According to one or more embodiments of the present disclosure, errors can be effectively located.

[0011] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0013] Figure 1 A schematic diagram showing an exemplary system in which the various methods described herein may be implemented according to an embodiment of the present disclosure;

[0014] Figure 2 A flow chart of an automatic error location method according to an embodiment of the present disclosure is shown;

[0015] Figure 3A and Figure 3B A schematic diagram showing a node graph according to an embodiment of the present disclosure is shown;

[0016] Figure 4 A schematic diagram showing a node matching process of an automatic error location method according to an embodiment of the present disclosure is shown;

[0017] Figure 5A flow chart of an automatic error location method according to another embodiment of the present disclosure is shown;

[0018] Figure 6A-6E A schematic diagram showing a node matching process of an automatic error location method according to another embodiment of the present disclosure is shown;

[0019] Figure 7 A structural block diagram of an automatic error positioning device according to an embodiment of the present disclosure is shown;

[0020] Figure 8 A structural block diagram of an exemplary electronic device that can be used to implement the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0021] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0022] In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

[0023] The terms used in the description of various examples in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. In addition, the term "and / or" used in this disclosure covers any one of the listed items and all possible combinations.

[0024] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 FIG. 1 is a schematic diagram of an exemplary system 100 in which various methods and apparatuses described herein may be implemented according to an embodiment of the present disclosure. Figure 1, the system 100 includes one or more client devices 101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105, and 106 may be configured to execute one or more applications.

[0026] In an embodiment of the present disclosure, the server 120 may run one or more services or software applications that enable the automatic error location method according to the present disclosure to be performed.

[0027] In some embodiments, server 120 may also provide other services or software applications, which may include non-virtualized environments and virtualized environments. In some embodiments, these services may be provided as web-based services or cloud services, such as provided to users of client devices 101, 102, 103, 104, 105, and / or 106 under a software as a service (SaaS) model.

[0028] exist Figure 1 In the configuration shown, the server 120 may include one or more components that implement the functions performed by the server 120. These components may include software components, hardware components, or a combination thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 may in turn utilize one or more client applications to interact with the server 120 to utilize the services provided by these components. It should be understood that a variety of different system configurations are possible, which may differ from the system 100. Therefore, Figure 1 is one example of a system for implementing the various methods described herein and is not intended to be limiting.

[0029] A user may use client devices 101, 102, 103, 104, 105, and / or 106 to locate an error, determine a fault, etc. The client device may provide an interface that enables a user of the client device to interact with the client device. The client device may also output information to the user via the interface. Figure 1 Only six client devices are depicted, but one skilled in the art will appreciate that the present disclosure may support any number of client devices.

[0030] Client devices 101, 102, 103, 104, 105 and / or 106 may include various types of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptop computers), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, game systems, thin clients, various messaging devices, sensors or other sensing devices, etc. These computer devices may run various types and versions of software applications and operating systems, such as MICROSOFT Windows, APPLE iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as GOOGLE Chrome OS); or include various mobile operating systems, such as MICROSOFT Windows Mobile OS, iOS, Windows Phone, Android. Portable handheld devices may include cellular phones, smart phones, tablet computers, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Game systems may include various handheld game devices, Internet-enabled game devices, etc. Client devices are capable of executing various different applications, such as various Internet-related applications, communication applications (such as email applications), short message service (SMS) applications, and may use various communication protocols.

[0031] The network 110 may be any type of network known to those skilled in the art that may support data communications using any of a variety of available protocols, including but not limited to TCP / IP, SNA, IPX, etc. By way of example only, the one or more networks 110 may be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0032] Server 120 may include one or more general purpose computers, dedicated server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 120 may include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that may be virtualized to maintain a server's virtual storage device). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0033] The computing units in the server 120 may run one or more operating systems including any of the above operating systems and any commercially available server operating systems. The server 120 may also run any of a variety of additional server applications and / or middle-tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0034] In some implementations, server 120 may include one or more applications to analyze and consolidate data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0035] In some embodiments, the server 120 may be a server of a distributed system, or a server combined with a blockchain. The server 120 may also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in a cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.

[0036] The system 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. The databases 130 may reside in various locations. For example, the database used by the server 120 may be local to the server 120, or may be remote from the server 120 and may communicate with the server 120 via a network-based or dedicated connection. The databases 130 may be of different types. In some embodiments, the databases used by the server 120 may be, for example, relational databases. One or more of these databases may store, update, and retrieve data to and from the databases in response to commands.

[0037] In some embodiments, one or more of the databases 130 may also be used by applications to store application data. The databases used by the applications may be different types of databases, such as a key-value store, an object store, or a conventional store backed by a file system. Figure 1 The system 100 may be configured and operated in various ways to enable the application of various methods and apparatuses described in the present disclosure.

[0038] Reference below Figure 2 An automatic error location method 200 according to an exemplary embodiment of the present disclosure is described.

[0039] In step S201, a first node graph is obtained by loading an inference model through a first inference framework, wherein errors to be detected exist in the first node graph.

[0040] In step S202, a second node graph is obtained by loading the reasoning model through a second reasoning framework.

[0041] At step S203, in response to determining that a first node in the first node graph satisfies an error occurrence condition, the first node is determined as a node where an error occurs, wherein the first node satisfies the error occurrence condition including that there is no matching node in the second node graph for the first node.

[0042] According to the method described in the embodiment of the present disclosure, errors can be effectively located.

[0043] When different chips and different frameworks are used for calculation, errors or faults may occur. However, since different chips and different frameworks may correspond to inconsistent node graphs, it may be difficult to locate the location where the error or fault occurs. By using the second node graph as the reference node graph, the nodes are compared. If they do not match, it is considered that there is an error or fault here, which can facilitate the location of the error or fault.

[0044] With the continuous development of semiconductor technology, AI acceleration chips based on semiconductor integrated circuits are in a state of flourishing, and various companies have launched their own AI acceleration chips. In order to better demonstrate the reasoning power of their own chips, each company will choose one or more, open source or self-developed reasoning frameworks. However, what follows is that when each framework performs reasoning on each AI acceleration card, the problem of inaccurate numerical calculation results may occur: for example, it may be that the model format of one framework is converted to the model format of another framework, and problems occur during the conversion process; it may also be that there is no problem with the conversion process, but problems occur during the process of running reasoning on the acceleration card. Once an error occurs in the final calculation result, engineers often need to spend a lot of time to locate which computing node it starts from, resulting in errors. How to enable engineers to quickly locate the computing node with problems is the problem to be solved by the present invention.

[0045] In the prior art, generally speaking, there is a prerequisite for error location, that is, there needs to be a one-to-one correspondence between the computing nodes of the "accelerator card and reasoning framework that can obtain correct operating results" as a reference and the "accelerator card and reasoning framework that obtains incorrect results" that need to be located, so as to ensure that the same output can be obtained under a computing node of the two frameworks using the same input, and then compared.

[0046] But more often, what needs to be compared is the combination of any two different inference frameworks + accelerator cards for inference. There is no corresponding relationship information between the computing nodes between the two, and the number of computing nodes of the two inference frameworks is likely to be different due to different fusion strategies. As a specific example, it is known that using the tensorflow framework to infer a certain .pb format model on the NVIDIA GPU can get the correct calculation result. Converting this .pb format model to the self-developed model format and using the self-developed framework to infer this model on the self-developed accelerator card, but getting the wrong calculation result. At this time, the correspondence between the computing nodes under the tensorflow framework and the self-developed framework cannot be obtained, and some nodes are not corresponding. For example, a task that requires two computing nodes to complete in the tensorflow framework may have been fused into one computing node in the self-developed framework, or vice versa. For example, the sigmoid and multiply computing tasks corresponding to two computing nodes in the tensorflow framework are fused into a single computing node swish in the self-developed framework, so that there is no one-to-one correspondence between the computing nodes. Using the existing technology, it is impossible to locate which computing node has an error during reasoning on the self-developed framework + self-developed acceleration card. However, if the method of the present invention is used, successful positioning can be achieved.

[0047] According to one or more embodiments of the present disclosure, when the same set of models is loaded into different chips by different frameworks to form different operator node graphs but leads to different calculation results, erroneous operator nodes can be quickly located.

[0048] According to the automatic location method of inference calculation errors based on breadth-first graph search proposed in the embodiments of the present invention, it is not necessary to provide the correspondence between the computing nodes of the two reasoning frameworks in advance, nor is it necessary for the computing nodes of the two reasoning frameworks to correspond one to one, nor is it necessary for engineers to manually compare layer by layer. It is possible to complete the location of calculation errors when any software + hardware combination is used for reasoning.

[0049] As described in reference method 200, according to one or more embodiments of the present disclosure, a software + hardware combination that can infer an erroneous final result is required as a fault combination, and a software + hardware combination that can infer a correct final result is required as a reference combination. As described in reference method 200, the node graph corresponding to the fault combination is called the first node graph, which may also be called an error node graph, a fault node graph, an error combination calculation graph, a fault combination calculation graph, etc. The node graph corresponding to the reference combination is called the second node graph, which may also be called a reference node graph, a reference combination calculation graph, etc. It can be understood that the above naming method is only for narration and distinction, and the present disclosure is not limited to this. It is hoped that based on these two node graphs, it is found from which computing node the calculation result of the fault combination begins to be wrong, so that the problem can be further located and repaired.

[0050] Input data can be constructed and used as input of the reference combination and the fault combination, and the output data of each computing node and all its child nodes can be obtained respectively.

[0051] It is understandable that, although the first node graph corresponding to the fault combination and the second node graph corresponding to the reference combination are recorded in the order of step S201 and step S202, it is not required that the two be performed in such an order. The second node graph may be obtained first and then the first node graph, or the two may be obtained alternately, in parallel or almost simultaneously, etc., and the present disclosure is not limited thereto.

[0052] refer to Figure 3A and Figure 3B ,in Figure 3A An example of a first node graph is shown, and Figure 3B An example of a second node graph is shown.

[0053] For example, by recording the output data of each computing node and all its child nodes when using the fault combination for reasoning, and then using all the recorded computing nodes and all the child nodes of the node, we can construct the following Figure 3A The example computation graph shown is a first node graph, or an error node graph, where each of pf0, pf1, ..., pf7 represents a node in the first node graph, where a fault exists at at least one of the nodes.

[0054] Similarly, based on the same input data, by recording the output data of each computing node and all its child nodes when using the reference combination for reasoning, and using all the recorded computing nodes and all the child nodes of the node, we can construct the following Figure 3BThe example computation graph shown is a second node graph, or referred to as a reference node graph, wherein each of pt0, pt1, ... pt7 represents a node in the second node graph and wherein no fault exists.

[0055] Exemplarily, node pf4 may correspond to node pt3, that is, some nodes of the error node graph and the reference node graph may have a one-to-one correspondence. Exemplarily, nodes pf3 and pf3 may correspond to node pt2, that is, for some reasoning processes, the error node graph may have more nodes than the reference node graph. As another example, node pf5 may correspond to nodes pt4 and pt5, that is, for some reasoning processes, the error node graph may have fewer nodes than the reference node graph. It is understandable that Figure 3A and Figure 3B The number of nodes in the node graph, the topology, the correspondence between the two node graphs, etc. are merely examples, and the present disclosure is not limited thereto.

[0056] According to some embodiments, the method may further include obtaining a first inference data set obtained by processing input data through a first node graph and a second inference data set obtained by processing the input data through a second node graph. In such an embodiment, determining that a first node in the second node graph satisfies an error occurrence condition may include: determining that the first node satisfies the error occurrence condition by comparing the first inference data set with the inference data in the second inference data set.

[0057] Thus, it is possible to determine whether a node matches by using the reasoning data of the node. It is understandable that the first reasoning data set may include at least one first reasoning data corresponding to at least one node in the first node graph, and the second reasoning data set includes at least one second reasoning data corresponding to at least one node in the second node graph. The reasoning data may correspond to the data output by the node.

[0058] According to some embodiments, the first node satisfying the error occurrence condition may include: the reasoning data of the first node does not match the reasoning data of any node in the second node graph.

[0059] When the inference data does not match, it is considered that the node has no corresponding node, and then the node is considered to be wrong. For example, when the difference between the inference data of the first node in the first node graph and the inference data of any node in the second node graph is greater than a threshold, it is considered that the inference data of the first node does not match the inference data of any node in the second node graph.

[0060] According to some embodiments, the error node graph and the reference node graph have different topological structures. In such embodiments, the error occurrence condition may also include: the reasoning data of each subsequent node in the reasoning path of the first node in the first node graph does not match the reasoning data of any node in the second node graph.

[0061] In some embodiments where the node graph topologies generated by the two inference frameworks are different, the method may further include comparing subsequent nodes, so that even when the topologies of the two nodes are inconsistent, it is still possible to accurately determine whether the nodes fall on a path mismatch.

[0062] It can be understood that a subsequent node of a node refers to another node located after the node in the reasoning path of the node graph, which, for example, uses the output of the node as input, or uses the output of other subsequent nodes of the node as input, and as those skilled in the art can understand, in the present disclosure, the subsequent node may also be referred to as a child node.

[0063] In other words, in such an example, the error occurrence condition includes: the reasoning data of the error node does not match the reasoning data of any node in the reference node graph; and the reasoning data of each child node of the error node does not match the reasoning data of any node in the reference node graph. When the difference between the reasoning data of the first node of the error node graph and the reasoning data of the second node of the reference node graph is not greater than a threshold, it is considered that the first node does not match the second node.

[0064] Continue to refer Figure 3A and Figure 3B According to one or more embodiments of the present disclosure, an algorithm based on breadth-first graph search may be used to search Figure 3A For each node in Figure 3B If no matching node is found after the search, it means that the computing node fails to match. Figure 3A If the matching information of all nodes in the result is found, starting from a certain node, it, all the nodes after it, and even the final output node fail to match, then the node can be determined as the node where the calculation error first occurred. Exemplarily, matching can refer to whether the maximum difference of the output data of two nodes is greater than a threshold, and whether the ratio of the maximum difference to the output value is greater than a threshold. If both are greater than the threshold, it is determined to be mismatched, otherwise it is determined to be matched.

[0065] According to some embodiments, the first node satisfying an error occurrence condition may further include: the first node is an input node in the first node graph, or a predecessor node of the first node in the first node graph has a matching node in the second node graph.

[0066] Therefore, the first node that fails to match on the fault path can be used as the error node, so as to conveniently locate the position where the error first occurs.

[0067] According to some embodiments, determining that a first node in the first node graph satisfies an error occurrence condition may include: obtaining the first node in the first node graph as a current node to be matched; and in response to determining that there is no node in the second node graph that matches the current node to be matched and in response to determining that the current node to be matched does not have a child node that can be further used for matching, determining that the first node satisfies the error occurrence condition.

[0068] In such an embodiment, if the current node fails to match and has no child nodes, the match fails and is an error node. In other words, if it is determined that the first node to be matched does not have a child node that has been successfully matched or has not been matched, the first node to be matched fails to match. Alternatively, in response to determining that there is no node matching the first node to be matched in the reference node graph and there is no node matching any subsequent node of the first node to be matched in the reference node graph, the first node to be matched is marked as an error node.

[0069] For example, the name of the current node to be matched is used here to facilitate describing the node currently undergoing the matching operation, but the present disclosure is not limited thereto. The current node to be matched may be a child node of the currently matched node, which (and optionally, its child nodes) is to be matched. The node matching order and matching logic will be described below in conjunction with Figure 5 The specific non-limiting embodiments are further described in detail, and they are only examples, and the present disclosure is not limited thereto.

[0070] According to some embodiments, determining that a first node in the first node graph satisfies an error occurrence condition may include: obtaining the first node in the first node graph as a current node to be matched; in response to determining that there is no node in the second node graph that matches the current node to be matched and in response to determining that the current node to be matched has a subsequent node that can be further used for matching, obtaining a subsequent node of the current node to be matched as a temporary node to be matched for matching; and in response to determining that the temporary node to be matched does not have a subsequent node that can be matched with a node in the second node graph, determining that the first node satisfies the error occurrence condition.

[0071] For example, if the current node fails to match, but the current node has child nodes, the child nodes can be taken as "temporary nodes to be matched". The difference between temporary nodes to be matched and current nodes to be matched is that the parent node of the current node to be matched is the matching node, and the matching result is for itself; while the parent node of the temporary node to be matched is the questionable node, and the matching result is traced back to the parent node to be matched.

[0072] According to some embodiments, the method may further include, in response to determining that the second node in the first node graph does not satisfy the error occurrence condition, marking the second node as a matching node. In such an embodiment, the method may further include an operation of marking as a matching node, thereby facilitating the location of the fault.

[0073] According to some embodiments, in response to determining that a second node in the first node graph does not satisfy an error occurrence condition, marking the second node as a matching node may include: obtaining the second node in the first node graph as a current node to be matched; and in response to determining that there is a node in the second node graph that matches the current node to be matched, marking the second node as a matching node.

[0074] In such an embodiment, if the current node matches successfully, it is marked as a match, which can be applicable to situations corresponding to the node topology.

[0075] According to some embodiments, in response to determining that a second node in the first node graph does not satisfy an error occurrence condition, marking the second node as a matching node may include: obtaining the second node in the first node graph as a current node to be matched; and in response to determining that there is no node in the second node graph that matches the current node to be matched, and there is a node in the second node graph that matches a subsequent node of the current node to be matched, marking the second node as a matching node.

[0076] In such an embodiment, if the current node fails to match, but the subsequent node matches successfully, it is marked as a match, which can be applicable to the case where the node topology does not correspond.

[0077] According to some optional exemplary embodiments, determining the error node in the first node graph may be achieved by a matching operation on the current node to be matched, wherein the matching operation is used to determine whether the current node to be matched matches a node in the reference node graph. Exemplarily, obtaining the current node to be matched in the first node graph may include obtaining a child node of an input node in the first node graph or a child node that has been marked as a matching node as the current node to be matched.

[0078] According to some embodiments, the matching operation of the current node to be matched with the reference node graph may include: in response to determining that there is no node matching the current node to be matched in the second node graph, and there is a node matching the first subsequent node of the current node to be matched in the second node graph, marking the current node to be matched as a matching node; obtaining a child node of the current node to be matched as an updated current node to be matched for matching; and determining the error node in the first node graph based on the matching operation of the updated current node to be matched with the second node graph. In other words, if the match is successful, the next child node can be obtained and the matching process continues.

[0079] Exemplarily, the matching operation of the current node to be matched with the second node graph may include: in response to determining that there is no node matching the current node to be matched in the second node graph and in response to determining that the current node to be matched does not have a child node that can be further used for matching, marking the current node to be matched as an error node.

[0080] Exemplarily, the matching operation of the current node to be matched with the second node graph may include: in response to determining that there is no node matching the current node to be matched in the second node graph and in response to determining that the current node to be matched has child nodes that can be further used for matching, obtaining the child nodes of the current node to be matched as temporary nodes to be matched for matching; and based on the matching operation of the temporary node to be matched with the second node graph, determining the error node in the first node graph.

[0081] Exemplarily, the matching operation of the temporary node to be matched with the second node graph may include: in response to determining that there is no node matching the temporary node to be matched in the second node graph, and there is a node matching the second subsequent node of the temporary node to be matched in the second node graph, marking the current node to be matched as a matching node. As described above, the matching result of the temporary node to be matched is traced back to the parent current node to be matched.

[0082] Exemplarily, the matching operation of the temporary node to be matched with the second node graph may include: in response to determining that there is no node matching the temporary node to be matched in the second node graph and in response to determining that the temporary node to be matched has no child nodes that can be further used for matching, marking the current node to be matched as an error node.

[0083] Exemplarily, the matching operation of the temporary node to be matched with the second node graph may include: in response to determining that there is no node matching the temporary node to be matched in the second node graph and in response to determining that the temporary node to be matched has a child node, obtaining the child node of the temporary node to be matched as a further temporary node to be matched for matching; and based on the matching operation of the further temporary node to be matched with the second node graph, determining the error node in the first node graph. The logic of the "further temporary node to be matched" is similar to that of the "temporary node to be matched", and finally traces back to the "current node to be matched" according to the matching result, that is, as long as there is a matching node later, it is traced back to the current node to be matched, and it is considered that there is no fault, and it will not be repeated here.

[0084] continue Figure 3A and Figure 3B For node examples, refer to Figure 4 A schematic diagram describing an exemplary graph node matching process based on breadth-first graph search according to an embodiment of the present disclosure, wherein unmatched nodes, nodes being matched, successfully matched nodes, failed matching nodes, and completed nodes are shown in different colors.

[0085] Assumptions Figure 3A and Figure 3B The actual matching relationship of the computing nodes in is that pf0 matches pt0, pf1 matches pt1, pf3 matches pt2 (that is, the data that can be obtained by calculating the pt2 node in the reference combination needs to be calculated by both pf2 and pf3 nodes in the fault combination, but as long as pf3, as the child node of pf2, successfully matches the output data of pt2, it does not matter even if pf2 fails to match, that is, it can be considered that pf2 is not the node where the calculation error occurs), pf4 matches pt3, pf5 matches pt5 (that is, the data that needs to be calculated by both pt4 and pt5 nodes in the reference combination can be obtained by only calculating the pf5 node in the fault combination, even if no node matches pt4, it does not matter, because only the matching information of the nodes in the fault combination will be collected in the end), pf6 matches pt6, and pf7 matches pt7.

[0086] Assume that the node with the calculation error is the pf6 node in the fault combination: that is, the output data of pf6 and the output data of the pt6 node should have matched successfully, but due to the calculation error, it was judged as a match failure. Correspondingly, due to the calculation error of the output data of pf6, the output data of pf7 will also be calculated incorrectly, resulting in the output data of the pf7 and pt7 nodes also being judged as a match failure.

[0087] Combine the following Figure 4 The matching process is described in detail in each section.

[0088] refer to Figure 4 In part 4a, two node graphs are obtained and matching begins.

[0089] exist Figure 4 At part 4B of , the node pf0 in the first node graph (fault combination computation graph) is obtained as the node currently being matched, and is successfully matched with the node pt0 in the second node graph (reference combination computation graph).

[0090] exist Figure 4 In part 4C of , the node pf1 in the first node graph is obtained as the node currently being matched, and is successfully matched with the node pt1 in the second node graph.

[0091] exist Figure 4 At part 4D, the child node pf4 of the successfully matched node pf0 in the first node graph is obtained as the currently matched node, and is successfully matched with the node pt3 in the second node graph.

[0092] exist Figure 4 At part 4E, the child node pf2 of the successfully matched node pf1 in the first node graph is obtained as the currently matched node, and the matching with the corresponding child node pt2 in the second node graph fails.

[0093] exist Figure 4 In part 4F, the child node pf5 of the successfully matched node pf4 in the first node graph is obtained as the currently matched node. It fails to match the node pt4 in the second node graph, but successfully matches the subsequent node pt5 of pt4, then pf5 is considered to be matched successfully.

[0094] exist Figure 4 At part 4G, another child node pf6 of the successfully matched node pf4 in the first node graph is obtained as the currently matched node, which fails to match the node pt6 in the second node graph, and fails to match the subsequent node pt7 of pt6. Since pt7 has no further child nodes, the process cannot continue matching here.

[0095] exist Figure 4 At part 4H, node pf3 is obtained as the node currently being matched, and is successfully matched with node pt2 in the second node graph.

[0096] exist Figure 4 In part 4I, the child node pf7 of the successfully matched node pf5 in the first node graph is obtained as the currently matched node, and the matching with the corresponding child node pt7 in the second node graph fails.

[0097] Figure 4Part 4J shows the current matching results, and Figure 4 Part 4K shows the final fault location, which is nodes pf6 and pf7. Although there is no corresponding node for node pf2 in the first node graph and node pt4 in the second node graph, it is not considered that an error occurs because the subsequent nodes can be matched. Therefore, it can be concluded that the calculation error occurs starting from the pf6 node of the fault combination.

[0098] According to one or more embodiments of the present disclosure, a method for locating erroneous operator nodes is provided for error scenarios in which the same set of models is loaded into different chips using two different frameworks to form different operator node graphs and result in different calculation results. Exemplarily, the correct node graph is regarded as a reference node graph, the erroneous node graph is regarded as an error node graph, and for each node in the error node graph, it is checked whether there is a matching node in the reference node graph. If the difference is less than a threshold, it is considered to be matched, and if it is not found, it is considered to be unmatched; if a node is unmatched, but its child nodes are matched, it is considered not to be a node where a calculation error occurs.

[0099] Figure 5 A flowchart 500 is provided to illustrate an automatic error location method according to a specific non-limiting exemplary embodiment of the present disclosure, wherein a queue-based node search scheme is used. Figure 6A-6E The node schematic diagram of the flowchart 500 is described in detail.

[0100] Similarly, Figure 6A-6E Different colors are used to show unmatched nodes, nodes being matched, matched nodes, matched failed nodes, and completed nodes, where the left side is an exemplary reference combination calculation graph, i.e., the second node graph, and the right side is an exemplary fault combination calculation graph, i.e., the first node graph. Fig. 6E In the example of , it is shown that the fault combination calculation graph has more nodes, and it can be understood that this is only an example and the present disclosure is not limited to this.

[0101] Return to reference Figure 5 At 501, a double-layer queue QF is constructed for storing computing nodes of a fault combination and is initialized to be empty, and a double-layer queue QT is constructed for storing computing nodes of a reference combination and is initialized to be empty.

[0102] Then, at 502, all input nodes of the fault combination are placed in a temporary queue, the temporary queue is placed in QF, and all input nodes of the reference combination are placed in a temporary queue, the temporary queue is placed in QT, as shown in FIG. Fig. 6A As shown in part 6A1, QT = [[t0]] and QF = [[f0]].

[0103] Return to reference Figure 5 At 503, determine whether the queue QF is empty, if not, proceed to 504, if yes, proceed to 522.

[0104] At 504, the head of QF is taken out to obtain queue qf. Fig. 6A Part 6A2 in FIG. 6A shows qf = [f0].

[0105] Return to reference Figure 5 At 505, determine whether the queue qf is empty, if not, proceed to 507, if yes, proceed to 506.

[0106] Return to reference Figure 5 At 507, the head of queue qf is taken out to obtain node pfx; if pfx is marked as completed, another one is taken. At 508, a copy of the head of QT is made to obtain queue qt, and the head of the queue does not leave the queue.

[0107] like Fig. 6A As shown in part 6A3, when the queue qf is not empty, the head f0 of the queue qf is taken out for matching.

[0108] Return to reference Figure 5 At 509 , determine whether the queue qf is empty, if not, proceed to 510 , if yes, proceed to 518 .

[0109] Return to reference Figure 5 At 510, the head of the queue gt is taken out and the node ptx is obtained. If ptx is marked as completed, another one is taken.

[0110] Return to reference Figure 5 At 511, determine whether pfx and ptx match successfully, if not, proceed to 512, if yes, proceed to 513. Fig. 6A Parts 6A4-6A5 in FIG. 5 show the case where f0 and t0 are matched successfully.

[0111] Return to reference Figure 5 If the match at 511 fails, at 512, all child nodes of ptx are put into queue qt. If ptx has no child nodes, they are not put, and the step returns to 510.

[0112] If the match at 511 is successful, at 513 , determine whether the current pfx has child nodes, if so, proceed to 514 , otherwise proceed to 516 .

[0113] At 514, all child nodes of pfx are placed into a temporary queue, and the temporary queue is placed into QF.

[0114] At 515, all child nodes of ptx are placed in a temporary queue, and the temporary queue is placed in QT (if ptx has no child nodes, an empty queue is constructed and placed in QT).

[0115] At 516, the information that the nodes pfx and ptx are successfully matched is printed.

[0116] At 517, nodes pfx, ptx are marked as completed.

[0117] If it is determined at 509 that yes, then the process proceeds to 518 to determine whether the current pt has a child node.

[0118] Refer to part 6A6. When the queue qf is empty, take out the head of the QT queue.

[0119] Return to reference Figure 5 , at 519 , all child nodes of pfx are placed into a temporary queue, and the temporary queue is placed into QF.

[0120] At 520, a copy of the head of QT is made and placed at the end of QT, and the head of QT does not leave the queue. Figure 6B Sections 6B1-6B2 in show an example of step 520.

[0121] Return to reference Figure 5 At 521, print the node pfx matching failure information, which corresponds to Figure 6B Section 6B3.

[0122] Similarly, the loop steps in the flowchart are repeatedly executed, for example, Figure 6B Sections 6B4-6B6 and Figure 6C The steps shown in parts 6C1-6C5 are repeated, and the principles are not repeated again.

[0123] In part 6C6, the queue qf is empty, and the head of the queue QT is removed. Return to reference Figure 5 , if the queue qf is empty, the process goes to 506 and takes out the head of the queue of QT.

[0124] Similarly, the loop steps in the flowchart are repeatedly executed, such as Fig.6D Sections 6D1-6D6 and Fig. 6E The steps shown in parts 6E1-6E5 are repeated, and the principles are not repeated again.

[0125] In part 6E6, the queue QF is empty and the matching is complete. Return to reference Figure 5 If the queue QF is determined to be empty at 503, the process goes to 522, where all matching information is collected and the matching ends.

[0126] Although the present disclosure refers to Figure 5 as well as Figure 6A-6E A scheme of searching child nodes in sequence in a queue form is provided, but the present disclosure is not limited thereto. As another optional embodiment, a pure brute force search may be used, where for each node in the fault combination, all nodes in the reference combination are searched to see which node can be successfully matched.

[0127] According to one or more embodiments of the present disclosure, the automatic location of the reasoning calculation error can be completed without knowing the correspondence between the calculation nodes in two calculation graphs under two different reasoning frameworks, or even without requiring the nodes in the two calculation graphs to correspond one to one (regardless of whether one is more or less than the other). As a result, it is completely free from the restrictions of the reasoning framework and the computing device, and any reasoning framework + computing device, as long as the result is correct, can be used as a reference combination to locate the error node of the fault combination.

[0128] According to one or more embodiments of the present disclosure, by using an algorithm based on breadth-first graph search, the correspondence between nodes can be searched without knowing the correspondence between the reference node graph and the error node graph in advance, and even without a one-to-one correspondence between the reference node graph and the error node graph. For nodes that cannot be matched, the node can be skipped to search for its child nodes. Therefore, through the embodiments of the present disclosure, the application scenarios of the automatic error location solution can be greatly expanded, and any reasoning framework + computing device can be used as a reference, and any reasoning framework + computing device can be used to automatically locate the error node.

[0129] Reference now Figure 7 The automatic error location device 700 according to an embodiment of the present disclosure is described. The automatic error location device 700 may include a first node graph obtaining unit 701 , a second node graph obtaining unit 702 , and an error node determining unit 703 .

[0130] The first node graph obtaining unit 701 can be used to obtain a first node graph obtained by loading an inference model through a first inference framework, wherein the first node graph has an error to be detected. The second node graph obtaining unit 702 can be used to obtain a second node graph obtained by loading the inference model through a second inference framework. The error node determination unit 703 can be used to determine a first node in the first node graph as a node where an error occurs in response to determining that the first node in the first node graph satisfies an error occurrence condition, wherein the first node satisfies the error occurrence condition including that there is no matching node in the second node graph for the first node.

[0131] According to the device described in the embodiment of the present disclosure, errors can be effectively located.

[0132] According to some embodiments, the apparatus may further include a unit for obtaining a first inference data set obtained by processing input data through a first node graph and a second inference data set obtained by processing the input data through a second node graph. In such an embodiment, determining that a first node in the second node graph satisfies an error occurrence condition includes: determining that the first node satisfies the error occurrence condition by comparing the first inference data set with the inference data in the second inference data set.

[0133] According to some embodiments, the first node satisfies an error occurrence condition including: the reasoning data of the first node does not match the reasoning data of any node in the reference node graph.

[0134] According to some embodiments, the error node graph and the reference node graph have different topological structures. In such an embodiment, the error occurrence condition may also include: the reasoning data of each subsequent node in the reasoning path of the first node in the first node graph does not match the reasoning data of any node in the second node graph.

[0135] According to some embodiments, the first node satisfying the error occurrence condition may also include: the first node is an input node in the first node graph, or a predecessor node of the first node in the first node graph has a matching node in the second node graph.

[0136] According to some embodiments, the unit for determining that the first node in the first node graph satisfies an error occurrence condition includes a unit for the following operations: obtaining the first node in the first node graph as a current node to be matched; and determining that the first node satisfies the error occurrence condition in response to determining that there is no node in the second node graph that matches the current node to be matched and in response to determining that the current node to be matched does not have a child node that can be further used for matching.

[0137] According to some embodiments, the unit for determining that the first node in the first node graph satisfies an error occurrence condition includes a unit for the following operations: obtaining the first node in the first node graph as a current node to be matched; in response to determining that there is no node in the second node graph that matches the current node to be matched and in response to determining that the current node to be matched has a subsequent node that can be further used for matching, obtaining a subsequent node of the current node to be matched as a temporary node to be matched for matching; and in response to determining that the temporary node to be matched does not have a subsequent node that can be matched with a node in the second node graph, determining that the first node satisfies the error occurrence condition.

[0138] According to some embodiments, the apparatus may further include means for marking a second node in the first node graph as a matching node in response to determining that the second node does not satisfy an error occurrence condition.

[0139] According to some embodiments, in response to determining that a second node in the first node graph does not satisfy an error occurrence condition, a unit for marking the second node as a matching node includes a unit for the following operations: obtaining the second node in the first node graph as a current node to be matched; and in response to determining that there is a node in the second node graph that matches the current node to be matched, marking the second node as a matching node.

[0140] According to some embodiments, in response to determining that a second node in the first node graph does not satisfy an error occurrence condition, a unit for marking the second node as a matching node includes a unit for the following operations: obtaining the second node in the first node graph as a current node to be matched; and in response to determining that there is no node in the second node graph that matches the current node to be matched, and there is a node in the second node graph that matches a subsequent node of the current node to be matched, marking the second node as a matching node.

[0141] In the technical solution disclosed herein, the collection, acquisition, storage, use, processing, transmission, provision and public application of user personal information involved are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0142] According to an embodiment of the present disclosure, an electronic device, a readable storage medium and a computer program product are also provided.

[0143] refer to Figure 8 , a block diagram of an electronic device 800 that can be used as a server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0144] like Figure 8As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0145] Multiple components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, an output unit 807, a storage unit 808, and a communication unit 809. The input unit 806 can be any type of device that can input information to the electronic device 800. The input unit 806 can receive input digital or character information and generate key signal input related to user settings and / or function control of the electronic device, and can include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and / or a remote controller. The output unit 807 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 808 can include but is not limited to a disk, an optical disk. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and can include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0146] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as methods 200 and / or 500 and their variants, etc. For example, in some embodiments, methods 200 and / or 500 and their variants, etc. may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the methods 200 and / or 500 and their variants, etc. described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the method 200 and / or 500 and its variations, etc., in any other appropriate manner (eg, by means of firmware).

[0147] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0148] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0149] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0150] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0151] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0152] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0153] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0154] Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-mentioned methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples, but only by the claims after authorization and their equivalent scope. Various elements in the embodiments or examples can be omitted or replaced by their equivalent elements. In addition, each step can be performed in an order different from that described in the present disclosure. Further, the various elements in the embodiments or examples can be combined in various ways. It is important that with the evolution of technology, many elements described herein can be replaced by equivalent elements that appear after the present disclosure.

Claims

1. An automatic error location method, comprising: Obtaining a first node graph obtained by loading the inference model through a first inference framework, wherein there is an error to be detected in the first node graph; Obtaining a second node graph obtained by loading the reasoning model through a second reasoning framework; and In response to determining that a first node in the first node graph satisfies an error occurrence condition, the first node is determined as a node where an error occurs, wherein the first node satisfies the error occurrence condition including that there is no matching node in the second node graph for the first node.

2. The method according to claim 1 further comprises obtaining a first inference data set obtained by processing input data through a first node graph and a second inference data set obtained by processing the input data through a second node graph, and wherein, Determining that a first node in the second node graph satisfies an error occurrence condition includes: determining that the first node satisfies an error occurrence condition by comparing the first reasoning data set with reasoning data in the second reasoning data set.

3. The method according to claim 2, wherein: The first node satisfies the error occurrence condition including: the reasoning data of the first node does not match the reasoning data of any node in the second node graph.

4. The method according to claim 3, wherein: The first node graph and the second node graph have different topological structures, and wherein the error occurrence condition further includes: the reasoning data of each subsequent node in the reasoning path of the first node in the first node graph does not match the reasoning data of any node in the second node graph.

5. The method according to any one of claims 1 to 4, wherein: The first node satisfies an error occurrence condition further including: the first node is an input node in the first node graph, or a preceding node of the first node in the first node graph has a matching node in the second node graph.

6. The method according to any one of claims 1 to 4, wherein: Determining that the first node in the first node graph satisfies the error occurrence condition includes: Obtaining the first node in the first node graph as a current node to be matched; and In response to determining that there is no node matching the current node to be matched in the second node graph and in response to determining that the current node to be matched has no child nodes that can be further used for matching, it is determined that the first node satisfies an error occurrence condition.

7. The method according to any one of claims 1 to 4, wherein: Determining that the first node in the first node graph satisfies the error occurrence condition includes: Obtaining the first node in the first node graph as a current node to be matched; In response to determining that there is no node matching the current node to be matched in the second node graph and in response to determining that the current node to be matched has a subsequent node that can be further used for matching, obtaining the subsequent node of the current node to be matched as a temporary node to be matched for matching; and In response to determining that the temporary to-be-matched node does not have a subsequent node that can be matched with a node in the second node graph, it is determined that the first node satisfies an error occurrence condition.

8. The method according to any one of claims 1-4, further comprising, in response to determining that a second node in the first node graph does not satisfy an error occurrence condition, marking the second node as a matching node.

9. The method according to claim 8, wherein: In response to determining that a second node in the first node graph does not satisfy an error occurrence condition, marking the second node as a matching node includes: Obtaining the second node in the first node graph as a current node to be matched; and In response to determining that there is a node matching the current to-be-matched node in the second node graph, marking the second node as a matching node.

10. The method according to claim 8, wherein: In response to determining that a second node in the first node graph does not satisfy an error occurrence condition, marking the second node as a matching node includes: Obtaining the second node in the first node graph as a current node to be matched; and In response to determining that there is no node matching the current node to be matched in the second node graph, and there is a node matching a subsequent node of the current node to be matched in the second node graph, marking the second node as a matching node.

11. An automatic error positioning device, comprising: A first node graph obtaining unit, configured to obtain a first node graph obtained by loading the reasoning model through a first reasoning framework, wherein the first node graph has an error to be detected; A second node graph obtaining unit, configured to obtain a second node graph obtained by loading the reasoning model through a second reasoning framework; and An error node determination unit is used to determine a first node in the first node graph as a node where an error occurs in response to determining that the first node in the first node graph satisfies an error occurrence condition, wherein the first node satisfies the error occurrence condition including that there is no matching node in the second node graph for the first node.

12. The apparatus according to claim 11, further comprising a unit for obtaining a first inference data set obtained by processing input data through a first node graph and a second inference data set obtained by processing the input data through the second node graph, and wherein, The error node determination unit includes: a unit for determining that the first node satisfies an error occurrence condition by comparing the first reasoning data set with the reasoning data in the second reasoning data set.

13. The device according to claim 12, wherein: The first node satisfies the error occurrence condition including: the reasoning data of the first node does not match the reasoning data of any node in the second node graph.

14. The device according to claim 13, wherein: The first node graph and the second node graph have different topological structures, and wherein the error occurrence condition further includes: the reasoning data of each subsequent node in the reasoning path of the first node in the first node graph does not match the reasoning data of any node in the second node graph.

15. The device according to any one of claims 11 to 14, wherein: The first node satisfies an error occurrence condition further including: the first node is an input node in the first node graph, or a preceding node of the first node in the first node graph has a matching node in the second node graph.

16. The device according to any one of claims 11 to 14, wherein: The error node determination unit comprises: A unit for obtaining the first node in the first node graph as a current node to be matched; and A unit for determining that the first node satisfies an error occurrence condition in response to determining that there is no node matching the current node to be matched in the second node graph and in response to determining that the current node to be matched has no child nodes that can be further used for matching.

17. The device according to any one of claims 11 to 14, wherein: The error node determination unit comprises: A unit for obtaining the first node in the first node graph as a current node to be matched; A unit for obtaining a subsequent node of the current node to be matched as a temporary node to be matched for matching in response to determining that there is no node matching the current node to be matched in the second node graph and in response to determining that the current node to be matched has a subsequent node that can be further used for matching; and A unit for determining that the first node satisfies an error occurrence condition in response to determining that the temporary to-be-matched node does not have a subsequent node that can be matched with a node in the second node graph.

18. The apparatus according to any one of claims 11-14, further comprising a unit for marking a second node in the first node graph as a matching node in response to determining that the second node does not satisfy an error occurrence condition.

19. The device according to claim 18, wherein: The unit for marking a second node in the first node graph as a matching node in response to determining that the second node in the first node graph does not satisfy an error occurrence condition comprises: Obtaining the second node in the first node graph as a unit of a current node to be matched; and In response to determining that there is a node in the second node graph that matches the current node to be matched, the second node is marked as a unit of a matching node.

20. The device according to claim 18, wherein The unit for marking a second node in the first node graph as a matching node in response to determining that the second node in the first node graph does not satisfy an error occurrence condition comprises: A unit for obtaining the second node in the first node graph as a current node to be matched; and A unit for marking the second node as a matching node in response to determining that there is no node matching the current node to be matched in the second node graph and there is a node matching a subsequent node of the current node to be matched in the second node graph.

21. An electronic device, comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 10.

22. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-10.

23. A computer program product comprising a computer program, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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