Chip congestion prediction method

Abstract

The invention discloses a chip congestion prediction method, which comprises the following steps: constructing a unit operation set, constructing a search space based on the unit operation set, selecting a neural network architecture by using a gradient descent method, and carrying out iterative updating to obtain an optimal neural network architecture; obtaining chip layout and wiring design atlas of the target field and the source field, selecting a preset number of images, obtaining a target training set and a source training atlas, and training a cyclic generative adversarial network through the selected images; obtaining an auxiliary data set based on the chip layout and wiring design atlas of the source field and the cyclic generative adversarial network; and training the optimal neural network structure based on the target training set and the auxiliary training set to obtain a final chip congestion prediction model, and performing chip congestion prediction based on the final chip congestion prediction model. The problem that a large amount of professional knowledge and huge engineering consumption are needed when a machine learning model is used for congestion prediction is solved, and the number of data samples needed by cross-chip congestion prediction is greatly reduced.

Description

Technical Field

[0001] The invention belongs to the field of chip physical design, and in particular relates to a chip congestion prediction method. Background Art

[0002] Chip congestion prediction is a key task in the chip design process. It is used to estimate potential congestion problems in the physical design stage and then take optimization measures. Congestion refers to the phenomenon of excessive congestion in certain areas or signal paths due to resource constraints or unreasonable layout during chip layout and routing. This phenomenon will have a negative impact on indicators such as chip performance, power consumption or area. In FPGA or ASIC design, congestion is mainly manifested in tight routing resources. Although logic resources may still be sufficient, the exhaustion of routing resources will limit the performance of the chip or hinder the successful implementation of the design.

[0003] Traditional FPGA chip congestion prediction mainly relies on the congestion analysis function in the placement and routing tools. After the designer completes the placement and routing, he estimates possible congestion problems by analyzing resource utilization, signal path length, and timing constraints, and then makes optimization suggestions. However, traditional methods usually rely on rule-based or experience-based analysis, which takes a long time to process and is difficult to guarantee prediction accuracy. In particular, when the design scale increases and the congestion problem becomes more complex, traditional methods often have difficulty in making quick and accurate predictions.

[0004] In recent years, FPGA congestion prediction methods based on deep neural networks have gradually gained attention. These methods use a large number of data-driven models to learn congestion features from historical design data, which can predict faster and improve the accuracy of prediction. Yu et al. proposed a method for predicting routing congestion using conditional generative adversarial nets (cGANs). This method uses a conditional generative adversarial network model to predict routing congestion heatmaps. The prediction problem is described as an image translation task, with the input being an image after layout completion and the output being a congestion heatmap generated after detailed routing processing. Compared with previous work, this method only relies on features collected in and before the layout stage. The proposed algorithm can also predict routing congestion in real time during the design layout process. By modeling the FPGA congestion prediction problem as an image translation problem, the above method can better handle complex routing patterns in the design. However, machine learning-based methods also face certain challenges.

[0005] First, the development of traditional machine learning models relies on rich domain knowledge, and the process of training and verifying models is very time-consuming and labor-intensive, which is particularly evident for large-scale FPGA designs. Secondly, due to the complexity of FPGA architecture, the congestion characteristics between different chip designs vary greatly. The existing congestion prediction models have weak generalization capabilities across design scenarios and are difficult to adapt to the needs of different designs. To this end, the development of a universal congestion prediction model requires a lot of manual adjustments and optimizations, which undoubtedly increases the engineering cost of model development. In addition, existing machine learning models often rely on large-scale training data, but in many actual design scenarios, it is not easy to obtain enough high-quality training data, especially for some new designs or specific application scenarios. Insufficient data samples may lead to the inability to fully train the model, which in turn affects the accuracy and reliability of its predictions. These problems make it difficult for existing machine learning-based congestion prediction methods to be widely promoted in practical applications, limiting their application potential in large-scale chip design. Summary of the invention

[0006] In order to solve the above technical problems, the present invention proposes a chip congestion prediction method to solve the above problems in the prior art.

[0007] To achieve the above object, the present invention provides a chip congestion prediction method, comprising:

[0008] Constructing a unit operation set, and constructing a search space based on the unit operation set; searching the search space using a gradient descent method, selecting a neural network architecture and performing iterative updates to obtain an optimal neural network architecture;

[0009] Determine the target domain and the source domain, obtain chip layout and wiring design atlases of the target domain and the source domain respectively, and select a preset number of chip layout and wiring design drawings to obtain a target training set and a source training atlas;

[0010] Train a recurrent generative adversarial network based on the target training set and the source training graph set;

[0011] Auxiliary datasets are obtained based on chip layout and wiring design atlases in the source domain and recurrent generative adversarial networks;

[0012] The optimal neural network structure is trained based on the target training set and the auxiliary training set to obtain a final chip congestion prediction model, and chip congestion prediction is performed based on the final chip congestion prediction model.

[0013] Optionally, the unit operation set includes but is not limited to an identity operation, a zeroing operation, a 3x3 depthwise separable convolution, a 3x3 transposed convolution, a 5x5 depthwise separable convolution, a 5x5 transposed convolution, a 3x3 average pooling, and a 3x3 maximum pooling.

[0014] Optionally, the neural network structure in the search space is parameterized, and an alternating optimization strategy and a gradient descent algorithm are used to update model weights and architecture parameters to obtain an optimized neural network architecture.

[0015] Optionally, the process of updating model weights and architecture parameters includes:

[0016] Obtain a training data set, sample the training data set, input the sampled data into the neural network architecture, calculate the loss function, and update the model weights through the gradient descent method; sample data in the validation set, calculate the validation loss, and update the architecture parameters through the gradient descent method. During the training process, the architecture parameters and model weights are optimized alternately.

[0017] Optionally, a lightweight single performance evaluation strategy is used after each update to obtain the optimal neural network architecture; the lightweight single performance evaluation strategy includes: after each architecture update, training and verification are performed to obtain the relative advantages and disadvantages of the performance of different architectures.

[0018] Optionally, a chip layout and wiring design drawing of a preset proportion is selected from the chip layout and wiring design drawing set in the source domain to obtain a source data atlas; the source data atlas is input into a recursive generative adversarial network to obtain an auxiliary data set; wherein the chip layout and wiring design drawings of each congestion prediction in the source domain are set to be of equal proportion.

[0019] Compared with the prior art, the present invention has the following advantages and technical effects:

[0020] The present invention introduces neural network architecture search technology into the field of chip physical design, applies it to chip congestion prediction, and effectively improves the efficiency and performance of the design through automated architecture optimization. By combining cyclic generative adversarial networks and synthetic data, the distribution difference problem between FPGA design data sets is solved, and the adaptability of the congestion prediction model to new designs is significantly improved. The present invention overcomes the problem of requiring a lot of expertise and huge engineering consumption when using machine learning models for congestion prediction, and greatly reduces the number of data samples required for cross-chip congestion prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 is a flow chart of a method according to an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of a search space according to an embodiment of the present invention;

[0024] Figure 3A schematic diagram of a cyclic generative adversarial network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0027] Embodiment 1

[0028] like Figure 1 As shown, this embodiment provides a chip congestion prediction method, including:

[0029] 1. Congestion prediction method based on neural network architecture search

[0030] Neural Architecture Search (NAS) is a method for automated neural network design that can significantly reduce the time and experience required to manually design complex architectures. The success of deep learning is partly due to automatic feature engineering through end-to-end learning, but as the complexity of the task increases, the difficulty of manually designing the architecture also increases. NAS transcends the limitations of manual design by automatically exploring the architecture of neural networks, and has demonstrated superior performance in multiple fields, such as image classification, object detection and other tasks. The present invention introduces NAS technology into the field of chip design automation and applies it to chip congestion prediction, aiming to effectively improve the efficiency and performance of the design through automated architecture optimization.

[0031] NAS methods are classified into three dimensions: search space, search strategy, and performance evaluation strategy. These three together constitute the automated search process of neural networks.

[0032] (1) Search space

[0033] The search space determines the set of neural network architectures that can be explored. The NAS search space of the present invention combines the specific requirements of the design, narrows the scope of exploration, and enables the search to be more focused on the network architecture suitable for the task. The search space is mainly optimized for the image translation problem, using operations such as convolution and deconvolution. Specifically, NAS connects different unit operations through a directed acyclic graph (DAG), and gradually builds an optimized neural network model through the transfer and conversion of feature tensors. Figure 2As shown in the figure, each edge has a set of weighted operations, and each node is data that has been processed. The data is transformed from the input point input into a layer of intermediate data through various operations in turn, and finally the output congestion prediction graph output is obtained.

[0034] The unit operation set used in this embodiment includes but is not limited to the following operations: identity operation, zeroize operation, 3x3 depth-wise separate conv, 3x3 transpose conv, 5x5 depth-wise separate conv, 5x5 transpose conv, 3x3 average pooling and 3x3 max pooling.

[0035] (2) Search strategy

[0036] The NAS search strategy efficiently explores and optimizes in a huge and complex search space. In order to quickly find a suitable architecture, a gradient descent-based architecture search algorithm, GDAS (Gradient-based searching approach using Differentiable Architecture Sampling), is used. GDAS can quickly find the optimal neural network architecture in the design process of congestion prediction by searching in a continuous parameter space. Compared with traditional discrete search methods, GDAS significantly improves search efficiency while reducing computational costs. This search strategy iteratively optimizes architecture parameters and model parameters used for evaluation, thereby accelerating NAS search efficiency.

[0037] The GDAS algorithm optimizes the neural network architecture by alternating between updating the model weights W and the architecture parameters A. First, from the training set D T Sample a batch of data and calculate the loss function L T , and update the model weight W by gradient descent. Next, from the validation set D V Sampling data, calculating the validation loss L V , and update the architecture parameters A by gradient descent. This method allows the architecture parameters A and weights W to be optimized alternately during the training process, and ultimately finds the optimal neural network architecture.

[0038] (3) Performance evaluation strategy

[0039] Since the training and verification costs of a complete neural network are extremely high, the performance evaluation of NAS uses an estimation method to reduce computational overhead. This paper adopts a lightweight single-shot performance evaluation strategy. After each architecture update, the model only needs to be trained and verified once, and only the relative performance comparison of different architectures is obtained instead of precise performance scores, which greatly reduces the demand for computing resources. This strategy provides fast iteration capabilities for FPGA congestion prediction tasks and ensures that the architecture finally searched has good generalization performance.

[0040] Through the above neural network architecture search process, the existing chip congestion prediction design process is optimized, solving the problem that designing deep neural networks requires expert knowledge and a lot of design time. In addition, compared with traditional design methods, NAS also significantly improves the prediction accuracy and speed of the design process through efficient search algorithms. In practical applications, this method can help designers quickly iterate design solutions and avoid congestion problems, thereby improving chip performance and stability.

[0041] 2. Congestion prediction optimization based on transfer learning

[0042] In actual design scenarios, for some new designs or specific application scenarios, it is difficult for designers to obtain enough FPGA congestion data samples, which may result in the model being unable to be fully trained, thereby affecting the accuracy and reliability of model prediction. This embodiment uses transfer learning to map the relationship between a small number of samples in the FPGA field and samples in other fields such as ASIC, and uses the congestion prediction knowledge contained in samples in other fields to generate samples in the FPGA field to assist target training.

[0043] Transfer learning mainly solves the problem that the source and target domains have differences in feature space, edge distribution, label space, conditional probability, etc. For the congestion prediction problem of FPGA chips, the application of transfer learning can integrate congestion cases in different design scenarios, realize the generalization ability of the model, and reduce data requirements.

[0044] (1) Cycle Generative Adversarial Network (CycleGAN)

[0045] In transfer learning, Generative Adversarial Network (GAN) is a commonly used method that solves the domain adaptation problem between different data distributions by generating realistic synthetic data. In particular, the CycleGAN model can learn the mapping between the source domain and the target domain without one-to-one paired data, which has a significant effect on cross-designed dataset domain adaptation.

[0046] like Figure 3As shown in the figure, CycleGAN realizes the bidirectional mapping of source domain and target domain data through two generators and two discriminators. The generator is responsible for converting data from the source domain to data from the target domain and vice versa, while the discriminator is used to distinguish generated data from real data. Unlike traditional GAN, CycleGAN introduces cycle consistency loss to ensure that the generated images can remain consistent when mapped back to the source domain. That is, when an image in the source domain is converted to an image in the target domain and then converted back to the source domain, it should remain similar to the original image. This mechanism enables CycleGAN to perform well in cross-domain adaptation tasks, especially in FPGA congestion prediction, when there are significant differences in wiring images of different designs, CycleGAN can generate images that match the characteristics of the target design, helping the model to better adapt to the target domain.

[0047] In the scenario of FPGA congestion prediction, CycleGAN can be used to convert layout images and congestion graphs in other fields such as ASIC congestion prediction into relevant images in FPGA design, so that congestion prediction datasets in other fields can be used to guide the training of FPGA congestion prediction models, and the target model can be better generalized to more designs.

[0048] (2) Using synthetic data for transfer learning

[0049] A CNN model trained on a specifically designed dataset does not work equally well on other designed datasets. To address this problem, the CycleGAN-based approach described above is used to achieve cross-dataset domain adaptation and learn with synthetic data. This process is described in detail below.

[0050] First, m samples are randomly selected from the source domain and the target domain to train the CycleGAN model. After the training is completed, a small part of the images in the source domain are synthesized into the target domain through this model. Finally, these synthesized images are combined with the original samples in the target domain to form a training set for training the chip congestion prediction model.

[0051] Furthermore, the chip layout and wiring design atlases of the target domain and the source domain are obtained respectively, and a preset number of chip layout and wiring design drawings are selected to obtain a target training set and a source training atlas; a recurrent generative adversarial network is trained based on the target training set and the source training atlas; an auxiliary data set is obtained based on the chip layout and wiring design atlas of the source domain and the recurrent generative adversarial network; the optimal neural network structure is trained based on the target training set and the auxiliary training set to obtain a final chip congestion prediction model, and chip congestion prediction is performed based on the final chip congestion prediction model.

[0052] Different FPGA design datasets represent different layout and routing designs, so there is an internal distribution shift between them. In order to enable a model to generalize to multiple designs, CycleGAN is used to convert images of one design to images of another design (and vice versa). The generator G takes a layout and routing design image from one design as input and is trained to produce a new layout and routing design image that adapts to the characteristics of another design. The discriminator D is trained to distinguish between real design images and "fake" images synthesized from one design.

[0053] Synthesized design routing images are then generated, and variability is introduced by adjusting the label distribution. Despite having higher contrast and consistency along routing boundaries in one design dataset, the synthesized design images look quite realistic.

[0054] Use the original image X of the target dataset T The converted synthetic images of the source dataset are used to train the FPGA routing congestion prediction model. S p% images are randomly selected as auxiliary data. Each category is set to an equal proportion to maintain the same congestion distribution. The selected images are passed to the pre-trained source-to-target domain CycleGAN model to create an FPGA domain dataset with similar data distribution and properties. The synthetic dataset Used to train the model. The scale of the synthesized image can be controlled in the CycleGAN framework.

[0055] In general, the transfer learning-based approach, by combining CycleGAN and synthetic data, not only solves the distribution difference problem between FPGA design datasets, but also significantly improves the adaptability of the congestion prediction model to new designs. This approach provides an efficient and flexible solution for congestion prediction in the field of FPGA chip design.

[0056] This embodiment uses the FPGA congestion prediction datasets of FPGA-CPB and FPGA-CPB-reduced to conduct congestion prediction experiments, as shown in Table 1. This dataset uses the VTR tool to collect features and congestion prediction labels obtained by layout and routing of 17 circuits in VTR Benchmarks on the same FPGA architecture. The circuits cover different fields and are suitable for FPGA-related research. The FPGA-CPB dataset samples 400 congestion data for each circuit, and FPGA-CPB-reduced samples 200.

[0057] Table 1

[0058]

[0059]

[0060] The algorithm development software uses Python, and PyTorch is used for experiments. All experiments are run on a Linux server consisting of an Intel(R) Core(TM) i9-10920X CPU@3.50GHz (8 cores) and an NVIDIARTX3090 GPU.

[0061] The software environment used in the test environment is: Ubuntu 22.04LTS, Vscode 1.86.2 (OS: Linuxx64.6.2.0-34-generic, python 3.10.12)

[0062] The test results are shown in Table 2 and Table 3. Prediction accuracy is a key indicator to measure the performance of the congestion prediction model. Here, two error functions commonly used in image prediction are used, namely, the regularized root mean square error (NRMSE) and the structural similarity index (SSIM). The smaller the NRMSE and the larger the SSIM, the more accurate the prediction. From Table 2, it can be seen that the congestion prediction method based on neural network architecture search can search for models that are better than manually designed networks in less time. From Table 3, it can be seen that the congestion prediction method using transfer learning can reduce the number of samples used by more than 50% while maintaining the prediction accuracy.

[0063] Table 2

[0064]

[0065] Table 3

[0066]

[0067] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip congestion prediction method, characterized in that: The following steps are involved: Construct a unit operation set, and construct a search space based on the unit operation set; Using the gradient descent method to search the search space, selecting a neural network architecture and performing iterative updates to obtain an optimal neural network architecture; Determine the target domain and the source domain, obtain chip layout and wiring design atlases of the target domain and the source domain respectively, and select a preset number of chip layout and wiring design drawings to obtain a target training set and a source training atlas; Train a recurrent generative adversarial network based on the target training set and the source training graph set; Auxiliary datasets are obtained based on chip layout and wiring design atlases in the source domain and recurrent generative adversarial networks; The optimal neural network structure is trained based on the target training set and the auxiliary training set to obtain a final chip congestion prediction model, and chip congestion prediction is performed based on the final chip congestion prediction model.

2. The chip congestion prediction method according to claim 1, characterized in that: The unit operation set includes but is not limited to an identity operation, a zeroing operation, a 3x3 depthwise separable convolution, a 3x3 transposed convolution, a 5x5 depthwise separable convolution, a 5x5 transposed convolution, a 3x3 average pooling, and a 3x3 maximum pooling.

3. The chip congestion prediction method according to claim 1, characterized in that: The neural network structure in the search space is parameterized, and the model weights and architecture parameters are updated using an alternating optimization strategy and a gradient descent algorithm to obtain an optimized neural network architecture.

4. The chip congestion prediction method according to claim 1, characterized in that: The process of updating model weights and architecture parameters includes: Obtain a training data set, sample the training data set, input the sampled data into the neural network architecture, calculate the loss function, and update the model weights by gradient descent; sample data in the validation set, calculate the validation loss, and update the architecture parameters by gradient descent. During the training process, the architecture parameters and model weights are optimized alternately.

5. The chip congestion prediction method according to claim 1, characterized in that: After each update, a lightweight single-shot performance evaluation strategy is used to evaluate and obtain the optimal neural network architecture; The lightweight single-shot performance evaluation strategy includes: performing training and verification once after each architecture update to obtain the relative advantages and disadvantages of the performance of different architectures.

6. The chip congestion prediction method according to claim 1, characterized in that: A chip layout and wiring design drawing of a preset proportion is selected from the chip layout and wiring design drawing set in the source domain to obtain a source data atlas; the source data atlas is input into a recurrent generative adversarial network to obtain an auxiliary data set; wherein the chip layout and wiring design drawings of each congestion prediction in the source domain are set to be of equal proportion.

Images