Display driving circuit, display panel and display equipment

Abstract

The invention discloses a display driving circuit, a display panel and display equipment, and the display driving circuit comprises a signal generation module which is configured to generate a first clock signal; the frequency multiplication module is connected with the signal generation module, and the frequency multiplication module is configured to perform frequency multiplication processing on the first clock signal so as to output a second clock signal after frequency multiplication processing; and the pixel driving module comprises a light-emitting unit and at least one switching tube arranged on a current path of the light-emitting unit, and the control end of the switching tube is connected with the frequency doubling module to input a second clock signal. In this way, aging of the transistor in the signal generation module can be reduced, and the service life of the display driving circuit is prolonged.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driving circuit, a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display device is an active self-luminous display device based on organic light-emitting diode materials. Compared with LCD (Liquid Crystal Display), it has the characteristics of high brightness, large operating temperature range, wide color gamut, high contrast and light weight. It is receiving more and more attention in the display field, especially in the consumer electronics field.

[0003] However, since OLED is driven by thin film transistors (TFT), the driving transistor works in the saturation region, and the output current is greatly affected by Vgs (gate-source voltage) and Vds (drain-source voltage). In addition, due to process uniformity issues, the subthreshold swing (SS) is uneven and has certain differences. Therefore, OLED display devices generally use pulse width modulation (PWM).

[0004] Generally, pulse width dimming is achieved by a timing signal output by a scanning driving circuit. However, since a high-frequency timing signal is output, the switching frequency of the TFT in the scanning driving circuit will inevitably increase, thereby accelerating the aging of the TFT in the scanning driving circuit. Summary of the invention

[0005] To solve the above problems, the present application provides a display driving circuit, a display panel and a display device, which can reduce the aging of transistors in a signal generating module and extend the life of the display driving circuit.

[0006] A technical solution adopted by the present application is: to provide a display driving circuit, which includes: a signal generating module, the signal generating module is configured to generate a first clock signal; a frequency multiplication module, connected to the signal generating module, the frequency multiplication module is configured to perform frequency multiplication processing on the first clock signal to output a second clock signal after the frequency multiplication processing; a pixel driving module, the pixel driving module includes a light-emitting unit and at least one switch tube arranged on the current path of the light-emitting unit, and the control end of the switch tube is connected to the frequency multiplication module to input the second clock signal.

[0007] In one embodiment, the frequency multiplication module includes: a logic processing unit, a first input end of the logic processing unit is connected to the signal generation module to input a first clock signal, and an output end of the logic processing unit is connected to the pixel driving module to output a second clock signal; a level trigger unit, a synchronization end of the level trigger unit is connected to the output end of the logic processing unit, and the input end and the output end of the level trigger unit are connected to the second input end of the logic processing unit.

[0008] In one embodiment, there are multiple signal generating modules and logic processing units, and the multiple signal generating modules, the multiple logic processing units and the multiple scanning lines correspond one to one. The synchronization end of the level trigger unit is connected to the output ends of the multiple logic processing units, and the input end and the output end of the level trigger unit are connected to the second input ends of the multiple logic processing units.

[0009] In one embodiment, the frequency multiplication module further includes a plurality of diodes. According to the scanning order of the scanning lines, the cathode of each diode is connected to the output end of the previous logic processing unit of two adjacent logic processing units, and the anode of each diode is connected to the output end of the next logic processing unit of two adjacent logic processing units.

[0010] In one embodiment, the signal generation module and the logic processing unit are arranged on the side of at least one end of the corresponding scan line; and / or the level trigger unit is arranged on the side of at least one end of the corresponding data line.

[0011] In one embodiment, the display driving circuit also includes a compensation module, the input end of the compensation module is connected to the output end of the frequency multiplication module to input the second clock signal, and the output end of the compensation module is connected to the control end of the switch tube; wherein the compensation module is configured to compensate and adjust the potential of the second clock signal to output the adjusted third clock signal to the control end of the switch tube.

[0012] In one embodiment, the compensation module includes: a first transistor, the first end of the first transistor is configured to input a first level signal, and the control end of the first transistor is connected to the output end of the frequency multiplication module to input a second clock signal; a second transistor, the first end of the second transistor is configured to input a second level signal, the control end of the second transistor is connected to the output end of the frequency multiplication module to input the second clock signal, and the second end of the second transistor is connected to the second end of the first transistor and the control end of the switch tube to output a third clock signal.

[0013] In one embodiment, at least one switching tube includes a third transistor and a fourth transistor, and the pixel driving module also includes a driving tube; wherein the first end of the third transistor is configured to input a high voltage signal, the second end of the third transistor is connected to the first end of the driving tube, the first end of the fourth transistor is connected to the second end of the driving tube, the second end of the fourth transistor is connected to the first end of the light-emitting unit, and the second end of the light-emitting unit is configured to input a low voltage signal.

[0014] Another technical solution adopted by the present application is to provide a display panel, which includes the display driving circuit as described above.

[0015] Another technical solution adopted by the present application is to provide a display device, which includes the display panel as described above, and a power supply for supplying power to the display panel.

[0016] The display driving circuit provided by the present application includes: a signal generating module, the signal generating module is configured to generate a first clock signal; a frequency multiplication module, connected to the signal generating module, the frequency multiplication module is configured to perform frequency multiplication processing on the first clock signal to output a second clock signal after the frequency multiplication processing; a pixel driving module, the pixel driving module includes a light-emitting unit and at least one switch tube arranged on the current path of the light-emitting unit, and the control end of the switch tube is connected to the frequency multiplication module to input the second clock signal. Through the above method, in this embodiment, it is not necessary to improve the signal generating module and the pixel driving module in the relevant embodiment, but a frequency multiplication module is added between the signal generating module and the pixel driving module to increase the frequency of the signal. Through the above method, on the one hand, by additionally adding a frequency multiplication module at the end of the signal generating module to adjust the frequency, the problem of the signal generating module generating a high-frequency signal and accelerating the aging of the transistor will not be caused, the load of the signal generating module is reduced, and the life of the signal generating module is extended; on the other hand, by controlling the switch tube to perform high-frequency dimming through the second clock signal after the frequency multiplication, the visual fatigue of the human eye can be reduced, and the damage of the display device to the human eye can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0018] Figure 1 is a structural schematic diagram of an embodiment of a pixel driving circuit provided by the present application;

[0019] Figure 2 is a structural schematic diagram of an embodiment of a signal generating circuit provided by the present application;

[0020] Figure 3 is a structural schematic diagram of an embodiment of a display driving circuit provided by the present application;

[0021] Figure 4 This is a first structural diagram of a frequency multiplication module in one embodiment of the present application;

[0022] Figure 5 is a second structural schematic diagram of a frequency multiplication module in one embodiment of the present application;

[0023] Figure 6 yes Figure 5 A circuit diagram corresponding to an XOR logic processing module;

[0024] Figure 7 yes Figure 6 The corresponding timing diagram;

[0025] Figure 8 is a third structural schematic diagram of a frequency multiplication module in one embodiment of the present application;

[0026] Fig. 9 is a structural schematic diagram of another embodiment of the display driving circuit provided by the present application;

[0027] Fig.10 is a schematic diagram of the structure of a compensation module in one embodiment;

[0028] Fig.11 is a structural schematic diagram of yet another embodiment of a display driving circuit provided by the present application;

[0029] Fig.12 is a schematic structural diagram of an embodiment of a display panel provided by the present application;

[0030] Fig.13 It is a structural schematic diagram of an embodiment of a display device provided in the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0032] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0033] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] See also Figure 1 , Figure 1 : is a schematic diagram of the structure of an embodiment of a pixel driving circuit provided by the present application. The driving of the circuit mainly includes the following three stages:

[0035] Reset stage: N-Scan (nx) signal and P-Scan signal control transistor T4 and transistor T7 to turn on, reset signal Vint is input to the gate of transistor T1 and the anode of light-emitting diode OLED, and reset signal Vint is a low level signal for reset operation.

[0036] Compensation stage: N-Scan signal controls transistor T2 and transistor T3 to turn on. At this time, the voltage at the first end of transistor T1 is Vdata. Since the gate and the second end of transistor T1 are short-circuited, transistor T1 is equivalent to a diode, so the gate voltage of transistor T1 is Vdata-Vth, where Vdata is the voltage of the data signal Data and Vth is the threshold voltage of transistor T1.

[0037] Light-emitting stage: the EM signal controls the transistors T5 and T6 to turn on, a current path is formed between the power supply voltage ELVDD, the transistors T5, T1, T6, the light-emitting diode OLED and the ground voltage ELVSS, and the light-emitting diode OLED emits light.

[0038] It can be understood that the above embodiment only takes a "7T1C" pixel driving circuit as an example. In other embodiments, other pixel driving circuits may also be used, which is not limited here.

[0039] In the above embodiment, since the OLED is driven by a thin film transistor (TFT), the driving transistor works in the saturation region, and the output current is greatly affected by Vgs and Vds. In addition, due to the problem of process uniformity, the subthreshold swing (SS) is uneven and there are certain differences. Therefore, OLED display devices generally use pulse width dimming (PWM). Since PWM dimming is more likely to cause visual fatigue than direct current dimming (DC), high-frequency PWM is used for dimming in this embodiment. That is, when the duty cycle remains unchanged, the higher the frequency of flickering, the less likely it is for the human eye to notice it, thereby reducing the burden on the eyes. This is the principle that high-frequency PWM dimming is relatively more eye-friendly. Specifically, for the above Figure 1 For example, the EM signal is replaced by a high-frequency PWM signal.

[0040] In one embodiment, the above Figure 1 The N-Scan signal, P-Scan signal and EM signal are all timing signals generated by a signal generating circuit, for example, generated by a GOA (Gate Driven on Array, a gate drive integrated on an array substrate) circuit.

[0041] like Figure 2 As shown, Figure 2 1 is a schematic diagram of a structure of an embodiment of a signal generating circuit provided by the present application. The GOA circuit includes cascaded GOA units, each of which includes: Figure 2 The circuit structure shown in FIG. 1 is composed of a large number of transistors and capacitors, and finally outputs the required first clock signal CLK1 through inputting clock signal CK, clock signal XCK, high level signal H, low level signal L and light control signal EMO. Among them, the clock signal CK / XCK input, high level signal H, low level signal L and reset signal, as well as the output signal, the latter is also responsible for the reset of the uplink and the input of the downlink. Through the cascade connection, GOA drives row by row, the first row is triggered by STV, and the last row is reset by the redundant unit, ensuring the stability and efficiency of the system.

[0042] It can be understood that the above embodiment only takes one signal generating circuit as an example. In other embodiments, other circuit structures may also be used, which is not limited here.

[0043] It can be understood that in the relevant embodiments, the above Figure 1 The EM signal required in the embodiment is obtained by Figure 2 The first clock signal CLK1 output in the embodiment is provided. Since the frequency of the EM signal needs to be increased, if Figure 2 The signal generation circuit is improved, in which a large number of transistors are switched at a higher frequency, which accelerates the aging of the transistors.

[0044] See also Figure 3 , Figure 3 1 is a schematic diagram of the structure of an embodiment of a display driving circuit provided in the present application. The display driving circuit 100 includes a signal generating module 10 , a frequency multiplying module 20 and a pixel driving module 30 .

[0045] Among them, the signal generating module 10 is configured to generate a first clock signal CLK1; the frequency multiplying module 20 is connected to the signal generating module 10, and the frequency multiplying module 20 is configured to perform frequency multiplication processing on the first clock signal CLK1 to output a second clock signal CLK2 after the frequency multiplication processing; the pixel driving module 30 includes a light-emitting unit and at least one switch tube arranged on the current path of the light-emitting unit, and the control end of the switch tube is connected to the frequency multiplying module 20 to input the second clock signal CLK2.

[0046] Optionally, in one embodiment, the signal generating module 10 may be as follows: Figure 1 The circuit structure described in the embodiment.

[0047] Optionally, in one embodiment, the pixel driving module 30 may be as follows: Figure 2 The circuit structure described in the embodiment. Wherein, the light emitting unit of the pixel driving module 30 can be as follows Figure 2 For the OLED shown in FIG. , the switch tube can be Figure 2 The transistor T5 and the transistor T6 are shown in FIG. 1 , and the second clock signal CLK2 serves as the EM signal therein.

[0048] Optionally, the frequency multiplication module 20 in this embodiment can be double frequency, triple frequency, quadruple frequency, etc., which is not limited here. As long as the frequency of the second clock signal CLK2 is greater than the frequency of the first clock signal CLK1, it should be included in the limited range of this embodiment.

[0049] It can be understood that in this embodiment, there is no need to improve the signal generating module 10 and the pixel driving module 30 in the related embodiments. For example, there is no need to improve the signal generating module 10 and the pixel driving module 30 in the related embodiments. Figure 1 The pixel driving circuit shown in FIG. Figure 2 The signal generating circuit shown in the figure is improved, and a frequency multiplication module 20 is added between the signal generating module 10 and the pixel driving module 30 to increase the frequency of the signal. In the above manner, on the one hand, by additionally adding the frequency multiplication module 20 at the end of the signal generating module 10 to adjust the frequency, the problem of accelerating the aging of the transistor due to the high-frequency signal generated by the signal generating module 10 will not be caused, the load of the signal generating module 10 will be reduced, and the life of the signal generating module 10 will be extended; on the other hand, by controlling the switch tube to perform high-frequency dimming through the second clock signal after frequency multiplication, the visual fatigue of the human eye can be reduced, and the damage of the display device to the human eye can be reduced.

[0050] Further reading Figure 4 , Figure 4 2 is a first structural diagram of a frequency multiplication module in an embodiment of the present application. The frequency multiplication module 20 includes a logic processing unit 21 and a level trigger unit 22 .

[0051] Among them, the first input end of the logic processing unit 21 is connected to the signal generating module 10 to input the first clock signal CLK1, and the output end of the logic processing unit 21 is connected to the pixel driving module 30 to output the second clock signal CLK2; the synchronization end of the level trigger unit 22 is connected to the output end of the logic processing unit 21, and the input end and the output end of the level trigger unit 22 are connected to the second input end of the logic processing unit 21.

[0052] The logic processing unit 21 is used to perform logic processing on the input first clock signal CLK1 and the output signal of the level trigger unit 22. Taking the frequency doubling as an example, the logic processing unit 21 here can be an exclusive OR logic processing or an exclusive OR logic processing. The level trigger unit 22 is used to generate an output signal (1 or 0) according to the rising edge or falling edge of the first clock signal CLK1. Taking the frequency doubling as an example, the level trigger unit 22 here can be a D trigger, an RS trigger, or a JK trigger, etc.

[0053] Taking double frequency as an example, Figure 5 As shown, Figure 5 2 is a second structural diagram of the frequency multiplication module in one embodiment of the present application. The frequency multiplication module 20 includes an XOR logic processing module and an RS trigger.

[0054] The first input terminal of the XOR logic processing module XOR is configured to input the first clock signal CLK1, and the synchronization terminal of the RS trigger is connected to the S input terminal of the RS trigger and Q* (ie ) output terminal is connected to the second input terminal of the exclusive OR logic processing module XOR.

[0055] Further reading Figure 6 , Figure 7 and Table 1, Figure 6 yes Figure 5 The circuit diagram corresponding to the XOR logic processing module, Figure 7 yes Figure 6 The corresponding timing diagram,Table 1 is the truth table of the RS flip-flop.

[0056] Table 1:

[0057] CP S R <![CDATA[Q n ]]> <![CDATA[Q n+1 ]]> Function 0 × × 0 0 Keep 0 × × 1 1 Keep 1 0 0 0 0 Keep 1 0 0 1 1 Keep 1 0 1 0 0 Set to 0 1 0 1 1 0 Set to 0 1 1 0 0 1 Set to 1 1 1 0 1 1 Set to 1 1 1 1 0 1* indefinite 1 1 1 1 1* indefinite

[0058] Combined with the above Figure 6 , Figure 7 and Table 1, Figure 6 The principle of the double frequency circuit is as follows (within one cycle of the first clock signal CLK1):

[0059] Phase 1: When the first clock signal CLK1 and the node A are both at high levels, transistors T9, T13, and T14 are turned on, and the second clock signal CLK2 is at a high level (ie, VGH).

[0060] In the second stage, when the first clock signal CLK1 is at a high level and the node A is at a low level, the transistors T9, T10, T11, T12, and T15 are turned on, and the second clock signal CLK2 is at a low level (ie, VGL).

[0061] Phase 3: When the first clock signal CLK1 and the node A are both at low levels, the transistors T8, T10, T11, T12, and T14 are turned on, and the second clock signal CLK2 is at a high level (ie, VGH).

[0062] In the fourth stage, when the first clock signal CLK1 is at a low level and the node A is at a high level, the transistors T8, T13, and T15 are turned on, and the second clock signal CLK2 is at a low level (ie, VGL).

[0063] It can be known from the above process that within one cycle of the first clock signal CLK1, the second clock signal CLK2 generates two cycles, that is, the frequency of the second clock signal CLK2 is twice that of the first clock signal CLK1.

[0064] The above-mentioned frequency doubling circuit formed by the XOR logic processing unit and the RS flip-flop is only an example. In other embodiments, other logic processing units and flip-flops may also be used. For example, the frequency doubling circuit may also be formed by the XOR logic processing unit and the D flip-flop, which will not be described in detail here.

[0065] Take the triple frequency as an example, Figure 8 As shown, Figure 8 2 is a third structural diagram of a frequency multiplication module in an embodiment of the present application. The frequency multiplication module 20 includes two JK flip-flops.

[0066] The synchronization terminals of the two JK flip-flops are configured to input the first clock signal CLK1, the Q output terminal of the first JK flip-flop is connected to the J input terminal of the second JK flip-flop, and the J input terminal of the first JK flip-flop is connected to the Q* (i.e. ) output terminal, the Q output terminal of the second JK flip-flop is used to output the second clock signal CLK2.

[0067] See also Fig. 9 , Fig. 9 1 is a schematic diagram of the structure of another embodiment of the display driving circuit provided in the present application. The display driving circuit 100 includes a signal generating module 10 , a frequency multiplication module 20 , a compensation module 40 and a pixel driving module 30 .

[0068] Among them, the signal generating module 10 is configured to generate a first clock signal CLK1; the frequency multiplication module 20 is connected to the signal generating module 10, and the frequency multiplication module 20 is configured to perform frequency multiplication processing on the first clock signal CLK1 to output the second clock signal CLK2 after the frequency multiplication processing; the input end of the compensation module 40 is connected to the output end of the frequency multiplication module 20 to input the second clock signal, and the compensation module is configured to compensate and adjust the potential of the second clock signal CLK2 to output the adjusted third clock signal CLK3, and the output end of the compensation module 40 is connected to the control end of the switch tube in the driving module 30 to output the third clock signal CLK3 to the control end of the switch tube.

[0069] It is understandable that the potential of the second clock signal CLK2 may be unstable after the frequency doubling process. For example, the potentials of high levels in different cycles may not be equal, or glitches may occur in the signal, etc. This will affect the display of the pixel driving module 30 and cause display abnormality. The function of the compensation module 40 is to make the potential more stable.

[0070] Further reading Fig.10 , Fig.10 1 is a schematic diagram of the structure of a compensation module in an embodiment, the compensation module 40 includes a first transistor T16 and a second transistor T17, the first end of the first transistor T16 is configured to input a first level signal, and the control end of the first transistor T16 is connected to the output end of the frequency multiplication module to input the second clock signal CLK2; the first end of the second transistor T17 is configured to input a second level signal, the control end of the second transistor T17 is connected to the output end of the frequency multiplication module to input the second clock signal CLK2, and the second end of the second transistor T17 is connected to the second end of the first transistor T16 and the control end of the switch tube (not shown) to output the third clock signal CLK3.

[0071] In one embodiment, the first transistor T16 is an NMOS transistor, and the second transistor T17 is a PMOS transistor. When the second clock signal CLK2 is at a high level, the first transistor T16 is turned on, the second transistor T17 is turned off, and the third clock signal CLK3 is at a low level (i.e., VGL). When the second clock signal CLK2 is at a low level, the first transistor T16 is turned off, the second transistor T17 is turned on, and the third clock signal CLK3 is at a high level (i.e., VGH). It can be understood that the levels of the second clock signal CLK2 and the third clock signal CLK3 are opposite.

[0072] In the above manner, by adjusting the voltages of VGL and VGH, the level of the third clock signal CLK3 can be adjusted. For example, the high level voltage of the first clock signal CLK1 output by the signal generating module 10 can be set to be relatively low, while the high level voltage of the third clock signal CLK3 can be set to be relatively high according to actual needs, which can also reduce the load of the signal generating module 10, thereby slowing down the aging of the transistors in the signal generating module 10 and extending the life of the signal generating module 10.

[0073] See also Fig.11 , Fig.11 1 is a schematic structural diagram of another embodiment of a display driving circuit provided in the present application. The display driving circuit 100 includes a signal generating module 10, a frequency multiplying module 20, a compensation module 40 and a pixel driving module (not shown).

[0074] Among them, the frequency multiplication module 20 includes a logic processing unit and a level trigger unit, the number of signal generating modules 10, logic processing units and compensation modules 40 is multiple, multiple signal generating modules 10, multiple logic processing units, and compensation modules 40 correspond one-to-one to multiple scan lines, the synchronization end of the level trigger unit is connected to the output ends of the multiple logic processing units, and the input end and output end of the level trigger unit are connected to the second input ends of the multiple logic processing units.

[0075] The frequency multiplication module 20 further includes a plurality of diodes. According to the scanning order of the scanning lines, the cathode of each diode is connected to the output end of the previous logic processing unit of two adjacent logic processing units, and the anode of each diode is connected to the output end of the next logic processing unit of two adjacent logic processing units.

[0076] The above method takes the XOR logic processing unit and the RS trigger as an example, the number of the signal generation module 10, the XOR logic processing unit and the compensation module 40 is multiple, the multiple signal generation modules 10, the multiple XOR logic processing units, and the compensation module 40 correspond to the multiple scan lines one by one, the synchronization end of the RS trigger is connected to the output ends of the multiple XOR logic processing units, and the input end S and the output end Q* of the RS trigger are connected to the second input ends of the multiple XOR logic processing units. The cathode of each diode is connected to the output end of the previous XOR logic processing unit of the two adjacent XOR logic processing units, and the anode of each diode is connected to the output end of the next XOR logic processing unit of the two adjacent XOR logic processing units.

[0077] It can be understood that since the display circuit adopts a line-by-line scanning method, when a certain line is scanned, the unidirectional conduction principle of the diode is used to prevent the current from flowing to the next line.

[0078] In addition, the display panel generally includes an AA area for display, a driving circuit area arranged on the left and right sides of the AA area, and a circuit board area arranged on the lower side of the AA area. In one embodiment, the signal generating module 10 and the logic processing unit (such as an XOR logic processing unit) are arranged on the side of at least one end of the corresponding scanning line, that is, on the left and right sides of the AA area, and the level trigger unit (such as an RS trigger) is arranged on the side of at least one end of the corresponding data line, that is, on the lower side of the AA area.

[0079] Optionally, the level trigger unit may be specifically disposed on a circuit board below, or inside a TDDI (Touch and Display Driver Integration).

[0080] See also Fig.12 , Fig.12 1 is a schematic diagram of the structure of an embodiment of a display panel provided in the present application. The display panel 120 includes a display driving circuit 100. The display driving circuit 100 is the display driving circuit 100 introduced in the above embodiment.

[0081] Optionally, the display panel 120 is an OLED display panel. The signal generation module in the display driving circuit 100 and the logic processing unit in the frequency multiplication module can be arranged on the left and right sides of the AA area of ​​the display panel 120, and the level trigger unit in the frequency multiplication module can be arranged on the lower side of the AA area of ​​the display panel 120.

[0082] See also Fig.13 , Fig.13 It is a structural schematic diagram of an embodiment of a display device provided in the present application. The display device 130 includes a display panel 120 and a power supply 131. The display panel 120 is the display panel 120 introduced in the above embodiment. The power supply 131 is connected to the display panel 120 to supply power to the display panel 120.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0084] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0086] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display driving circuit, characterized in that: The display driving circuit comprises: A signal generating module, wherein the signal generating module is configured to generate a first clock signal; a frequency multiplication module, connected to the signal generation module, and configured to perform frequency multiplication processing on the first clock signal to output a second clock signal after the frequency multiplication processing; A pixel driving module includes a light-emitting unit and at least one switch tube arranged on a current path of the light-emitting unit, wherein a control end of the switch tube is connected to the frequency multiplication module to input the second clock signal.

2. The display driving circuit according to claim 1, characterized in that: The frequency multiplication module comprises: a logic processing unit, wherein a first input end of the logic processing unit is connected to the signal generating module to input the first clock signal, and an output end of the logic processing unit is connected to the pixel driving module to output the second clock signal; A level trigger unit, wherein the synchronization end of the level trigger unit is connected to the output end of the logic processing unit, and the input end and the output end of the level trigger unit are connected to the second input end of the logic processing unit.

3. The display driving circuit according to claim 2, characterized in that: There are multiple signal generating modules and multiple logic processing units, and the multiple signal generating modules, the multiple logic processing units and the multiple scanning lines correspond one to one. The synchronization end of the level trigger unit is connected to the output ends of the multiple logic processing units, and the input end and the output end of the level trigger unit are connected to the second input ends of the multiple logic processing units.

4. The display driving circuit according to claim 3, characterized in that: The frequency multiplication module also includes multiple diodes. According to the scanning order of the scanning lines, the cathode of each diode is connected to the output end of the previous logic processing unit of the two adjacent logic processing units, and the anode of each diode is connected to the output end of the latter logic processing unit of the two adjacent logic processing units.

5. The display driving circuit according to claim 2 or 3, characterized in that: The signal generating module and the logic processing unit are arranged on the side of at least one end of the corresponding scanning line; and / or The level trigger unit is arranged on the side of at least one end of the corresponding data line.

6. The display driving circuit according to claim 1, characterized in that: The display driving circuit further comprises a compensation module, wherein an input end of the compensation module is connected to an output end of the frequency multiplication module to input the second clock signal, and an output end of the compensation module is connected to a control end of the switch tube; The compensation module is configured to perform compensation adjustment on the potential of the second clock signal to output an adjusted third clock signal to the control end of the switch tube.

7. The display driving circuit according to claim 6, characterized in that: The compensation module comprises: A first transistor, wherein a first end of the first transistor is configured to input a first level signal, and a control end of the first transistor is connected to an output end of the frequency multiplication module to input the second clock signal; A second transistor, wherein the first end of the second transistor is configured to input a second level signal, the control end of the second transistor is connected to the output end of the frequency multiplication module to input the second clock signal, and the second end of the second transistor is connected to the second end of the first transistor and the control end of the switch tube to output the third clock signal.

8. The display driving circuit according to claim 1, characterized in that: The at least one switch tube includes a third transistor and a fourth transistor, and the pixel driving module also includes a driving tube; Among them, the first end of the third transistor is configured to input a high voltage signal, the second end of the third transistor is connected to the first end of the driving tube, the first end of the fourth transistor is connected to the second end of the driving tube, the second end of the fourth transistor is connected to the first end of the light-emitting unit, and the second end of the light-emitting unit is configured to input a low voltage signal.

9. A display panel, characterized in that: The display panel comprises the display driving circuit as claimed in any one of claims 1 to 8.

10. A display device, characterized in that: The display device includes the display panel according to claim 9, and a power source for supplying power to the display panel.

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