Preparation method of integrated packaging structure with buried power rail

Abstract

The invention provides a preparation method of an integrated packaging structure with a buried power rail, and the method comprises the steps: carrying out the oxygen ion implantation on the front surface of a first semiconductor substrate, carrying out the high-temperature annealing, enabling the oxygen ions to react with silicon to form a first silicon oxide layer, and replacing a germanium-silicon layer with the first silicon oxide layer to serve as a thinning stop layer during the grinding, epitaxial silicon is grown on the front surface of the first semiconductor substrate, an STI groove and a buried power rail are prepared on the epitaxial silicon, and a nanometer silicon through hole is formed in the back surface of the first semiconductor substrate and is electrically connected with the buried power rail; the technical requirement of growing epitaxial silicon on the front surface of the first semiconductor substrate is simpler than that of growing a germanium-silicon layer on the front surface of the first semiconductor substrate, the control is easier in the actual production process, and a wet etching solution is not needed to remove the germanium-silicon layer, so that the wafer is not damaged, the production yield is greatly improved, and the production cost is reduced. Furthermore, the requirement of epitaxial silicon on equipment is relatively low, so that the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for preparing an integrated packaging structure with a buried power rail. Background Art

[0002] In existing integrated packaging structures, the power supply network is mostly set on the front side of the wafer, so as to provide a continuous supply of power and reference voltage (i.e., VDD and VSS) to the active devices on the chip through the power supply network. However, as the size of integrated circuits gradually shrinks, the back-end process flow of integrated circuits can hardly keep up with the pace of transistor scaling, and there is also a signal network in the front area of ​​the wafer. Therefore, it is becoming increasingly difficult to arrange the power supply network on the front side of the chip.

[0003] Backside power supply technology is expected to solve the above-mentioned problems. The starting point of backside power supply technology is to separate the power transmission network from the signal network by moving the entire power supply network structure to the back side of the wafer. The wafer is only used as a carrier, and electrons do not need to pass through the complex back-end process stack, so that power can be directly delivered to the standard battery through wider and less resistive metal wires. It is expected to reduce IR voltage drop, improve power transmission performance, reduce wiring congestion in the back-end process, and further expand the height of standard units.

[0004] At present, in the commonly used back power supply technology, when preparing devices, it is necessary to first epitaxially grow a layer of germanium silicon layer on the surface of the wafer, and the germanium silicon layer can be used as a stop layer when the wafer is ground and thinned. Then, silicon is epitaxially grown on the surface of the germanium silicon layer, and active areas, STI grooves, and buried power rails and other devices are prepared on the epitaxial silicon layer. The wafer prepared with the device is bonded to another wafer on the front side, and the back of the wafer prepared with the device is thinned to the germanium silicon layer and the germanium silicon layer is removed by a wet etching process. Finally, a nano-silicon through-hole connecting the buried power rail is prepared. However, due to the high technical requirements of the epitaxial germanium silicon layer, it is difficult to control it in the actual production process, resulting in a low yield rate of the product. In addition, the epitaxial germanium silicon layer also has high requirements for equipment, thereby increasing the production cost in disguise. In addition, when using a wet etching solution to remove the germanium silicon layer, it is easy to cause the surface of the wafer to be uneven, thereby damaging the wafer, further reducing the production yield rate. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, an object of the present invention is to provide a method for preparing an integrated packaging structure with a buried power rail, which is used to solve the problems of difficult control in the production process, easy damage to the wafer, low production yield and high production cost caused by the use of an epitaxial germanium silicon layer in the preparation of devices in the existing back-side power supply technology.

[0006] To achieve the above objectives and other related objectives, the present invention provides a method for preparing an integrated packaging structure with a buried power rail, the preparation method comprising:

[0007] Providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a front surface and a back surface that are oppositely disposed;

[0008] Performing oxygen ion implantation and high temperature annealing on the front surface of the first semiconductor substrate to form a first silicon oxide layer in the first semiconductor substrate, wherein the first silicon oxide layer divides the first semiconductor substrate into a first region and a second region;

[0009] forming an epitaxial silicon layer on the upper surface of the first region;

[0010] forming an active area on the epitaxial silicon layer and a plurality of STI trenches for isolating the active area;

[0011] forming a buried power rail between the plurality of STI trenches, and then inverting the first semiconductor substrate;

[0012] Providing a second semiconductor substrate and forming a second silicon oxide layer on the front surface of the second semiconductor substrate;

[0013] Bonding the second silicon oxide layer to the epitaxial silicon layer and grinding the back side of the first semiconductor substrate to remove the second region to expose the first silicon oxide layer;

[0014] Etching and removing the first silicon oxide layer to expose the first region;

[0015] The first region is etched to form a through silicon via and the through silicon via is filled to form a conductive contact electrically connected to the buried power rail, wherein a top surface of the conductive contact is flush with a top of the first region.

[0016] Optionally, the step of forming the conductive contact comprises: first forming a barrier layer in the through silicon via, the barrier layer covering the bottom wall of the through silicon via, forming a seed layer in the through silicon via that completely covers the barrier layer and the bottom wall of the through silicon via, growing a conductive material at the bottom of the seed layer and performing a planarization process on the conductive material.

[0017] Optionally, the conductive material and the buried power rail include refractory metals such as tungsten or ruthenium.

[0018] Optionally, the thickness of the first semiconductor substrate is 300 μm to 1000 μm.

[0019] Optionally, the epitaxial silicon layer has a thickness of 5 μm to 100 μm.

[0020] Optionally, the oxygen ion implantation energy for forming the first silicon oxide layer is 1 keV to 50 keV and the implantation dose is 5e13 / cm 2 ~10e13 / cm 2 .

[0021] Optionally, the implantation depth of oxygen ions into the first silicon oxide layer is 0.5 μm to 10 μm.

[0022] Optionally, the spacing between the through silicon vias is 50 μm to 130 μm.

[0023] Optionally, the through silicon via and the buried power rail are arranged opposite to each other and have the same size.

[0024] Optionally, before forming the through silicon via, the first region of the first substrate may be etched to remove the first region of the first substrate.

[0025] As described above, a method for preparing an integrated packaging structure with a buried power rail of the present invention has the following beneficial effects: oxygen ion implantation is performed on the front side of the first semiconductor substrate, and after high-temperature annealing, the oxygen ions react with silicon to form a first silicon oxide layer inside the first semiconductor substrate. When grinding and thinning are performed, the first silicon oxide layer can replace the silicon germanium layer as a grinding and thinning stop layer, and epitaxial silicon is grown on the front side of the first semiconductor substrate and STI grooves and buried power rails are prepared on the epitaxial silicon, and nano-silicon through-holes are formed on the back side of the first semiconductor substrate to be electrically connected to the buried power rail. Since the technical requirements for growing epitaxial silicon on the front side of the first semiconductor substrate are simpler than those for growing an epitaxial silicon germanium layer on the front side of the first semiconductor substrate, it is easier to control in the actual production process. In addition, there is no need to use a wet etching solution to remove the silicon germanium layer, so that no damage is caused to the wafer, which greatly improves the production yield. Furthermore, the requirements of epitaxial silicon on equipment are relatively low, thereby reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart showing the steps of a method for preparing an integrated package structure with buried power rails according to the present invention.

[0027] Figure 2 It is a cross-sectional schematic diagram of a first semiconductor substrate in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0028] Figure 3 It is a cross-sectional schematic diagram showing the formation of a first silicon oxide layer in the first semiconductor substrate in the method for preparing the integrated package structure with buried power rails of the present invention.

[0029] Figure 4It is a cross-sectional schematic diagram showing the formation of an epitaxial silicon layer in the method for preparing an integrated packaging structure with a buried power rail according to the present invention.

[0030] Figure 5 It is a cross-sectional schematic diagram showing the formation of STI trenches in the method for preparing an integrated package structure with buried power rails according to the present invention.

[0031] Figure 6 It is a cross-sectional schematic diagram showing the formation of an initial power rail groove in the method for preparing an integrated package structure with a buried power rail of the present invention.

[0032] Figure 7 It is a cross-sectional schematic diagram showing the formation of a buried power rail in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0033] Figure 8 It is a cross-sectional schematic diagram showing the first semiconductor substrate being inverted in the method for preparing the integrated packaging structure with buried power rails of the present invention.

[0034] Fig. 9 It is a cross-sectional schematic diagram showing the formation of a second silicon oxide layer in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0035] Fig.10 It is a cross-sectional schematic diagram showing the back side of the first semiconductor substrate after grinding in the method for preparing the integrated package structure with buried power rails of the present invention.

[0036] Fig.11 It is a cross-sectional schematic diagram showing the first region in the method for preparing the integrated package structure with buried power rails of the present invention.

[0037] Fig.12 It is a cross-sectional schematic diagram showing the formation of a through silicon via in the method for preparing an integrated packaging structure with a buried power rail according to the present invention.

[0038] Fig.13 It shows a cross-sectional schematic diagram of an integrated package structure with a buried power rail prepared by the method for preparing the integrated package structure with a buried power rail of the present invention.

[0039] Component number description

[0040] 101, first semiconductor substrate; 1011, front side; 1012, back side; 1013, first region; 1014, second region; 102, first silicon oxide layer; 103, epitaxial silicon layer; 104, active region; 105, STI groove; 107, initial power rail groove; 108, buried power rail; 109, second semiconductor substrate; 110, second silicon oxide layer; 111, through silicon via; 112, barrier layer; 113, conductive contact; S1~S9, steps. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0043] It should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the above components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0044] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limitations of the present invention. As used herein, unless the context otherwise clearly indicates, the singular form "a (kind / person)" is also intended to include the plural form. It will also be understood that when the terms "comprise" and its variations, "include" and its variations are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations are not excluded.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0046] See also Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0047] This embodiment provides a method for preparing an integrated packaging structure with a buried power rail. Figure 1 , which is a flow chart of the steps of the preparation method, and the preparation method comprises the following steps:

[0048] S1: providing a first semiconductor substrate 101, wherein the first semiconductor substrate 101 comprises a front surface 1011 and a back surface 1012 which are arranged opposite to each other;

[0049] S2: performing oxygen ion implantation and high temperature annealing on the front surface 1011 of the first semiconductor substrate 101 to form a first silicon oxide layer 102 in the first semiconductor substrate 101 , wherein the first silicon oxide layer 102 divides the first semiconductor substrate 101 into a first region 1013 and a second region 1014 ;

[0050] S3: forming an epitaxial silicon layer 103 on the upper surface of the first region 1013;

[0051] S4: forming an active area 104 and a plurality of STI trenches 105 for isolating the active area 104 on the epitaxial silicon layer 103;

[0052] S5: forming a buried power rail 108 between the plurality of STI trenches 105, and then inverting the first semiconductor substrate 101;

[0053] S6: providing a second semiconductor substrate 109 and forming a second silicon oxide layer 110 on the front surface of the second semiconductor substrate 109;

[0054] S7: bonding the second silicon oxide layer 110 to the epitaxial silicon layer 103 and grinding the back side 1012 of the first semiconductor substrate 101 to remove the second region 1014 to expose the first silicon oxide layer 102;

[0055] S8: etching and removing the first silicon oxide layer 102 to expose the first region 1013;

[0056] S9: etching the first region 1013 to form a through silicon via 111 and filling the through silicon via 111 to form a conductive contact 113 electrically connected to the buried power rail 108 , wherein a top surface of the conductive contact 113 is flush with a top of the first region 1013 .

[0057] The following is a further introduction to the preparation method of the integrated packaging structure with buried power rails with reference to the accompanying drawings, as follows:

[0058] In step S1, see Figure 1 and Figure 2 , providing a first semiconductor substrate 101, wherein the first semiconductor substrate 101 includes a front side 1011 and a back side 1012 that are oppositely arranged.

[0059] Optionally, the material of the first semiconductor substrate 101 includes but is not limited to one of a bare silicon (Si) wafer, gallium nitride, silicon carbide or glass, and the thickness of the first semiconductor substrate 101 is 300μm to 1000μm, for example, 300μm, 650μm or 1000μm, and its shape can be circular, square or any other desired shape.

[0060] Specifically, in this embodiment, the first semiconductor substrate 101 is a bare silicon (Si) wafer, and the thickness of the first semiconductor substrate 101 is 650 μm.

[0061] In step S2, see Figure 1 and Figure 3 Oxygen ion implantation and high temperature annealing are performed on the front surface 1011 of the first semiconductor substrate 101 to form a first silicon oxide layer 102 in the first semiconductor substrate 101. The first silicon oxide layer 102 divides the first semiconductor substrate 101 into a first region 1013 and a second region 1014.

[0062] Optionally, the oxygen ion implantation energy for forming the first silicon oxide layer 102 is 1 keV to 50 keV and the implantation dose is 5e13 / cm 2 ~10e13 / cm 2 , the implantation depth of oxygen ions in the first silicon oxide layer 102 is 0.5 μm to 10 μm.

[0063] Specifically, in the present embodiment, oxygen ion implantation is first performed on the front surface 1011 of the first semiconductor substrate 101. At this time, the silicon layer on the front surface 1011 of the first semiconductor substrate 101 is destroyed due to the implantation of high-energy oxygen ions. Then, a high-temperature annealing process is performed on the first semiconductor substrate 101 so that the silicon inside the first semiconductor substrate 101 reacts with the oxygen ions to form a first silicon oxide layer 102. The silicon layer on the front surface 1011 of the first semiconductor substrate 101 will be recrystallized under the action of high-temperature annealing, so that the formed first silicon oxide layer 102 is located inside the first semiconductor substrate 101. The implantation energy of the oxygen ions when forming the first silicon oxide layer 102 is 1keV to 50keV and the implantation dose is 5e13 / cm 2 ~10e13 / cm 2 In this embodiment, the depth of the formed first silicon oxide layer 102 is 0.5 μm to 10 μm, and the first silicon oxide layer 102 divides the first semiconductor substrate 101 into a first region 1013 and a second region 1014, wherein the first region 1013 is a recrystallized silicon layer. In this embodiment or other further embodiments, the high temperature annealing when forming the first silicon oxide layer 102 may include annealing the first semiconductor substrate 101 at a temperature of about 650° C. or greater (such as greater than about 700° C. or greater than about 800° C.).

[0064] In step S3, see Figure 1 and Figure 4 , an epitaxial silicon layer 103 is formed on the upper surface of the first region 1013.

[0065] Optionally, after the oxygen ion implantation is completed, since the first region 1013 is a silicon layer after recrystallization, but the silicon layer after recrystallization will have certain crystal defects, its crystal quality cannot meet the requirements for manufacturing devices, so it is necessary to grow another layer of epitaxial silicon layer 103 above the first region 1013 so that the subsequently manufactured devices meet the quality requirements, and the thickness of the epitaxial silicon layer 103 is 5μm to 100μm, and the thickness of different epitaxial silicon layers 103 is adapted to different device manufacturing needs. In other embodiments, the thickness of the epitaxial silicon layer 103 can also be flexibly selected according to the requirements of device manufacturing.

[0066] In step S4, see Figure 1 and Figure 5 An active region 104 and a plurality of STI trenches 105 for isolating the active region 104 are formed on the epitaxial silicon layer 103 .

[0067] Specifically, ion implantation is first performed on the top of the epitaxial silicon layer 103 to form an active area 104, and then a trench isolation process is performed in the active area 104 to form a plurality of STI trenches 105. The shape of the STI trenches 105 can be controlled by controlling etching parameters. For example, a dry etching process in which the longitudinal etching rate is equivalent to the lateral etching rate can be used to obtain an STI trench 105 with a square cross-sectional shape. This method does not add additional operations to the etching process and is simple and easy to implement. The plurality of STI trenches 105 obtained by the above process are independent structures.

[0068] In step S5, refer to Figure 1 , Figure 6 , Figure 7 and Figure 8 , forming a buried power rail 108 between the plurality of STI trenches 105 , and then inverting the first semiconductor substrate 101 .

[0069] Specifically, in this embodiment, the step of forming the buried power rail 108 between the plurality of STI grooves 105 is as follows: when forming the plurality of STI grooves 105, an initial power rail groove 107 is reserved on the active area 104, such as Figure 6 As shown, the initial power rail trench 107 is located between the STI trenches 105 and exposes the epitaxial silicon layer 103. The exposed epitaxial silicon layer 103 is etched using a patterned mask process to form a power rail trench located in the epitaxial silicon layer 103. A conductive material is filled in each power rail trench, and then a chemical deposition process is performed on the active area 104, so that the buried power rail is completely surrounded or encapsulated by the active area 104, as shown in FIG. Figure 7 After forming the buried power rail 108, the first semiconductor substrate 101 is also turned upside down so that the front side 1011 of the first semiconductor substrate 101 can be bonded with other unpatterned semiconductor substrates.

[0070] In step S6, refer to Figure 1 and Fig. 9 , providing a second semiconductor substrate 109 and forming a second silicon oxide layer 110 on the front surface of the second semiconductor substrate 109 .

[0071] Optionally, the material of the second semiconductor substrate 109 includes, but is not limited to, a bare silicon (Si) wafer, gallium nitride, silicon carbide or glass, and its shape may be circular, square or any other desired shape.

[0072] Preferably, the second semiconductor substrate 109 is a bare silicon (Si) wafer, so that the material of the second semiconductor substrate 109 is consistent with the material of the first semiconductor substrate 101, so as to achieve a better bonding effect, and a second silicon oxide layer 110 is formed on the front side of the second semiconductor substrate 109 by a thermal oxidation process, so that the second silicon oxide layer 110 can form a silicon / silicon dioxide bond with the active area 104, wherein the formed second silicon oxide layer 110 can act as an insulating layer on the one hand, and on the other hand, it can also improve the bonding strength between the first semiconductor substrate 101 and the second semiconductor substrate 109.

[0073] In step S7, refer to Figure 1 and Fig.10 , bonding the second silicon oxide layer 110 to the epitaxial silicon layer 103 and grinding the back side 1012 of the first semiconductor substrate 101 to remove the second region 1014 to expose the first silicon oxide layer 102 .

[0074] Specifically, Fig.10 As shown, the second semiconductor substrate 109 is bonded to the first semiconductor substrate 101, so that the second silicon oxide layer 110 is contact-bonded with the active area 104. Since the first silicon oxide layer 102 is formed inside the first semiconductor substrate 101, the hardness of the first silicon oxide layer 102 is greater than that of the first semiconductor substrate 101. Therefore, the first silicon oxide layer 102 can be used as a stop layer for grinding. When grinding the back side 1012 of the first semiconductor substrate 101, the second area 1014 can be removed to expose the first silicon oxide layer 102.

[0075] In step S8, refer to Figure 1 and Fig.11 , the first silicon oxide layer 102 is etched away to expose the first region 1013 .

[0076] Specifically, the first silicon oxide layer 102 is further removed by a dry etching process, thereby exposing the first region 1013 of the first semiconductor substrate 101 .

[0077] Optionally, the first region 1013 may be removed by etching to expose the epitaxial silicon layer 103 .

[0078] In step S9, refer to Figure 1 , Fig.12 and Fig.13 , the first region 1013 is etched to form a through silicon via 111 and the through silicon via 111 is filled to form a conductive contact 113 electrically connected to the buried power rail 108 , wherein the top surface of the conductive contact 113 is flush with the top of the first region 1013 .

[0079] The steps of forming the conductive contact 113 include: first forming a barrier layer 112 in the silicon via 111, the barrier layer 112 covers the side wall of the silicon via 111, forming a seed layer in the silicon via 111 that completely covers the barrier layer 112 and the bottom wall of the silicon via 111, growing a conductive material at the bottom of the seed layer and performing a planarization process on the conductive material, and finally forming the conductive contact 113.

[0080] Specifically, Fig.12 As shown, the first region 1013 is patterned and etched to form through silicon vias 111, and the spacing between the through silicon vias 111 is 50 μm to 130 μm, for example, 50 μm, 90 μm or 130 μm, wherein the through silicon vias 111 are arranged opposite to the buried power rail 108 and have the same size, such as Fig.13 As shown, a barrier layer 112 is first formed in the through silicon via 111. The formation of the barrier layer 112 includes depositing a dielectric material layer on the first region 1013 or thermally oxidizing the first region 1013 of the first semiconductor substrate 101 to form the barrier layer 112. The barrier layer 112 covers the sidewalls of the through silicon via 111 and the non-through silicon via 111 region of the first region 1013. Then, a seed layer is deposited on the barrier layer 112. The seed layer completely covers the pad dielectric layer 112 lining the sidewalls of the through silicon via 111 and the bottom wall of the through silicon via 111. Finally, a conductive material is grown from the bottom of the seed layer, and a planarization process is performed on the protruding conductive material so that the top of the conductive material is flush with the top of the barrier layer 112. In this embodiment or other embodiments, the conductive material and the buried power rail 108 include refractory metals such as tungsten or ruthenium or any other suitable metal.

[0081] In summary, the present invention provides a method for preparing an integrated packaging structure with a buried power rail 108, by implanting oxygen ions on the front side of the first semiconductor substrate, and after high temperature annealing, the oxygen ions react with silicon to form a first silicon oxide layer inside the first semiconductor substrate, and the first silicon oxide layer can replace the silicon germanium layer as a grinding and thinning stop layer when grinding and thinning, and epitaxial silicon is grown on the front side of the first semiconductor substrate and STI grooves and buried power rails are prepared on the epitaxial silicon, and nano silicon through holes are formed on the back side of the first semiconductor substrate to be electrically connected to the buried power rail. Since the technical requirements for growing epitaxial silicon on the front side of the first semiconductor substrate are simpler than epitaxially growing a silicon germanium layer on the front side of the first semiconductor substrate, the actual production process is easier to control. In addition, there is no need to use a wet etching solution to remove the silicon germanium layer, so that the wafer will not be damaged, and the production yield is greatly improved. Furthermore, the requirements of epitaxial silicon on equipment are relatively low, thereby reducing the production cost. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an integrated package structure with a buried power rail, characterized in that: The preparation method comprises: Providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a front surface and a back surface that are oppositely disposed; Performing oxygen ion implantation and high temperature annealing on the front surface of the first semiconductor substrate to form a first silicon oxide layer in the first semiconductor substrate, wherein the first silicon oxide layer divides the first semiconductor substrate into a first region and a second region; forming an epitaxial silicon layer on the upper surface of the first region; forming an active area on the epitaxial silicon layer and a plurality of STI trenches for isolating the active area; forming a buried power rail between the plurality of STI trenches and inverting the first semiconductor substrate; Providing a second semiconductor substrate and forming a second silicon oxide layer on the front surface of the second semiconductor substrate; Bonding the second silicon oxide layer to the epitaxial silicon layer and grinding the back side of the first semiconductor substrate to remove the second region to expose the first silicon oxide layer; Etching and removing the first silicon oxide layer to expose the first region; The first region is etched to form a through silicon via, and the through silicon via is filled to form a conductive contact electrically connected to the buried power rail, wherein a top surface of the conductive contact is flush with a top of the first region.

2. The preparation method according to claim 1, characterized in that: The steps of forming the conductive contact include: first forming a barrier layer in the silicon via, the barrier layer covers the bottom wall of the silicon via, forming a seed layer in the silicon via that completely covers the barrier layer and the bottom wall of the silicon via, growing a conductive material at the bottom of the seed layer and performing a planarization process on the conductive material.

3. The preparation method according to claim 1, characterized in that: The conductive material and the buried power rail include refractory metals such as tungsten or ruthenium.

4. The preparation method according to claim 1, characterized in that: The thickness of the first semiconductor substrate is 300 μm to 1000 μm.

5. The preparation method according to claim 1, characterized in that: The thickness of the epitaxial silicon layer is 5 μm to 100 μm.

6. The preparation method according to claim 1, characterized in that: The oxygen ion implantation energy for forming the first silicon oxide layer is 1 keV to 50 keV and the implantation dose is 5e13 / cm 2 ~10e13 / cm 2 .

7. The preparation method according to claim 1, characterized in that: The implantation depth of oxygen ions into the first silicon oxide layer is 0.5 μm to 10 μm.

8. The preparation method according to claim 1, characterized in that: The spacing between the through silicon vias is 50 μm to 130 μm.

9. The preparation method according to claim 1, characterized in that: The through silicon via and the buried power rail are arranged opposite to each other and have the same size.

10. The preparation method according to claim 1, characterized in that: Before forming the through silicon via, the first region of the first substrate may be etched to remove the first region of the first substrate.

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