Stacked packaging structure corresponding to wafer back power supply of chips of 2nm and below

Abstract

The invention provides a stacked packaging structure corresponding to wafer back power supply of chips of 2nm and below, and high-efficiency and low-loss power supply is realized through accurate correspondence of wafer back power supply metal contacts on a carrier plate and chip back metal contacts in combination with a conductive network constructed by vertical and transverse metal blocks. According to the structure, a signal transmission path is optimized, signal delay and loss are remarkably reduced, and the working efficiency and performance of the chip are improved. The stacking design makes full use of a three-dimensional space, the carrier plate, the substrate, the adapter plate and the chip are closely integrated, and the utilization rate of the packaging space is greatly improved. The conductive network and the solder ball connection enhance the packaging mechanical strength, and improve the vibration and impact resistance. And the vertical metal blocks have conductive and supporting functions, so that the structural stability is enhanced. The packaging size of the first chips in flip connection is reduced, the density is improved, and the pinboard provides a heightening effect, so that subsequent connection is facilitated. The chip packaging efficiency, performance and stability are comprehensively improved, and the method is suitable for the field of high-end chip packaging.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a stacked packaging structure corresponding to back-side power supply of chips with a nanometer (nm) or less. Background Art

[0002] With the rapid development of semiconductor technology, especially in the 2nm and below process era, the integration and performance of chips have been significantly improved. However, this technological advancement has put forward higher requirements for chip packaging technology. Traditional packaging technology has encountered many challenges when facing chips with 2nm and below process.

[0003] First, due to the significant increase in chip power density and the surge in the number of transistors, the resistance control of the power supply line has become particularly critical. High resistance not only leads to energy waste, but also may cause voltage drop, seriously affecting the stability and performance of the chip. Secondly, high power consumption brings greater heat generation, which puts higher requirements on the heat dissipation capacity of the chip. If the heat cannot be effectively dissipated, the chip may suffer performance degradation or damage due to overheating. In addition, the existing packaging technology faces the problem of physical size control when facing high-end chips.

[0004] In view of the above problems, how to further reduce the package size while ensuring the stability and reliability of the package structure to meet the needs of increasingly miniaturized electronic devices has become an issue that needs to be solved urgently. Summary of the invention

[0005] The present invention is a stacked packaging structure for back-side power supply of chips of 2nm and below, aiming to solve the problems existing in the existing packaging technology.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A stacking packaging structure corresponding to back-end power supply of chips of 2nm and below, characterized in that it includes a carrier 100 and a chip packaging structure 300 stacked on the carrier 100 through a first solder ball 200, the chip packaging structure 300 includes: a substrate 1, an adapter board 2 connected to the upper surface of the substrate 1, and a first chip 3 of 2nm and below thickness connected to the upper surface of the adapter board 2 in a flip-chip manner; a plurality of first metal contacts 31 are provided on the back of the first chip 3, and the carrier 100 has a plurality of back-end power supply metal contacts 11 formed on its upper surface corresponding to the number of the first metal contacts 31, a first conductive material layer 41 is provided on the surface of each first metal contact 31, each back-end power supply metal contact 11 is connected to a vertical metal block 5 through a second conductive material layer 42, and a third conductive material layer 43 is provided on the upper surface of each vertical metal block 5; the upper surface of each vertical metal block 5 is at the same height as the back of the first chip 3; the first conductive material layer 41 and the third conductive material layer 43 are conductively connected through a horizontal metal block 6.

[0008] Preferably, the carrier 100 is provided with a chip packaging structure installation area 110 and a back power supply area 120 arranged around the chip packaging structure installation area 110, the carrier 100 is provided with the back power supply metal contact 11 in the back power supply area 120, and is provided with a plurality of first solder joints 101 embedded in the top of the chip packaging structure installation area 110; the substrate 1 is provided with a second solder joint 12 embedded in the bottom, and the first solder joint 101 is connected to the second solder joint 12 in a one-to-one correspondence through a first solder ball 200.

[0009] Preferably, the substrate 1 has a plurality of second solder balls 13 formed on its upper surface, and the adapter board 2 has a plurality of third solder points 21 protruding from its lower surface and correspondingly connected to the second solder balls 13; the first chip 3 has a plurality of second metal contacts 32 on the front side, and the adapter board 2 has a fourth solder point 22 embedded in the top and bonded to the second metal contact 32 on its upper surface.

[0010] Preferably, the carrier 100 forms a vertical interlayer via 14 therein, and a multi-layer vertically connected circuit layer structure 15 is provided in the interlayer via 14, the top circuit layer of the circuit layer structure 15 serves as the back-end power supply metal contact 11, and the bottom circuit layer is exposed on the lower surface of the carrier 100.

[0011] Preferably, the vertical metal block 5 and the horizontal metal block 6 are both made of metal with high conductivity.

[0012] Preferably, a filling glue layer 8 for filling the gap is provided in the gap between the lower surface of the adapter plate 2 and the upper surface of the base plate 1 .

[0013] Preferably, a plastic sealing layer 9 for sealing all components into one is provided on the upper surface of the substrate 1 .

[0014] Preferably, the first conductive material layer 41 , the second conductive material layer 42 , and the third conductive material layer 43 are solder paste layers or conductive adhesive layers.

[0015] Preferably, the vertical metal block 5 is mounted on the carrier board 100 in a SMT mounting manner.

[0016] Preferably, the substrate 1 is a FCBGA substrate.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. This case provides a stacked packaging structure that can meet the requirements of low resistance, high current and strong heat dissipation capacity of chips of 2nm and below; this case realizes efficient and low-loss power supply from the carrier to the chip by accurately corresponding the back-side power supply metal contact on the carrier board to the first metal contact on the back of the chip, combined with the conductive network formed by the vertical metal block and the horizontal metal block. The stacked packaging structure also optimizes the signal transmission path, reduces signal delay and loss, and improves the working efficiency and performance of the chip. The stacked packaging structure makes full use of the three-dimensional space, stacks the carrier board, substrate, adapter board and chip tightly together, and greatly improves the space utilization of the package. The conductive network formed by the horizontal metal block and the vertical metal block optimizes the signal transmission path, reduces signal delay and loss, and improves the working efficiency and performance of the chip. The chip packaging structure enhances the mechanical strength of the overall package through the first solder ball connection and the setting of each layer of conductive material layer, and improves the vibration and impact resistance of the packaging structure. In addition, the vertical metal block is not only used for conduction, but also plays a role in supporting and reinforcing the packaging structure, further enhancing the stability of the package. The first chip connected by flip-chip can reduce the package size and improve the packaging density. Furthermore, since the thickness of the first chip is relatively small, the adapter plate can also play a certain role in raising the chip, so as to facilitate subsequent connection to the first metal contact on the back side of the first chip through the vertical metal column and the horizontal metal block. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the cross-sectional structure of this case.

[0020] Figure 2 It is a structural schematic diagram of the chip packaging structure in this case.

[0021] Figure 3 This is a schematic diagram of the top view of the structure of this case, which does not include the plastic sealing layer, vertical metal blocks, and horizontal metal blocks.

[0022] Figure 4 This is a schematic diagram of the top view of the structure of this case without the plastic sealing layer. DETAILED DESCRIPTION

[0023] The features of the present invention and other related features are further described in detail below through embodiments to facilitate understanding by those skilled in the art:

[0024] like Figure 1 and Figure 4As shown, a stacked packaging structure corresponding to back-end power supply of chips of 2nm and below is characterized in that it includes a carrier 100 and a chip packaging structure 300 stacked on the carrier 100 through a first solder ball 200, the chip packaging structure 300 includes: a substrate 1, an adapter board 2 connected to the upper surface of the substrate 1, and a first chip 3 of 2nm and below thickness connected to the upper surface of the adapter board 2 in a flip-chip manner; a plurality of first metal contacts 31 are provided on the back of the first chip 3, and the carrier 100 has a plurality of back-end power supply metal contacts 11 formed on its upper surface corresponding to the number of the first metal contacts 31, a first conductive material layer 41 is provided on the surface of each first metal contact 31, each back-end power supply metal contact 11 is connected to a vertical metal block 5 through a second conductive material layer 42, and a third conductive material layer 43 is provided on the upper surface of each vertical metal block 5; the upper surface of each vertical metal block 5 is at the same height as the back of the first chip 3; the first conductive material layer 41 and the third conductive material layer 43 are conductively connected through a horizontal metal block 6.

[0025] As described above, this case provides a stacked packaging structure that can meet the requirements of low resistance, high current and strong heat dissipation capacity of chips of 2nm and below; this case realizes efficient and low-loss power supply from the carrier to the chip by precisely corresponding the back-side power supply metal contact on the carrier board to the first metal contact on the back of the chip, combined with the conductive network formed by the vertical metal block and the horizontal metal block, and the stacked packaging structure also optimizes the signal transmission path, reduces signal delay and loss, and improves the working efficiency and performance of the chip. The stacked packaging structure makes full use of the three-dimensional space, stacks the carrier board, substrate, adapter board and chip tightly together, and greatly improves the space utilization of the package. The conductive network formed by the horizontal metal block and the vertical metal block optimizes the signal transmission path, reduces signal delay and loss, and improves the working efficiency and performance of the chip. The chip packaging structure enhances the mechanical strength of the overall package through the first solder ball connection and the setting of each layer of conductive material layer, and improves the vibration and impact resistance of the packaging structure. In addition, the vertical metal block is not only used for conduction, but also plays a role in supporting and reinforcing the packaging structure, further enhancing the stability of the package. The first chip connected by flip-chip can reduce the package size and improve the packaging density. Moreover, since the thickness of the first chip 3 is relatively small, the adapter plate can also play a certain role in raising the chip 3, so as to facilitate the subsequent connection to the first metal contact 31 on the back of the first chip 3 through the vertical metal column and the horizontal metal block. In addition, the first chip 3 is provided with the first metal contact 31 on the back, so that all electrodes do not need to be arranged on the front, and a larger metal contact can be arranged on the back, so that a larger horizontal metal block can be arranged to connect with it, and the larger horizontal metal block is connected in a way that meets the requirements of low resistance and large current.

[0026] Furthermore, the carrier 100 of the present case is a PCB carrier, the structure of which is relatively simple, and the chip packaging structure 300 is mounted on the PCB carrier, so there is no need to set metal leads / contacts on the surface of the substrate 1, which greatly reduces the difficulty of production. Moreover, the upper surface of each vertical metal block 5 of the stacked structure is set at the same height as the back of the first chip 3, so that the vertical metal block and the back of the first chip can be directly connected horizontally through an ordinary horizontally extending square metal block, without the need for complex design, while ensuring heat transfer and conduction, saving costs. Moreover, the equal height design allows the current to be more evenly distributed on the contact surface between the metal block and the chip, which can reduce the congestion of the current during the transmission process, thereby reducing the resistance.

[0027] As a specific implementation, the carrier 100 is provided with a chip packaging structure mounting area 110 and a back power supply area 120 arranged around the chip packaging structure mounting area 110. The carrier 100 is provided with the back power supply metal contact 11 in the back power supply area 120, and is provided with a plurality of first solder joints 101 embedded in the top of the chip packaging structure mounting area 110; the substrate 1 is provided with a second solder joint 12 embedded in the bottom, and the first solder joint 101 is connected one-to-one with the second solder joint 12 through a first solder ball 200.

[0028] As described above, by setting a special chip packaging structure installation area 110 and a back power supply area 120 on the carrier 100, the packaging structure can be reasonably laid out to facilitate subsequent packaging, so that chip packaging and power supply can be carried out separately, thereby improving the efficiency of the entire packaging process. The first solder joint 101 and the second solder joint 12 are connected one by one through the first solder ball 200 to ensure the accuracy of the connection and improve the packaging accuracy. The substrate of this case is divided into the chip installation area 110 and the back power supply area 120, which can reasonably lay out the packaging structure to facilitate subsequent packaging. By protruding a plurality of first solder balls 7 on the upper surface of the chip installation area 110, which are directly connected to the first solder joint 21 on the adapter board 2, the packaging process is simplified and the integration and efficiency of the packaging are improved. A back-end power supply area 120 is arranged around the chip mounting area 110, so that a plurality of vertical metal blocks 5 can be arranged around the chip packaging structure, and the space of the carrier board can be used to form a good heat dissipation channel and protect the internal chip packaging structure. The power supply path is optimized, making the power supply more stable and reliable, and reducing the voltage drop and signal interference that may be caused by the long-distance power supply line.

[0029] like Figure 3As shown, in a specific implementation, the substrate 1 is provided with a plurality of second solder balls 13 on its upper surface, and the adapter board 2 is provided with a plurality of third solder points 21 correspondingly connected to the second solder balls 13 on its lower surface; the first chip 3 is provided with a plurality of second metal contacts 32 on the front side, and the adapter board 2 is provided with a fourth solder point 22 embedded in the top and bonded to the second metal contact 32 on its upper surface.

[0030] As described above, in this case, the third solder joint 21 of the adapter board 2 is connected to the second solder ball 13 on the substrate, and the fourth solder joint 22 is bonded to the second metal contact 32 of the first chip 3, thereby achieving a stable connection between the multi-layer structure, so as to reduce the stress concentration and unstable connection problems that may be caused by direct connection, and improve the connection reliability of the overall structure. The introduction of the adapter board 2 makes the connection between the substrate 1 and the first chip 3 more flexible, so that by adjusting the layout and number of solder joints on the adapter board 2, it can adapt to the connection requirements of first chips of different specifications and types. In addition, the adapter board 2 can serve as a transition layer for heat dissipation, and more effectively transfer the heat generated by the first chip 3 to the substrate 1.

[0031] like Figure 1 or Figure 2 or Figure 4 As shown, in a specific implementation, the carrier 100 forms a vertical interlayer via 14 therein, and a multi-layer vertically connected circuit layer structure 15 is provided in the interlayer via 14, the top circuit layer of the circuit layer structure 15 serves as the back-end power supply metal contact 11, and the bottom circuit layer is exposed on the lower surface of the carrier 100.

[0032] As described above, the present invention allows the current to be transmitted vertically between different layers through the provision of the interlayer vias 14 and the circuit layer structure 15, forming a three-dimensional electrical connection path, further enhancing the stability and reliability of the electrical connection, and ensuring that the current can be smoothly transmitted between the layers. The provision of the topmost circuit layer of the circuit layer structure 15 as the back-end power supply metal contact 11 makes the power supply network more compact and efficient, and can directly supply the first chip through the back-end power supply metal contact 11, reducing the loss during the power transmission process and improving the power supply efficiency. In addition, the vertical interlayer vias 14 and the multi-layer circuit layer structure 15 are not only used for electrical connection, but also can be used as heat dissipation channels, so that the heat from the chip and the vertical metal block can be transferred through these channels inside the carrier board, and dissipated into the air through the surface of the carrier board, so as to improve the heat dissipation efficiency, help reduce the operating temperature of the chip, and extend its service life. Moreover, by forming a vertical electrical connection path and a circuit layer structure inside the substrate, a higher degree of integration can be achieved without increasing the package size. In addition, through the setting of the circuit processing of the bottom layer, it can directly contact the external environment, thereby improving the heat dissipation efficiency. At the same time, it is convenient to carry out electrical performance testing after packaging or can be used as an electrical connection interface to connect with external components or packaging structures.

[0033] As a preferred embodiment, the vertical metal block 5 and the horizontal metal block 6 are both made of a metal with high conductivity. The metal with high conductivity is copper, aluminum or its alloy, preferably copper. In this way, the back conductive network of the present application has excellent conductive properties, can significantly reduce resistance, and improve current transmission efficiency.

[0034] like Figure 1 As shown, a filling glue layer 8 is provided in the gap between the lower surface of the adapter plate 2 and the upper surface of the substrate 1 to fill the gap therein; thus, through the provision of the filling glue layer 8, on the one hand, after curing, the adapter plate 2 and the substrate 1 can be firmly bonded to enhance the connection strength between them; on the other hand, the filling glue layer 8 can have good thermal conductivity, so as to transfer the heat generated by the chip to the substrate 1, further improving the heat dissipation efficiency. Moreover, the filling glue layer 8 can fill the tiny gap between the adapter plate 2 and the substrate 1, reduce thermal resistance, and improve thermal conduction efficiency.

[0035] like Figure 1 As shown, the upper surface of the substrate 1 is provided with a plastic layer 9 for packaging all components into one. In this way, it is convenient to package all components into one, so as to provide insulation protection and moisture-proof effect to the internal components. In specific implementation, the plastic layer 9 is usually epoxy resin material.

[0036] As a preferred embodiment, the first conductive material layer 41, the second conductive material layer 42, and the third conductive material layer 43 are solder paste layers or conductive adhesive layers. Thus, solder paste layers or conductive adhesive layers are selected as the first conductive material layer 4, the second conductive material layer 42, and the third conductive material layer 43 to meet the requirements of conduction and heat dissipation, and both solder paste layers and conductive adhesive layers are commonly used conductive materials in the packaging process, so as to reduce the complexity and cost of the packaging process.

[0037] As a preferred embodiment, the vertical metal block 5 is mounted on the carrier 100 in an SMT mounting manner. In specific implementation, solder paste can be firstly coated on the back power supply metal contact 11 of the substrate 1, and then the vertical metal block can be mounted on the solder paste by a chip mounter to achieve connection. In this way, the existing mounting technology can be used for packaging to ensure the stability and reliability of the packaging.

[0038] As a preferred embodiment, the substrate 1 is a FCBGA packaging substrate. In this way, the use of the FCBGA packaging substrate can realize the flip chip technology, that is, the chip is flipped upside down and attached to the substrate, so as to facilitate the subsequent realization of the back-side power supply of the 2nm & 2nm chips below, without the need to use wires to connect the chip and the substrate, so as to achieve higher integration and higher density packaging.

[0039] As mentioned above, this case protects a stacked packaging structure corresponding to the back-end power supply of 2nm and below chips. All technical solutions that are the same or similar to this case should be deemed to fall within the scope of protection of this case.

Claims

1. A stacked packaging structure corresponding to 2nm and below chip backside power supply, characterized in that The invention comprises a carrier (100) and a chip packaging structure (300) stacked on the carrier (100) via first solder balls (200), wherein the chip packaging structure (300) comprises: a substrate (1), an adapter board (2) connected to the upper surface of the substrate (1), and a first chip (3) with a thickness of 2 nm or less connected to the upper surface of the adapter board (2) in a flip-chip manner; a plurality of first metal contacts (31) are provided on the back of the first chip (3); and the carrier (100) has corresponding first metal contacts (31) on its upper surface according to the number of the first metal contacts (31). A plurality of back-end power supply metal contacts (11) are formed, a first conductive material layer (41) is provided on the surface of each first metal contact (31), each back-end power supply metal contact (11) is connected to a vertical metal block (5) via a second conductive material layer (42), a third conductive material layer (43) is provided on the upper surface of each vertical metal block (5); the upper surface of each vertical metal block (5) is at the same height as the back surface of the first chip (3); and the first conductive material layer (41) and the third conductive material layer (43) are conductively connected via a horizontal metal block (6).

2. The package stack structure according to claim 1, characterized in that The carrier (100) is provided with a chip packaging structure installation area (110) and a back-end power supply area (120) arranged around the chip packaging structure installation area (110); the carrier (100) is provided with the back-end power supply metal contact (11) in the back-end power supply area (120); and the chip packaging structure installation area (110) is provided with a plurality of first solder joints (101) embedded in the top thereof; the substrate (1) is provided with a second solder joint (12) embedded in the bottom thereof, and the first solder joint (101) and the second solder joint (12) are connected in a one-to-one correspondence via a first solder ball (200).

3. The stacked package structure according to claim 1 or 2, characterized in that The substrate (1) is provided with a plurality of second solder balls (13) on its upper surface, and the adapter plate (2) is provided with a plurality of third solder points (21) on its lower surface that are correspondingly connected to the second solder balls (13); the first chip (3) is provided with a plurality of second metal contacts (32) on its front surface, and the adapter plate (2) is provided with a fourth solder point (22) embedded in the top and bonded to the second metal contacts (32) on its upper surface.

4. The package stack structure according to claim 1, characterized in that The carrier (100) has a vertical interlayer via (14) formed therein, and a multi-layer vertically connected circuit layer structure (15) is provided in the interlayer via (14), the uppermost circuit layer of the circuit layer structure (15) serving as the back-side power supply metal contact (11), and the lowermost circuit layer is exposed on the lower surface of the carrier (100).

5. The package stack structure according to claim 1, characterized in that The vertical metal block (5) and the horizontal metal block (6) are both metal blocks made of highly conductive metal.

6. The package stack structure according to claim 1, characterized in that A filling glue layer (8) for filling the gap is provided in the gap between the lower surface of the adapter plate (2) and the upper surface of the base plate (1).

7. The package stack structure according to claim 1, characterized in that The upper surface of the substrate (1) is provided with a plastic sealing layer (9) for sealing all components into one body.

8. The package stack structure according to claim 1, characterized in that The first conductive material layer (41), the second conductive material layer (42), and the third conductive material layer (43) are solder paste layers or conductive adhesive layers.

9. The package-on-package structure according to claim 1, wherein The vertical metal block (5) is mounted on the carrier board (100) in a SMT mounting manner.

10. The package-on-package structure according to claim 1, wherein The substrate (1) is a FCBGA substrate.

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