Packaging structure and packaging method
By bonding the interconnection structure of the re-wiring layer and the chip bridge on the substrate, the existing packaging structure is complex and cost-effective, and efficient electrical connection between chips is achieved, and the packaging effect is improved.
Patent Information
- Application Number
- CN202310955558.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-31
- Publication Date
- 2025-02-14
AI Technical Summary
The existing packaging structure is complex, has high cost and poor application, making it difficult to achieve high-speed and small-volume interconnection between chips.
The interconnect structure bonded on the substrate is adopted, including a re-wiring layer and a chip bridge embedded in the re-wiring layer. The electrical connection between the chip structure and the substrate is realized through the re-wiring layer, and the chip structure and the first chip are realized through the chip bridge. electrical connection.
The formation of the interconnect structure is simplified, the cost is reduced, the integration of the re-wiring layer and the chip bridge is improved, the height difference caused by the chip bridge is reduced, and the packaging effect of the packaging structure is improved.
Smart Images
Figure CN119447094A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method. Background Art
[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.
[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.
[0004] However, the current packaging structure is relatively complex. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to improving the packaging effect of the packaging structure.
[0006] To solve the above problems, the present invention provides a packaging structure, including: a substrate; an interconnection structure bonded to the substrate, the interconnection structure including a rewiring layer and a chip bridge embedded in the rewiring layer, the interconnection structure including a bonding surface, the bonding surface exposing the chip bridge surface; a first chip bonded to the bonding surface of the interconnection structure, the first chip is electrically connected to the rewiring layer and the chip bridge; a chip structure bonded to the bonding surface of the interconnection structure on the side of the first chip, the chip structure is electrically connected to the rewiring layer, and the chip structure is electrically connected to the first chip through the chip bridge.
[0007] Optionally, on the bonding surface, the rewiring layer is flush with the chip bridge surface.
[0008] Optionally, the chip bridge is electrically isolated from the redistribution layer.
[0009] Optionally, the packaging structure also includes: a first conductive bump, located between the rewiring layer and the first chip, and between the rewiring layer and the chip structure, and electrically connecting the rewiring layer and the first chip, and electrically connecting the rewiring layer and the chip structure; a second conductive bump, located between the chip bridge and the first chip, and between the chip bridge and the chip structure, and electrically connecting the chip bridge and the first chip, and electrically connecting the chip bridge and the chip structure.
[0010] Optionally, the packaging structure further includes: a first sealing layer, which fills the gaps between adjacent first conductive bumps and between adjacent second conductive bumps and covers the first conductive bumps and the second conductive bumps.
[0011] Optionally, the packaging structure further includes: a third conductive bump, located between the interconnection structure and the substrate, and electrically connecting the interconnection structure and the substrate.
[0012] Optionally, the packaging structure further includes: a second sealing layer, located between the interconnect structure and the substrate, and filling the gap between the interconnect structure and the substrate and the gap between adjacent third conductive bumps.
[0013] Optionally, the first chip includes a logic chip, the chip structure includes one or a plurality of second chips stacked vertically, and the second chip includes a memory chip.
[0014] Optionally, the chip bridge has a thickness of 2 μm to 15 μm.
[0015] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a substrate; forming an interconnection structure, including a rewiring layer, and a chip bridge embedded in the rewiring layer, the interconnection structure including a bonding surface, the bonding surface exposing the chip bridge surface; providing a first chip; providing a chip structure; bonding the chip structure and the first chip to the bonding surface of the interconnection structure, the chip structure is located on the side of the first chip, the chip structure is electrically connected to the rewiring layer, the first chip is electrically connected to the rewiring layer, and the first chip is electrically connected to the chip structure through the chip bridge; after bonding the chip structure and the first chip to the bonding surface of the interconnection structure, the interconnection structure is bonded to the substrate, with the bonding surface facing away from the substrate.
[0016] Optionally, in the step of forming the interconnect structure, on the bonding surface, the rewiring layer is flush with the surface of the chip bridge.
[0017] Optionally, in the step of forming the interconnect structure, the chip bridge is electrically isolated from the redistribution layer.
[0018] Optionally, the step of forming the interconnection structure includes: providing a first carrier substrate; bonding a chip bridge on the first carrier substrate; forming a rewiring layer covering the chip bridge, the rewiring layer and the chip bridge forming an interconnection structure, wherein the bonding surface faces the first carrier substrate;
[0019] The first carrier substrate is removed.
[0020] Optionally, the step of bonding a chip bridge on a first carrier substrate includes: providing an initial chip bridge; bonding the initial chip bridge to the first carrier substrate, wherein the circuit structure of the initial chip bridge faces the first carrier substrate; thinning the initial chip bridge, retaining the remaining initial chip bridge with the circuit structure as a chip bridge.
[0021] Optionally, the step of forming a rewiring layer covering the chip bridge includes: forming a dielectric layer covering the chip bridge; and forming an electrical connection structure in the dielectric layer to constitute the rewiring layer.
[0022] Optionally, after forming the interconnection structure and before removing the first carrier substrate, the packaging method also includes: bonding a second carrier substrate on the interconnection structure; removing the first carrier substrate to expose the bonding surface; after bonding the chip structure and the first chip to the bonding surface of the interconnection structure and before bonding the interconnection structure to the substrate, removing the second carrier substrate.
[0023] Optionally, after forming the interconnect structure and before bonding the chip structure and the first chip to the bonding surface of the interconnect structure, the packaging method further includes: forming a first conductive bump on the redistribution layer of the bonding surface; and forming a second conductive bump on the chip bridge of the bonding surface.
[0024] Optionally, the packaging method further includes: forming a first sealing layer filled in gaps between adjacent first conductive bumps and between adjacent second conductive bumps, wherein the first sealing layer covers the first conductive bumps and the second conductive bumps.
[0025] Optionally, after the chip structure and the first chip are bonded to the bonding surface of the interconnection structure and before the interconnection structure is bonded to the substrate, the packaging method also includes: forming a third conductive bump on the substrate; in the step of bonding the interconnection structure to the substrate, the third conductive bump electrically connects the interconnection structure and the substrate.
[0026] Optionally, after bonding the interconnect structure to the substrate, the packaging method further includes: forming a second sealing layer between the interconnect structure and the substrate to fill the gap between the interconnect structure and the substrate and the gap between adjacent third conductive bumps.
[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0028] An embodiment of the present invention provides a packaging structure, wherein an interconnection structure is bonded to a substrate, the interconnection structure includes a rewiring layer and a chip bridge embedded in the rewiring layer, the interconnection structure includes a bonding surface, and the bonding surface exposes the chip bridge surface; in the embodiment of the present invention, the rewiring layer is used to realize the electrical connection between the chip structure and the substrate, and between the first chip and the substrate, and the chip bridge is used to realize the electrical connection between the chip structure and the first chip, and the rewiring layer and the chip bridge embedded in the rewiring layer are used as the interconnection structure, so that the formation of the interconnection structure is relatively simple and the cost is low, and it is also beneficial to improve the integration of the rewiring layer and the chip bridge. Moreover, the chip bridge is embedded in the rewiring layer, which is beneficial to reducing the height difference caused by the chip bridge compared to bonding the chip bridge to the rewiring layer, and is beneficial to the bonding of the first chip and the chip structure on the interconnection structure, thereby facilitating the packaging effect of the packaging structure.
[0029] An embodiment of the present invention provides a packaging method, forming an interconnection structure, including a rewiring layer and a chip bridge embedded in the rewiring layer, the interconnection structure including a bonding surface, the bonding surface exposing the chip bridge surface; in the embodiment of the present invention, the rewiring layer is used to realize the electrical connection between the chip structure and the substrate, and the first chip and the substrate, the chip bridge is used to realize the electrical connection between the chip structure and the first chip, and the rewiring layer and the chip bridge embedded in the rewiring layer are used as the interconnection structure, so that the formation of the interconnection structure is relatively simple and low in cost, and it is also beneficial to improve the integration of the rewiring layer and the chip bridge. Moreover, the chip bridge is embedded in the rewiring layer, compared with bonding the chip bridge to the rewiring layer, it is beneficial to reduce the height difference caused by the chip bridge, and it is beneficial to the bonding of the first chip and the chip structure on the interconnection structure, so as to improve the packaging effect of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a schematic diagram of the structure of a packaging structure;
[0031] Figure 2 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;
[0032] Figures 3 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION
[0033] As can be seen from the background technology, the current packaging structure is relatively complex, and the packaging cost is high and the applicability is poor. Now, the reasons for the high packaging cost and poor applicability are analyzed in combination with a packaging structure.
[0034] Figure 1 It is a structural diagram of a packaging structure.
[0035] The packaging structure includes: a substrate 10, including a bonding surface, and a groove is formed on one side of the bonding surface of the substrate 10; a silicon bridge 20, bonded to the bonding surface of the substrate 10; a first chip 31, bonded to the substrate 10 on one side of the groove; a second chip 32, bonded to the substrate 10 on the other side of the groove; a first bump 11, located between the first chip 31 and the substrate 10, and between the second chip 32 and the substrate 10 on the side of the groove, for electrically connecting the first chip 31 and the substrate 10, and the second chip 32 and the substrate 10; a chip bridge 20, bonded to the first chip 31 and the second chip 32, and facing one side of the substrate 10, and the chip bridge 20 is located in the groove; a second bump 12, located between the first chip 31 and the chip bridge 20, and between the second chip 32 and the chip bridge 20, for electrically connecting the first chip 31 and the chip bridge 20, and the second chip 32 and the chip bridge 20, so that the first chip 31 and the second chip 32 are electrically connected through the chip bridge 20.
[0036] The silicon bridge 20 is used to electrically connect the first chip 31 and the second chip 32. Currently, the chip bridge 20 is usually thicker and the second bump 12 also has a certain height. Therefore, the total height of the second bump 12 and the chip bridge 20 bonded to the first chip 31 and the second chip 32 is relatively large, so it is necessary to increase the height of the first bump 11 to compensate for the height from the top surface of the first chip 31 and the second chip 32 to the bottom surface of the chip bridge 20. At the same time, it is also necessary to form an additional groove in the substrate 10 to place the chip bridge 20 to compensate for the height difference between the top surface of the first chip 31 and the second chip 32 to the bottom surface of the chip bridge 20 and the top surface of the first chip 31 and the second chip 32 to the bottom of the first bump 11. The packaging structure is complex and the packaging cost is high.
[0037] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, including: a substrate; an interconnection structure bonded to the substrate, the interconnection structure including a rewiring layer and a chip bridge embedded in the rewiring layer, the interconnection structure including a bonding surface, the bonding surface exposing the chip bridge surface; a first chip bonded to the bonding surface of the interconnection structure, the first chip is electrically connected to the rewiring layer and the chip bridge; a chip structure bonded to the bonding surface of the interconnection structure on the side of the first chip, the chip structure is electrically connected to the rewiring layer, and the chip structure is electrically connected to the first chip through the chip bridge.
[0038] In the embodiment of the present invention, the rewiring layer is used to realize the electrical connection between the chip structure and the substrate, and between the first chip and the substrate, and the chip bridge is used to realize the electrical connection between the chip structure and the first chip. The rewiring layer and the chip bridge embedded in the rewiring layer are used as the interconnection structure, so that the formation of the interconnection structure is relatively simple and the cost is low, which is also beneficial to improve the integration of the rewiring layer and the chip bridge. Moreover, the chip bridge is embedded in the rewiring layer, which is beneficial to reduce the height difference caused by the chip bridge compared to bonding the chip bridge to the rewiring layer, and is beneficial to the bonding of the first chip and the chip structure on the interconnection structure, thereby helping to improve the packaging effect of the packaging structure.
[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0040] Figure 2 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention.
[0041] The packaging structure includes: a substrate 700; an interconnection structure (not marked), bonded to the substrate 700, the interconnection structure including a rewiring layer 320, and a chip bridge 200 embedded in the rewiring layer 320, the interconnection structure including a bonding surface 30a, the bonding surface 30a exposing the surface of the chip bridge 200; a first chip 440, bonded to the bonding surface 30a of the interconnection structure, the first chip 440 is electrically connected to the rewiring layer 320 and the chip bridge 200; a chip structure 400, bonded to the bonding surface 30a of the interconnection structure on the side of the first chip 440, the chip structure 400 is electrically connected to the rewiring layer 320, and the chip structure 400 is electrically connected to the first chip 440 through the chip bridge 200.
[0042] The substrate 700 is used to provide a process operation basis for bonding the chip structure 400 , the first chip 440 and the interconnection structure.
[0043] In this embodiment, the substrate 700 includes a base and an interconnection layer located on the base, and the exposed surface of the interconnection layer is a process operation platform.
[0044] The interconnection layer is used to bond with the interconnection structure, thereby achieving electrical connection with the chip structure 400 and the first chip 440. The interconnection layer is also used to achieve electrical connection with the substrate, and accordingly can achieve electrical connection between the chip structure 400 and the first chip 440 and the substrate.
[0045] In this embodiment, the interconnection layer is a redistribution structure. Specifically, the redistribution structure may include one or more layers of redistribution interconnection layers.
[0046] The substrate is used to realize electrical connection between the chip structure 400 and the first chip 440 through the interconnection layer, and can be electrically connected to the external structure accordingly, thereby realizing electrical connection between the chip structure 400 and the first chip 440 and the external structure.
[0047] Specifically, in this embodiment, the substrate is a packaging substrate, and the packaging substrate is a printed circuit board (Printed Circuit Board, PCB).
[0048] The interconnection structure is used to provide a process operation basis for bonding the chip structure 400 to the first chip 440 , wherein the bonding surface 30 a is used as a process operation platform for bonding the chip structure 400 to the first chip 440 .
[0049] Specifically, in this embodiment, the interconnection structure is used to electrically connect the chip structure 400 and the first chip 440 to achieve electrical connection between the chip structure 400 and the substrate 700, between the first chip 440 and the substrate 700, and between the chip structure 400 and the first chip 440.
[0050] The chip bridge 200 is used to realize electrical connection between the chip structure 400 and the first chip 440 , and the redistribution layer 320 is used to realize electrical connection between the chip structure 400 and the substrate 700 , and between the first chip 440 and the substrate 700 .
[0051] In this embodiment, the rewiring layer 320 is used to realize the electrical connection between the chip structure 400 and the substrate, and the first chip 440 and the substrate 700, and the chip bridge 200 is used to realize the electrical connection between the chip structure 400 and the first chip 440. The rewiring layer 320 and the chip bridge 200 embedded in the rewiring layer 320 are used as the interconnection structure, so that the formation of the interconnection structure is relatively simple and the cost is low, which is also beneficial to improve the integration of the rewiring layer 320 and the chip bridge 200. Moreover, the chip bridge 200 is embedded in the rewiring layer 320. Compared with bonding the chip bridge to the rewiring layer, it is beneficial to reduce the height difference caused by the chip bridge 200, which is beneficial to the bonding of the first chip 440 and the chip structure 440 on the interconnection structure, thereby facilitating the packaging effect of the packaging structure.
[0052] In this embodiment, the redistribution layer 320 is a redistribution structure (Redistribution Layer), including one or more redistribution interconnection layers. Specifically, the redistribution layer 320 includes a dielectric layer 300 and an electrical connection structure 310 located in the dielectric layer 300 .
[0053] The dielectric layer 300 is used to isolate the electrical connection structures 310 from each other. The electrical connection structures 310 are used to realize electrical connection between the chip structure 400 and the substrate 700 , and between the first chip 440 and the substrate 700 .
[0054] In this embodiment, a circuit structure is formed in the chip bridge 200 , and the first chip 440 is electrically connected to the chip structure 400 via the circuit structure.
[0055] In this embodiment, the chip bridge 200 includes a silicon bridge (Si bridge) or an interposer.
[0056] It should be noted that, in this embodiment, the thickness of the chip bridge 200 should not be too large or too small. If the thickness of the chip bridge 200 is too large, it is easy to cause the thickness of the interconnection structure to be too large, which is not conducive to improving the integration of the packaging structure; if the thickness of the chip bridge 200 is too small, it is easy to affect the formation of the circuit structure in the chip bridge 200 and affect the electrical connection performance of the chip bridge 200. For this reason, in this embodiment, the thickness of the chip bridge 200 is 2μm to 15μm.
[0057] In this embodiment, on the bonding surface 30 a , the redistribution layer 320 is flush with the surface of the chip bridge 200 .
[0058] The rewiring layer 320 is flush with the surface of the chip bridge 200, so that the flatness of the bonding surface 30a is better, providing a better process platform for the bonding of the chip structure 400 and the first chip 440, and the rewiring layer 320 is flush with the surface of the chip bridge 200, which is beneficial to further improve the integration of the rewiring layer 320 and the chip bridge 200. Moreover, the rewiring layer 320 is flush with the surface of the chip bridge 200, and the chip bridge 200 is completely embedded in the rewiring layer 320, which is beneficial to completely avoid the height difference caused by the chip bridge 200, and is further beneficial to the bonding of the first chip 440 and the chip structure 440 on the interconnection structure, thereby further helping to improve the packaging effect of the packaging structure.
[0059] In this embodiment, the chip bridge 200 is electrically isolated from the redistribution layer 320 .
[0060] The chip bridge 200 is electrically isolated from the redistribution layer 320 , so that the chip bridge 200 and the redistribution layer 320 can respectively realize their own electrical connection functions without interfering with each other.
[0061] The first chip 440 is used to be electrically connected to the interconnection structure to achieve electrical connection between the first chip 440 and the chip structure 400 , and between the first chip 440 and the substrate 700 .
[0062] Specifically, in this embodiment, the first chip 440 is electrically connected to the wiring layer 320 , and is electrically connected to the substrate 700 through the rewiring layer 320 . The first chip 440 is electrically connected to each chip structure 400 through the chip bridge 200 .
[0063] In this embodiment, the first chip 440 is a logic chip, and in this embodiment, as a first logic chip, it is used to control the memory chip of the chip structure 400. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).
[0064] The chip structure 400 is used to be electrically connected to the interconnection structure to achieve electrical connection between the chip structure 400 and the first chip 440 , and electrical connection between the chip structure 400 and the substrate 700 .
[0065] In this embodiment, the chip structure 400 includes one or more longitudinal directions (such as Figure 2 The plurality of second chips 410 are stacked (as shown in the Z direction), thereby realizing electrical connection between each second chip 410 and the first chip 440, and electrical connection between each second chip 410 and the substrate 700.
[0066] Specifically, in this embodiment, the chip structure 400 is electrically connected to the wiring layer 320 , and is electrically connected to the substrate 700 through the rewiring layer 320 . The chip structure 400 is electrically connected to the first chip 440 through the chip bridge 200 .
[0067] In this embodiment, in the chip structure 400, a plurality of second chips 410 stacked in the vertical direction form a high bandwidth memory (HBM) structure, which is conducive to meeting the requirement for higher information transmission speed by adopting the HBM structure.
[0068] The second chip 410 includes a bottom chip at the bottom and a top chip stacked on the bottom chip, and the number of the top chips can be one or more. In this embodiment, the number of the top chips is four as an example for description. In other embodiments, the number of the top chips can also be other numbers.
[0069] Therefore, in this embodiment, the top chip is a memory chip. In a specific implementation, the top chip is a high bandwidth memory chip.
[0070] In this embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as a logic control chip in the chip structure 400 .
[0071] In this embodiment, the bottom chip and the substrate 700 , as well as the adjacent second chips 410 in the vertical direction are electrically connected, thereby achieving electrical integration between the second chips 410 and electrical integration between the second chips 410 and the substrate 700 .
[0072] In this embodiment, there are multiple chip structures 400 , and multiple chip structures 400 are electrically connected to the first chip 440 , which is beneficial to increasing the memory of the package structure, improving the chip speed and reducing the chip power consumption.
[0073] In this embodiment, the packaging structure also includes: a first conductive bump 510, which is located between the redistribution layer 320 and the first chip 440, and between the redistribution layer 320 and the chip structure 400, and electrically connects the redistribution layer 320 and the first chip 440, and electrically connects the redistribution layer 320 and the chip structure 400.
[0074] The first conductive bumps 510 are used to realize electrical connection between the first chip 440 and the redistribution layer 320 , and between the chip structure 400 and the redistribution layer 320 .
[0075] In this embodiment, the material of the first conductive bump 510 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 510 is tin.
[0076] In this embodiment, the first conductive bumps 510 may be micro bumps (uBumps), which have a higher density and are beneficial for improving the communication speed between the first chip 440 and the redistribution layer 320 , and between the chip structure 400 and the redistribution layer 320 .
[0077] In this embodiment, the packaging structure further includes: a second conductive bump 520 , which is located between the chip bridge 200 and the first chip 440 , and between the chip bridge 200 and the chip structure 400 , and electrically connects the chip bridge 200 and the first chip 440 , and electrically connects the chip bridge 200 and the chip structure 400 .
[0078] The second conductive bumps 520 are used to realize electrical connection between the first chip 440 and the chip bridge 200 , and between the chip structure 400 and the chip bridge 200 .
[0079] In this embodiment, the material of the second conductive bump 520 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 520 is tin.
[0080] In this embodiment, the second conductive bumps 520 may be micro bumps (uBumps), which have a higher density and are beneficial for improving the communication speed between the first chip 440 and the chip bridge 200 , and between the chip structure 400 and the chip bridge 200 .
[0081] In this embodiment, the packaging structure further includes: a first sealing layer 600 filling the gaps between adjacent first conductive bumps 510 and between adjacent second conductive bumps 520 and covering the first conductive bumps 510 and the second conductive bumps 520 .
[0082] The first sealing layer 600 is used to achieve sealing between the interconnect structure and the first chip 440 , to achieve sealing between the interconnect structure and the chip structure 400 , and to achieve sealing between the first conductive bump 510 and the second conductive bump 520 .
[0083] In this embodiment, the packaging structure further includes: a third conductive bump 530 , which is located between the interconnection structure and the substrate 700 and electrically connects the interconnection structure and the substrate 700 .
[0084] The third conductive bump 530 is used to realize electrical connection between the interconnect structure and the substrate 700 .
[0085] In this embodiment, the material of the third conductive bump 530 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 530 is tin.
[0086] In this embodiment, the third conductive bump 530 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.
[0087] In this embodiment, the packaging structure further includes: a second sealing layer 620 located between the interconnect structure and the substrate 700 , and filling the gap between the interconnect structure and the substrate 700 and the gap between adjacent third conductive bumps 530 .
[0088] The second sealing layer 620 is used to achieve sealing between the interconnect structure and the substrate 700 , and to achieve sealing of the third conductive bump 530 .
[0089] In this embodiment, the packaging structure further includes: a fourth conductive bump 540 located at the bottom of the substrate 700 .
[0090] The fourth conductive bump 540 is used to realize electrical connection between the substrate 700 and the outside.
[0091] In this embodiment, the material of the fourth conductive bump 540 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the fourth conductive bump 540 is tin.
[0092] In this embodiment, the fourth conductive bump 540 may be a ball grid array (BGA) structure.
[0093] In this embodiment, a plastic encapsulation layer 610 is formed on the sidewalls of the chip structure 400 , the sidewalls of the first chip 440 , and between the chip structure 400 and the first chip 440 .
[0094] The plastic encapsulation layer 610 is used to protect the chip structure 400 and the first chip 440 .
[0095] In this embodiment, the material of the plastic encapsulation layer 610 is a plastic encapsulation material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the first plastic encapsulation layer can also be made of other suitable packaging materials.
[0096] Figures 3 to 12It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.
[0097] Combined with reference Figures 3 to 6 , forming an interconnection structure, including a rewiring layer 320 and a chip bridge 200 embedded in the rewiring layer 320 , the interconnection structure includes a bonding surface 30 a , and the bonding surface 30 a is exposed on the surface of the chip bridge 200 .
[0098] The interconnection structure is used to provide a process operation basis for the subsequent bonding of the chip structure and the first chip, wherein the bonding surface 30a is used as a process operation platform for the subsequent bonding of the chip structure and the first chip.
[0099] Specifically, in this embodiment, the interconnection structure is used to subsequently electrically connect the chip structure and the first chip to achieve electrical connection between the chip structure and the substrate, between the first chip and the substrate, and between the chip structure and the first chip.
[0100] The chip bridge 200 is used to subsequently realize electrical connection between the chip structure and the first chip, and the redistribution layer 320 is used to realize electrical connection between the chip structure and the substrate, and between the first chip and the substrate.
[0101] In this embodiment, the rewiring layer 320 is used to realize the electrical connection between the chip structure and the substrate, and between the first chip and the substrate, and the chip bridge 200 is used to realize the electrical connection between the chip structure and the first chip. The rewiring layer 320 and the chip bridge 200 embedded in the rewiring layer 320 are used as the interconnection structure, so that the formation of the interconnection structure is relatively simple and the cost is low, which is also beneficial to improve the integration of the rewiring layer 320 and the chip bridge 200. Moreover, the chip bridge 200 is embedded in the rewiring layer 320, which is beneficial to reduce the height difference caused by the chip bridge 200 compared to bonding the chip bridge to the rewiring layer, and is beneficial to the bonding of the first chip and the chip structure on the interconnection structure, thereby helping to improve the packaging effect of the packaging structure.
[0102] In this embodiment, the redistribution layer 320 is a redistribution structure (Redistribution Layer), including one or more redistribution interconnection layers.
[0103] In this embodiment, a circuit structure is formed in the chip bridge 200 , and subsequently the first chip is electrically connected to the chip structure via the circuit structure.
[0104] In this embodiment, the chip bridge 200 includes a silicon bridge (Si bridge) or an interposer.
[0105] It should be noted that in this embodiment, in the step of forming the interconnection structure, the thickness of the chip bridge 200 should not be too large or too small. If the thickness of the chip bridge 200 is too large, it is easy to cause the thickness of the interconnection structure to be too large, which is not conducive to improving the integration of the packaging structure; if the thickness of the chip bridge 200 is too small, it is easy to affect the formation of the circuit structure in the chip bridge 200 and affect the electrical connection performance of the chip bridge 200. For this reason, in this embodiment, in the step of forming the interconnection structure, the thickness of the chip bridge 200 is 2μm to 15μm.
[0106] In this embodiment, in the step of forming the interconnection structure, on the bonding surface 30 a , the redistribution layer 320 is flush with the surface of the chip bridge 200 .
[0107] The rewiring layer 320 is flush with the surface of the chip bridge 200, so that the flatness of the bonding surface 30a is better, providing a better process platform for the bonding of the chip structure 400 and the first chip 440, and the rewiring layer 320 is flush with the surface of the chip bridge 200, which is beneficial to further improve the integration of the rewiring layer 320 and the chip bridge 200. Moreover, the rewiring layer 320 is flush with the surface of the chip bridge 200, and the chip bridge 200 is completely embedded in the rewiring layer 320, which is beneficial to completely avoid the height difference caused by the chip bridge 200, and is further beneficial to the bonding of the first chip 440 and the chip structure 440 on the interconnection structure, thereby further helping to improve the packaging effect of the packaging structure.
[0108] In this embodiment, in the step of forming the interconnection structure, the chip bridge 200 is electrically isolated from the redistribution layer 320 .
[0109] The chip bridge 200 is electrically isolated from the redistribution layer 320 , so that the chip bridge 200 and the redistribution layer 320 can respectively realize their own electrical connection functions without interfering with each other.
[0110] refer to Figure 3 The step of forming the interconnection structure includes: providing a first carrier substrate 100 .
[0111] The first carrier substrate 100 is used to carry the interconnection structure and provide a process platform for forming the interconnection structure.
[0112] In this embodiment, the first carrier substrate 100 is a wafer. In other embodiments, the first carrier substrate may also be a glass substrate.
[0113] In this embodiment, a first adhesive layer 110 is formed on the first carrier substrate 100 .
[0114] The first adhesive layer 110 is used to adhere the chip bridge 200 to the first carrier substrate 100 .
[0115] Combined with reference Figure 3 and Figure 4, a chip bridge 200 is bonded on the first carrier substrate 100 .
[0116] Specifically, in this embodiment, the chip bridge 200 is bonded on the first adhesive layer 110 of the first carrier substrate 100 .
[0117] In this embodiment, the side of the chip bridge 200 having the external connection end of the circuit structure faces the first carrier substrate 100, so that after the interconnection structure is subsequently bonded to the second carrier substrate and the first carrier substrate 100 is removed, the external connection end of the interconnection structure is exposed in preparation for external interconnection.
[0118] Specifically, refer to Figure 3 The step of bonding the chip bridge 200 on the first carrier substrate 100 includes: providing an initial chip bridge 201 .
[0119] The initial chip bridge 201 includes a substrate and a circuit structure located on the substrate.
[0120] Continue to refer Figure 3 , the initial chip bridge 201 is bonded to the first carrier substrate 100 , wherein the circuit structure of the initial chip bridge 201 faces the first carrier substrate 100 .
[0121] The circuit structure of the initial chip bridge 201 faces the first carrier substrate 100 , so that the substrate of the initial chip bridge 201 is exposed, so that the initial chip bridge 201 can be thinned.
[0122] Specifically, in this embodiment, the initial chip bridge 201 is bonded to the first bonding layer 110 of the first carrier substrate 100 .
[0123] refer to Figure 4 , the initial chip bridge 201 is thinned, and the remaining initial chip bridge 201 with the circuit structure is retained as the chip bridge 200.
[0124] The initial chip bridge 201 is thinned and the substrate is removed to obtain a chip bridge 200 with a smaller thickness, which is beneficial for embedding the chip bridge 200 in the rewiring layer 320, reducing the height difference caused by the introduction of the chip bridge 200, and reducing the volume occupied by the chip bridge 200.
[0125] Combined with reference Figure 5 and Figure 6 , a rewiring layer 320 covering the chip bridge 200 is formed, and the rewiring layer 320 and the chip bridge 200 constitute an interconnection structure, wherein the bonding surface 30 a faces the first carrier substrate 100 .
[0126] By first forming the chip bridge 200 and then forming the rewiring layer 320 covering the chip bridge 200, an interconnection structure having a structure in which the chip bridge 200 is embedded in the rewiring layer 320 is obtained. The formation process is simple and easy to operate, and the process of additionally grooving the rewiring layer 320 in order to embed the chip bridge 200 in the rewiring layer 320 is omitted, thereby simplifying the process flow and reducing the process cost.
[0127] The bonding surface 30a faces the first carrier substrate 100, so that after the interconnection structure is subsequently bonded to the second carrier substrate and the first carrier substrate 100 is removed, the bonding surface 30a of the interconnection structure is exposed, preparing for the subsequent bonding of the first chip and the chip structure on the bonding surface 30a.
[0128] Specifically, refer to Figure 5 The step of forming a redistribution layer 320 covering the chip bridge 200 includes: forming a dielectric layer 300 covering the chip bridge 200 .
[0129] The dielectric layer 300 is used to isolate the electrical connection structures in the redistribution layer 320 from each other.
[0130] refer to Figure 6 , an electrical connection structure 310 is formed in the dielectric layer 300 to constitute a rewiring layer 320 .
[0131] The electrical connection structure 310 is used to subsequently realize electrical connection between the chip structure and the substrate, and electrical connection between the first chip and the substrate.
[0132] refer to Figure 7 After forming the interconnect structure and before subsequently removing the first carrier substrate 100 , the packaging method further includes: bonding the second carrier substrate 120 on the interconnect structure.
[0133] The second carrier substrate 120 is used to carry the interconnection structure and provide a process platform for subsequently bonding the first chip and the chip structure on the interconnection structure.
[0134] In this embodiment, the second carrier substrate 120 is a wafer. In other embodiments, the second carrier substrate may also be a glass substrate.
[0135] In this embodiment, a second adhesive layer 130 is formed on the second carrier substrate 120 .
[0136] The second adhesive layer 130 is used to adhere the interconnect structure to the second carrier substrate 120 .
[0137] Accordingly, in this embodiment, the interconnection structure is bonded to the second adhesive layer 130 .
[0138] Combined with reference Figure 7 and Figure 8 , remove the first carrier substrate 100.
[0139] The first carrier substrate 100 is removed to expose the bonding surface 30a, in preparation for subsequently bonding the first chip and the chip structure on the interconnection structure.
[0140] Specifically, refer to Figure 8 After bonding the second carrier substrate 120 to the interconnect structure, the first carrier substrate 100 is removed to expose the bonding surface 30a.
[0141] The interconnect structure is flipped over so that the bonding surface 30a faces upward, thereby providing an easy-to-operate platform for subsequently bonding the first chip and the chip structure on the interconnect structure.
[0142] refer to Fig. 9 After the interconnect structure is formed, before the chip structure and the first chip are subsequently bonded to the bonding surface 30a of the interconnect structure, the packaging method further includes: forming a first conductive bump 510 on the redistribution layer 320 of the bonding surface 30a; and forming a second conductive bump 520 on the chip bridge 200 of the bonding surface 30a.
[0143] The first conductive bumps 510 are used to subsequently realize electrical connection between the first chip and the rewiring layer 320 , and electrical connection between the chip structure and the rewiring layer 320 .
[0144] In this embodiment, the material of the first conductive bump 510 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 510 is tin.
[0145] In this embodiment, the first conductive bump 510 may be a micro bump (uBump), which has a high density and is beneficial for improving the communication speed between the first chip and the redistribution layer 320 , and between the chip structure and the redistribution layer 320 .
[0146] The second conductive bumps 520 are used to realize electrical connection between the first chip and the chip bridge 200 , and electrical connection between the chip structure and the chip bridge 200 .
[0147] In this embodiment, the material of the second conductive bump 520 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 520 is tin.
[0148] In this embodiment, the second conductive bumps 520 may be micro bumps (uBumps), which have a higher density and are beneficial for improving the communication speed between the first chip 440 and the chip bridge 200 , and between the chip structure 400 and the chip bridge 200 .
[0149] refer to Fig.10, providing a first chip 440; providing a chip structure 400.
[0150] The first chip 440 is used to be electrically connected to the interconnection structure to achieve electrical connection between the first chip 440 and the chip structure 400 , and subsequently, electrical connection between the first chip 440 and the substrate.
[0151] In this embodiment, the first chip 440 is a logic chip, and in this embodiment, as a first logic chip, it is used to control the memory chip of the chip structure 400. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).
[0152] The chip structure 400 is used to be electrically connected to the interconnection structure to achieve electrical connection between the chip structure 400 and the first chip 440 , and subsequent electrical connection between the chip structure 400 and the substrate.
[0153] In this embodiment, the chip structure 400 includes one or more longitudinal directions (such as Figure 2 A plurality of second chips 410 are stacked (as shown in the Z direction), so as to subsequently realize electrical connection between each second chip 410 and the first chip 440, and electrical connection between each second chip 410 and the substrate.
[0154] In this embodiment, in the chip structure 400, a plurality of second chips 410 stacked in the vertical direction form a high bandwidth memory (HBM) structure, which is conducive to meeting the requirement for higher information transmission speed by adopting the HBM structure.
[0155] The second chip 410 includes a bottom chip at the bottom and a top chip stacked on the bottom chip, and the number of the top chips can be one or more. In this embodiment, the number of the top chips is four as an example for description. In other embodiments, the number of the top chips can also be other numbers.
[0156] Therefore, in this embodiment, the top chip is a memory chip. In a specific implementation, the top chip is a high bandwidth memory chip.
[0157] In this embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as a logic control chip in the chip structure 400 .
[0158] Continue to refer Fig.10, the chip structure 400 and the first chip 440 are bonded to the bonding surface 30a of the interconnection structure, the chip structure 400 is located on the side of the first chip 440, the chip structure 400 is electrically connected to the rewiring layer 320, the first chip 440 is electrically connected to the rewiring layer 320, and the first chip 440 is electrically connected to the chip structure 400 through the chip bridge 200.
[0159] Specifically, the first chip 440 is electrically connected to the wiring layer 320, and is subsequently electrically connected to the substrate through the re-wiring layer 320. The first chip 440 is electrically connected to each chip structure 400 through the chip bridge 200. The chip structure 400 is electrically connected to the wiring layer 320, and is subsequently electrically connected to the substrate through the re-wiring layer 320. The chip structure 400 is electrically connected to the first chip 440 through the chip bridge 200.
[0160] refer to Fig.11 The packaging method further includes: forming a first sealing layer 600 filling the gaps between adjacent first conductive bumps 510 and between adjacent second conductive bumps 520 , wherein the first sealing layer 600 covers the first conductive bumps 510 and the second conductive bumps 520 .
[0161] The first sealing layer 600 is used to achieve sealing between the interconnect structure and the first chip 440 , to achieve sealing between the interconnect structure and the chip structure 400 , and to achieve sealing between the first conductive bump 510 and the second conductive bump 520 .
[0162] Continue to refer Fig.11 The packaging method further includes: forming a plastic encapsulation layer 610 on the sidewalls of the chip structure 400 , the sidewalls of the first chip 440 , and between the chip structure 400 and the first chip 440 .
[0163] The plastic encapsulation layer 610 is used to protect the chip structure 400 and the first chip 440 .
[0164] In this embodiment, the material of the plastic encapsulation layer 610 is a plastic encapsulation material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the first plastic encapsulation layer can also be made of other suitable packaging materials.
[0165] In this embodiment, after the chip structure 400 and the first chip 440 are bonded to the bonding surface 30 a of the interconnection structure, the second carrier substrate 120 is removed before the interconnection structure is subsequently bonded to the substrate.
[0166] The second carrier substrate 120 is removed to expose the surface of the interconnection structure facing away from the bonding surface 30 a , in preparation for subsequently bonding the interconnection structure to the substrate.
[0167] refer to Fig.12 , providing a substrate 100.
[0168] The substrate 700 is used to provide a process operation basis for bonding the chip structure 400 , the first chip 440 and the interconnection structure.
[0169] In this embodiment, the substrate 700 includes a base and an interconnection layer located on the base, and the exposed surface of the interconnection layer is a process operation platform.
[0170] The interconnection layer is used to bond with the interconnection structure, thereby achieving electrical connection with the chip structure 400 and the first chip 440. The interconnection layer is also used to achieve electrical connection with the substrate, and accordingly can achieve electrical connection between the chip structure 400 and the first chip 440 and the substrate.
[0171] In this embodiment, the interconnection layer is a redistribution structure. Specifically, the redistribution structure may include one or more layers of redistribution interconnection layers.
[0172] The substrate is used to realize electrical connection between the chip structure 400 and the first chip 440 through the interconnection layer, and can be electrically connected to the external structure accordingly, thereby realizing electrical connection between the chip structure 400 and the first chip 440 and the external structure.
[0173] Specifically, in this embodiment, the substrate is a packaging substrate, and the packaging substrate is a printed circuit board (Printed Circuit Board, PCB).
[0174] In this embodiment, after the chip structure 400 and the first chip 440 are bonded to the bonding surface 30 a of the interconnect structure and before the interconnect structure is bonded to the substrate 700 , the packaging method further includes: forming a third conductive bump 530 on the substrate 700 .
[0175] The third conductive bump 530 is used to realize electrical connection between the interconnect structure and the substrate 700 .
[0176] In this embodiment, the material of the third conductive bump 530 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the third conductive bump 530 is tin.
[0177] In this embodiment, the third conductive bump 530 can be C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the same first conductive bump spacing, the I / O number can be very high and is not limited by the size of the rewiring structure. In addition, it is suitable for mass production and greatly reduces size and weight.
[0178] Continue to refer Fig.12 After the chip structure 400 and the first chip 440 are bonded to the bonding surface 30 a of the interconnection structure, the interconnection structure is bonded to the substrate 700 , with the bonding surface 30 a facing away from the substrate 700 .
[0179] Specifically, the first chip 440 is electrically connected to the wiring layer 320, and is electrically connected to the substrate 700 through the re-wiring layer 320. The first chip 440 is electrically connected to each chip structure 400 through the chip bridge 200. The chip structure 400 is electrically connected to the wiring layer 320, and is electrically connected to the substrate 700 through the re-wiring layer 320. The chip structure 400 is electrically connected to the first chip 440 through the chip bridge 200.
[0180] In this embodiment, the bottom chip and the substrate 700 , as well as the adjacent second chips 410 in the vertical direction are electrically connected, thereby achieving electrical integration between the second chips 410 and electrical integration between the second chips 410 and the substrate 700 .
[0181] In this embodiment, there are multiple chip structures 400 , and multiple chip structures 400 are electrically connected to the first chip 440 , which is beneficial to increasing the memory of the package structure, improving the chip speed and reducing the chip power consumption.
[0182] Accordingly, in this embodiment, in the step of bonding the interconnect structure to the substrate 700, the third conductive bump 530 electrically connects the interconnect structure to the substrate 700.
[0183] In this embodiment, after bonding the interconnect structure to the substrate 700 , the packaging method further includes: forming a second sealing layer 620 between the interconnect structure and the substrate 700 to fill the gap between the interconnect structure and the substrate 700 and the gap between adjacent third conductive bumps 530 .
[0184] The second sealing layer 620 is used to achieve sealing between the interconnect structure and the substrate 700 , and to achieve sealing of the third conductive bump 530 .
[0185] In this embodiment, the packaging method further includes: forming a fourth conductive bump 540 on the bottom of the substrate 700 .
[0186] The fourth conductive bump 540 is used to realize electrical connection between the substrate 700 and the outside.
[0187] In this embodiment, the material of the fourth conductive bump 540 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the fourth conductive bump 540 is tin.
[0188] In this embodiment, the fourth conductive bump 540 may be a ball grid array (BGA) structure.
[0189] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A packaging structure, characterized in that: include: substrate; An interconnect structure bonded to the substrate, the interconnect structure comprising a rewiring layer and a chip bridge embedded in the rewiring layer, the interconnect structure comprising a bonding surface, the bonding surface exposing the chip bridge surface; A first chip bonded to a bonding surface of the interconnect structure, the first chip being electrically connected to the redistribution layer and the chip bridge; A chip structure is bonded to a bonding surface of an interconnection structure on a side of the first chip, the chip structure is electrically connected to the redistribution layer, and the chip structure is electrically connected to the first chip via the chip bridge.
2. The packaging structure according to claim 1, characterized in that: On the bonding surface, the redistribution layer is flush with the chip bridge surface.
3. The packaging structure according to claim 1, characterized in that: The chip bridge is electrically isolated from the redistribution layer.
4. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a first conductive bump, located between the rewiring layer and the first chip, and between the rewiring layer and the chip structure, and electrically connecting the rewiring layer and the first chip, and electrically connecting the rewiring layer and the chip structure; The second conductive bump is located between the chip bridge and the first chip, and between the chip bridge and the chip structure, and electrically connects the chip bridge and the first chip, and electrically connects the chip bridge and the chip structure.
5. The packaging structure according to claim 4, characterized in that: The packaging structure further includes: a first sealing layer, which fills the gaps between adjacent first conductive bumps and between adjacent second conductive bumps and covers the first conductive bumps and the second conductive bumps.
6. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a third conductive bump located between the interconnection structure and the substrate and electrically connecting the interconnection structure and the substrate.
7. The packaging structure according to claim 6, characterized in that: The packaging structure further includes: a second sealing layer, which is located between the interconnection structure and the substrate and fills the gap between the interconnection structure and the substrate and the gap between adjacent third conductive bumps.
8. The packaging structure according to claim 1, characterized in that: The first chip includes a logic chip, the chip structure includes one or a plurality of second chips stacked in a longitudinal direction, and the second chip includes a memory chip.
9. The packaging structure according to claim 1, characterized in that: The chip bridge has a thickness of 2 μm to 15 μm.
10. A packaging method, characterized in that: include: providing a substrate; forming an interconnect structure, including a rewiring layer and a chip bridge embedded in the rewiring layer, wherein the interconnect structure includes a bonding surface, and the bonding surface exposes a surface of the chip bridge; providing a first chip; Providing chip structure; Bonding the chip structure and the first chip to the bonding surface of the interconnect structure, wherein the chip structure is located on the side of the first chip, the chip structure is electrically connected to the rewiring layer, the first chip is electrically connected to the rewiring layer, and the first chip is electrically connected to the chip structure via the chip bridge; After the chip structure and the first chip are bonded to the bonding surface of the interconnection structure, the interconnection structure is bonded to the substrate, with the bonding surface facing away from the substrate.
11. The packaging method according to claim 10, characterized in that: In the step of forming the interconnect structure, on the bonding surface, the rewiring layer is flush with the chip bridge surface.
12. The packaging method according to claim 10, characterized in that: In the step of forming the interconnect structure, the chip bridge is electrically isolated from the redistribution layer.
13. The packaging method according to claim 10, characterized in that: The steps of forming the interconnect structure include: providing a first carrier substrate; bonding the chip bridge on the first carrier substrate; forming a rewiring layer covering the chip bridge, wherein the rewiring layer and the chip bridge constitute the interconnection structure, wherein the bonding surface faces the first carrier substrate; The first carrier substrate is removed.
14. The packaging method according to claim 13, characterized in that: The step of bonding the chip bridge on the first carrier substrate includes: providing an initial chip bridge; bonding the initial chip bridge to the first carrier substrate, wherein the circuit structure of the initial chip bridge faces the first carrier substrate; The initial chip bridge is thinned, and the remaining initial chip bridge having the circuit structure is retained as the chip bridge.
15. The packaging method according to claim 13, characterized in that: The step of forming a rewiring layer covering the chip bridge includes: forming a dielectric layer covering the chip bridge; An electrical connection structure is formed in the dielectric layer to constitute the rewiring layer.
16. The packaging method according to claim 13, characterized in that: After forming the interconnect structure and before removing the first carrier substrate, the packaging method further includes: bonding a second carrier substrate on the interconnect structure; removing the first carrier substrate to expose the bonding surface; After the chip structure and the first chip are bonded to the bonding surface of the interconnection structure, and before the interconnection structure is bonded to the substrate, the second carrier substrate is removed.
17. The packaging method according to claim 10, characterized in that: After forming the interconnect structure and before bonding the chip structure and the first chip to the bonding surface of the interconnect structure, the packaging method further includes: forming a first conductive bump on the rewiring layer of the bonding surface; and forming a second conductive bump on the chip bridge of the bonding surface.
18. The packaging method according to claim 17, characterized in that: The packaging method further includes: forming a first sealing layer filled in gaps between adjacent first conductive bumps and between adjacent second conductive bumps, wherein the first sealing layer covers the first conductive bumps and the second conductive bumps.
19. The packaging method according to claim 10, characterized in that: After bonding the chip structure and the first chip to the bonding surface of the interconnect structure and before bonding the interconnect structure to the substrate, the packaging method further includes: forming a third conductive bump on the substrate; In the step of bonding the interconnect structure to the substrate, the third conductive bump electrically connects the interconnect structure and the substrate.
20. The packaging method according to claim 19, characterized in that: After bonding the interconnect structure to the substrate, the packaging method further includes: forming a second sealing layer between the interconnect structure and the substrate to fill the gap between the interconnect structure and the substrate and the gap between adjacent third conductive bumps.