Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a first carrier plate, and forming a plastic packaging layer covering a first chip and at least one metal column; removing a part of the plastic packaging layer and a part of the semiconductor layer to obtain a groove at least located between adjacent electric connecting pieces; forming a dielectric layer covering the top surface of the electric connector at least in the groove; removing at least part of the dielectric layer until the top surfaces of the residual dielectric layer, the electric connecting piece and the metal column are flush with one another; after a second circuit layer electrically connected with the metal columns and the electric connecting pieces is formed, a second carrier plate is formed on the second circuit layer; removing the first carrier plate to expose the first circuit layer used for being electrically connected with at least one second chip; according to the embodiment of the invention, the circuit bearing capacity of the packaging body can be improved at least under the condition that the yield and the reliability of the packaged semiconductor structure are not reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor technology, the integration of semiconductor structure packages is getting higher and higher, resulting in an increase in the bearing pressure of a single circuit in the package.

[0003] In the related art, a bridge chip is generally introduced to increase the circuit bearing pressure. However, during or after the bonding connection between the bridge chip and the chip to be packaged, some process steps will inevitably be introduced, resulting in adverse effects on the chip to be packaged, and reducing the yield and reliability of the semiconductor structure after packaging. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure to address the technical problems in the prior art, which can at least improve the circuit carrying capacity of the package body while ensuring that the yield and reliability of the semiconductor structure after packaging are not reduced.

[0005] In order to achieve the above objectives, on the one hand, the present application provides a method for preparing a semiconductor structure, comprising:

[0006] A first carrier is provided, wherein the top surface of the first carrier comprises a first circuit layer; the first circuit layer comprises a first chip and at least one metal column located outside the first chip; the first chip comprises an electrical connector and a semiconductor layer wrapping the electrical connector;

[0007] forming a plastic encapsulation layer covering the first chip and at least one metal pillar;

[0008] Removing part of the plastic encapsulation layer and part of the semiconductor layer to obtain a groove at least between adjacent electrical connectors;

[0009] forming a dielectric layer covering a top surface of the electrical connector at least in the groove;

[0010] Removing at least a portion of the dielectric layer until the top surfaces of the remaining dielectric layer, the electrical connector, and the metal pillars are flush;

[0011] After forming a second circuit layer electrically connected to the metal pillars and the electrical connectors, forming a second carrier on the second circuit layer;

[0012] The first carrier is removed to expose a first circuit layer for electrically connecting to at least one second chip.

[0013] In one embodiment, the top surface of the semiconductor layer is higher than the top surface of the metal pillar; and forming the groove comprises:

[0014] Removing part of the plastic encapsulation layer until the top surface of the semiconductor layer is flush with the top surface of the remaining plastic encapsulation layer;

[0015] The top surface of the semiconductor layer is etched back to obtain grooves at least between adjacent electrical connectors.

[0016] In one embodiment, removing at least a portion of the dielectric layer includes:

[0017] The top surface of the dielectric layer is planarized until the top surface of the remaining electrical connector is flush with the top surfaces of the remaining metal pillar and the remaining dielectric layer.

[0018] In one embodiment, after the top surface of the dielectric layer is planarized by a chemical mechanical polishing process;

[0019] A targeted cleaning process is used to remove grinding debris.

[0020] In one embodiment, forming the groove includes:

[0021] Selectively etching and removing a portion of the semiconductor layer to expose the electrical connectors at a first target height, and forming grooves between adjacent electrical connectors and between adjacent electrical connectors and the plastic packaging layer.

[0022] In one embodiment, a first carrier board is provided, comprising:

[0023] Providing a substrate, the substrate comprising a first carrier and a first bonding layer located on the first carrier;

[0024] forming a first circuit layer on the first bonding layer; wherein the first circuit layer includes a plurality of first connecting members;

[0025] A first chip and at least one metal column located outside the first chip are formed on the first circuit layer; the electrical connection member of the first chip is electrically connected to a part of the first connection member.

[0026] In one embodiment, forming the second circuit layer includes:

[0027] A plurality of third connecting members are formed on the plastic encapsulation layer; wherein the third connecting members are at least electrically connected to the electrical connecting member;

[0028] forming a solder pad at an end of the third connecting member facing away from the first carrier board;

[0029] A soldering point is formed on the soldering pad; a side of the soldering point facing away from the first carrier board is used for fixing with the second carrier board.

[0030] In one embodiment, forming the second carrier includes:

[0031] Forming a protective layer on the solder joint;

[0032] The side of the protective layer facing away from the first carrier board is fixed to the second carrier board.

[0033] In one embodiment, the first target height is 10 micrometers to 15 micrometers.

[0034] In the second aspect, the present application also provides a semiconductor structure, including a second carrier, a second circuit layer, a first chip, a metal column and a dielectric layer, the second circuit layer is located on the second carrier, the second circuit layer is on a side away from the second carrier, and includes a first chip and at least one metal column located outside the first chip; between adjacent metal columns, and between adjacent metal columns and the first chip, a plastic encapsulation layer whose top surface is flush with the top surface of the metal column; the first chip includes an electrical connector and a semiconductor layer wrapping the electrical connector; the top surface of the semiconductor layer is lower than the top surface of the electrical connector and the top surface of the plastic encapsulation layer and forms a groove; the groove includes a dielectric layer whose top surface is flush with the top surface of the electrical connector; the second circuit layer is electrically connected to the metal column and the electrical connector; the first chip includes a first circuit layer on a side away from the second carrier, and the first circuit layer is used to be electrically connected to at least one second chip.

[0035] In one embodiment, the distance between the top surface of the electrical connection and the top surface of the semiconductor layer is a first target height.

[0036] The semiconductor structure preparation method and semiconductor structure of the present application have the following unexpected technical effects:

[0037] A first carrier is provided, wherein the top surface of the first carrier comprises a first circuit layer, the first circuit layer comprises a first chip and at least one metal column located at the periphery of the first chip, and the first chip comprises an electrical connector and a semiconductor layer wrapping the electrical connector; then a plastic encapsulation layer covering the first chip and the at least one metal column is formed, and after removing a portion of the plastic encapsulation layer and a portion of the semiconductor layer, a groove at least located between adjacent electrical connectors is obtained, so that a dielectric layer covering the top surface of the electrical connector is formed at least in the groove, and the top surface of the electrical connector and the semiconductor layer are isolated by the dielectric layer, so that in the process of removing a portion of the dielectric layer to obtain the dielectric layer, the electrical connector and the metal column with uniform top surfaces, contamination of the removed material of the electrical connector is avoided The semiconductor layer is contaminated to avoid the formation of a current leakage channel by the removed material of the electrical connector; then after forming a second circuit layer electrically connected to the metal pillar and the electrical connector, a second carrier is formed on the second circuit layer, and then the first carrier is removed to expose the first circuit layer for electrical connection with at least one second chip. Since the second chip electrically connected to the first circuit layer is formed after forming the first chip for acting as a "bridge chip" and debonding and removing the first carrier, it is possible to avoid the first chip being adversely affected by the process technology during the introduction of the first chip or debonding and removal of the first carrier, and the first chip can act as a "bridge chip" to improve the circuit carrying capacity of the package. Therefore, the embodiment of the present application can at least improve the circuit carrying capacity of the package while ensuring that the yield and reliability of the semiconductor structure after packaging are not reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0040] Figure 2a-2j is a schematic cross-sectional view of a semiconductor structure provided in an embodiment;

[0041] Figure 3a-3h Schematic cross-sectional view of a first carrier provided in a method for preparing a semiconductor structure provided in an embodiment, wherein the first carrier includes a first bonding layer, a first circuit layer, a first chip, a metal column and a plastic packaging layer;

[0042] Figure 4a-4e is a schematic cross-sectional view of a structure obtained after a dielectric layer is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0043] Figure 5a-5c It is a schematic cross-sectional view of a structure obtained after forming a second carrier in a method for preparing a semiconductor structure provided in an embodiment;

[0044] Figure 6a-6c It is a schematic cross-sectional view of a structure obtained after forming a second chip in a method for preparing a semiconductor structure provided in an embodiment.

[0045] Reference numerals and descriptions:

[0046] 101, first carrier; 102, protective layer; 103, second carrier; 20, first bonding layer; 40, first chip; 401, adhesive layer; 402, semiconductor layer; 403, internal connector; 404, electrical connector; 301, first dielectric layer; 302, metal pillar; 303, first connector; 501, first plastic layer; 502, second plastic layer; 503, plastic layer; 60, first redistribution layer; 601, second dielectric layer; 602, first metal layer; 603, pad; 701, second chip; 702, glue layer; 80, second redistribution layer; 801, third dielectric layer; 802, second metal layer; 803, solder joint; 804, third connector; 805, fourth dielectric layer; 90, dielectric layer. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0050] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0051] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0053] In some embodiments, please refer to Figure 1 , the present application provides a method for preparing a semiconductor structure, including: step S10-step S40.

[0054] Step S10: providing a first carrier, wherein the top surface of the first carrier comprises a first circuit layer; the first circuit layer comprises a first chip and at least one metal pillar located outside the first chip; the first chip comprises an electrical connector and a semiconductor layer wrapping the electrical connector;

[0055] Step S20: forming a plastic encapsulation layer covering the first chip and at least one metal pillar;

[0056] Step S30: removing part of the plastic packaging layer and part of the semiconductor layer to obtain a groove at least between adjacent electrical connectors;

[0057] Step S40: forming a dielectric layer at least in the groove to cover the top surface of the electrical connector;

[0058] Step S50: removing at least part of the dielectric layer until the top surfaces of the remaining dielectric layer, the electrical connector and the metal pillar are flush with each other;

[0059] Step S60: After forming a second circuit layer electrically connected to the metal pillars and the electrical connectors, a second carrier is formed on the second circuit layer;

[0060] Step S70: removing the first carrier to expose a first circuit layer for electrically connecting to at least one second chip.

[0061] For example, please continue to refer to Figure 1, by providing a first carrier, the top surface of the first carrier includes a first circuit layer, the first circuit layer includes a first chip and at least one metal column located outside the first chip, the first chip includes an electrical connector and a semiconductor layer wrapping the electrical connector; then forming a plastic encapsulation layer covering the first chip and the at least one metal column, after removing part of the plastic encapsulation layer and part of the semiconductor layer, obtaining a groove at least between adjacent electrical connectors, so as to form a dielectric layer covering the top surface of the electrical connector at least in the groove, and using the dielectric layer to isolate the top surface of the electrical connector and the semiconductor layer, so as to avoid contamination of the electrical connector by removing material in the process of removing part of the dielectric layer to obtain the dielectric layer, the electrical connector and the metal column with uniform top surfaces The semiconductor layer is contaminated to avoid the formation of a current leakage channel by the removed material of the electrical connector; then after forming a second circuit layer electrically connected to the metal pillar and the electrical connector, a second carrier is formed on the second circuit layer, and then the first carrier is removed to expose the first circuit layer for electrical connection with at least one second chip. Since the second chip electrically connected to the first circuit layer is formed after forming the first chip for acting as a "bridge chip" and debonding and removing the first carrier, it is possible to avoid the first chip being adversely affected by the process technology during the introduction of the first chip or debonding and removal of the first carrier, and the first chip can act as a "bridge chip" to improve the circuit carrying capacity of the package. Therefore, the embodiment of the present application can at least improve the circuit carrying capacity of the package while ensuring that the yield and reliability of the semiconductor structure after packaging are not reduced.

[0062] In some embodiments, step S10 includes:

[0063] Step S102: Provide a first carrier, the top surface of the first carrier includes a first bonding layer, a first circuit layer, and a first chip stacked in sequence along a direction away from the first carrier; the first circuit layer includes a first chip and at least one metal column located outside the first chip; the first chip includes an electrical connector and a semiconductor layer wrapping the electrical connector.

[0064] As an example, the material of the first carrier may include one of glass, metal, semiconductor, polymer and ceramic; in other embodiments, the present application does not limit the material and shape of the first carrier, and the first carrier is used to support the subsequently formed film layer.

[0065] As an example, the material of the first bonding layer may include a double-sided adhesive tape or an adhesive layer. The present application does not limit the material of the first bonding layer, as long as it can meet the requirement of bonding the first carrier board and the first circuit layer.

[0066] As an example, the first circuit layer may include a circuit layer, for example, a stack of a dielectric layer and a metal layer, or may include multiple circuit layers, for example, multiple dielectric layers and metal layers. In other embodiments, the present application does not impose any specific restrictions on the number of layers of the first circuit layer, and the first circuit layer is used to connect chips or other circuit layers on both sides of the first circuit layer along the first direction.

[0067] As an example, the first chip may include a bridge chip, a system on chip (SOC), a high bandwidth memory (HBM), etc. In other embodiments, the present application does not specifically limit the type of the first chip, and the first chip is used to implement a certain function.

[0068] As an example, the materials of the first connector and the electrical connector may include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0069] As an example, the material of the semiconductor layer may include silicon (Si) material, silicon germanium (SiGe) material, silicon germanium carbon (SiGeC) material, silicon carbide (SiC) material, gallium arsenide (GaAs) material, indium arsenide (InAs) material, indium phosphide (InP) material or other III / V semiconductor materials or II / VI semiconductor materials. The electrical connector is located in the semiconductor layer, and one end of the electrical connector is exposed to the semiconductor layer, and the surface of the semiconductor layer that exposes one end of the electrical connector is the active surface of the first chip.

[0070] In some embodiments, an injection molding process may be used in step S20 to form a plastic packaging layer covering the first chip and the metal pillars.

[0071] As an example, the material of the plastic encapsulation layer may include one or a combination of a polyimide layer (PI), a silicone layer, and an epoxy resin layer. The present application does not impose any specific restrictions on the material of the plastic encapsulation layer.

[0072] In some embodiments, in step S30, one or more of grinding, dry etching, and wet etching can be used to remove part of the plastic encapsulation layer and part of the semiconductor layer until the end of the electrical connector facing away from the first carrier protrudes out of the remaining semiconductor layer, thereby obtaining a groove at least between adjacent electrical connectors.

[0073] In some embodiments, a spin coating process may be used to form a dielectric layer in the groove in step S40 .

[0074] Illustratively, the height of the electrical connector above the semiconductor layer portion is a first target height, and the thickness of the dielectric layer is greater than the first target height, so that the dielectric layer covers the top surface of the electrical connector.

[0075] In some embodiments, in step S50, a grinding process may be used to remove part of the dielectric layer and part of the plastic layer along a first direction perpendicular to the top surface of the first carrier until the electrical connectors and the metal pillars are exposed, so that the top surfaces of the remaining dielectric layer, electrical connectors and metal pillars are all flush.

[0076] In the above embodiment, since the circuit material generated during the grinding process will not diffuse into the semiconductor layer below the dielectric layer, the use of the dielectric layer to cover the semiconductor layer can avoid the formation of a current leakage channel to induce a short circuit event.

[0077] In some embodiments, the second carrier in step S60 may be a single-layer structure or a multi-layer structure including different film layers.

[0078] In some embodiments, in step S70, an exposure method may be used to reduce the viscosity of the first bonding layer, thereby removing the first carrier and the first bonding layer without damaging other film layers. The present application does not limit the specific method for removing the first carrier and the first bonding layer, and the method may be selected according to the material of the first bonding layer.

[0079] As an example, the second chip may include a bridge chip, a system on chip (SOC) high bandwidth memory (HBM), etc. In other embodiments, the present application does not specifically limit the type of the second chip, and the second chip is used to implement a certain function.

[0080] In addition, in some related technologies, please refer to Figure 2a-2jThe method for preparing the semiconductor structure may further include: providing a first carrier 101, forming a first bonding layer 20 on the first carrier 101, bonding the back side (i.e., the side opposite to the active side) of at least one first chip 40 to the first bonding layer 20 using an adhesive layer 401, and forming a first dielectric layer 301 and a plurality of metal pillars 302 on the first bonding layer 20, wherein the first chip 40 includes an internal connector 403 and a semiconductor layer 402 wrapping the internal connector, forming a first plastic encapsulation layer 501 on the first bonding layer 20, the first chip 40, and the metal pillars 302, removing a portion of the first plastic encapsulation layer 501 in a direction perpendicular to the top surface of the first carrier to expose the connection pins and the metal pillars 302 on the active side of the first chip 40, and forming a first redistribution layer 60 on the remaining first plastic encapsulation layer 501, the first redistribution layer 60 including a second dielectric layer 601, a first metal layer 602, The first redistribution layer 60 is connected to the connection pins of the first chip 40 and the metal pillar 302, at least one second chip 701 is formed on the first redistribution layer 60, the pad 603 of the second chip 701 is connected to the pad 603 of the first redistribution layer 60, the pad 603 is wrapped with the glue layer 702, and a second plastic encapsulation layer 502 is formed on the first redistribution layer 60 and the second chip 701, the semiconductor structure is turned over, and the first bonding layer 20 and the first carrier 101 are removed to expose the back side of the first chip 40, a part of the first plastic encapsulation layer 501 and the adhesive layer 401 are removed to expose the metal pillar 302, and a second redistribution layer 80 and a plurality of solder joints 803 are formed on the remaining first plastic encapsulation layer 501, the second redistribution layer 80 includes a third dielectric layer 801 and a second metal layer 802, and the second metal layer 802 is respectively connected to the metal pillar 302 and the plurality of solder joints 803. In the above example, since the performance of the semiconductor device is easily degraded or even scrapped due to high temperature during the process of removing the first bonding layer 20 and forming the solder joint 803, and the production cost of the second chip 701 is relatively high, the process of first forming the second chip 701 and then removing the first bonding layer 20 and forming the solder joint 803 greatly increases the probability of scrapping the second chip 701, resulting in an increase in the preparation cost of the semiconductor structure. In the present application, the second chip 701 is connected to the first circuit layer after removing the first carrier 101 and the first bonding layer 20, which greatly reduces the probability of scrapping the second chip 701 and saves production costs.

[0081] Please refer to Figure 3a-Figure 3bIn some embodiments, step S102 further includes a step of forming a reflective layer (not shown) on the first bonding layer 20; wherein the material of the reflective layer may include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al). In the above example, by forming the reflective layer on the first bonding layer 20, the reflection can be enhanced when the first bonding layer 20 is removed, thereby improving the efficiency of removing the first bonding layer 20.

[0082] As an example, see Figure 3c and Figure 3d , forming a first circuit layer on the first bonding layer 20 may include: forming a first dielectric layer 301 on the first bonding layer 20, the first dielectric layer 301 including a plurality of openings exposing the first bonding layer 20, forming a plurality of first connectors 303 on the first bonding layer 20 and the first dielectric layer 301 exposed by the openings, forming a second dielectric layer 601 on the plurality of first connectors 303 and the first dielectric layer 301, the second dielectric layer 601 including a plurality of openings exposing the plurality of first connectors 303; the first dielectric layer 301, the plurality of first connectors 303 and the second dielectric layer 601 are used to jointly constitute the first circuit layer.

[0083] As an example, see Figure 3e-3g Before the electrical connection member 404 of the first chip 40 is electrically connected to the first connection member 303, a step of forming a pad 603 on the first connection member 303 exposed by the partial opening is also included. By forming the pad 603 at one end of the electrical connection member 404 exposed on the active surface of the first chip 40, the pad 603 on the first chip 40 is connected to the pad 603 on the first connection member 303 by a welding technique such as reflow soldering, so that the electrical connection member 404 of the first chip 40 is electrically connected to the first connection member 303.

[0084] As an example, please refer to Figure 3g and Figure 3h Before forming the plastic encapsulation layer 503 on the first circuit layer and the first chip 40, a glue layer 702 can be formed between the active surface of the first chip 40 and the first circuit layer by a glue filling process. The glue layer 702 wraps the pads 603, the solder joints 605 on the first chip 40 and the pads 603 on the first connector 303, thereby enhancing the stability of the connection between the first chip 40 and the first circuit layer.

[0085] As an example, please refer to Figure 3h The first circuit layer includes a plurality of metal pillars 302, and the material of the metal pillars 302 may include one or more of metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0086] In some embodiments, please refer to Figure 4a and Figure 4b , remove part of the plastic encapsulation layer 503 and part of the semiconductor layer 402 , and make the remaining plastic encapsulation layer 503 cover the metal pillar 302 when the remaining semiconductor layer 402 exposes the electrical connection member 404 of the first target height.

[0087] As an example, see Figure 4a and Figure 4b , at the same time, the grinding process removes the same thickness of each region of the plastic encapsulation layer 503 and the semiconductor layer 402 in the first direction. The grinding process is used to remove part of the plastic encapsulation layer 503 and part of the semiconductor layer 402 along the first direction, so that the remaining semiconductor layer 402 and the remaining plastic encapsulation layer 503 cover the electrical connector 404 and the metal column 302. After the grinding process, the surface of the remaining semiconductor layer 402 away from the first carrier is higher than the surface of the electrical connector 404 away from the first carrier, and the second target distance B between the surface of the remaining semiconductor layer 402 away from the first carrier and the surface of the electrical connector 404 away from the first carrier is 5 microns-15 microns.

[0088] As an example, the second target distance B is 5 microns, 8 microns, 10 microns, 12 microns, 13 microns, 14 microns, 15 microns, etc.

[0089] As an example, the dry etching includes at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high concentration plasma etching (HDP).

[0090] In some embodiments, the first target height A is 10 micrometers to 15 micrometers.

[0091] As an example, see Figure 4c , the first target height A is 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, and 15 microns.

[0092] In the above embodiment, a grinding process is first used to remove part of the plastic encapsulation layer 503 and part of the semiconductor layer 402 along the first direction, so that the remaining semiconductor layer 402 and the remaining plastic encapsulation layer 503 do not expose the electrical connector 404 and the metal column 302, and then a dry etching process is used to remove part of the semiconductor layer 402 along the first direction to expose the electrical connector 404 of the first target height A. On the one hand, compared with directly using the dry etching process, this embodiment takes less time and can improve the removal efficiency of the plastic encapsulation layer 503 and the semiconductor layer 402. On the other hand, it can avoid the generation of circuit material in the process of removing the semiconductor layer 402 and exposing the electrical connector 404 during the grinding process, resulting in the diffusion of the circuit material into the remaining semiconductor layer 402, resulting in the formation of a current leakage channel between the circuit material in the semiconductor layer 402 and the devices and circuit structures in the semiconductor layer 402 in the subsequent process of connecting the electrical connector 404 and the second circuit layer.

[0093] As an example, see Figure 4d , the top surface of the dielectric layer 90 is planarized until the top surface of the remaining electrical connection 404 is flush with the top surfaces of the remaining metal pillars 302 and the remaining dielectric layer 90 .

[0094] The material of the dielectric layer 90 may include, but is not limited to, one or more of a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide (Al 2 O 3 ) or a silicon oxynitride layer (SiON).

[0095] As an example, the thickness of the dielectric layer 90 is greater than the first target height. In addition, the dielectric layer 90 may also cover the remaining plastic layer 503 .

[0096] As an example, see Figure 4e , a grinding process may be used to remove a portion of the dielectric layer 90 and the remaining plastic encapsulation layer 503 along a first direction until the electrical connector 404 and the metal pillar 302 are exposed.

[0097] In some embodiments, after the top surface of the dielectric layer is planarized by chemical mechanical polishing, a target cleaning process is used to remove polishing appendages. For example, conductive material debris, such as copper debris, remaining on the plastic encapsulation layer and the top surface of the first chip can be removed by dry etching.

[0098] In some embodiments, the target cleaning process includes: cleaning the top surfaces of the plastic encapsulation layer and the dielectric layer by air flow to remove conductive material debris, such as copper debris, remaining on the top surfaces of the plastic encapsulation layer and the dielectric layer.

[0099] In some embodiments, please refer to Figure 5a-5c In step S60, a second circuit layer (not shown) is formed on the plastic layer 503, including: step S602-step S606.

[0100] Step S602 : forming a plurality of third connecting members 804 on the plastic encapsulation layer 503 ; wherein the third connecting members 804 are at least electrically connected to the electrical connecting member 404 .

[0101] As an example, see Figure 5a and Figure 5b The second circuit layer includes a third dielectric layer 801 , a third connecting member 804 and a fourth dielectric layer 805 .

[0102] Step S604 : forming a solder pad 603 at one end of the third connecting member 804 away from the first carrier 101 .

[0103] As an example, please refer to Figure 5b , the pad 603 is electrically connected to the third connecting member 804 .

[0104] Step S606 : forming a solder joint 803 on the solder pad 603 . The solder joint 803 , which faces away from the first carrier 101 , is used for fixing to the second carrier 103 .

[0105] As an example, please refer to Figure 5b , a solder joint 803 may be formed on the solder pad 603 by using a reflow soldering process or a wave soldering process.

[0106] As an example, see Figure 5c The material of the protection layer 102 may include an adhesive layer having an adhesive property, and the solder joint 803 is fixed to the second carrier board 103 through the adhesive layer.

[0107] In some embodiments, please refer to Figure 6a-6c In step S70, an exposure process can be used to remove the first bonding layer 20 and the first carrier 101, a pad 603 is formed on the exposed first connector 303, the pad 603 on the active surface of the second chip 701 is connected to the pad 603 on the first connector 303, and the pad 603 is wrapped with an adhesive layer 702 to fix the second chip 701.

[0108] In the aforementioned embodiment of the present application, part of the first connector of the first circuit layer is electrically connected to the electrical connector of the first chip, the first circuit layer is electrically connected to at least one second chip, and the electrical connector of the first chip is also electrically connected to the second circuit layer. The first chip is directly used to connect to the second circuit layer and the second chip respectively, which increases the number of circuits, thereby reducing the bearing pressure of a single circuit. After removing part of the plastic encapsulation layer and part of the semiconductor layer and exposing the electrical connector of the first chip, a second circuit layer electrically connected to the electrical connector is formed on the plastic encapsulation layer, a second carrier is formed on the second circuit layer, and then the first carrier and the first bonding layer are removed by debonding to expose the first circuit layer, and then the second chip is formed on the first circuit layer, that is, the second chip is formed after the step of removing the first carrier and the first bonding layer by debonding. Compared with the step of performing the step of removing the first carrier and the first bonding layer by debonding after the second chip is formed, this embodiment avoids the adverse effects of the debonding process on the second chip, and effectively improves the yield and reliability of the semiconductor structure.

[0109] Furthermore, the present application can arrange for the electrical connector to partially protrude from the remaining semiconductor layer to form a groove, so that the dielectric layer covering the top surface of the electrical connector can be filled in the groove, thereby preventing the circuit material from diffusing into the remaining semiconductor layer during the process of planarizing the top surface of the dielectric layer. Therefore, when the electrical connector is electrically connected to the second circuit layer, it will not cause electrical connection between devices, circuit materials, etc. in the semiconductor layer, thereby avoiding the formation of a short circuit.

[0110] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0111] Please refer to Figure 6cIn some embodiments, the present application further provides a semiconductor structure, including: a second carrier 103, a plastic encapsulation layer 503, a first chip 40, a first circuit layer (not shown), a second circuit layer (not shown), a metal column 302 and a dielectric layer; the second circuit layer is located on the second carrier 103, the second circuit layer is away from the second carrier 103, and includes a first chip 40 and at least one metal column 302 located outside the first chip 40; adjacent metal columns 302, and adjacent metal columns 302 and the first chip 40 include top surfaces flush A plastic encapsulation layer 503 is provided on the top surface of the metal pillar 302; the first chip 40 includes an electrical connector 404 and a semiconductor layer 402 wrapping the electrical connector; the top surface of the semiconductor layer 402 is lower than the top surface of the electrical connector 404 and the top surface of the plastic encapsulation layer 503 and forms a groove; the groove includes a dielectric layer whose top surface is flush with the top surface of the electrical connector 402; the second circuit layer is electrically connected to the metal pillar 302 and the electrical connector 404; the side of the first chip 40 facing away from the second carrier 103 includes a first circuit layer, and the first circuit layer is used to be electrically connected to at least one second chip 701.

[0112] Please refer to Figure 4c-4d In some embodiments, the height of the electrical connector 404 protruding from the semiconductor layer 402 is a first target height A; the dielectric layer 90 is located between the second carrier 103 and the semiconductor layer 402, surrounding the electrical connector 404 of the first target height A; the surface of the dielectric layer 90 close to the second carrier 103 is flush with the surface of the plastic encapsulation layer 503 close to the second carrier 103.

[0113] In some embodiments, the first target height A is 10 micrometers to 15 micrometers.

[0114] As an example, the first target height A is 10 microns, 11 microns, 12 microns, 13 microns, 14 microns, or 15 microns.

[0115] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: A first carrier is provided, wherein the top surface of the first carrier comprises a first circuit layer; the first circuit layer comprises a first chip and at least one metal pillar located outside the first chip; the first chip comprises an electrical connector and a semiconductor layer wrapping the electrical connector; forming a plastic encapsulation layer covering the first chip and the at least one metal pillar; Removing part of the plastic encapsulation layer and part of the semiconductor layer to obtain a groove at least between adjacent electrical connectors; forming a dielectric layer covering a top surface of the electrical connector at least in the groove; removing at least a portion of the dielectric layer until the top surfaces of the remaining dielectric layer, the electrical connector, and the metal pillar are flush with each other; After forming a second circuit layer electrically connected to the metal pillars and the electrical connectors, forming a second carrier on the second circuit layer; The first carrier is removed to expose the first circuit layer for electrically connecting to at least one second chip.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The top surface of the semiconductor layer is higher than the top surface of the metal pillar; Forming the groove comprises: Removing part of the plastic encapsulation layer until the top surface of the semiconductor layer is flush with the top surface of the remaining plastic encapsulation layer; The top surface of the semiconductor layer is back-etched to obtain a groove at least between adjacent electrical connectors.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The at least partially removing the dielectric layer comprises: The top surface of the dielectric layer is planarized until the top surface of the remaining electrical connector is flush with the top surfaces of the remaining metal pillar and the remaining dielectric layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: After the top surface of the dielectric layer is planarized by chemical mechanical polishing process; A targeted cleaning process is used to remove grinding debris.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that: Forming the groove comprises: The semiconductor layer is partially etched and removed to expose the electrical connectors at a first target height, and the grooves are formed between adjacent electrical connectors and between adjacent electrical connectors and the plastic packaging layer.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The providing of the first carrier board comprises: Providing a substrate, the substrate comprising a first carrier and a first bonding layer located on the first carrier; forming a first circuit layer on the first bonding layer; wherein the first circuit layer includes a plurality of first connecting members; A first chip and at least one metal column located outside the first chip are formed on the first circuit layer; and the electrical connector of the first chip is electrically connected to a part of the first connector.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: Forming the second circuit layer includes: A plurality of third connecting members are formed on the plastic encapsulation layer; wherein the third connecting members are at least electrically connected to the electrical connecting members; forming a solder pad at an end of the third connecting member facing away from the first carrier board; A soldering point is formed on the soldering pad; a side of the soldering point facing away from the first carrier board is used for fixing with the second carrier board.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The second carrier board is formed, comprising: forming a protective layer on the solder joint; The side of the protective layer facing away from the first carrier board is fixed to the second carrier board.

9. A semiconductor structure, characterized in that: include: Second carrier board; A second circuit layer is located on the second carrier board, and the second circuit layer is on a side facing away from the second carrier board, and includes a first chip and at least one metal column located outside the first chip; a plastic packaging layer whose top surface is flush with the top surface of the metal column is included between adjacent metal columns, and between adjacent metal columns and the first chip; The first chip includes an electrical connector and a semiconductor layer wrapping the electrical connector; the top surface of the semiconductor layer is lower than the top surface of the electrical connector and the top surface of the plastic packaging layer and forms a groove; The groove includes a dielectric layer whose top surface is flush with the top surface of the electrical connector; the second circuit layer is electrically connected to the metal column and the electrical connector; The side of the first chip facing away from the second carrier board includes a first circuit layer, and the first circuit layer is used for electrically connecting to at least one second chip.

10. The semiconductor structure according to claim 9, characterized in that: The distance between the top surface of the electrical connection member and the top surface of the semiconductor layer is a first target height.

Images