Chip, protection circuit thereof and electronic device

Abstract

The invention discloses a protection circuit for a chip, and the circuit comprises an electrostatic detection unit which is used for generating and outputting an electrostatic generation signal when static electricity is generated on the chip; and the chip restarting unit is used for receiving the electrostatic generation signal and generating and outputting a chip restarting signal for restarting the chip in response to the electrostatic generation signal. The invention also discloses a chip comprising the protection circuit and an electronic device comprising the chip. By arranging the electrostatic detection unit and the chip restart unit, when ESD occurs on the chip, the electrostatic detection unit outputs the electrostatic generation signal, and the chip restart unit responds to the electrostatic generation signal and outputs the chip restart signal to restart the chip, so that a system where the chip is located is prevented from being in a crash state and still can work normally.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular, relates to a chip and a protection circuit and an electronic device thereof. Background Art

[0002] ESD (Electro-Static discharge) means "electrostatic discharge". The definition of electrostatic discharge or ESD is the transfer of electrostatic charge between objects or surfaces at different electrostatic potentials. The discharge releases extremely high voltage in a short period of time, in the kilovolt (kV) range of 1 to 100 nanoseconds (ns). Therefore, ESD generated on electronic components can cause serious damage to electronic components.

[0003] Generally speaking, when ESD occurs on a chip, the data in the chip will be disordered, which may cause the system where the chip is located to be in a "freeze" state and unable to work normally. Therefore, it is necessary to provide a solution to prevent the system where the chip is located from being in a "freeze" state when ESD occurs on the chip, and to still work normally. Summary of the invention

[0004] In order to solve the technical problems existing in the above-mentioned prior art, a chip and a protection circuit thereof, and an electronic device are provided according to an embodiment of the present invention.

[0005] According to one aspect of an embodiment of the present invention, a protection circuit for a chip provided includes: an electrostatic detection unit, which is used to generate and output an electrostatic generation signal when static electricity occurs on the chip; a chip restart unit, which is used to receive the electrostatic generation signal and generate and output a chip restart signal for restarting the chip in response to the electrostatic generation signal.

[0006] In an example of the protection circuit provided in the above aspect, the static electricity generation signal includes at least two level signals, wherein at least one of the level signals has a high level.

[0007] In an example of the protection circuit provided in the above aspect, the chip restart unit is composed of an OR gate, and the OR gate is used to receive the at least two level signals and output the chip restart signal with a high level in response to the at least two level signals.

[0008] In an example of the protection circuit provided in the above aspect, the electrostatic detection unit includes: at least two data storage modules, the data storage modules are used to store data; at least two data comparison modules, the data comparison modules correspond to the data storage modules one by one, the data comparison modules are used to compare the data stored in the corresponding data storage modules with the correct data, and output a level signal according to the comparison result; wherein, when static electricity occurs on the chip, the data stored in at least one of the data storage modules that is the same as the correct data is changed, and the corresponding data comparison module outputs a level signal with a high level according to the comparison result between the changed data and the correct data.

[0009] In an example of the protection circuit provided in the above aspect, the data storage module is composed of a register.

[0010] In an example of the protection circuit provided in the above aspect, the data comparison module is composed of an XOR gate.

[0011] In an example of the protection circuit provided in the above aspect, the register is adjacent to an input / output pin of the chip.

[0012] In an example of the protection circuit provided in the above aspect, the chip charging unit is connected to a restart pin of the chip to output the chip restart signal to the restart pin of the chip.

[0013] According to another aspect of an embodiment of the present invention, a chip is provided including the above protection circuit.

[0014] According to another aspect of an embodiment of the present invention, an electronic device is provided including the above chip.

[0015] Beneficial effect: According to an embodiment of the present invention, a protection circuit for a chip provided includes an electrostatic detection unit and a chip restart unit. The electrostatic detection unit is used to generate and output an electrostatic generation signal when static electricity occurs on the chip; the chip restart unit is used to receive the electrostatic generation signal, and generate and output a chip restart signal for restarting the chip in response to the electrostatic generation signal; when ESD occurs on the chip, the electrostatic detection unit outputs an electrostatic generation signal, and the chip restart unit outputs a chip restart signal in response to the electrostatic generation signal to restart the chip, thereby preventing the system where the chip is located from being in a "freeze" state and still being able to work normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and advantages of the embodiments of the present invention will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0017] Figure 1is a schematic diagram of a protection circuit for a chip according to an embodiment of the present invention;

[0018] Figure 2 is a circuit structure diagram of a static electricity detection unit according to an embodiment of the present invention;

[0019] Figure 3 4 is a circuit structure diagram of a chip restart unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following detailed description is provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present invention, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be clear. In addition, for greater clarity and simplicity, descriptions of features known in the art may be omitted.

[0021] The features described herein can be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein, which will be clear after understanding the disclosure of the present invention.

[0022] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more.

[0023] The terms used herein are only used to describe various examples and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" indicate the presence of the described features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the present invention belongs after understanding the present invention. Unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the present invention, and should not be interpreted in an idealized or overly formal manner.

[0025] Furthermore, in the description of the examples, when it is considered that a detailed description of a well-known related construction or function will cause vague interpretation of the present invention, such a detailed description will be omitted.

[0026] Figure 1is a schematic diagram of a protection circuit for a chip according to an embodiment of the present invention.

[0027] Reference Figure 1 According to an embodiment of the present invention, a protection circuit for a chip includes: an electrostatic detection unit 10 and a chip restart unit 20. The electrostatic detection unit 10 and the chip restart unit 20 can both be arranged on the chip XP.

[0028] Specifically, the static electricity detection unit 10 is used to generate and output a static electricity non-occurrence signal and a static electricity occurrence signal. When static electricity does not occur on the chip XP, the static electricity detection unit 10 generates and outputs a static electricity non-occurrence signal; and when static electricity occurs on the chip XP, the static electricity detection unit 10 generates and outputs a static electricity occurrence signal.

[0029] The chip restart unit 20 is used to generate and output a chip normal signal for enabling the chip XP to continue to work normally and a chip restart signal for restarting the chip XP. The chip restart unit 20 is connected to the static electricity detection unit 10 to receive a static electricity non-occurrence signal or a static electricity occurrence signal from the static electricity detection unit 10. When static electricity does not occur on the chip XP, the chip restart unit 20 receives the static electricity non-occurrence signal from the static electricity detection unit 10, and generates and outputs the chip normal signal in response to the static electricity non-occurrence signal; when static electricity occurs on the chip XP, the chip restart unit 20 receives the static electricity occurrence signal from the static electricity detection unit 10, and generates and outputs the chip restart signal in response to the static electricity occurrence signal.

[0030] As described above, when ESD occurs on chip XP, the electrostatic detection unit 10 generates and outputs an electrostatic generation signal, the chip restart unit 20 receives the electrostatic generation signal, and generates and outputs a chip restart signal in response to the electrostatic generation signal to restart the chip XP, thereby preventing the system where the chip XP is located from being in a "freeze" state and still being able to work normally.

[0031] The module principle of the above-mentioned static electricity detection unit 10 is further explained below. Figure 2 is a circuit structure diagram of a static electricity detection unit 10 according to an embodiment of the present invention.

[0032] Reference Figure 2 According to an embodiment of the present invention, the static electricity detection unit 10 includes: a data storage module 11 and a data comparison module 12 .

[0033] Specifically, the data storage module 11 is configured to store correct data, such as 8-bit binary data (eg, 10101010). When ESD occurs on the chip XP, the correct data stored in the data storage module 11 will be disturbed and changed, such as to "11101010".

[0034] That is, when ESD does not occur on chip XP, the data storage module 11 stores correct data such as "10101010"; when ESD occurs on chip XP, the correct data stored in the data storage module 11 is disturbed and changed to "11101010".

[0035] In this embodiment, the data storage module 11 is composed of a register, but the present invention is not limited thereto. In this case, the data storage module 11 is the register 11 .

[0036] Further, the data comparison module 12 is used to compare the data stored in the data storage module 11 with the correct data, and generate and output a level signal according to the comparison result. In this embodiment, the data comparison module 12 is composed of an XOR gate. In this case, the data comparison module 12 is the XOR gate 12.

[0037] In order to cover various areas near the input / output pins on the chip XP as much as possible, in this embodiment, a register 11 is respectively provided at the top, bottom, left, right and middle of the chip XP. That is, in this embodiment, five registers 11 are shown, but the present invention is not limited thereto, and the required number of registers 11 can be arbitrarily set according to actual needs, but at least two must be guaranteed.

[0038] Furthermore, since ESD is generally transmitted to the inside of the chip XP through the input / output pins, each register 11 is provided adjacent to the input / output pin to be detected.

[0039] Accordingly, the XOR gates 12 correspond to the registers 11 one by one, that is, the number of the XOR gates 12 is also 5. That is, one of the two input terminals of the XOR gate 12 is connected to the output terminal of the corresponding register 11, and the other is set to always receive the correct data.

[0040] When ESD does not occur on chip XP, the data stored in all registers 11 are not changed, that is, they are all correct data. At this time, each XOR gate 12 outputs a level signal with a low level, that is, 5 XOR gates 12 output 5 level signals with a low level, and these 5 level signals with a low level constitute the static electricity non-occurrence signal.

[0041] When ESD occurs on chip XP, for example, the data stored in one register 11 is changed by interference, that is, the data stored in this register 11 is the data after the interference change. At this time, the XOR gate 12 corresponding to this register 11 outputs a level signal with a high level, and the data stored in the other four registers 11 are not changed. The corresponding four XOR gates 12 all output level signals with low levels. At this time, one XOR gate 12 outputs a level signal with a high level, and the other four XOR gates 12 output four level signals with low levels. Therefore, this one level signal with a high level and the four level signals with a low level constitute the static electricity generation signal.

[0042] After describing the principle of the protection circuit and the circuit structure of the static electricity detection unit 10 , the circuit structure of the chip restart unit 20 will be described in detail below. Figure 3 FIG. 4 is a circuit structure diagram of a chip restart unit 20 according to an embodiment of the present invention.

[0043] Reference Figure 3 According to the embodiment of the present invention, the chip restart unit 20 is composed of an OR gate. In this case, the chip restart unit 20 is the OR gate 20. Next, the working process of the OR gate 20 is described by taking five registers 11 and five XOR gates 12 as an example.

[0044] When ESD does not occur on the chip XP, the data stored in all the registers 11 are not changed, that is, they are all correct data, and at this time, each XOR gate 12 outputs a level signal with a low level, that is, 5 XOR gates 12 output 5 level signals with a low level. The 5 input ends of the OR gate 20 receive the 5 level signals with a low level respectively, and in response to the 5 level signals with a low level, generate and output the chip normal signal with a low level to the restart pin of the chip XP, so that the chip XP continues to maintain normal operation.

[0045] When ESD occurs on chip XP, for example, the data stored in one register 11 is disturbed and changed, that is, the data stored in this register 11 is the data after the disturbance, at this time, the XOR gate 12 corresponding to this register 11 outputs a level signal with a high level, and the data stored in the other four registers 11 are not changed, and the corresponding four XOR gates 12 all output level signals with a low level. The five input ends of the OR gate 20 receive the one level signal with a high level and the four level signals with a low level respectively, and in response to the five level signals, generate and output the chip restart signal with a high level to the restart pin of the chip XP, so that the chip XP is restarted.

[0046] According to an embodiment of the present invention, there is also provided a chip XP, which includes the above protection circuit, wherein the chip XP may be a power management chip used in a television.

[0047] According to an embodiment of the present invention, an electronic device is also provided, the electronic device comprising a display panel and a chip XP. The display panel may be a liquid crystal display panel or an organic light emitting diode display panel. The electronic device provided by the embodiment of the present invention may be a product or component with a display function such as a mobile phone, a tablet computer, a laptop computer, a television, a digital camera, a navigator, etc.

[0048] In summary, a protection circuit for a chip provided according to an embodiment of the present invention includes an electrostatic detection unit and a chip restart unit. The electrostatic detection unit is used to generate and output an electrostatic generation signal when static electricity occurs on the chip; the chip restart unit is used to receive the electrostatic generation signal, and generate and output a chip restart signal for restarting the chip in response to the electrostatic generation signal; when ESD occurs on the chip, the electrostatic detection unit outputs an electrostatic generation signal, and the chip restart unit outputs a chip restart signal in response to the electrostatic generation signal to restart the chip, thereby preventing the system where the chip is located from being in a "freeze" state and still being able to work normally.

[0049] The specific implementation methods of the present invention are described in detail above. Although some embodiments have been shown and described, those skilled in the art should understand that these embodiments may be modified and varied without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents. These modifications and variations should also be within the scope of protection of the claims of the present invention.

Claims

1. A protection circuit for a chip, characterized in that: The protection circuit comprises: An electrostatic detection unit, used to generate and output a static electricity occurrence signal when static electricity occurs on the chip; The chip restart unit is used to receive the static electricity generation signal, and generate and output a chip restart signal for restarting the chip in response to the static electricity generation signal.

2. The protection circuit according to claim 1, characterized in that: The static electricity generation signal includes at least two level signals, wherein at least one of the level signals has a high level.

3. The protection circuit according to claim 2, characterized in that: The chip restart unit is composed of an OR gate, and the OR gate is used to receive the at least two level signals and output the chip restart signal with a high level in response to the at least two level signals.

4. The protection circuit according to claim 2 or 3, characterized in that: The electrostatic detection unit comprises: At least two data storage modules, wherein the data storage modules are used to store data; At least two data comparison modules, each corresponding to each of the data storage modules, and configured to compare the data stored in the corresponding data storage module with the correct data, and output a level signal according to the comparison result; When static electricity occurs on the chip, data stored in at least one of the data storage modules that is the same as the correct data is changed, and the corresponding data comparison module outputs a level signal with a high level according to the comparison result between the changed data and the correct data.

5. The protection circuit according to claim 4, characterized in that: The data storage module is composed of registers.

6. The protection circuit according to claim 4, characterized in that: The data comparison module is composed of an XOR gate.

7. The protection circuit according to claim 5, characterized in that: The registers are adjacent to input / output pins of the chip.

8. The protection circuit according to claim 1, characterized in that: The chip charging unit is connected to the restart pin of the chip to output the chip restart signal to the restart pin of the chip.

9. A chip, characterized in that: The protection circuit comprises the protection circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

Images