Power conversion circuit, memory and chip

Abstract

The invention provides a power conversion circuit, a memory and a chip. The power conversion circuit comprises an internal power conversion unit arranged in a redundant unit, and the redundant unit is located in a load area; wherein the internal power supply conversion unit receives a control signal and an external power supply, converts the external power supply into an internal power supply under the control of the control signal, and supplies power to each load unit in a load area; when each load unit is in the sleep mode, the internal power supply conversion unit cuts off the power supply of each load unit based on the control signal. According to the power conversion circuit, the memory and the chip, a power conversion function is added on the premise of not increasing extra modules and areas, so that an external power signal is converted into an internal signal, electric leakage is reduced, and a low-power-consumption design is realized; or after an additional power supply conversion function module is added, signal enhancement and voltage drop optimization are carried out on the internal signal.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a power conversion circuit, a memory and a chip. Background Art

[0002] During the use of integrated circuits, current will flow through various loads in the circuit. In addition to the normally working devices, unnecessary current loss is inevitable (such as transistor leakage current, parasitic capacitor charging and discharging, etc.). With the improvement of semiconductor manufacturing technology, the size of transistors is getting smaller and smaller, and the integration is getting higher and higher. The reduction of power supply voltage and threshold voltage will cause the leakage of transistors to increase sharply, and even reach almost the same as the dynamic current, which will cause the chip to generate a large amount of static power consumption. Excessive static power consumption will directly lead to an increase in the temperature of the chip, requiring a more expensive packaging and cooling system. In severe cases, it will also reduce the reliability and service life of the chip, and even cause the chip to fail.

[0003] Therefore, how to reduce the static power consumption and cost of the chip as much as possible while ensuring the area is a difficult problem that needs to be solved urgently by technical personnel in this field.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power conversion circuit, a memory and a chip, which are used to solve the problems of high static power consumption, large chip area and high cost in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a power conversion circuit, the power conversion circuit comprising:

[0007] An internal power conversion unit disposed in a redundant unit, wherein the redundant unit is located in the load region;

[0008] Among them, the internal power conversion unit receives a control signal and an external power supply, converts the external power supply into an internal power supply under the control of the control signal, and supplies power to each load unit in the load area; when each load unit is in a sleep mode, the internal power conversion unit cuts off the power supply of each load unit based on the control signal.

[0009] Optionally, the redundant unit is located at at least one end of the load area.

[0010] Optionally, a redundant transistor is provided in the redundant unit, and the internal power conversion unit is formed based on the redundant transistor.

[0011] Optionally, the power conversion circuit also includes an external power conversion unit arranged outside the load area, the external power conversion unit receives the control signal and the external power supply, converts the external power supply into an internal power supply under the control of the control signal, and supplies power to each load unit in the load area; when each load unit is in sleep mode, the external power conversion unit cuts off the power supply of each load unit based on the control signal.

[0012] More optionally, the driving current of the external power conversion unit is greater than the driving current of the internal power conversion unit.

[0013] More optionally, each power conversion unit converts a single external power supply into a corresponding single internal power supply based on a single control signal; or each power conversion unit converts N external power supplies into one-to-one corresponding N internal power supplies based on a single control signal; or each power conversion unit converts N external power supplies into one-to-one corresponding N internal power supplies based on N control signals; N is a natural number greater than or equal to 2.

[0014] More optionally, a PMOS tube is used to realize power conversion; the gate of the PMOS tube is connected to the corresponding control signal, the source is connected to the corresponding external power supply, and the drain outputs the converted internal power supply;

[0015] Alternatively, an NMOS tube is used to realize power conversion; the gate of the NMOS tube is connected to a corresponding control signal, the source is connected to a corresponding external power supply, and the drain outputs the converted internal power supply.

[0016] More optionally, the power conversion circuit further includes a control unit disposed outside the load region, and the control unit provides the control signal to each power conversion unit based on a clock signal and an external control instruction.

[0017] In order to achieve the above-mentioned object and other related objects, the present invention further provides a memory, wherein the memory at least comprises:

[0018] A memory cell array, redundant cells located around the memory cell array, a control module and a decoding module located outside the redundant cells, and the power conversion circuit;

[0019] The storage cell array and the redundant unit constitute the load area, and the internal power conversion unit is disposed in at least one redundant unit located at one side of the storage cell array.

[0020] In order to achieve the above-mentioned object and other related objects, the present invention further provides a chip, which at least includes: a load area and the above-mentioned power conversion circuit, and a redundant unit is arranged in the load area.

[0021] As described above, the power conversion circuit, memory and chip of the present invention have the following beneficial effects:

[0022] The power conversion circuit, memory and chip of the present invention can utilize the original module inside the IP, place the power conversion unit inside the load area, and realize low-power design by utilizing the existing layout, thereby reducing the design difficulty and layout complexity, and reducing the IP area; or, under the condition of the presence of an external power conversion unit, enhance the signal strength, reduce the IR voltage drop of the internal signal, and improve the performance of the chip. The power conversion circuit, memory and chip of the present invention are applicable to various process platforms and are suitable for promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a structural schematic diagram of an integrated circuit IP for reducing the static power consumption of a load module.

[0024] Figure 2 Shown is a structural schematic diagram of the power conversion circuit of the present invention.

[0025] Figure 3 It shows a schematic diagram of the structure of the present invention realizing a control signal controlling a power conversion based on a PMOS tube.

[0026] Figure 4 It shows a schematic diagram of the structure of the present invention realizing a control signal controlling a power conversion based on an NMOS tube.

[0027] Figure 5 It shows a schematic diagram of the structure of the present invention that realizes one control signal to control multiple power conversions based on PMOS tube.

[0028] Figure 6 It shows a schematic diagram of the structure of the present invention that realizes one control signal to control multiple power conversions based on NMOS tubes.

[0029] Figure 7 It shows a schematic diagram of the structure of the present invention that realizes multiple control signals to control multiple power conversions based on PMOS tubes.

[0030] Figure 8 It shows a schematic diagram of the structure of the present invention that realizes multiple control signals to control multiple power conversions based on NMOS tubes.

[0031] Fig. 9 Shown is another structural schematic diagram of the power conversion circuit of the present invention.

[0032] Fig.10 Shown is a schematic structural diagram of the memory of the present invention.

[0033] Component number description

[0034] 1 Load area

[0035] 11 Bottom load cell

[0036] 12 Top load cell

[0037] 13 Bottom redundant unit

[0038] 14 Top Redundant Units

[0039] 2 Power conversion module

[0040] 3 Power conversion circuit

[0041] 31 First internal power conversion unit

[0042] 32. Second internal power conversion unit

[0043] 33 Control unit

[0044] 34 External power conversion unit

[0045] 4 Memory

[0046] 41 Memory Cell Array

[0047] 42 Word Line Edge Cell

[0048] 43 bit line edge cells

[0049] 44 Control Module

[0050] 45 Decoding module

[0051] 46 Corner Unit DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] See also Figure 1-Figure 10It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] One method to reduce the static power consumption of the load module is to add an additional power switch module to the integrated circuit IP (Intellectual Property) to convert the external power signal (VDD, VSS) into the internal power signal used by the load module, and reduce the leakage by turning off the internal power signal in sleep mode. The additional power switch module 2 requires an increase in the layout area and the complexity of the layout and wiring, especially in a large IP. The external power switch module 2 is connected through a long-distance metal wire, the resistance of the metal wire increases, and the IR voltage drop of the internal power signal will be very serious. Figure 1 As shown, the internal power signal needs to be generated in an additional power conversion module 2, which increases the design difficulty and layout area; in addition, when the internal power signal passes through the load area 1, except for the bottom load unit that is closer, it has to pass through a long metal wire and then be supplied to the remote top load unit. The internal power signal becomes weaker and weaker. Even when it is transmitted to the farthest top load unit, the resistance value R generated by the metal wire is too large, and the internal power signal cannot reach the flipping voltage, causing the chip to fail to work properly.

[0055] In order to achieve low power consumption and save layout area, the present invention provides a power conversion circuit, and the specific scheme is as follows:

[0056] Embodiment 1

[0057] like Figure 2 As shown, this embodiment provides a power conversion circuit 3, and the power conversion circuit 3 includes:

[0058] An internal power conversion unit disposed in a redundant unit, the redundant unit being located in a load area;

[0059] Among them, the internal power conversion unit receives a control signal and an external power supply, converts the external power supply into an internal power supply under the control of the control signal, and supplies power to each load unit in the load area; when each load is in sleep mode, the internal power conversion unit cuts off the power supply of each load based on the control signal.

[0060] Specifically, at least two load units are provided in the load area 1, and each load unit can be arranged in a straight line, a curve, or an array. The specific number and arrangement method are configured according to actual needs, and will not be described in detail here; as an example, Figure 2 As shown, this embodiment includes at least two load units, which are arranged in sequence along the longitudinal direction. Figure 2 Only the bottom load cell 11 and the top load cell 12 are shown.

[0061] In order to meet the high-precision requirements of the signals generated in each load unit, redundant units (DUMMY) are set in the edge area or internal area of ​​the load area 1. These redundant units are only used to protect the transistors in the load area in terms of process, and do not have any substantial circuit design. The redundant units can be set at any position in the load area 1, including but not limited to the two oppositely set edge areas of the load area 1 (two ends), the edge areas of the load area 1 that are set opposite to each other (four ends), the edge areas of any orientation in the load area 1, or between any two load units (i.e., the middle area). As an example, Figure 2 As shown, in this embodiment, the bottom redundant unit 13 and the top redundant unit 14 are respectively located at the upper and lower ends of the load area 1, that is, the bottom redundant unit 13 is located outside the bottom load unit 11, and the top redundant unit 14 is located outside the top load unit 12.

[0062] Specifically, the internal power conversion unit is set in at least one redundant unit. For the case where the number of load units is large (occupying a large area), the internal power conversion unit can be set in multiple (2 or more) redundant units to provide a sufficiently large driving capability; of course, for the case where the number of load units is small (small area), the internal power conversion unit can also be set in only one redundant unit. The number of internal power conversion units can be adjusted according to the actual design requirements of the IP and the number of redundant units in the layout, which will not be described one by one here. As an example, Figure 2 As shown, in this embodiment, two internal power conversion units are provided, wherein the first internal power conversion unit 31 is provided in the bottom redundant unit 13, and the second internal power conversion unit 32 is provided in the top redundant unit 14; that is, internal power conversion units are provided in the redundant units located at opposite ends of the load area 1.

[0063] More specifically, the internal power conversion unit is controlled by the control signal CNT_PW, and converts the external power Vp into the internal power Vpw required by the load unit, where the external power Vp is the power voltage VDD and / or the reference ground VSS. In this embodiment, the internal power conversion unit is formed by the redundant transistors provided in the redundant unit through electrical connection, and the front-end process does not need to be changed.

[0064] As an implementation of the present invention, the load unit uses a single power supply, and the internal power conversion unit converts the single external power supply into a corresponding single internal power supply based on a single control signal. As an example, a PMOS tube is used to implement power conversion, such as Figure 3As shown, the gate of the PMOS tube is connected to the control signal CNT_PW_P, the source is connected to the external power supply Vp_P, and the drain outputs the internal power supply Vpw_P. As another example, an NMOS tube is used to implement power conversion, such as Figure 4 As shown, the gate of the NMOS tube is connected to the control signal CNT_PW_N, the source is connected to the external power supply Vp_N, and the drain outputs the internal power supply Vpw_N.

[0065] As another implementation of the present invention, the load unit uses N (N is a natural number greater than or equal to 2) power supplies, and the internal power conversion unit converts the N external power supplies into one-to-one corresponding N internal power supplies based on a single control signal. As an example, a PMOS tube is used to implement power conversion, such as Figure 5 As shown, N PMOS tubes are needed at this time, one PMOS tube corresponds to the conversion of one power supply, the gate of each PMOS tube is connected to the same control signal CNT_PW_P, the source is respectively connected to the corresponding external power supply Vp_P[N-1:0], and the drain outputs the corresponding internal power supply Vpw_P[N-1:0] obtained by conversion. As another example, NMOS tubes are used to realize power conversion, such as Figure 6 As shown, N NMOS tubes are needed at this time, one NMOS tube corresponds to the conversion of one power supply, the gate of each NMOS tube is connected to the same control signal CNT_PW_N, the source is connected to the corresponding external power supply Vp_N[N-1:0], and the drain outputs the corresponding internal power supply Vpw_N[N-1:0] obtained by conversion.

[0066] As another implementation of the present invention, the load unit uses N (N is a natural number greater than or equal to 2) power supplies, and the internal power conversion unit converts the N external power supplies into one-to-one corresponding N internal power supplies based on N control signals. As an example, a PMOS tube is used to implement power conversion, such as Figure 7 As shown, N PMOS tubes are needed at this time, one PMOS tube corresponds to the conversion of one power supply, the gate of each PMOS tube is connected to the corresponding control signal CNT_PW_P[N-1:0], the source is connected to the corresponding external power supply Vp_P[N-1:0], and the drain outputs the converted corresponding internal power supply Vpw_P[N-1:0]. As another example, NMOS tubes are used to realize power conversion, such as Figure 8 As shown, N NMOS tubes are needed at this time, one NMOS tube corresponds to the conversion of one power supply, the gate of each NMOS tube is connected to the corresponding control signal CNT_PW_N[N-1:0], the source is connected to the corresponding external power supply Vp_N[N-1:0], and the drain outputs the converted corresponding internal power supply Vpw_N[N-1:0].

[0067] It should be noted that in actual use, the circuit structure of the power conversion can be set as needed. When multiple power conversion units are set, each power conversion unit can be set to a different circuit structure, and the conversion of multiple power supplies in the same power conversion unit can also be set to a different circuit structure; in addition, the number and corresponding relationship of the control signal, external power supply, and internal power supply can be set based on actual needs, and are not limited to this embodiment. For example, the number of control signals is less than the number of internal power supplies (that is, some internal power conversion units share one control signal), and the number of internal power supplies is less than the number of external power supplies (that is, some internal power conversion units convert the same external power supply into different internal power supplies based on different control signals), which will not be repeated here.

[0068] In another example, the power conversion circuit 3 further includes a control unit 33 disposed outside the load region 1, and the control unit 33 provides a control signal CNT_PW (corresponding to CNT_PW_P, CNT_PW_N, CNT_PW_P[N-1:0], CNT_PW_N[N-1:0] in each example) to each power conversion unit based on the clock signal CLK and the external control instruction CNT. In this example, the control unit 33 includes but is not limited to a digital logic circuit composed of devices such as an inverter, a NAND gate, a NOR gate, and a transmission gate; any circuit structure that can implement the logic of the present invention is applicable, and will not be described one by one here.

[0069] The internal power conversion unit (31, 32) of this embodiment utilizes part of the layout of the redundant unit to realize the power conversion function, thereby maintaining the area of ​​the original integrated circuit IP and saving the area of ​​the additional power conversion unit; at the same time, the transistors in the redundant unit are directly used to form the power conversion circuit to minimize the design difficulty.

[0070] Embodiment 2

[0071] like Fig. 9 As shown, this embodiment provides a power conversion circuit 3 , which is different from the first embodiment in that it further includes an external power conversion unit 34 .

[0072] like Fig. 9 As shown, the external power conversion unit 34 is arranged outside the load area 1, and the external power conversion unit 34 receives the control signal CNT_PW and the external power Vp, converts the external power Vp into the internal power Vpw under the control of the control signal CNT_PW, and supplies power to each load unit in the load area 1; when each load unit is in the sleep mode, the external power conversion unit 24 cuts off the power of each load unit based on the control signal CNT_PW.

[0073] Specifically, the structure of the external power conversion unit 34 may be the same as or different from the implementation method of the internal power conversion unit described in the first embodiment; any circuit structure that can realize power conversion is applicable to the present invention and will not be described in detail here.

[0074] In this embodiment, the external power conversion unit 34 is connected to the output end of the internal power conversion unit to provide an internal power supply of the same voltage. When the area of ​​the load region 1 is relatively large and the area of ​​the redundant unit is relatively small, the internal power Vpw provided by the internal power conversion unit is insufficient to drive all the load units in the load region 1; at this time, the external power conversion unit 34 and the internal power conversion unit receive the same signal and provide the internal power Vpw together, and the internal power conversion unit is used to enhance the signal strength of the internal power Vpw, thereby reducing the IR voltage drop and ensuring the normal operation of each load unit. For power conversion units with the same driving capability requirements, compared with the solution of only setting an external power conversion unit, due to the existence of the internal power conversion unit of this embodiment, the area of ​​the external power conversion unit 34 of this embodiment can be made smaller, thereby achieving the purpose of saving chip area.

[0075] As an example, the driving current of the external power conversion unit 34 is greater than the driving current of the internal power conversion unit; in actual use, the driving current of the external power conversion unit 34 may also be less than or equal to the driving current of the internal power conversion unit, according to actual needs.

[0076] The power conversion circuit 3 of this embodiment is provided with an additional external power conversion unit and utilizes a part of the redundant unit area to act as an internal power conversion unit to increase the strength of the internal power supply, thereby reducing the IR voltage drop.

[0077] Embodiment 3

[0078] This embodiment provides a memory 4, which includes:

[0079] A memory cell array 41, redundant cells located around the memory cell array 41, a control module 44 and a decoding module 45 located outside the redundant cells, and the power conversion circuit 3 of the first or second embodiment; as an example, the memory is a static random access memory (SRAM).

[0080] Specifically, taking into account the need to protect the memory cell array 41 in the process, in the present embodiment, word line edge units 42, bit line edge units 43 and corner units 46 are arranged around the memory cell array 41, the word line edge units 42 are arranged on the upper and lower sides of the memory cell array 41, and the bit line edge units 43 are arranged on the left and right sides of the memory cell array 41; wherein the word line edge units 42 and the bit line edge units 43 are redundant units, which are designed to be similar to the memory cell structure in the layout, but do not have any substantial function in the circuit.

[0081] Specifically, the memory cell array 41 and the redundant cells (word line edge cells 42, bit line edge cells 43) constitute the load area. Assuming that the power conversion unit is placed in a module outside the load area, such as the control module 44 and the decoding module 45, this low-power design method not only increases the design difficulty, but also increases the layout area; in addition, assuming that the power conversion unit is placed in the control module 44 below the memory cell array 41, the internal power supply Vpw needs to pass through the entire array area to reach the topmost memory cell. As the memory capacity increases, the path passed by the internal power supply Vpw becomes longer, the parasitic resistance of the metal wire increases, and the signal becomes weaker when reaching the farthest end, which may cause the IP function to be lost. The present invention is provided with an internal power conversion unit in the redundant cell located at least on one side of the memory cell array 41. In this embodiment, the internal power conversion unit is provided in each of the four redundant cells to obtain a sufficiently large driving capability. Since the redundant cell design on the layout is similar to the memory cell (BITCELL) structure, the redundant cell can be directly converted into a transistor device with a power conversion function, which reduces the design difficulty of the layout and does not require additional layout area. In addition, when the memory capacity is too large and the internal power conversion unit set in the redundant unit is insufficient to assume the power conversion function, an external power conversion unit 34 can be added outside the redundant unit (the external power conversion unit 34 can also be set in the control module 44 or the decoding module 45, configured according to actual needs, and will not be described in detail here), and the internal power conversion unit in the redundant unit can play a role in enhancing the signal in the power conversion signal with a longer path, thereby preventing the loss of the memory IP function.

[0082] Specifically, in the case of configuring the control unit 33, the control unit 33 can be set in the control module 44 or the decoding module 45; it is configured according to actual needs, and is not described in detail here. In this embodiment, the control unit 33 is set in the decoding module 45, and the control unit 33 generates a power conversion control signal CNT_PW under the action of the clock signal CLK and the external control instruction CNT. The control signal CNT_PW is directly connected to the transistor control terminal for power conversion in the word line edge unit 42 and the bit line edge unit 43, and the external power supply Vp is converted into the internal power supply Vpw through control to power each storage unit.

[0083] When the memory 4 is in a non-working state, each internal power conversion unit (and external power conversion unit) turns off the transistor that performs power conversion internally based on the control signal CNT_PW, thereby stopping the power supply to each load unit, achieving the purpose of reducing leakage and achieving low power consumption. When the memory 4 is in a normal working state, each internal power conversion unit (and external power conversion unit) converts the external power Vp into the internal power Vpw based on the control signal CNT_PW, and supplies power to each load unit through the internal power Vpw; simplifying the design difficulty on the basis of making full use of the redundant unit layout.

[0084] It should be noted that the redundant unit of the memory cell array 41 can be set not only at the periphery of the memory cell array 41, but also inside the memory cell array 41, that is, the internal power conversion unit can also be set inside the memory cell array 41, which is not limited to this embodiment. The control signal, external power supply, and internal power supply can be set to multiple channels respectively to realize the conversion of multiple power supplies, which will not be described one by one here.

[0085] This embodiment also provides a chip, which includes: a load area and the above-mentioned power conversion circuit 3, and a redundant unit is set in the load area (edge ​​or between load units). The chip includes but is not limited to static random access memory, and any IP with power conversion requirements can use the redundant unit as a power conversion module to reduce design difficulty and save layout area.

[0086] In summary, the present invention provides a power conversion circuit, memory and chip, including: an internal power conversion unit arranged in a redundant unit, the redundant unit is located in the load area; wherein the internal power conversion unit receives a control signal and an external power supply, converts the external power supply into an internal power supply under the control of the control signal, and supplies power to each load unit in the load area; when each load unit is in a sleep mode, the internal power conversion unit cuts off the power supply of each load unit based on the control signal. The power conversion circuit, memory and chip of the present invention add a power conversion function without adding additional modules and area, thereby converting the external power supply signal into an internal signal, reducing leakage, and realizing a low-power design; or after adding an additional power conversion function module, the internal signal is enhanced and the voltage drop is optimized. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0087] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power conversion circuit, characterized in that: The power conversion circuit comprises: An internal power conversion unit disposed in a redundant unit, wherein the redundant unit is located in the load region; Among them, the internal power conversion unit receives a control signal and an external power supply, converts the external power supply into an internal power supply under the control of the control signal, and supplies power to each load unit in the load area; when each load unit is in a sleep mode, the internal power conversion unit cuts off the power supply of each load unit based on the control signal.

2. The power conversion circuit according to claim 1, characterized in that: The redundant unit is located at at least one end of the load region.

3. The power conversion circuit according to claim 1, characterized in that: The redundant unit is provided with a redundant transistor, and the internal power conversion unit is formed based on the redundant transistor.

4. The power conversion circuit according to claim 1, characterized in that: The power conversion circuit also includes an external power conversion unit arranged outside the load area, the external power conversion unit receives the control signal and the external power supply, converts the external power supply into an internal power supply under the control of the control signal, and supplies power to each load unit in the load area; when each load unit is in a sleep mode, the external power conversion unit cuts off the power supply of each load unit based on the control signal.

5. The power conversion circuit according to claim 4, characterized in that: The driving current of the external power conversion unit is greater than the driving current of the internal power conversion unit.

6. The power conversion circuit according to any one of claims 1 to 5, characterized in that: Each power conversion unit converts a single external power source into a corresponding single internal power source based on a single control signal; or each power conversion unit converts N external power sources into one-to-one corresponding N internal power sources based on a single control signal; or each power conversion unit converts N external power sources into one-to-one corresponding N internal power sources based on N control signals; N is a natural number greater than or equal to 2.

7. The power conversion circuit according to claim 6, characterized in that: A PMOS tube is used to realize power conversion; the gate of the PMOS tube is connected to the corresponding control signal, the source is connected to the corresponding external power supply, and the drain outputs the converted internal power supply; Alternatively, an NMOS tube is used to realize power conversion; the gate of the NMOS tube is connected to a corresponding control signal, the source is connected to a corresponding external power supply, and the drain outputs the converted internal power supply.

8. The power conversion circuit according to any one of claims 1 to 5, characterized in that: The power conversion circuit further includes a control unit disposed outside the load region, and the control unit provides the control signal to each power conversion unit based on a clock signal and an external control instruction.

9. A memory, characterized in that: The memory includes at least: A memory cell array, redundant cells located around the memory cell array, a control module and a decoding module located outside the redundant cells, and a power conversion circuit according to any one of claims 1 to 8; The storage cell array and the redundant unit constitute the load area, and the internal power conversion unit is disposed in at least one redundant unit located at one side of the storage cell array.

10. A chip, characterized in that: The chip at least comprises: a load area and a power conversion circuit as claimed in any one of claims 1 to 8, wherein a redundant unit is arranged in the load area.

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