A radiation-resistant level conversion circuit

Abstract

The present application relates to a radiation-resistant level conversion circuit. The circuit includes a level conversion circuit based on a DICE structure and an anti-radiation reinforcement circuit; the level conversion circuit based on the DICE structure is used to realize level conversion using redundant control nodes; it includes: an input module and a DICE module, the DICE module includes four branches consisting of 1 PMOS transistor and 1 NMOS tube connected in series; the drain connection of the PMOS transistor and the NMOS transistor in each branch is used as a control node; the input module is used to control the MOS switch to transmit the differential input signal to the DICE module through a transmission tube; the anti-radiation reinforcement circuit is used to feedback and adjust the control nodes of the second and third branches through a cross-coupling structure. The circuit can complete the level switching from ultra-low voltage to high voltage, improve the radiation resistance of the level converter, can resist harsh environments, and reduce power consumption and delay.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a radiation-resistant level conversion circuit. Background Art

[0002] With the popularity of integrated circuits for aerospace, the requirements for integrated circuits are not limited to area, power consumption, and delay. More attention will be paid to its radiation resistance, tolerance to harsh environments, and ability to work in harsh space. In order to connect subthreshold voltages to high-voltage circuits, unique level shifters are required. Subthreshold to superthreshold level shifters are required to connect circuits operating at subthreshold voltages to circuits communicating with the outside world. Circuits operating at these low voltages are less robust to noise and radiation, which may inadvertently change circuit operation. This effect is more serious in timing circuits such as flip-flops, latches, and memories, because radiation can remove or introduce additional charge held at the node, resulting in transient voltage pulses. If the charge exceeds the critical charge of the node ( ), the stored data is destroyed. The value is a measure of robustness, with higher The maximum amount of charge stored on a node depends on the node capacitance and the supply voltage, and is given by Thus, for each new technology, the critical charge decreases as both the supply voltage and the node capacitance decrease, the sensitivity to radiation in the subthreshold region becomes more pronounced, and the circuit becomes increasingly susceptible to soft errors. If the amount of charge stored at a node exceeds the critical charge ( ), a soft error occurs. To measure the circuit , a double exponential current source is inserted between each sensitive node and ground, and particle impact produces current spikes to simulate radiation conditions. Summary of the invention

[0003] Based on this, it is necessary to provide a radiation-resistant level conversion circuit to address the above technical problems.

[0004] A radiation-resistant level conversion circuit comprises: a level conversion circuit based on a DICE structure and an radiation-resistant reinforcement circuit.

[0005] The level conversion circuit based on the DICE structure is used to realize level conversion by using redundant control nodes; it includes: two input modules and one DICE module, the DICE module includes four branches consisting of one PMOS transistor and one NMOS tube connected in series; the drain of the PMOS transistor and the drain of the NMOS transistor in each branch are connected as a control node.

[0006] The input module is used to control the MOS switch to transmit the differential input signal to the DICE module through the transmission tube; the two output ends of the first input module are respectively connected to the control nodes of the first branch and the second branch of the DICE module; the two output ends of the second input module are respectively connected to the control nodes of the third branch and the fourth branch of the DICE module.

[0007] The anti-radiation reinforcement circuit is used to perform feedback adjustment on the control nodes of the second branch and the third branch of the DICE module through a cross-coupling structure to improve the radiation resistance; the anti-radiation reinforcement circuit is connected to the control nodes of the second branch and the third branch of the DICE module.

[0008] In one embodiment, the first input module includes a fifth NMOS transistor and a sixth NMOS transistor; the second input module includes a seventh NMOS transistor and an eighth NMOS transistor.

[0009] The source of the fifth NMOS transistor and the gate of the sixth NMOS transistor are connected to the input node IN, the gate of the fifth PMOS transistor is connected to the power supply VDDL terminal, and the drain of the fifth NMOS transistor is connected to the control node of the first branch of the DICE module; the source of the sixth PMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected to the control node of the second branch of the DICE module.

[0010] The source of the seventh NMOS transistor and the gate of the eighth NMOS transistor are connected to the input node IN, the gate of the seventh NMOS transistor is connected to the power supply VDDL terminal, and the drain of the seventh NMOS transistor is connected to the control node of the third branch of the DICE module; the source of the eighth NMOS transistor is grounded, and the drain of the eighth NMOS transistor is connected to the control node of the fourth branch of the DICE module; wherein the input node IN is used to receive an input signal.

[0011] In one embodiment, the radiation hardening circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor.

[0012] The power source VDDH is connected to sources of the fifth PMOS transistor and the sixth PMOS transistor.

[0013] The drains of the ninth NMOS transistor and the seventh PMOS transistor and the gates of the fifth PMOS transistor and the eighth PMOS transistor are all connected to the control node of the second branch of the DICE module; the drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor.

[0014] The drains of the eighth PMOS transistor and the tenth NMOS transistor and the gates of the sixth PMOS transistor and the seventh PMOS transistor are all connected to the control node of the third branch of the DICE module.

[0015] The source of the ninth NMOS transistor is connected to the ground GD, the gate of the tenth NMOS transistor is connected to the power supply VDDL, and the gate of the ninth NMOS transistor and the source of the tenth NMOS transistor are both connected to the input node IN; wherein the input node IN is used to receive an input signal.

[0016] In one embodiment, both the PMOS transistor and the NMOS transistor are metal oxide semiconductor field effect transistors.

[0017] The above-mentioned radiation-resistant level conversion circuit includes a level conversion circuit based on a DICE structure and an anti-radiation reinforcement circuit; the level conversion circuit based on the DICE structure is used to realize level conversion by using redundant control nodes; it includes: an input module and a DICE module, the DICE module includes four branches composed of 1 PMOS transistor and 1 NMOS tube connected in series; the drain connection of the PMOS transistor and the NMOS transistor in each branch is used as a control node; the input module is used to control the MOS switch to transmit the differential input signal to the DICE module through the transmission tube; the anti-radiation reinforcement circuit is used to feedback and adjust the control nodes of the second and third branches through a cross-coupling structure. The circuit can complete the level switching from ultra-low voltage to high voltage, improve the radiation resistance of the level converter, can withstand harsh environments, and reduce power consumption and delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a radiation-resistant level conversion circuit in one embodiment;

[0019] Figure 2 This is the schematic diagram of the traditional level conversion circuit based on DICE structure;

[0020] Figure 3 A sensitive node in a radiation-resistant level conversion circuit design in another embodiment;

[0021] Figure 4 is an input-output curve diagram when the input signal frequency is 1G in another embodiment;

[0022] Figure 5 is an input-output curve diagram when the input signal frequency is 2G in another embodiment;

[0023] Figure 6 is an input-output curve diagram when the input signal frequency is 3G in another embodiment;

[0024] Figure 7 is a curve diagram of an input of 0.9V and an output of 2.5V when the input signal frequency is 500M in another embodiment;

[0025] Figure 8 is a curve diagram of an input of 0.6V and an output of 1.8V when the input signal frequency is 500M in another embodiment;

[0026] Fig. 9 is a simulation result diagram when the first control node A flips from 0 to 1 in another embodiment;

[0027] Fig.10 This is a simulation result diagram when the first control node A flips from 1 to 0 in another embodiment;

[0028] Fig.11 is a diagram of simulation results when the second control node B flips from 0 to 1 in another embodiment;

[0029] Fig.12 is a diagram of simulation results when a 1-to-0 flip occurs in the second control node B in another embodiment;

[0030] Fig.13 is a simulation result diagram when the third control node C flips from 0 to 1 in another embodiment;

[0031] Fig.14 is a simulation result diagram when the third control node C flips from 1 to 0 in another embodiment;

[0032] Fig.15 is a simulation result diagram of another embodiment when the output node OUT flips from 0 to 1;

[0033] Fig.16 is a simulation result diagram of another embodiment when the output node OUT flips from 1 to 0;

[0034] Fig.17 This is a simulation result diagram of another embodiment in which the first control node A undergoes a 0-1 flip and the second control node B undergoes a 1-0 flip;

[0035] Fig.18 This is a simulation result diagram of another embodiment in which the first control node A undergoes a 0-1 flip, and the second control node B and the third control node C undergo a 1-0 flip;

[0036] Fig.19 A simulation result diagram of another embodiment in which the first control node A and the output node OUT undergo a 0-1 flip, and the second control node B and the third control node C undergo a 1-0 flip;

[0037] Fig. 20 A simulation result diagram of another embodiment in which a 1-0 flip occurs at the first control node A and the output node OUT, and a 0-1 flip occurs at the second control node B and the third control node C;

[0038] Fig.21 is a diagram of simulation results when a 1-to-0 flip occurs in the second control node B in another embodiment;

[0039] Fig. 22 is a simulation result diagram of another embodiment when the output node OUT flips from 0 to 1;

[0040] Fig.23 is a simulation result diagram of another embodiment when the output node OUT flips from 1 to 0;

[0041] Fig.24 A diagram showing simulation results of another embodiment in which a 0-1 flip occurs at the first control node A and a 1-0 flip occurs at the second control node B;

[0042] Fig.25 FIG. 1 is a simulation result diagram of another embodiment in which a 0-1 flip occurs in the first control node A and a 1-0 flip occurs in the second control node B and the third control node C;

[0043] Fig.26 A diagram showing simulation results of another embodiment in which a 0-1 flip occurs on the first control node A and the output node OUT, and a 1-0 flip occurs on the second control node B and the third control node C;

[0044] Fig. 27 This is a simulation result diagram of another embodiment in which a 1-0 flip occurs on the first control node A and the output node OUT, and a 0-1 flip occurs on the second control node B and the third control node C. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0046] In one embodiment, Figure 1 As shown, a radiation-resistant level conversion circuit is provided. The circuit includes a level conversion circuit 10 based on a DICE structure and an anti-radiation reinforcement circuit 20.

[0047] The level conversion circuit 10 based on the DICE structure is used to realize level conversion by using redundant control nodes; it includes: two input modules and four branches composed of a PMOS transistor and an NMOS tube connected in series; the first PMOS transistor M in the first branch P1 The drain of the first NMOS transistor M N1 The drain of the second branch is connected as the first control node A; the second PMOS transistor M P2 The drain of the second NMOS transistor M N2 The drain of the third branch is connected as the second control node B; the third PMOS transistor M P3 The drain of the third NMOS transistor M N3 The drain of the fourth branch is connected as the output node OUT, and the fourth PMOS transistor M P4 The drain of the fourth NMOS transistor M N4 The drain of the first PMOS transistor M is connected as the third control node C. P1 , the second PMOS transistor M P2 , the third PMOS transistor M P3 And the fourth PMOS transistor M P4 The source of the first NMOS transistor M is connected to the power supply VDDH. N1 , the second NMOS transistor M N2 , the third NMOS transistor M N3 And the fourth NMOS transistor M N4 The sources are connected to the ground GD.

[0048] The first control node A is connected to the second PMOS transistor M in the second branch. P2 The gate of the fourth NMOS transistor M in the fourth branch N4 of the gate.

[0049] The second control node B is connected to the first NMOS transistor M in the first branch. N1 and the third PMOS transistor M in the third branch P3 of the gate.

[0050] The output node OUT is connected to the second NMOS transistor M in the second branch. N2 and the fourth PMOS transistor M in the fourth branch P4 of the gate.

[0051] The third control node C is connected to the third NMOS transistor M in the third branch. N3 and the first PMOS transistor M in the first branch P1of the gate.

[0052] The input module is used to convert the input signal into a set of inverted signals using a transmission tube; the first output end and the second output end of the first input module are respectively connected to the first control node A and the second control node B, and the first output end and the second output end of the second input module are respectively connected to the output node OUT and the third control node C.

[0053] The anti-radiation reinforcement circuit 20 is used for improving the radiation resistance by feedback adjustment of the second control node B and the output node OUT through a cross-coupling structure; the anti-radiation reinforcement circuit is connected to the second control node B and the output node OUT.

[0054] In one embodiment, the first input module includes a fifth NMOS transistor M N5 and the sixth NMOS transistor M N6 ; The second input module includes a seventh NMOS transistor M N7 and the eighth NMOS transistor M N8 .

[0055] The fifth NMOS transistor M N5 The source of the sixth NMOS transistor M N6 The gate of the fifth NMOS transistor M is connected to the input node IN. N5 The gate of the fifth PMOS transistor M is connected to the power supply VDDL. N5 The drain of the sixth NMOS transistor M is connected to the first control node A; N6 The source of the sixth NMOS transistor M is grounded. N6 The drain of is connected to the second control node B.

[0056] The seventh NMOS transistor M N7 The source of the eighth NMOS transistor M N8 The gate of the seventh NMOS transistor M is connected to the input node IN. N7 The gate of the seventh NMOS transistor M is connected to the power supply VDDL. N7 The drain of the eighth NMOS transistor M is connected to the output node OUT; N8 The source of the eighth NMOS transistor M is grounded. N8 The drain of is connected to the third control node C; wherein the input node IN is used to receive an input signal.

[0057] Specifically, the radiation-resistant level conversion circuit proposed in the present application is mainly composed of two parts: a level conversion circuit based on the DICE structure and an anti-radiation reinforcement circuit. The inverter used for the differential signal input in the traditional circuit is removed, and a transmission tube is directly used to control the MOS switch to transmit the differential signal, thereby further reducing power consumption and delay.

[0058] The principle of the level conversion circuit based on the DICE structure of the inverter used for the input differential signal is as follows Figure 2 As shown, the inverter will increase delay and power consumption.

[0059] The radiation-resistant level conversion circuit mainly relies on the circuit combined with the traditional level converter with RCC pull-up network and the traditional DICE design, based on the principle of dual-node feedback control to achieve anti-interference. The design contains four nodes, whose logic state is controlled by two feedback nodes located in the previous stage, thereby improving the radiation resistance. At the same time, the input uses a transmission tube instead of the inverter input in the traditional level converter, which can further reduce power consumption and delay.

[0060] The basic device used in the traditional level converter circuit is the metal oxide semiconductor field effect transistor (MOSFET). The high reliability level conversion circuit proposed in this example is also based on the MOSFET device in the traditional level conversion circuit, but it changes the cross-coupled LS (CMPLS) and current mirror-based LS (CMLS) circuits in the traditional circuits, and adopts a circuit that combines the traditional level converter with adjustable cross-coupling function and the traditional DICE storage unit design, based on the dual-node feedback control principle, to achieve anti-interference. Figure 3 As shown, in the DICE structure, the second control node B is a sensitive node. By adding an RCC circuit with cross-coupling, the second control node B can be adjusted when an error occurs. When an error occurs in the A, B, and C control nodes, the other two nodes store the correct nodes. Based on feedback regulation, the control nodes are recharged and discharged, so that the control nodes return to normal. The design includes four nodes, whose logic states are controlled by two feedback nodes located in the previous level, that is, the second control node B is controlled by the first control node A and the output node OUT at the same time. When an error occurs in the second control node B, the value of the second control node B can be quickly restored. The other nodes are similarly controlled by adjacent nodes, thereby improving the radiation resistance. At the same time, the input uses a transmission tube instead of the inverter input in the traditional level converter, which can further reduce power consumption and delay.

[0061] The above-mentioned radiation-resistant level conversion circuit includes a level conversion circuit based on a DICE structure and an anti-radiation reinforcement circuit; the level conversion circuit based on the DICE structure is used to realize level conversion by using redundant control nodes; it includes: an input module and a DICE module, the DICE module includes four branches composed of 1 PMOS transistor and 1 NMOS tube connected in series; the drain connection of the PMOS transistor and the NMOS transistor in each branch is used as a control node; the input module is used to control the MOS switch to transmit the differential input signal to the DICE module through the transmission tube; the anti-radiation reinforcement circuit is used to feedback and adjust the control nodes of the second and third branches through a cross-coupling structure. The circuit can complete the level switching from ultra-low voltage to high voltage, improve the radiation resistance of the level converter, can withstand harsh environments, and reduce power consumption and delay.

[0062] In one embodiment, the radiation hardening circuit 20 includes a fifth PMOS transistor M P5 The sixth PMOS transistor M P6 , the seventh PMOS transistor M P7 , the eighth PMOS transistor M P8 , the ninth NMOS transistor M N9 and the tenth NMOS transistor M N10 .

[0063] The power supply VDDH and the fifth PMOS transistor M P5 and the sixth PMOS transistor M P6 Source connection.

[0064] The ninth NMOS transistor M N9 and the seventh PMOS transistor M P7 The drain of the fifth PMOS transistor M P5 and the eighth PMOS transistor M P8 The gates of the fifth PMOS transistor M are connected to the second control node B; P5 The drain of the seventh PMOS transistor M P7 Source connection.

[0065] The eighth PMOS transistor M P8 and the tenth NMOS transistor M N10 The drain of the sixth PMOS transistor M P6 and the seventh PMOS transistor M P7 The gates of the transistors are connected to the output node OUT.

[0066] The ninth NMOS transistor M N9 The source of the tenth NMOS transistor M is connected to the ground GD. N10The gate of the ninth NMOS transistor M is connected to the power supply VDDL. N9 The gate and the tenth NMOS transistor M N10 The sources of the transistors are connected to an input node IN, wherein the input node IN is used to receive an input signal.

[0067] In one embodiment, both the PMOS transistor and the NMOS transistor are metal oxide semiconductor field effect transistors.

[0068] In a specific embodiment, the structural diagram of a high-reliability radiation-resistant level conversion circuit is as follows: Figure 1 As shown, the circuit includes ten NMOS transistors, namely: the first NMOS transistor M N1 , the second NMOS transistor M N2 , the third NMOS transistor M N3 , the fourth NMOS transistor M N4 , the fifth NMOS transistor M N5 , the sixth NMOS transistor M N6 , the seventh NMOS transistor M N7 , the eighth NMOS transistor M N8 , the ninth NMOS transistor M N9 , the tenth NMOS transistor M N10 ; Eight PMOS transistors, respectively: the first PMOS transistor M P1 , the second PMOS transistor M P2 , the third PMOS transistor M P3 , the fourth PMOS transistor M P4 , the fifth PMOS transistor M P5 , the sixth PMOS transistor M P6 , the seventh PMOS transistor M P7 , the eighth PMOS transistor M P8 .

[0069] The power supply VDDH and the first PMOS transistor M P1 , the second PMOS transistor M P2 , the third PMOS transistor M P3 , the fourth PMOS transistor M P4 , the fifth PMOS transistor M P5 and the sixth PMOS transistor M P6 The source (denoted as S) is connected to the first NMOS transistor M in the middle N1 , the second NMOS transistor M N2 , the third NMOS transistor M N3 , the fourth NMOS transistor MN4 , the seventh PMOS transistor M P7 and the eighth PMOS transistor M P8 As the core of radiation-resistant design, they and the first PMOS transistor M P1 , the second PMOS transistor M P2 , the third PMOS transistor M P3 , the fourth PMOS transistor M P4 , the fifth PMOS transistor M P5 and the sixth PMOS transistor M P6 The cross-coupling circuit is formed, which affects each other so that the control node can be quickly restored. The fifth NMOS transistor M N5 , the sixth NMOS transistor M N6 , the seventh NMOS transistor M N7 , the eighth NMOS transistor M N8 , the ninth NMOS transistor M N9 and the tenth NMOS transistor M N10 The six NMOS transistors act as input circuits and reverse input circuits respectively. In this design, the reverse input circuit adopts a transmission tube structure to replace the inverter function in the traditional circuit, thereby reducing the use of inverters and reducing their power consumption and delay.

[0070] The input and output functions of the high-reliability radiation-resistant level conversion circuit under normal conditions are simulated and the following results are obtained: Figures 4 to 8 The simulation results are shown. Figure 4 is the input-output curve when the input signal frequency is 1G, Figure 5 This is the input-output curve when the input signal frequency is 2G. Figure 6 is the input-output curve when the input signal frequency is 3G, Figure 7 This is the curve of input 0.9V and output 2.5V when the input signal frequency is 500M. Figure 8 The curve is 0.6V input and 1.8V output when the input signal frequency is 500M. The simulation results show that the radiation-resistant level converter can work at a maximum frequency of 2G and can output waveforms normally. And at an input of 500M, it can achieve a low-level conversion of 0.6V-1.8V at a maximum, and a conversion of 0.9V-2.5V at a maximum.

[0071] right Figure 1 The level conversion circuit shown in the figure is functionally analyzed. When the input voltage is 0V, the second PMOS transistor M P2 , the fourth PMOS transistor M P4 , the sixth PMOS transistor M P6 , the seventh PMOS transistor MP7 、The first NMOS transistor M N1 , the third NMOS transistor M N3 , the fifth NMOS transistor M N5 , the seventh NMOS transistor M N7 , a tenth NMOS transistor and a tenth NMOS transistor M N10 All turned on, the first PMOS transistor M P1 , the third PMOS transistor M P3 , the fifth PMOS transistor M P5 , the eighth PMOS transistor M P8 , the second NMOS transistor M N2 , the fourth NMOS transistor M N4 , the sixth NMOS transistor M N6 , the eighth NMOS transistor M N8 and the ninth NMOS transistor M N9 All are turned off, so that the output node OUT is 0; when the input voltage is 0.9V, the second PMOS transistor M P2 , the fourth PMOS transistor M P4 , the sixth PMOS transistor M P6 , the seventh PMOS transistor M P7 、The first NMOS transistor M N1 , the third NMOS transistor M N3 , the fifth NMOS transistor M N5 , the seventh NMOS transistor M N7 The tenth NMOS transistor is all turned off, and the first PMOS transistor M P1 , the third PMOS transistor M P3 , the fifth PMOS transistor M P5 , the eighth PMOS transistor M P8 , the second NMOS transistor M N2 , the fourth NMOS transistor M N4 , the sixth NMOS transistor M N6 , the eighth NMOS transistor M N8 and the ninth NMOS transistor M N9All are turned on so that the output node OUT is 1.8V, thereby realizing the function of level conversion. When affected by the radiation effect, the circuit structure can still work. In this embodiment, a double exponential current source is used to bombard each control node to simulate the harsh environment in space. The current size of the double exponential current source used is 600uA, and the duration is 150ps, that is, the maximum charge is 90fC, which can meet the requirements of radiation resistance. When the first control node A is bombarded, if the first control node A is at level 0 at this time, then after the bombardment, the first control node A will flip from 0 to 1. At this time, the second control node B and the third control node C are both at level 1, and the second control node B controls the first NMOS transistor M N1 The first control node A is turned on, so that the first control node A can be quickly discharged, so that the first control node A is pulled to a low voltage. Similarly, when flipping from 1 to 0, if the first control node A is at 0 level at this time, then after the bombardment, the first control node A will flip from 1 to 0. At this time, the second control node B and the third control node C are both at 0 level. The third control node C controls the first PMOS transistor M P1 The first control node A is turned on, so that the first control node A can be quickly charged, so that the first control node A is pulled to a high voltage. When the second control node B is bombarded, if the second control node B is at a 0 level at this time, then after the bombardment, the second control node B will flip from 0 to 1. At this time, the first control node A is at a 1 level, the third control node C is at a 0 level, and the output node OUT is at a 1 level. The output node OUT controls the second NMOS transistor M N2 The tube is turned on, causing the second control node B to drop to 0 quickly, and the input signal is also 1 at this time, which can also be achieved through the sixth NMOS transistor M N6 and the ninth NMOS transistor M N9 The transistor causes the second control node B to be quickly pulled down to 0, thereby quickly discharging the second control node B and pulling the second control node B to a low voltage. Similarly, when flipping from 1 to 0, the output node OUT is at 0, the first control node A is also at 0, and the first control node A controls the second PMOS transistor M P2 The output node OUT controls the seventh PMOS transistor M P7The third control node C is turned on, so that the second control node B is quickly charged to 1. When the third control node C is bombarded, if the third control node C is at 0 level at this time, then after the bombardment, the third control node C will flip from 0 to 1. At this time, the first control node A is at 1 level, the second control node B is at 0 level, and the output node OUT is at 1 level. The first control node A controls the fourth NMOS transistor M N4 The third control node C is turned on, causing it to drop to 0 quickly. Similarly, when it flips from 1 to 0, the output node OUT is at 0 level, and the output node OUT controls the fourth PMOS transistor M P4 The third control node C is turned on to quickly charge the third control node C, so that the third control node C is quickly pulled up to 1, thereby achieving radiation resistance performance.

[0072] In order to more clearly demonstrate the effect of the high-reliability radiation-resistant level conversion circuit provided by the present application, simulation experiments are performed on each control node and output node to obtain Fig. 9 The simulation results shown in the figure are as follows: Fig.10 The simulation results shown in the figure are as follows: Fig.11 The simulation results shown in the second control node B are when a 0 to 1 flip occurs. Fig.12 The simulation results shown in the second control node B are as follows: Fig.13 The simulation result diagram shown in the figure is when the third control node C flips from 0 to 1. Fig.14 The simulation result diagram when the third control node C flips from 1 to 0 is shown. Fig.15 The simulation result diagram shown in the figure shows that the output node OUT flips from 0 to 1. Fig.16 The simulation result diagram shown in the figure shows the output node OUT flipping from 1 to 0. Figures 9 to 16 The simulation waveform diagram and Table 1 of the input and output function example under the simulated radiation environment are analyzed, and the performance of the radiation-resistant level conversion circuit is compared with other level conversion circuits. The simulation diagram and table data are compared under the condition of input 100M. The specific contents are as follows: a double exponential current source is added at 12ns and 17ns respectively to simulate the radiation environment.

[0073] The simulation results show that when a single node flip occurs, the invention can maintain stable output, and only generates a pulse waveform when the output node OUT flips from 1 to 0. Overall, the radiation resistance requirements of a single node flip can be well met. In addition, the invention can also meet the radiation resistance requirements when resisting multiple node flips. Figures 17 to 20 This is the simulation result diagram of multi-node flipping, where: Fig.17 This is the simulation result of the first control node A flipping 0-1 and the second control node B flipping 1-0. Fig.18 The simulation results are as follows: the first control node A undergoes a 0-1 flip, and the second control node B and the third control node C undergo a 1-0 flip; Fig.19 The simulation results are as follows: the first control node A and the output node OUT undergo a 0-1 flip, and the second control node B and the third control node C undergo a 1-0 flip; Fig. 20 This is the simulation result that the first control node A and the output node OUT undergo a 1-0 flip, and the second control node B and the third control node C undergo a 0-1 flip.

[0074] The simulation results show that when multiple nodes flip, the invention can maintain stable output, and only generates pulse waveforms when the first control node A and the output node OUT flip 1-0 and the second control node B and the third control node C flip 0-1. It can well meet the requirements of radiation resistance. Figure 21 to Figure 27 This is a simulation diagram of the irradiation of some control nodes and multi-node flipping of the level converter of the traditional DICE structure. Fig.21 This is the simulation result when the second control node B flips from 1 to 0. Fig. 22 This is the simulation result when the output node OUT flips from 0 to 1. Fig.23 This is the simulation result when the output node OUT flips from 1 to 0. Fig.24 The simulation results are as follows: the first control node A undergoes a 0-1 flip and the second control node B undergoes a 1-0 flip. Fig.25 The simulation results are as follows: the first control node A undergoes a 0-1 flip, and the second control node B and the third control node C undergo a 1-0 flip. Fig.26 The simulation results are as follows: the first control node A and the output node OUT undergo a 0-1 flip, and the second control node B and the third control node C undergo a 1-0 flip. Fig. 27 These are simulation results of a 1-0 flip at the first control node A and the output node OUT, and a 0-1 flip at the second control node B and the third control node C.

[0075] In order to facilitate data comparison, the data of the two structures are now statistically summarized as Table 1. The following table is a comparison table of the static power consumption data, delay, and radiation resistance performance of the high-reliability radiation-resistant level conversion circuit provided by the present invention and the data of the traditional DICE structure. The table data are all simulation data with an input of 100M, a typical process angle, and room temperature. The radiation resistance is replaced by the level conversion value of the node when it is bombarded, that is, .

[0076] According to Table 1, it can be calculated that the delay of the inventive design is reduced by 24.79% compared with the traditional level conversion circuit based on the DICE structure, and the level change of the output node OUT from 1 to 0 is reduced by 48.37%; the level change of the first control node A from 0 to 1, the second control node B and the third control node C from 1 to 0 is reduced by 71.33%; the level change of the first control node A and the output node OUT from 0 to 1, the second control node B and the third control node C from 1 to 0 is reduced by 78.19%; the level change of the first control node A and the output node OUT from 1 to 0, the second control node B and the third control node C from 0 to 1 is reduced by 43.80%, and the power consumption is only increased by 13.46%. Therefore, the design of the present invention can achieve good radiation resistance performance, and has good delay and power consumption.

[0077] Table 1 Comparison of the performance of the level converter of the present invention and the conventional DICE

[0078]

[0079] Compared with the radiation-resistant level conversion circuit proposed in this application: mainly a MOS tube with a gate-drain short circuit is added to the branch where the control node is located. By reducing the source-drain voltage difference of the tube, the probability of the circuit being turned on at the same time with positive and negative voltages when a single-particle effect occurs is reduced. At the same time, single-particle transient pulses can be filtered out, thereby achieving an radiation-resistant effect.

[0080] In this radiation-resistant level conversion circuit, redundant nodes of the circuit are added. When a single-particle effect occurs at a node, the node can be charged and discharged through other redundant nodes to restore the node to an initial storage state. A cross-coupling (RCC) circuit is connected to the second control node B to quickly charge and discharge the node, thereby reducing the probability of the cutoff tube being turned on or the opening tube being turned off when a single-particle effect occurs in the circuit. At the same time, single-particle transient pulses can be filtered out, the node voltage value can be stabilized in the original state, the circuit can be restored to its original function, and circuit errors can be reduced.

[0081] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A radiation-resistant level conversion circuit, characterized in that: The circuit includes a level conversion circuit and an anti-radiation reinforcement circuit based on a DICE structure; The level conversion circuit based on the DICE structure is used to realize level conversion by using redundant control nodes; it includes: two input modules and one DICE module, the DICE module includes four branches consisting of one PMOS transistor and one NMOS transistor connected in series; the drain of the PMOS transistor and the drain of the NMOS transistor in each branch are connected as a control node; The input module is used to control the MOS switch to transmit the differential input signal to the DICE module through the transmission tube; the two output ends of the first input module are respectively connected to the control nodes of the first branch and the second branch of the DICE module; the two output ends of the second input module are respectively connected to the control nodes of the third branch and the fourth branch of the DICE module; The anti-radiation reinforcement circuit is used to perform feedback adjustment on the control nodes of the second branch and the third branch of the DICE module through a cross-coupling structure to improve the radiation resistance; the anti-radiation reinforcement circuit is connected to the control nodes of the second branch and the third branch of the DICE module; The input module is further used to change the connection mode of two NMOS transistors in the input circuit by removing the inverter at the reverse input end of the traditional level conversion circuit, convert an input signal into a differential signal and transmit it to the DICE module; Wherein, the first input module includes a fifth NMOS transistor and a sixth NMOS transistor; the second input module includes a seventh NMOS transistor and an eighth NMOS transistor; The source of the fifth NMOS transistor and the gate of the sixth NMOS transistor are connected to the input node IN, the gate of the fifth NMOS transistor is connected to the power supply VDDL terminal, and the drain of the fifth NMOS transistor is connected to the control node of the first branch of the DICE module; the source of the sixth NMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected to the control node of the second branch of the DICE module; The source of the seventh NMOS transistor and the gate of the eighth NMOS transistor are connected to the input node IN, the gate of the seventh NMOS transistor is connected to the power supply VDDL terminal, and the drain of the seventh NMOS transistor is connected to the control node of the third branch of the DICE module; the source of the eighth NMOS transistor is grounded, and the drain of the eighth NMOS transistor is connected to the control node of the fourth branch of the DICE module; wherein the input node IN is used to receive an input signal.

2. The radiation-resistant level conversion circuit according to claim 1, characterized in that: The radiation hardening circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; A power source VDDH is connected to sources of the fifth PMOS transistor and the sixth PMOS transistor; The drains of the ninth NMOS transistor and the seventh PMOS transistor and the gates of the fifth PMOS transistor and the eighth PMOS transistor are all connected to the control node of the second branch of the DICE module; the drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor; The drains of the eighth PMOS transistor and the tenth NMOS transistor and the gates of the sixth PMOS transistor and the seventh PMOS transistor are all connected to the control node of the third branch of the DICE module; The source of the ninth NMOS transistor is connected to the ground GD, the gate of the tenth NMOS transistor is connected to the power supply VDDL, and the gate of the ninth NMOS transistor and the source of the tenth NMOS transistor are both connected to the input node IN; wherein the input node IN is used to receive an input signal.

3. The radiation-resistant level conversion circuit according to claim 1 or 2, characterized in that: The PMOS transistor and the NMOS transistor are both metal oxide semiconductor field effect transistors.

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