Clock frequency dividing circuit and control method thereof, and frequency divider

Abstract

The invention provides a clock frequency dividing circuit and a control method thereof, and a frequency divider, the circuit comprises a clock frequency dividing module and a signal compensation module, the clock frequency dividing module comprises N clock anti-phase units, the N clock anti-phase units are sequentially connected in series to form a loop, and output N clock frequency dividing signals to the outside, the clock frequency division signal in a high impedance state is compensated through N compensation units in the signal compensation module, so that the stability of the clock frequency division signal is ensured. The clock frequency dividing circuit provided by the invention does not adopt a latch function, and does not need to overcome positive feedback to lock the circuit when the signal changes, so that the requirement on circuit driving is reduced, and the frequency dividing requirement during high-speed signal transmission is met.

Description

Technical Field

[0001] The present invention relates to the field of frequency divider circuit design, and in particular to a clock frequency dividing circuit and a control method thereof, and a frequency divider. Background Art

[0002] With the rapid development of electronic technology, frequency dividers have become an indispensable component in many fields, such as electronic clocks and frequency synthesizers, which require signals of various frequencies to work together. A common method is to use a highly stable crystal oscillator as the main oscillator source and transform it to obtain the required frequency components. Frequency divider circuits are commonly used in clock signal processing and can be used in phase-locked loop feedback loops and multi-frequency clock circuit systems. In related technologies, clock frequency divider circuits are generally composed of latches or triggers, so that the output signal frequency is related to the clock. The main function of the latch is to maintain signal stability. Because the latch function is implemented by positive feedback, when the signal changes, the latch function hinders the signal change, requiring a large drive capability and introducing a large delay. When the signal is transmitted at high speed, it cannot achieve signal frequency division.

[0003] Therefore, how to provide a clock frequency division circuit that is suitable for high speed and does not require signal latching is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a technical solution of a clock frequency dividing circuit to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned objectives and other related objectives, the technical solutions provided in this application are as follows.

[0006] According to a first aspect of an embodiment of the present application, a clock frequency division circuit is provided, comprising:

[0007] A clock frequency division module, comprising N clock inversion units, wherein a clock control terminal of each clock inversion unit is connected to a clock signal, the N clock inversion units are serially connected to form a loop, and each clock inversion unit in the loop outputs N clock frequency division signals based on the clock signal;

[0008] a signal compensation module comprising N compensation units, each of the compensation units generating a corresponding compensation signal based on the clock frequency division signal output from the loop and the clock signal, the output ends of the N compensation units being connected in a one-to-one correspondence with the output ends of the N clock inversion units;

[0009] Among them, if the clock frequency-divided signal output by the clock inversion unit of a certain level is in a high-impedance state, the clock frequency-divided signal is compensated by a corresponding compensation signal; N is an integer greater than or equal to 3.

[0010] In one embodiment of the present invention, the output of the i-th clock inversion unit is connected to the input of the (i+1)-th clock inversion unit, and the output of the N-th clock inversion unit is connected to the input of the first clock inversion unit, where 1≤i≤N is an integer.

[0011] In one embodiment of the present invention, the clock control terminal of the compensation unit is connected to the clock signal, the output terminal of the i-th compensation unit is connected to the output terminal of the i-th clock inversion unit, and multiple input terminals of the i-th compensation unit are connected to the output terminals of other clock inversion units in the loop.

[0012] In one embodiment of the present invention, the clock inversion unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to a power supply voltage, the gate of the first PMOS transistor is connected to the gate of the second NMOS transistor, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is connected to the gate of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded. The gate of the first PMOS transistor is connected to the clock signal, the gate of the second PMOS transistor is the input terminal of the clock inversion unit, and the drain of the second PMOS transistor is the output terminal of the clock inversion unit.

[0013] In one embodiment of the present invention, the compensation unit includes an AND gate, an OR gate, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, the gate of the third PMOS transistor is connected to the output of the AND gate, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the gate of the third NMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the output of the OR gate, the source of the fourth NMOS transistor is grounded, a first input of the OR gate is connected to the first input of the AND gate, and a second input of the OR gate is connected to the second input of the AND gate. The gate of the fourth PMOS transistor serves as the first input of the compensation unit, the first input of the AND gate is connected to the clock signal, the second end of the AND gate serves as the second input of the compensation unit, and the drain of the fourth PMOS transistor serves as the output of the compensation unit.

[0014] According to a second aspect of an embodiment of the present application, a control method for a clock frequency dividing circuit is provided, which is applied to the clock frequency dividing circuit as described above, comprising:

[0015] Outputting N clock frequency-divided signals to the outside according to the clock signal through the N clock inversion units in the clock frequency-dividing module;

[0016] Each compensation unit generates a compensation signal based on the clock signal and the clock frequency-divided signal output in the loop, so as to maintain the level of the clock frequency-divided signal unchanged when it is in a high-impedance state.

[0017] In one embodiment of the present invention, the clock inversion unit outputs the clock frequency-divided signal to the outside in a manner including: if the clock signal and the input terminal signal of the clock inversion unit are both low levels, the clock inversion unit outputs a high level; if the clock signal and the input terminal signal of the clock inversion unit are both high levels, the clock inversion unit outputs a low level; if the states of the clock signal and the input terminal signal of the clock inversion unit are opposite, the clock frequency-divided signal is in a high-impedance state to maintain the same state as the previous moment.

[0018] In one embodiment of the present invention, the compensation unit outputs the compensation signal including: if the clock frequency division signal at the current moment is in a high-impedance state and was at a high level at the previous moment, the compensation unit outputs a high-level compensation signal; if the clock frequency division signal at the current moment is in a high-impedance state and was at a low level at the previous moment, the compensation unit outputs a low-level compensation signal; if the clock frequency division signal at the current moment is at a high level or a low level, the compensation unit outputs a high-impedance compensation signal.

[0019] According to a third aspect of an embodiment of the present application, a frequency divider is provided, wherein the divider includes one or more clock frequency dividing circuits as described above.

[0020] The present application provides a clock frequency division circuit, a control method thereof, and a frequency divider. The circuit includes a clock frequency division module and a signal compensation module. The clock frequency division module includes N clock inversion units, which are serially connected to form a loop and output N clock frequency division signals. The N compensation units in the signal compensation module compensate the clock frequency division signal in a high-impedance state to ensure the stability of the clock frequency division signal. The clock frequency division circuit provided by the present application does not employ a latching function. When the signal changes, there is no need to overcome a positive feedback locking circuit, which reduces the requirements for circuit driving and meets the frequency division requirements for high-speed signal transmission.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0023] Figure 1 is a block diagram of a clock frequency dividing circuit according to an exemplary embodiment of the present invention;

[0024] Figure 2 is a block diagram showing a clock frequency dividing circuit including three clock inversion units according to an exemplary embodiment of the present invention;

[0025] Figure 3 is a specific circuit structure of a clock inversion unit shown in an exemplary embodiment of the present invention;

[0026] Figure 4 is a specific circuit structure of a compensation unit shown in an exemplary embodiment of the present invention;

[0027] Figure 5 is an operating timing diagram of a clock frequency dividing circuit shown in an exemplary embodiment of the present invention;

[0028] Figure 6 is a timing diagram showing the output states of each unit when the clock frequency dividing circuit is stable, according to an exemplary embodiment of the present invention;

[0029] Figure 7 FIG. 1 is a schematic diagram of an ideal state of a three-stage cascade clock inversion unit according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0031] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0032] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0033] High-impedance state is a common term in digital circuits, referring to an output state of the circuit, which is neither a high level nor a low level. If the high-impedance state is input into the next-level circuit, it will have no effect on the lower-level circuit, just like not being connected. If measured with a multimeter, it may be a high level or a low level, depending on what is connected to it.

[0034] With the rapid development of electronic technology, frequency dividers have become an indispensable component in many fields, such as electronic clocks and frequency synthesizers, which require signals of various frequencies to work together. A common method is to use a highly stable crystal oscillator as the main oscillator source and transform it to obtain the required frequency components. Frequency divider circuits are commonly used in clock signal processing and can be used in phase-locked loop feedback loops and multi-frequency clock circuit systems. In related technologies, clock frequency divider circuits are generally composed of latches or triggers, so that the output signal frequency is related to the clock. The main function of the latch is to maintain signal stability. Because the latch function is implemented by positive feedback, when the signal changes, the latch function hinders the signal change, requiring a large drive capability and introducing a large delay. When the signal is transmitted at high speed, it cannot achieve signal frequency division.

[0035] To solve the above problems, Figure 1 As shown, the present application provides a clock frequency division circuit, comprising:

[0036] The clock frequency division module 100 includes N clock inversion units, wherein the clock control terminal of the clock inversion unit is connected to the clock signal CLK. The N clock inversion units are connected in series to form a loop. Each clock inversion unit in the loop outputs N clock frequency division signals (Q1 to QN) based on the clock signal CLK.

[0037] A signal compensation module 200 includes N compensation units, each of which generates a corresponding compensation signal based on the clock frequency division signals (Q1 to QN) output from the loop and the clock signal CLK, and the output terminals of the N compensation units are connected to the output terminals of the N clock inversion units in a one-to-one correspondence;

[0038] Among them, if the clock frequency division signal Qi output by a certain level of clock inversion unit is in a high-impedance state, the clock frequency division signal Qi is compensated by the corresponding compensation signal Ci; N is an integer greater than or equal to 3, and 1≤i≤N.

[0039] In detail, the output of the i-th clock inversion unit is connected to the input of the (i+1)-th clock inversion unit, and the output of the N-th clock inversion unit is connected to the input of the first clock inversion unit, where 1≤i≤N is an integer.

[0040] In more detail, the clock control terminal of the compensation unit is connected to the clock signal, the output terminal of the i-th compensation unit is connected to the output terminal of the i-th clock inversion unit, and multiple input terminals of the i-th compensation unit are connected to the output terminals of other clock inversion units in the loop.

[0041] Specifically, if Figure 2 As shown, when N is 3, the clock division module 100 includes three clock inversion units, the clock control terminals of the three clock inversion units are all connected to the clock signal CLK, the output terminal of the first clock inversion unit is connected to the input terminal of the second clock inversion unit, the output terminal of the second clock inversion unit is connected to the input terminal of the third clock inversion unit, and the output terminal of the third clock inversion unit is connected to the input terminal of the first clock inversion unit. The three clock inversion units are connected in series to form a loop, and the three clock inversion units in the loop output three clock division signals (Q1 to Q3) based on the clock signal CLK.

[0042] like Figure 2As shown, the signal compensation module 200 includes three compensation units, each compensation unit generates a corresponding compensation signal based on the clock frequency division signal (Q1~Q3) output from the loop at the current moment and the clock signal CLK. The output end of the first compensation unit is connected to the output end of the first clock inversion unit, the output end of the second compensation unit is connected to the output end of the second clock inversion unit, and the output end of the third compensation unit is connected to the output end of the third clock inversion unit. The clock control ends of the three compensation units are all connected to the clock signal CLK. The first input end of the first compensation unit is connected to the output end of the second-stage clock inversion unit, the second input end of the first compensation unit is connected to the output end of the third-stage clock inversion unit, the first input end of the second compensation unit is connected to the output end of the third-stage clock inversion unit, the second input end of the second compensation unit is connected to the output end of the first-stage clock inversion unit, the first input end of the third compensation unit is connected to the output end of the first-stage clock inversion unit, and the second input end of the third compensation unit is connected to the output end of the second-stage clock inversion unit.

[0043] Among them, if the clock divided signal Q1 output by the first-stage clock inversion unit is in a high-impedance state, the clock divided signal Q1 is compensated by the first compensation signal C1. Similarly, the compensation principles of the second-stage clock inversion unit and the third-stage clock inversion unit are the same and will not be repeated here.

[0044] In detail, such as Figure 3 As shown, the clock inversion unit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor M1, and a second NMOS transistor M2. The source of the first PMOS transistor P1 is connected to the power supply voltage VCC, the gate of the first PMOS transistor P1 is connected to the gate of the second NMOS transistor M2, the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2, the gate of the second PMOS transistor P2 is connected to the gate of the first NMOS transistor M1, the drain of the second PMOS transistor P2 is connected to the drain of the first NMOS transistor M1, the source of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2, and the source of the second NMOS transistor M2 is grounded. The gate of the first PMOS transistor P1 serves as a clock control terminal of the clock inversion unit, and the clock control terminal of the clock inversion unit is connected to the clock signal CLK. The gate of the second PMOS transistor P2 serves as an input terminal D of the clock inversion unit, and the drain of the second PMOS transistor P2 serves as an output terminal Q of the clock inversion unit.

[0045] In more detail, Figure 4As shown, the compensation unit includes an AND gate AND, an OR gate OR, a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor M3 and a fourth NMOS transistor M4. The source of the third PMOS transistor P3 is connected to the power supply voltage VCC, the gate of the third PMOS transistor P3 is connected to the output end of the AND gate AND, the drain of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 is connected to the gate of the third NMOS transistor M3, the drain of the fourth PMOS transistor P4 is connected to the drain of the third NMOS transistor M3, and the source of the third NMOS transistor M3 is connected to the output end of the fourth NMOS transistor M4. The drain of the fourth NMOS transistor M4 is connected to the output end of the OR gate OR, the source of the fourth NMOS transistor M4 is grounded, the first input end of the OR gate OR is connected to the first input end of the AND gate AND, and the second input end of the OR gate OR is connected to the second input end of the AND gate AND. The gate of the fourth PMOS transistor P4 is the first input end of the compensation unit, the first input end of the AND gate AND is the clock control end of the compensation unit, the clock control end of the compensation unit is connected to the clock signal CLK, the second end of the AND gate AND is the second input end of the compensation unit, and the drain of the fourth PMOS transistor P4 is the output end of the compensation unit.

[0046] like Figures 1 to 7 As shown, the working principle of the clock frequency division circuit provided by this application is as follows:

[0047] like Figure 2 As shown in FIG, when N is 3, the clock frequency dividing circuit includes 3 clock inversion units and 3 compensation units. “X” indicates that the output signal is in a high-impedance state.

[0048] according to Figures 1-6 , perform timing analysis on the clock frequency division circuit. The specific analysis process is as follows:

[0049] (1) At time t0, the clock signal CLK is at a low level. If the output data Q1 of the first-stage clock inversion unit is at a low level, since the input data Q1 of the second-stage clock inversion unit and the clock signal CLK are both at a low level, in the second-stage clock inversion unit: the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, and the first NMOS transistor M1 and the second NMOS transistor M2 are turned off. The state of the output end of the second-stage clock inversion unit is a high level. Since the input data Q2 of the third-stage clock inversion unit is opposite to the clock signal CLK, in the third-stage clock inversion unit: the first PMOS transistor P1 and the second NMOS transistor M2 are turned off. The first NMOS transistor M1 is turned on, the second PMOS transistor P2 and the second NMOS transistor M2 are turned off, and the state of the output end of the third-stage clock inversion unit is a high-impedance state. To ensure that the third-stage clock inversion unit is the same as that in the previous time period, the third-stage clock inversion unit is compensated by the third-stage compensation unit. In the third-stage compensation unit, the third PMOS transistor P3 and the fourth PMOS transistor P4 are turned on, and the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned off. The third-stage compensation unit outputs a high level. Therefore, at time t0, the clock frequency division signal Q3 output by the third-stage clock inversion unit is a high level.

[0050] During the time period from t0 to t1, since the clock signal remains at a low level, the output of the clock frequency division circuit is stable. Figure 6 As shown, during the time period from t0 to t1, according to the clock frequency division signal Q3 and the clock signal CLK output by the third-stage clock inversion unit, it can be known that the output end of the first-stage clock inversion unit is in a high-impedance state. According to the high-level clock frequency division signal Q2, the high-level clock frequency division signal Q3 and the low-level clock signal CLK, it can be inferred that the output end of the first-stage compensation unit is at a low level. Therefore, during the time period from t0 to t1, the clock frequency division signal Q1 output by the first-stage clock inversion unit is at a low level; according to the clock frequency division signal Q1 and the clock signal CLK output by the first-stage clock inversion unit, it can be known that the output end of the second-stage clock inversion unit is at a high level. According to the high-level clock frequency division signal Q3, the low-level clock frequency division signal Q2, the low-level clock frequency division signal Q3 and the low-level clock signal CLK It can be inferred from the flat clock frequency-divided signal Q1 and the low-level clock signal CLK that the output end of the second-stage compensation unit is in a high-impedance state. Therefore, in the time period from t0 to t1, the clock frequency-divided signal Q2 output by the second-stage clock inversion unit is at a high level. According to the clock frequency-divided signal Q2 and the clock signal CLK output by the second-stage clock inversion unit, it can be known that the output end of the third-stage clock inversion unit is in a high-impedance state. According to the low-level clock frequency-divided signal Q1, the high-level clock frequency-divided signal Q2 and the low-level clock signal CLK, it can be inferred that the output end of the third-stage compensation unit is at a high level. Therefore, in the time period from t0 to t1, the clock frequency-divided signal Q3 output by the third-stage clock inversion unit is at a high level.

[0051] (2) At time t1, the clock signal CLK changes from a low level to a high level. Due to the time period t0-t1, the clock frequency division signal Q3 is at a high level. In the first-stage clock inversion unit: the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, and the first NMOS transistor M1 and the second NMOS transistor M2 are turned on. The state of the output end of the first-stage clock inversion unit is a low level. Since the input end data Q1 of the second-stage clock inversion unit is opposite to the clock signal CLK, the output end of the second-stage clock inversion unit is in a high-impedance state. The clock frequency division signal Q2 output by the second-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q2 is a high level. Since the input end data Q2 of the third-stage clock inversion unit and the clock signal CLK are both at a high level, the input clock frequency division signal Q2 is pulled down and output. The output end of the third-stage clock inversion unit is a low level, and the clock frequency division signal Q3 output by the third-stage clock inversion unit is a low level.

[0052] During the time period from t1 to t2, since the clock signal CLK maintains a high level, the output of the clock frequency division circuit is stable. Figure 6 As shown, during the time period t1-t2, the output end of the first-stage clock inversion unit is in a high-impedance state, the output end of the first-stage compensation unit is in a low level, and the clock frequency division signal Q1 is in a low level; the output end of the second-stage clock inversion unit is in a high-impedance state, the output end of the second-stage compensation unit is in a high level, and the clock frequency division signal Q2 is in a high level; the output end of the third-stage clock inversion unit is in a low level, the output end of the third-stage compensation unit is in a high configuration, and the clock frequency division signal Q3 is in a low level.

[0053] (3) At time t2, the clock signal CLK changes from a high level to a low level. Due to the time period t1-t2, the clock frequency division signal Q3 is at a low level. In the first-stage clock inversion unit: the first PMOS tube P1 and the second PMOS tube P2 are turned on, and the first NMOS tube M1 and the second NMOS tube M2 are turned off. The output end of the first-stage clock inversion unit is at a high level. Since the input end data Q1 of the second-stage clock inversion unit is opposite to the clock signal CLK, the output end of the second-stage clock inversion unit is in a high impedance state. The clock frequency division signal Q2 output by the second-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q2 is at a high level. Since the input end data Q2 of the third-stage clock inversion unit is opposite to the clock signal CLK, the output end of the third-stage clock inversion unit is in a high impedance state. The clock frequency division signal Q3 output by the third-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q3 is at a low level.

[0054] During the time period t2-t3, since the clock signal CLK remains at a low level, the output of the clock frequency division circuit is stable. Figure 6As shown, during the time period t2-t3, the output end of the first-stage clock inversion unit is high, the output end of the first-stage compensation unit is in a high-impedance state, and the clock frequency division signal Q1 is high; the output end of the second-stage clock inversion unit is in a high-impedance state, the output end of the second-stage compensation unit is high, and the clock frequency division signal Q2 is high; the output end of the third-stage clock inversion unit is in a high-impedance state, the output end of the third-stage compensation unit is low, and the clock frequency division signal Q3 is low.

[0055] (4) At time t3, the clock signal CLK changes from a low level to a high level. Since the clock frequency division signal Q3 is at a low level during the time period t2-t3, the output end of the first-stage clock inversion unit is in a high-impedance state. The clock frequency division signal Q1 output by the first-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q1 is at a high level. Since the input end data Q1 of the second-stage clock inversion unit and the clock signal CLK are both at a high level, the input clock frequency division signal Q1 is pulled down and output, and the clock frequency division signal Q2 is at a low level. Since the input end data Q1 of the third-stage clock inversion unit is opposite to the clock signal CLK, the output end of the third-stage clock inversion unit is in a high-impedance state. The clock frequency division signal Q3 output by the third-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q3 is at a low level.

[0056] During the time period t3-t4, since the clock signal CLK maintains a high level, the output of the clock frequency division circuit is stable. Figure 6 As shown, during the time period t3-t4, the output end of the first-stage clock inversion unit is in a high-impedance state, the output end of the first-stage compensation unit is at a high level, and the clock frequency division signal Q1 is at a high level; the output end of the second-stage clock inversion unit is at a low level, the output end of the second-stage compensation unit is in a high-impedance state, and the clock frequency division signal Q2 is at a low level; the output end of the third-stage clock inversion unit is in a high-impedance state, the output end of the third-stage compensation unit is at a low level, and the clock frequency division signal Q3 is at a low level.

[0057] (5) At time t4, the clock signal CLK changes from a high level to a low level. Due to the time period t3-t4, the clock frequency division signal Q3 is at a low level. In the first-stage clock inversion unit: the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, and the first NMOS transistor M1 and the second NMOS transistor M2 are turned off. The clock frequency division signal Q1 output by the first-stage clock inversion unit is at a high level. Since the input data Q1 of the second-stage clock inversion unit is opposite to the clock signal CLK, the output end of the second-stage clock inversion unit is in a high-impedance state. The clock frequency division signal Q2 output by the second-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q2 is at a low level. Since the input data Q2 and the clock signal CLK of the third-stage clock inversion unit are both at a low level, the input clock frequency division signal Q2 is pulled up and output, and the clock frequency division signal Q3 is at a high level.

[0058] During the time period t4-t5, since the clock signal CLK remains at a low level, the output of the clock frequency division circuit is stable. Figure 6 As shown, during the time period t4-t5, the output end of the first-stage clock inversion unit is in a high-impedance state, the output end of the first-stage compensation unit is in a high level, and the clock frequency division signal Q1 is in a high level; the output end of the second-stage clock inversion unit is in a high-impedance state, the output end of the second-stage compensation unit is in a low level, and the clock frequency division signal Q2 is in a low level; the output end of the third-stage clock inversion unit is in a high level, the output end of the third-stage compensation unit is in a high-impedance state, and the clock frequency division signal Q3 is in a high level.

[0059] (6) At time t5, the clock signal CLK changes from a low level to a high level. Due to the time period t4-t5, the clock frequency division signal Q3 is a high level. In the first-stage clock inversion unit: the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, and the first NMOS transistor M1 and the second NMOS transistor M2 are turned on. The clock frequency division signal Q1 output by the first-stage clock inversion unit is a low level. Since the input data Q1 of the second-stage clock inversion unit is opposite to the clock signal CLK, the output end of the second-stage clock inversion unit is in a high-impedance state. The clock frequency division signal Q2 output by the second-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q2 is a low level. Since the input data Q2 of the third-stage clock inversion unit is opposite to the clock signal CLK, the output end of the third-stage clock inversion unit is in a high-impedance state. The clock frequency division signal Q3 output by the third-stage clock inversion unit is the same as that at the previous moment, and the clock frequency division signal Q3 is a high level.

[0060] During the time period t5-t6, since the clock signal CLK maintains a high level, the output of the clock frequency division circuit is stable. Figure 6 As shown, during the time period t5-t6, the output end of the first-stage clock inversion unit is low, the output end of the first-stage compensation unit is in a high-impedance state, and the clock frequency division signal Q1 is low; the output end of the second-stage clock inversion unit is in a high-impedance state, the output end of the second-stage compensation unit is low, and the clock frequency division signal Q2 is low; the output end of the third-stage clock inversion unit is in a high-impedance state, the output end of the third-stage compensation unit is high, and the clock frequency division signal Q3 is high.

[0061] During the time period t6-t7, the states of Q1, Q2, and Q3, "011," are identical to those during the time period t0-t1, indicating a repetition. The waveforms of Q1, Q2, and Q3 show a signal flip every 1.5 clock cycles, resulting in a signal period of 3 clock cycles, thus achieving a divide-by-3 frequency function and a 50% duty cycle.

[0062] It should be noted that if Figure 6As shown, in order to avoid competition between the compensation unit and the output clock frequency division signal when the signal output by the clock inversion unit is flipped, in each time period, only one of the output ends of the clock inversion unit and the compensation unit is in a high-impedance state to ensure the stability of the signal output.

[0063] according to Figure 6 The output waveform of each level can be obtained as follows Figure 7 The ideal state machine diagram is shown in the figure. The three clock frequency division signals Q1, Q2, and Q3 have a total of 2×2×2=8 states. Each state can only be stable at the high or low level of the clock. Therefore, the states of Q1, Q2, and Q3 do not meet the requirements of the clock signal CLK. Figure 6 When the state machine requires it, it automatically enters the next state and stabilizes. Six of these states, "001," "011," "010," "110," "100," and "101," constitute the state machine for normal divide-by-3 operation. The other two states, "000" and "111," are very special. In these states, the clock division signals Q1, Q2, and Q3 flip simultaneously with the clock signal, resulting in the clock division signals being in the same frequency as the clock signal. However, this state requires that the switching times of Q1, Q2, and Q3 must be consistent. If there are any discrepancies, the signal that changes first will prevent the signal that changes later from flipping, thus entering a certain state within the divide-by-3 loop. In actual circuits, manufacturing variations exist between the three clock inversion units, and the clock division signals Q1, Q2, and Q3 can also be affected by noise, resulting in variations in the flip times of the clock division signals Q1, Q2, and Q3, thus escaping the "000" and "111" states and entering the divide-by-3 state.

[0064] The clock-divided signal flips every 1.5 clock cycles. Within this 1.5-clock cycle, only the 0.5-clock cycle where the flip occurs is determined by the clock inversion unit. For the remaining 1 clock cycle, the clock-divided signal is in a high-impedance state. Leakage or interference can affect signal quality and even cause bit errors. Therefore, a signal compensation unit is required to maintain the signal level during this high-impedance state.

[0065] It should be noted that the input of the clock inversion unit is related to the clock signal at the current moment and the output of the previous-level clock inversion unit. The input of the first-level clock inversion unit is related to the output of the last-level clock inversion unit at the previous moment. Since the output of the clock inversion unit is in a high-impedance state, the current moment is the same as the previous moment. Therefore, when the output level of the first clock inversion unit is determined, the first-moment level of the subsequent cascaded clock inversion unit is also determined. The compensation unit compensates the clock inversion unit according to the clock division signal output in the current time period to ensure that the output of the clock inversion unit at each level does not change during the high-impedance time period.

[0066] The present application also provides a control method for a clock frequency dividing circuit, which is applied to the clock frequency dividing circuit as described above, comprising:

[0067] Outputting N clock frequency-divided signals to the outside according to the clock signal through N clock inversion units in the clock frequency-dividing module;

[0068] Each compensation unit generates a compensation signal based on the clock signal and the clock frequency division signal output in the loop, so as to maintain the level of the clock frequency division signal unchanged when it is in a high impedance state.

[0069] Specifically, the clock inversion unit outputs the clock frequency division signal in the following manner: if the clock signal and the input terminal signal of the clock inversion unit are both low level, the clock inversion unit outputs a high level; if the clock signal and the input terminal signal of the clock inversion unit are both high level, the clock inversion unit outputs a low level; if the states of the clock signal and the input terminal signal of the clock inversion unit are opposite, the clock frequency division signal is in a high impedance state to maintain the same state as the previous moment. Specifically, Figure 3 As shown, if the clock signal CLK and the clock inverting unit input terminal signal D are both low, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, the first NMOS transistor M1 and the second NMOS transistor M2 are turned off, and the clock frequency division signal is high. If the clock signal CLK and the clock inverting unit input terminal signal D are both high, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, the first NMOS transistor M1 and the second NMOS transistor M2 are turned on, and the clock frequency division signal is low. If the clock signal CLK is low and the clock inverting unit input terminal signal D is high, or if the clock signal CLK is high and the clock inverting unit input terminal signal D is low, the clock frequency division signal is in a high-impedance state and is compensated by the compensation unit to maintain the same level as the previous moment.

[0070] In detail, such as Figure 6 As shown, the compensation unit outputs the compensation signal including: if the clock frequency division signal at the current moment is in a high-impedance state and was at a high level at the previous moment, the compensation unit generates a high-level compensation signal; if the clock frequency division signal at the current moment is in a high-impedance state and was at a low level at the previous moment, the compensation unit generates a low-level compensation signal; if the clock frequency division signal at the current moment is at a high level or a low level, the compensation unit outputs a high-impedance compensation signal.

[0071] The present application also provides a frequency divider, comprising one or more clock frequency dividing circuits as described above.

[0072] The present application provides a clock frequency division circuit, a control method thereof, and a frequency divider. The circuit includes a clock frequency division module and a signal compensation module. The clock frequency division module includes N clock inversion units, which are serially connected to form a loop and output N clock frequency division signals. The N compensation units in the signal compensation module compensate the clock frequency division signal in a high-impedance state to ensure the stability of the clock frequency division signal. The clock frequency division circuit provided by the present application does not employ a latching function. When the signal changes, there is no need to overcome a positive feedback locking circuit, which reduces the requirements for circuit driving and meets the frequency division requirements for high-speed signal transmission.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A clock frequency division circuit, characterized in that: include: A clock frequency division module, comprising N clock inversion units, wherein the clock control terminal of the clock inversion unit is connected to a clock signal, the N clock inversion units are serially connected in sequence to form a loop, and each clock inversion unit in the loop outputs N clock frequency division signals based on the clock signal; A signal compensation module, comprising N compensation units, each of which generates a corresponding compensation signal according to the clock frequency division signal output in the loop and the clock signal, and the output ends of the N compensation units are connected to the output ends of the N clock inversion units in a one-to-one correspondence; Among them, if the clock frequency division signal output by the clock inversion unit of a certain level is in a high-impedance state, the clock frequency division signal is compensated by a corresponding compensation signal; N is an integer greater than or equal to 3.

2. The clock frequency division circuit according to claim 1, characterized in that: The output end of the i-th clock inversion unit is connected to the input end of the i+1-th clock inversion unit, and the output end of the N-th clock inversion unit is connected to the input end of the first clock inversion unit, wherein 1≤i≤N is an integer.

3. The clock frequency division circuit according to claim 2, characterized in that: The clock control terminal of the compensation unit is connected to the clock signal, the output terminal of the i-th compensation unit is connected to the output terminal of the i-th clock inversion unit, and multiple input terminals of the i-th compensation unit are connected to the output terminals of other clock inversion units in the loop.

4. The clock frequency division circuit according to claim 1, characterized in that: The clock inversion unit includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the source of the first PMOS tube is connected to a power supply voltage, the gate of the first PMOS tube is connected to the gate of the second NMOS tube, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the gate of the second PMOS tube is connected to the gate of the first NMOS tube, the drain of the second PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is grounded, wherein the gate of the first PMOS tube is connected to the clock signal, the gate of the second PMOS tube is the input end of the clock inversion unit, and the drain of the second PMOS tube is the output end of the clock inversion unit.

5. The clock frequency division circuit according to claim 4, characterized in that: The compensation unit includes an AND gate, an OR gate, a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fourth NMOS tube, the source of the third PMOS tube is connected to the power supply voltage, the gate of the third PMOS tube is connected to the output end of the AND gate, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the third NMOS tube, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the output end of the OR gate, the source of the fourth NMOS tube is grounded, the first input end of the OR gate is connected to the first input end of the AND gate, the second input end of the OR gate is connected to the second input end of the AND gate, wherein the gate of the fourth PMOS tube is the first input end of the compensation unit, the first input end of the AND gate is connected to the clock signal, the second end of the AND gate is the second input end of the compensation unit, and the drain of the fourth PMOS tube is the output end of the compensation unit.

6. A method for controlling a clock frequency dividing circuit, characterized in that: A clock frequency dividing circuit as claimed in any one of claims 1 to 5, comprising: Outputting N clock frequency-dividing signals to the outside according to the clock signal through the N clock inversion units in the clock frequency-dividing module; Each of the compensation units generates a compensation signal based on the clock signal and the clock frequency division signal output in the loop, so as to maintain the level of the clock frequency division signal unchanged when it is in a high impedance state.

7. A method for controlling a clock frequency dividing circuit, characterized in that: The clock inversion unit outputs the clock frequency division signal externally in a manner including: If the clock signal and the input terminal signal of the clock inversion unit are both at a low level, the clock inversion unit outputs a high level; If the clock signal and the input terminal signal of the clock inversion unit are both high level, the clock inversion unit outputs a low level; If the states of the clock signal and the input terminal signal of the clock inversion unit are opposite, the clock frequency division signal is in a high impedance state to maintain the same state as that at the previous moment.

8. A method for controlling a clock frequency dividing circuit, characterized in that: The compensation unit outputting the compensation signal comprises: If the clock frequency division signal at the current moment is in a high impedance state and was at a high level at the previous moment, the compensation unit outputs a high level compensation signal; If the clock frequency division signal at the current moment is in a high impedance state and was at a low level at the previous moment, the compensation unit outputs a low level compensation signal; If the clock frequency division signal at the current moment is at a high level or a low level, the compensation unit outputs a high-impedance compensation signal.

9. A frequency divider, characterized in that: The frequency divider comprises one or more clock frequency dividing circuits as claimed in any one of claims 1-5.

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