Input signal quantification method and device, electronic equipment and computer storage medium

Abstract

The embodiment of the invention provides an input signal quantification method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of chips, and the method comprises the steps: in response to a quantification instruction for an input signal, resetting lower polar plates of N pairs of capacitors to a preset level, and determining the type of the input signal; determining a working mode of the ADC based on the type of the input signal; determining code values of N pairs of capacitors in the working mode to obtain N code values, and determining an (N + 1) th code value based on the Nth code value; and taking the N-bit code value and the (N + 1) th code value as a quantization result of the input signal. By means of the mode, the differential working mode and the single-end working mode of the ADC can be combined, in the single-end working mode, idle capacitors can be multiplexed, the problem that effective bits are reduced by 1 bit in the single-end working mode is avoided, and the precision of the ADC is effectively guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a quantization method for an input signal, a quantization device for an input signal, an electronic device, and a computer-readable storage medium. Background Art

[0002] Most of the existing ADC (Analog-to-Digital Converter) products on the market currently have only differential or single-ended working modes. In the actual application of successive approximation ADC (SAR ADC), there are also scenarios that need to support both single-ended and differential inputs. For example, in motor applications, it is necessary to cooperate with PGA (Programmable Gain Amplifier) ​​to collect the voltage at both ends of the resistor and then differentially amplify and output it to the ADC for quantization. At this time, the ADC is a differential input, while most other single voltage analog acquisitions only require a single-ended signal to be input to the ADC. At this time, the ADC works in single-ended mode.

[0003] In differential working mode, signal swing VFS=2VCC, delta(LSB)=VFS / 2 N In single-ended operation mode, if one end is connected to the signal and the other end is connected to GND, the signal swing is VFS = VCC, and delta (LSB) = VFS / (2*2 N ), the VFS swing is reduced by half, and the LSB is also reduced by half; if one end is connected to the signal and the other end is connected to the common mode voltage VCM=VCC / 2, then the signal swing is VFS=VCC / 2, at this time delta(LSB)=VFS / 2 N , the swing is reduced by half, and the LSB remains unchanged.

[0004] That is to say, in both solutions, although the other end can be connected to VCC / 2 to ensure that delta (LSB) reaches VFS / 2 N , but the swing will still drop to half of that of differential input. For the same SAR ADC capacitor array, if the quantization noise is constant and the signal swing drops by half, the SNR (Signal-to-Noise Ratio) will drop by 6db and the ENOB (effective-number-of-bits) will drop by 1 bit, resulting in lower ADC accuracy. For ENOB, the most important performance indicator of ADC, the performance loss is huge. Summary of the invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a method for quantizing an input signal, an input signal quantization device, an electronic device and a computer-readable storage medium that overcome the above problems or at least partially solve the above problems.

[0006] The embodiment of the present invention discloses a quantization method of an input signal, which is applied to an analog-to-digital conversion ADC, wherein the ADC includes a digital-to-analog conversion DAC capacitor array, wherein the DAC capacitor array includes N pairs of capacitors, where N is a positive integer; the method includes:

[0007] In response to a quantization instruction for an input signal, resetting the lower plates of the N pairs of capacitors to a preset level, and determining the type of the input signal;

[0008] determining an operating mode of the ADC based on the type of the input signal;

[0009] Determine the code values ​​of N pairs of capacitors in the working mode to obtain N-bit code values, and determine the N+1-th bit code value based on the N-th bit code value;

[0010] The N-bit code value and the N+1-th bit code value are used as quantization results of the input signal.

[0011] In an embodiment of the present invention, determining the working mode of the ADC based on the type of the input signal includes:

[0012] If the type of the input signal is a differential signal, setting the ADC to a differential working mode;

[0013] If the type of the input signal is a single-ended signal, the ADC is set to a single-ended working mode.

[0014] In an embodiment of the present invention, determining the code values ​​of N pairs of capacitors in the working mode to obtain N-bit code values, and determining the N+1-bit code value based on the N-bit code value includes:

[0015] In the working mode, determining the code value of a first pair of capacitors among the N pairs of capacitors based on the input signal, and switching the preset level of the lower plates of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors;

[0016] Determine the code values ​​of the second pair of capacitors to the Nth pair of capacitors in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching, and obtain an N-bit code value;

[0017] The N+1th bit code value is determined based on the Nth bit code value.

[0018] In an embodiment of the present invention, each pair of capacitors in the N pairs of capacitors includes an upper capacitor and a lower capacitor;

[0019] The method of determining the code value of the first pair of capacitors among the N pairs of capacitors based on the input signal in the working mode, and switching the preset level of the lower plate of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors includes:

[0020] In the working mode, the voltage of the input upper capacitor and the voltage of the input lower capacitor in the input signal are compared to obtain a code value of the first pair of capacitors;

[0021] Based on the code value of the first pair of capacitors, the preset level of the lower plate of the upper capacitor in the first pair of capacitors is switched, and the preset level of the lower plate of the lower capacitor in the first pair of capacitors is switched to obtain the switched first pair of capacitors; wherein the levels of the two lower plates in the switched first pair of capacitors are ground or a reference high level, and the levels of the two lower plates are different.

[0022] In the embodiment of the present invention, the code values ​​of the second pair of capacitors to the Nth pair of capacitors are determined in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching to obtain the N-bit code value, including:

[0023] S1, taking the first pair of capacitors after switching as the capacitors to be processed;

[0024] S2, using the weight of the capacitor to be processed to calculate the current voltage of the upper capacitor and the current voltage of the lower capacitor in the capacitor to be processed;

[0025] S3, comparing the current voltage of the upper capacitor with the current voltage of the lower capacitor to determine the code value of the candidate capacitor; the candidate capacitor is the next pair of capacitors of the capacitor to be processed;

[0026] S4, detecting whether the candidate capacitor is the Nth pair of capacitors, if not, executing S5, if yes, executing S7;

[0027] S5, using the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor, and switching the preset level of the lower plate of the lower capacitor in the candidate capacitor to obtain a first candidate capacitor after switching, and executing S6;

[0028] S6, taking the first candidate capacitor as the capacitor to be processed, and executing S2;

[0029] S7. Use the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor to obtain a second candidate capacitor after switching, and an N-bit code value.

[0030] Accordingly, an embodiment of the present invention discloses a quantization device for an input signal, which is applied to an analog-to-digital conversion ADC, wherein the ADC includes a digital-to-analog conversion DAC capacitor array, wherein the DAC capacitor array includes N pairs of capacitors, where N is a positive integer; the device includes:

[0031] A first processing module, configured to reset the lower plates of the N pairs of capacitors to a preset level in response to a quantization instruction for an input signal, and determine a type of the input signal;

[0032] A first determination module, configured to determine an operating mode of the ADC based on a type of the input signal;

[0033] A second determination module is used to determine the code values ​​of N pairs of capacitors in the working mode, obtain N-bit code values, and determine the N+1-th bit code value based on the N-th bit code value;

[0034] The second processing module is used to use the N-bit code value and the N+1-th bit code value as the quantization result of the input signal.

[0035] In the embodiment of the present invention, the first determining module is specifically configured to:

[0036] If the type of the input signal is a differential signal, setting the ADC to a differential working mode;

[0037] If the type of the input signal is a single-ended signal, the ADC is set to a single-ended working mode.

[0038] In this embodiment of the present invention, the second determining module includes:

[0039] a calculation submodule, configured to determine, in the working mode, a code value of a first pair of capacitors among the N pairs of capacitors based on the input signal;

[0040] A switching submodule, configured to switch the preset level of the lower plate of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors;

[0041] The calculation submodule is further used to determine the code values ​​of the second pair of capacitors to the Nth pair of capacitors in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching, so as to obtain an N-bit code value;

[0042] The calculation submodule is further used to determine the N+1th code value based on the Nth code value.

[0043] In an embodiment of the present invention, each pair of capacitors in the N pairs of capacitors includes an upper capacitor and a lower capacitor;

[0044] The computing submodule is specifically used for:

[0045] In the working mode, the voltage of the input upper capacitor and the voltage of the input lower capacitor in the input signal are compared to obtain a code value of the first pair of capacitors;

[0046] The switching submodule is specifically used for:

[0047] Based on the code value of the first pair of capacitors, the preset level of the lower plate of the upper capacitor in the first pair of capacitors is switched, and the preset level of the lower plate of the lower capacitor in the first pair of capacitors is switched to obtain the switched first pair of capacitors; wherein the levels of the two lower plates in the switched first pair of capacitors are ground or a reference high level, and the levels of the two lower plates are different.

[0048] In the embodiment of the present invention, the computing submodule is further configured to:

[0049] S1, taking the first pair of capacitors after switching as the capacitors to be processed;

[0050] S2, using the weight of the capacitor to be processed to calculate the current voltage of the upper capacitor and the current voltage of the lower capacitor in the capacitor to be processed;

[0051] S3, comparing the current voltage of the upper capacitor with the current voltage of the lower capacitor to determine the code value of the candidate capacitor; the candidate capacitor is the next pair of capacitors of the capacitor to be processed;

[0052] S4, detecting whether the candidate capacitor is the Nth pair of capacitors, if not, executing S5, if yes, executing S7;

[0053] S5, using the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor, and switching the preset level of the lower plate of the lower capacitor in the candidate capacitor to obtain a first candidate capacitor after switching, and executing S6;

[0054] S6, taking the first candidate capacitor as the capacitor to be processed, and executing S2;

[0055] S7. Use the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor to obtain a second candidate capacitor after switching, and an N-bit code value.

[0056] Correspondingly, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the various steps of the above-mentioned input signal quantization method embodiment when executed by the processor.

[0057] Accordingly, an embodiment of the present invention discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each step of the embodiment of the input signal quantization method is implemented.

[0058] The embodiments of the present invention include the following advantages:

[0059] In response to the quantization instruction for the input signal, the lower plates of N pairs of capacitors are reset to a preset level, and the type of the input signal is determined; the working mode of the ADC is determined based on the type of the input signal; the code values ​​of N pairs of capacitors are determined in the working mode to obtain N-bit code values, and the N+1-bit code value is determined based on the N-bit code value; the N-bit code value and the N+1-bit code value are used as the quantization result of the input signal. In the above manner, the differential working mode of the ADC can be combined with the single-ended working mode, and in the single-ended working mode, the idle capacitors can be reused, avoiding the problem of the effective number of bits dropping by 1 bit in the single-ended working mode, and effectively ensuring the accuracy of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 is a flowchart of a method for quantizing an input signal according to an embodiment of the present invention;

[0061] Figure 2 It is a circuit diagram of an ADC supporting a differential working mode of the present invention;

[0062] Figure 3 It is a circuit diagram of an ADC supporting a single-ended working mode of the present invention;

[0063] Figure 4 It is a schematic diagram of switching of a capacitor array in an ADC in a differential working mode of the present invention;

[0064] Figure 5 It is a schematic diagram of switching of a capacitor array in an ADC in a single-ended working mode of the present invention;

[0065] Figure 6 It is a structural block diagram of an embodiment of a quantization device for an input signal of the present invention. DETAILED DESCRIPTION

[0066] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] One of the core concepts of the embodiment of the present invention is that the differential working mode of the ADC can be combined with the single-ended working mode, and in the single-ended working mode, idle capacitors can be reused, avoiding the problem of the effective number of bits decreasing by 1 bit in the single-ended working mode, thereby effectively ensuring the accuracy of the ADC.

[0068] Reference Figure 1 , shows a flow chart of the steps of a first embodiment of a quantization method for an input signal of the present invention, which is applied to an analog-to-digital conversion ADC, wherein the ADC includes a digital-to-analog conversion DAC capacitor array, and the DAC capacitor array includes N pairs of capacitors. The type of the ADC may be a successive approximation register (SAR); and N is a positive integer.

[0069] Furthermore, the ADC can support a differential working mode and a single-ended working mode, that is, the input signal of the ADC can be either a differential signal or a single-ended signal.

[0070] Reference Figure 2 , shows a circuit diagram of an ADC supporting a differential working mode, the ADC includes three pairs of capacitors C2, C1 and C0, where V ip and V in It can be an analog input, that is, an external input signal, V p and V n It may be an intermediate quantity, that is, different voltages obtained after the capacitor array is set to the corresponding level from high to low according to the comparison result of the input signal.

[0071] If there are 3 pairs of capacitors, there will be 3 pairs in the middle. The first comparison will get the switching strategy of the highest-order (first pair) capacitor (C2) and get the first pair of V p and V n The second comparison obtains the switching strategy of the second highest capacitor (the second pair) (C1), and the second pair of V p and V n The third comparison obtains the switching strategy of the lowest-order (third pair) capacitor (C0), and the third pair of V p and V n .

[0072] The ADC includes a comparator for converting V p and V n Compare and get the code value.

[0073] It should be noted that Figure 2 Only N is 3 for example. In practical applications, the specific value of N can be set according to actual needs, and the embodiment of the present invention does not limit this. For example, when N is 5, there will be 5 pairs of intermediate quantities; when N is 11, there will be 11 pairs of intermediate quantities.

[0074] Reference Figure 3 , shows a circuit diagram of an ADC supporting single-ended working mode, the ADC includes three pairs of capacitors C2, C1 and C0, as well as switches 1, 2 and 3. In the single-ended working mode, the input signal, that is, the sampling end, needs to be connected to V ip In order to share all the capacitors, all the capacitors at the lower end need to be connected to the capacitors at the upper end, switched in phase, the capacitors at the lower end do not need to be connected to the input of the comparator, and one end of the rear comparator needs to be fixed to V cm , instead of connecting one of the inputs, so in single-ended operation mode, switches 1 and 3 are closed and switch 2 is open. In this way, the upper capacitor is connected to the lower capacitor, the capacitance is increased, the quantization noise is reduced by half, and thus ENOB is improved.

[0075] Among them, V cm is the reference common mode level, V cm =VCC / 2. V cm The function is to set the lower plate of the capacitor to the middle level. By switching the lower plate between different voltages of gnd, VCC / 2, and VCC, the voltage value of the upper plate is changed according to the principle of charge conservation and the different weights of the corresponding capacitors, so as to achieve the purpose of voltage bit-by-bit comparison.

[0076] Furthermore, the original external input signal is V ip and V in (that is, differential signal), but in single-ended mode there is only one input, so V in Also connected to V ip , so there are 2 V ip . V p and V n It is also the intermediate quantity, which is the input of the comparator inside the ADC, that is, V ip and V in The voltage value obtained by redistributing the charge after the capacitor plates are placed in different positions is used as the input of the comparator.

[0077] It should be noted that Figure 3 Only an example of N being 3 is used for illustration. In practical applications, the specific value of N can be set according to actual needs, and the embodiment of the present invention does not limit this.

[0078] The specific steps may include:

[0079] Step 101, in response to a quantization instruction for an input signal, resetting the lower plates of N pairs of capacitors to a preset level, and determining the type of the input signal.

[0080] Specifically, after the ADC obtains the quantization instruction for quantizing the input signal, it can reset the lower plates of all capacitors (including the upper capacitors and the lower capacitors) in the N pairs of capacitors to a preset level, and determine the type of the input signal. The preset level can be V cm ; The types of input signals include differential signals and single-ended signals, so that the working mode of the ADC can be determined according to the type of input signal.

[0081] In other words, the choice between differential working mode and single-ended working mode comes from the requirements of the input signal.

[0082] For example, a general voltage signal only requires single-ended sampling. If the input source is a PGA with differential output, such as a motor application scenario, it is necessary to detect the current of three-phase AC power. The current can only be inferred by detecting the voltage across the resistor when the current flows through it. Moreover, both ends of the resistor are not grounded and are at a level higher than the ground potential. At this time, the PGA output is two different voltage values. At this time, it can be broadly considered that this is a pair of differential signals. After the PGA differentially amplifies the weak signal, it is quantified to the ADC. At this time, the input of the ADC is a differential input.

[0083] ADC single-ended input generally means that it can only receive one input signal. Different ADCs have different architectures. If an ADC module supports both single-ended and differential, the circuit design needs to support both, and the circuit connection mode must be configured when using differential and single-ended.

[0084] There is a module called SAR logic in the SAR ADC. The design of this logic will have a series of triggers and buffer circuits. The triggers and buffer circuits will connect the corresponding circuits according to the configuration values ​​of the digital module. The implementation of SAR ADC is: receiving the SOC (System on Chip) instruction-sampling-quantization. Among them, the quantization process is a process of successive approximation quantization, that is, after getting the first result, for example, V ip >V in , the comparison result is 1 (or 0), then the highest capacitor of the capacitor array is set to low (or high), thereby changing the voltage value and giving the comparator the next comparison. For example, if V ip =3.3V maximum voltage, V in =0V minimum voltage, then each time the capacitor array is set, V ip <V in , all 1s will be output, that is, the quantization result is 1111, which is the maximum voltage 3.3V.

[0085] Each bit-by-bit quantization requires a clock. The SAR logic is designed with triggers and buffers to generate the quantization clock. All quantized data will be cached in the buffer. When the last bit is quantized, an EOC (end of conversion) quantization completion indication signal will be generated. This signal will trigger all the data in the buffer at the same time, generating 4-bit data such as D<3:0>, and then output EOC and D<3:0> to the digital module together. That is, a complete input quantization process is completed, and the D<3:0> code value is the quantization result.

[0086] Step 102: Determine the operating mode of the ADC based on the type of the input signal.

[0087] As mentioned above, the types of input signals include differential signals and single-ended signals. Therefore, after the type of input signal is determined, the ADC can be set to the working mode corresponding to the input signal.

[0088] In an embodiment of the present invention, determining the working mode of the ADC based on the type of the input signal includes:

[0089] If the type of the input signal is a differential signal, setting the ADC to a differential working mode;

[0090] If the type of the input signal is a single-ended signal, the ADC is set to a single-ended working mode.

[0091] Specifically, if Figure 3 As shown, the ADC is provided with switch 1, switch 2 and switch 3. When the input signal type is a differential signal, switch 1 can be opened, switch 2 can be closed, and switch 3 can be opened, thereby setting the ADC to a differential working mode; when the input signal type is a single-ended signal, switch 1 can be closed, switch 2 can be opened, and switch 3 can be closed, thereby setting the ADC to a single-ended working mode.

[0092] Step 103 , determining code values ​​of N pairs of capacitors in the working mode, obtaining N-bit code values, and determining the (N+1)th bit code value based on the (N)th bit code value.

[0093] After determining the working mode of the ADC, the code value of each pair of capacitors in the working mode can be determined to obtain an N-bit code value, and then the N+1-bit code value is determined based on the N-bit code value. For example, assuming that the ADC includes 3 pairs of capacitors, in the differential working mode, the code values ​​of the 3 pairs of capacitors can be determined to obtain a 3-bit code value, and then the 4th-bit code value is determined using the 3rd-bit code value, that is, a 4-bit code value is obtained through 3 pairs of capacitors, that is, a 4-bit ADC. Similarly, if an N-bit ADC is required, the ADC can be set to N-1 pairs of capacitors.

[0094] The code value is the result obtained by the comparator. For example, if V p >V n , the result is 1, and the code value is 1; if V p <V n , the result is 0, and the code value is 0. After obtaining the code value, the corresponding capacitor lower plate can be set according to the code value.

[0095] Assuming that the ADC includes 3 pairs of capacitors, the code values ​​after three comparisons are used to set the three pairs of capacitors, and the fourth code value does not need to set the capacitor again. That is, 3 pairs of capacitors can get a 4-bit code value, which is a 4-bit ADC.

[0096] For example, the code value of 4 bits from high to low is 1100, the highest bit is 1, that is, the code value obtained by the first comparison is 1, the second bit is also 1, that is, the code value obtained by the second comparison is 1, the third bit is 0, that is, the code value obtained by the third comparison is 0, and the fourth bit is 0, that is, the voltage obtained according to the third capacitor code value, the result of the comparison is 0, after the fourth bit is compared, there is no need to set the capacitor, because there is already a comparison result, so the fourth pair of capacitors is not needed, then this code value 1100 gets V p With V n The difference is the quantization result obtained by the ADC after successive quantization.

[0097] In an embodiment of the present invention, determining the code values ​​of N pairs of capacitors in the working mode to obtain N-bit code values, and determining the N+1-bit code value based on the N-bit code value includes:

[0098] In the working mode, determining the code value of a first pair of capacitors among the N pairs of capacitors based on the input signal, and switching the preset level of the lower plates of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors;

[0099] Determine the code values ​​of the second pair of capacitors to the Nth pair of capacitors in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching, and obtain an N-bit code value;

[0100] The N+1th bit code value is determined based on the Nth bit code value.

[0101] Specifically, in the current working mode, the ADC can directly determine the code value (0 or 1) of the first pair of capacitors in N pairs of capacitors based on the input signal, and then switch the preset level of the lower plate of the first pair of capacitors according to the code value of the first pair of capacitors, that is, switch the lower plates of the upper capacitors and the lower capacitors in the first pair of capacitors at the same time, so as to obtain the first pair of capacitors after switching.

[0102] It should be noted that before determining the code value of the first capacitor according to the input signal, the input signal can be sampled, and the sampling can be performed by the upper plate in each pair of capacitors. After the input signal sampling is completed, the input signal can be disconnected. If it is not disconnected, the sampled input signal will change with the change of the input, and it cannot be maintained, and it is impossible to compare and obtain the code value to switch the lower plate of the capacitor.

[0103] Furthermore, after the sampling is completed, the highest bit comparison is performed directly, that is, the input signal is directly given to the comparator for comparison. After the comparison, the comparator will generate a comparison result to the SAR digital logic unit. The SAR digital logic unit starts working, and the corresponding clock edge saves and transmits the data to the capacitor switch of the corresponding weight, and generates an indication signal for the next comparison. Therefore, the first comparison is a direct comparison. The second and subsequent comparisons all need to set the capacitors of different weights according to the results of the first and previous comparisons to obtain a new voltage value, and then compare. During the second comparison, the capacitor with the highest weight, that is, the largest capacitance, sets the upper plate to ground (GND) or V according to the comparison result. ref Among them, V ref is the reference high level, V ref =VCC, its function is to set the lower plate of the capacitor to the high level VCC.

[0104] Among them, the capacitance weight of each capacitor in the DAC capacitor array of the ADC is 2 times. If the highest bit is designed not to be compared directly, but requires the participation of capacitors, then one clock cycle is required to set the capacitor first, and there will be one more switching clock. Moreover, the highest capacitor is the sum of the second highest and all other capacitors. The larger the capacitance, the longer the charging time and the larger the charging current, which will also cause the cycle to become longer and increase power consumption. Therefore, directly comparing the highest bit after sampling omits the power consumption of the switching cycle of the highest capacitor, and at the same time, saves half of the DAC capacitor area.

[0105] In an embodiment of the present invention, determining the code value of the first pair of capacitors among the N pairs of capacitors based on the input signal in the working mode, and switching the preset level of the lower plate of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors includes:

[0106] In the working mode, the voltage of the input upper capacitor and the voltage of the input lower capacitor in the input signal are compared to obtain a code value of the first pair of capacitors;

[0107] Based on the code value of the first pair of capacitors, the preset level of the lower plate of the upper capacitor in the first pair of capacitors is switched, and the preset level of the lower plate of the lower capacitor in the first pair of capacitors is switched to obtain the switched first pair of capacitors; wherein the levels of the two lower plates in the switched first pair of capacitors are ground or a reference high level, and the levels of the two lower plates are different.

[0108] Specifically, in the current working mode, the voltage of the input upper capacitor can be compared with the voltage of the input lower capacitor, that is, the input signal is directly compared to the comparator to obtain the code value of the first capacitor, and then the preset levels of the upper capacitor and the lower capacitor in the first pair (highest bit) of capacitors are switched at the same time according to the code value to obtain the first pair of capacitors after switching. In the first pair of capacitors after switching, the lower plate of the upper capacitor and the lower plate of the lower capacitor are ground (GND) or reference high level (V ref ), that is, when the lower plate of the upper capacitor is GND, the lower plate of the lower capacitor is V ref , or, when the lower plate of the upper capacitor is V ref When , the lower plate of the lower capacitor is GND.

[0109] In the embodiment of the present invention, the code values ​​of the second pair of capacitors to the Nth pair of capacitors are determined in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching to obtain the N-bit code value, including:

[0110] S1, taking the first pair of capacitors after switching as the capacitors to be processed;

[0111] S2, using the weight of the capacitor to be processed to calculate the current voltage of the upper capacitor and the current voltage of the lower capacitor in the capacitor to be processed;

[0112] S3, comparing the current voltage of the upper capacitor with the current voltage of the lower capacitor to determine the code value of the first candidate capacitor; the first candidate capacitor is the next pair of capacitors of the capacitor to be processed;

[0113] S4, detecting whether the first candidate capacitor is the Nth pair of capacitors, if not, executing S5, if yes, executing S7;

[0114] S5, using the code value of the first candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the first candidate capacitor, and switching the preset level of the lower plate of the lower capacitor in the first candidate capacitor to obtain a switched second candidate capacitor, and executing S6;

[0115] S6, taking the second candidate capacitor as the capacitor to be processed, and executing S2;

[0116] S7. Use the code value of the first candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the first candidate capacitor to obtain a third candidate capacitor after switching, and an N-bit code value.

[0117] Specifically, after obtaining the first pair of capacitors after switching, the first pair of capacitors after switching can be used as capacitors to be processed. Since the lower plates of the two capacitors in the first capacitor have been switched, the voltage of the upper capacitor and the voltage of the lower capacitor in the first capacitor will change. Therefore, the weight of the capacitor to be processed can be used to calculate the current voltage of the upper capacitor and the current voltage of the lower capacitor. Then, the current voltage of the upper capacitor and the current voltage of the lower capacitor are compared to obtain the code value of the next pair of capacitors (recorded as "first candidate capacitors").

[0118] Detect whether the next pair of capacitors is the Nth pair of capacitors, that is, the last pair of capacitors in the capacitor array. If it is not the last pair of capacitors, then the preset level of the lower plate of the upper capacitor in the first candidate capacitor can be switched according to the code value of the first candidate capacitor, and the preset level of the lower plate of the lower capacitor in the first candidate capacitor can be switched to obtain a pair of capacitors after switching (recorded as "second candidate capacitors").

[0119] The second candidate capacitor is used as the capacitor to be processed, and the above steps are repeated until the first candidate capacitor is the Nth pair of capacitors, that is, the last pair of capacitors in the capacitor array. The code value of the first candidate capacitor is used to switch the preset level of the lower plate of the upper capacitor in the first candidate capacitor, and the preset level of the lower plate of the lower capacitor remains unchanged, so that a pair of capacitors after switching (recorded as "third candidate capacitor") can be obtained.

[0120] In this way, by switching half of the last pair of capacitors, tail capacitor reuse is achieved. Because the capacitance of the last pair of capacitors = the capacitance of the second to last pair = C u , if the last pair of capacitors and the penultimate pair of capacitors are cut on both sides, then the weight is the same, that is, the weight of the last pair of capacitors needs to be 1 / 2 times the weight of the penultimate pair of capacitors. If you need to get a 4-bit code value, then you need 4 pairs of capacitors, and the last capacitor does not participate in the switching, which is convenient for binary calculation. The embodiment of the present invention uses the last bit as both a padding bit for convenient calculation and as the lowest bit capacitor at the same time. Because only half of the last pair of capacitors is switched, even if its value is the same as the value of the penultimate pair of capacitors, it has only half the weight. If you need to get a 4-bit code value, then set 3 pairs of capacitors, which can save half of the capacitors, because the highest bit capacitor is the largest, and only half of the traditional capacitor value is needed, which can greatly optimize the design, reduce the capacitance and thus reduce the area, and the smaller the capacitance, the faster the speed.

[0121] Step 104: Use the N-bit code value and the (N+1)th bit code value as the quantization result of the input signal.

[0122] After obtaining the code values ​​corresponding to the N pairs of capacitors in the capacitor array and the N+1th code value, the N-bit code value and the N+1th code value are combined to obtain the quantization result of the input signal.

[0123] For ease of understanding, Figure 4 Figure 2 shows the switching diagram of the capacitor array in the ADC in differential working mode. The ADC includes three pairs of capacitors, and the ratio of the three pairs of capacitors is 2:1:1. For an n-bit ADC, the required capacitors are C0 to C n-1 , C n-1 =2 n-1 C u (n>1), for example, the capacitance values ​​of the three pairs of capacitors are: C0=C u , C1=2 0 C u =C u , C2=2 1 C u =2C u , that is, C2:C1:C0=2C u :C u :C u =2:1:1. For digits above 3, follow C n-1 =2 n-1 C u (n>1) formula to calculate the capacitance value, where C u is the unit capacitance.

[0124] At the beginning of the comparison phase, the bottom plates of all capacitors are connected to V cm The comparator directly obtains the highest bit code value according to the input signal and then switches the lower plate voltage of C2 through digital control logic. If V p >V n , then the code value is 1, V p The lower plate of terminal C2 is connected to GND, V n The lower plate of terminal C2 is connected to V ref ; If V p <V n , then the code value is 0, V p The lower plate of terminal C2 is connected to V ref , V n The lower plate of terminal C2 is connected to GND.

[0125] Then the second comparison is performed, for V p The lower plate of terminal C2 is connected to GND, V n The lower plate of terminal C2 is connected to V ref , if V p >V n, then the code value is 1, V p The lower plate of C1 is connected to GND, V n The lower plate of terminal C1 is connected to V ref ; If V p <V n , then the code value is 0, V p The lower plate of terminal C1 is connected to V ref , V n The lower plate of terminal C1 is connected to GND.

[0126] For V p The lower plate of terminal C2 is connected to V ref , V n The lower plate of terminal C2 is connected to GND. If V p >V n , then the code value is 1, V p The lower plate of C1 is connected to GND, V n The lower plate of terminal C1 is connected to V ref ; If V p <V n , then the code value is 0, V p The lower plate of terminal C1 is connected to V ref , V n The lower plate of terminal C1 is connected to GND.

[0127] Then the third comparison is performed, for V p The lower plate of terminal C2 is connected to GND, V n The lower plate of terminal C2 is connected to V ref , V p The lower plate of C1 is connected to GND, V n The lower plate of terminal C1 is connected to V ref , if V p >V n , then the code value is 1, V p The lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C1 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref , V n The lower plate at terminal C1 remains unchanged.

[0128] For V p The lower plate of terminal C2 is connected to GND, V n The lower plate of terminal C2 is connected to V ref , V p The lower plate of terminal C1 is connected to V ref , V n The lower plate of C1 is connected to GND. If V p >V n , then the code value is 1, V pThe lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C1 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref , V n The lower plate at terminal C1 remains unchanged.

[0129] For V p The lower plate of terminal C2 is connected to V ref , V n The lower plate of terminal C2 is connected to GND, V p The lower plate of C1 is connected to GND, V n The lower plate of terminal C1 is connected to V ref , if V p >V n , then the code value is 1, V p The lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C1 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref , V n The lower plate at terminal C1 remains unchanged.

[0130] For V p The lower plate of terminal C2 is connected to V ref , V n The lower plate of terminal C2 is connected to GND, V p The lower plate of terminal C1 is connected to V ref , V n The lower plate of C1 is connected to GND. If V p >V n , then the code value is 1, V p The lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C1 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref , V n The lower plate at terminal C1 remains unchanged.

[0131] At this point, the work of a 3-bit SAR ADC in differential working mode is completed within one cycle.

[0132] Among them, step 1 is to disconnect the switch, because the connection with the input must be disconnected to maintain the input value sampled at that time. Otherwise, it will keep changing with the input and cannot be maintained. This step is very critical.

[0133] The first time is to Vip and V in , that is, V after the switch is turned off p and V n Direct comparison gets a result, which can be a sign bit, indicating V p >V n , but this comparison result will be needed for the subsequent capacitor switching strategy.

[0134] Furthermore, the weights of C2, C1, and C0 are different. For example, if C2 = 2pf, C1 = 1pf, and C0 = 1pf, then each time the capacitor is switched to high or low, the V p and V n The voltage changes are different.

[0135] Assume that the weight of C2 changing the voltage is 3.3 / 4, the weight of C1 changing the voltage is 3.3 / 8, the weight of C0 changing the voltage is 3.3 / 16, and V p =3.3, V n =0, after C2 is set, V p =3.3-3.3 / 4=3.3*3 / 4, V n =0+3.3 / 4=3.3 / 4, V p >V n , the comparison result is still 1, and this result is used as the basis for the next capacitor setting, and C1 is continued to be set, because V p Or>V n , we can only continue to set C1 and then use the weight of C1 to lower V again p , pull up V n , such as V p =3.3*3 / 4-3.3 / 8, V n =3.3 / 4+3.3 / 8, and so on.

[0136] Since the weight of the capacitor is different each time, the change of voltage caused by setting is also different. Cutting the capacitor to GND will lower V p Voltage, cut to V ref Will pull up V p Voltage.

[0137] For ease of understanding, Figure 5 The switching diagram of the capacitor array in the ADC in the single-ended working mode is shown. The ADC includes three pairs of capacitors, and the ratio of the three pairs of capacitors is 2:1:1.

[0138] Three switches are added based on the differential working mode: During the single-ended switching process, the switch between the two DACs is in the closed state, ensuring that the upper and lower DAC boards are connected to the same potential, and the comparator input port Vn Connect V cm .

[0139] At the beginning of the comparison phase, the bottom plates of all capacitors are connected to V cm , the comparator obtains the highest bit code value and switches the lower plate voltage of C2 through the digital control logic. If V p >V n , then the code value is 1, and the lower plate of C2 is connected to GND; if V p <V n , then the code value is 0, and the lower plate of C2 is connected to V ref .

[0140] Then make a second comparison, connect the lower plate of C2 to GND, if V p >V n , then the code value is 1, and the lower plate of C1 is connected to GND; if V p <V n , then the code value is 0, and the lower plate of C1 is connected to V ref .

[0141] Connect the lower plate of C2 to V ref , if V p >V n , then the code value is 1, and the lower plate of C1 is connected to GND; if V p <V n , then the code value is 0, and the lower plate of C1 is connected to V ref .

[0142] Then make a third comparison, with the lower plate of C2 connected to GND and the lower plate of C1 connected to GND. If V p >V n , then the code value is 1, V p The lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C0 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref , V n The lower plate at terminal C0 remains unchanged.

[0143] Connect the lower plate of C2 to GND and the lower plate of C1 to V ref , if V p >V n , then the code value is 1, V p The lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C0 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref, V n The lower plate at terminal C0 remains unchanged.

[0144] Connect the lower plate of C2 to V ref , C1 lower plate connected to GND, if V p >V n , then the code value is 1, V p The lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C0 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref , V n The lower plate at terminal C0 remains unchanged.

[0145] Connect the lower plate of C2 to V ref , C1 lower plate connected to V ref , if V p >V n , then the code value is 1, V p The lower plate of terminal C0 is connected to GND, V n The lower plate of terminal C0 remains unchanged; if V p <V n , then the code value is 0, V p The lower plate of terminal C0 is connected to V ref , V n The lower plate at terminal C0 remains unchanged.

[0146] At this point, the work of a 3-bit SAR ADC in single-ended working mode is completed within one cycle.

[0147] It should be noted that, whether in differential working mode or single-ended working mode, when switching levels, the switching can be performed according to the principle of charge conservation. p >V n , then connect the lower plate of the capacitor to GND, then the voltage of the upper plate of the corresponding capacitor will decrease according to the weight V p , if the reduced V p Still V p >V n , then the lower plate of the next capacitor is connected to GND, and V p , until V p <V n , then connect the lower plate to V ref , raise V according to the weight p And so on, until the comparison is completed.

[0148] Furthermore, by applying the embodiment of the present invention to a SAR ADC with 12-bit precision, the following pre-simulation data (Tables 1 and 2) and post-simulation data (Tables 3 and 4) can be obtained:

[0149]

[0150] Table 1

[0151]

[0152] Table 2

[0153]

[0154]

[0155] Table 3

[0156]

[0157] Table 4

[0158] Among them, the pre-simulation is based on the schematic diagram and the device characteristics provided by the PDK (Process Design Kit) manufacturer, and is performed with certain ideal excitation signals and simulation settings. The post-simulation is based on the pre-simulation, and parasitic parameters are extracted according to the layout. For example, some parasitic capacitance and parasitic resistance are generated due to the position and size of the layout and wiring. These parasitic parameters are added to the simulation environment. The post-simulation may introduce more capacitance and resistance to produce delays, IRdrop or filtering effects, which may slightly change some behavioral characteristics of the circuit. The post-simulation is closer to the actual results.

[0159] Since the higher the ENOB, the better, it mainly measures the signal-to-noise ratio, which indicates the ratio of signal to noise. The larger the better, the better. Therefore, by comparing the pre-simulation-differential with the pre-simulation-single-ended, and the post-simulation-differential with the post-simulation-single-ended, it can be seen that the results of the single-ended and differential modes are relatively close. If tail capacitor reuse is used, the single-ended result will be about 1dB lower than the differential result.

[0160] In an embodiment of the present invention, in response to a quantization instruction for an input signal, the lower plates of N pairs of capacitors are reset to a preset level, and the type of the input signal is determined; the working mode of the ADC is determined based on the type of the input signal; the code values ​​of N pairs of capacitors are determined in the working mode to obtain N-bit code values, and the N+1-bit code value is determined based on the N-bit code value; the N-bit code value and the N+1-bit code value are used as the quantization result of the input signal. In the above manner, the differential working mode of the ADC can be combined with the single-ended working mode, and in the single-ended working mode, the idle capacitors can be reused, avoiding the problem of a 1-bit decrease in the effective number of bits in the single-ended working mode, and effectively ensuring the accuracy of the ADC.

[0161] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0162] Reference Figure 6 , shows a structural block diagram of an embodiment of a quantization device for an input signal of the present invention, which is applied to an analog-to-digital conversion ADC, wherein the ADC includes a digital-to-analog conversion DAC capacitor array, wherein the DAC capacitor array includes N pairs of capacitors, where N is a positive integer; and specifically includes the following modules:

[0163] A first processing module 601, configured to reset the lower plates of the N pairs of capacitors to a preset level in response to a quantization instruction for an input signal, and determine a type of the input signal;

[0164] A first determination module 602, configured to determine an operating mode of the ADC based on a type of the input signal;

[0165] A second determination module 603 is used to determine the code values ​​of N pairs of capacitors in the working mode, obtain N-bit code values, and determine the N+1-th bit code value based on the N-th bit code value;

[0166] The second processing module 604 is configured to use the N-bit code value and the (N+1)th bit code value as a quantization result of the input signal.

[0167] In the embodiment of the present invention, the first determining module is specifically configured to:

[0168] If the type of the input signal is a differential signal, setting the ADC to a differential working mode;

[0169] If the type of the input signal is a single-ended signal, the ADC is set to a single-ended working mode.

[0170] In this embodiment of the present invention, the second determining module includes:

[0171] a calculation submodule, configured to determine, in the working mode, a code value of a first pair of capacitors among the N pairs of capacitors based on the input signal;

[0172] A switching submodule, configured to switch the preset level of the lower plate of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors;

[0173] The calculation submodule is further used to determine the code values ​​of the second pair of capacitors to the Nth pair of capacitors in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching, so as to obtain an N-bit code value;

[0174] The calculation submodule is further used to determine the N+1th code value based on the Nth code value.

[0175] In an embodiment of the present invention, each pair of capacitors in the N pairs of capacitors includes an upper capacitor and a lower capacitor;

[0176] The computing submodule is specifically used for:

[0177] In the working mode, the voltage of the input upper capacitor and the voltage of the input lower capacitor in the input signal are compared to obtain a code value of the first pair of capacitors;

[0178] The switching submodule is specifically used for:

[0179] Based on the code value of the first pair of capacitors, the preset level of the lower plate of the upper capacitor in the first pair of capacitors is switched, and the preset level of the lower plate of the lower capacitor in the first pair of capacitors is switched to obtain the switched first pair of capacitors; wherein the levels of the two lower plates in the switched first pair of capacitors are ground or a reference high level, and the levels of the two lower plates are different.

[0180] In the embodiment of the present invention, the computing submodule is further configured to:

[0181] S1, taking the first pair of capacitors after switching as the capacitors to be processed;

[0182] S2, using the weight of the capacitor to be processed to calculate the current voltage of the upper capacitor and the current voltage of the lower capacitor in the capacitor to be processed;

[0183] S3, comparing the current voltage of the upper capacitor with the current voltage of the lower capacitor to determine the code value of the candidate capacitor; the candidate capacitor is the next pair of capacitors of the capacitor to be processed;

[0184] S4, detecting whether the candidate capacitor is the Nth pair of capacitors, if not, executing S5, if yes, executing S7;

[0185] S5, using the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor, and switching the preset level of the lower plate of the lower capacitor in the candidate capacitor to obtain a first candidate capacitor after switching, and executing S6;

[0186] S6, taking the first candidate capacitor as the capacitor to be processed, and executing S2;

[0187] S7. Use the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor to obtain a second candidate capacitor after switching, and an N-bit code value.

[0188] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0189] An embodiment of the present invention further provides an electronic device, including:

[0190] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, each process of the above-mentioned input signal quantization method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0191] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned input signal quantization method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0192] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0193] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0194] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0195] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0196] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0197] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0198] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0199] The above is a detailed introduction to a quantization method for an input signal and a quantization device for an input signal provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for quantizing an input signal, characterized in that: Applied in an analog-to-digital conversion ADC, the ADC includes a digital-to-analog conversion DAC capacitor array, the DAC capacitor array includes N pairs of capacitors, N is a positive integer; the method includes: In response to a quantization instruction for an input signal, resetting the lower plates of the N pairs of capacitors to a preset level, and determining the type of the input signal; determining an operating mode of the ADC based on the type of the input signal; Determine the code values ​​of N pairs of capacitors in the working mode to obtain N-bit code values, and determine the N+1-th bit code value based on the N-th bit code value; The N-bit code value and the N+1-th bit code value are used as quantization results of the input signal.

2. The method for quantizing an input signal according to claim 1, characterized in that: The determining the operating mode of the ADC based on the type of the input signal comprises: If the type of the input signal is a differential signal, setting the ADC to a differential working mode; If the type of the input signal is a single-ended signal, the ADC is set to a single-ended working mode.

3. The method for quantizing an input signal according to claim 1, characterized in that: Determining the code values ​​of N pairs of capacitors in the working mode to obtain N-bit code values, and determining the N+1-bit code value based on the N-bit code value, includes: In the working mode, determining the code value of a first pair of capacitors among the N pairs of capacitors based on the input signal, and switching the preset level of the lower plates of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors; Determine the code values ​​of the second pair of capacitors to the Nth pair of capacitors in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching, and obtain an N-bit code value; The N+1th bit code value is determined based on the Nth bit code value.

4. The method for quantizing an input signal according to claim 3, characterized in that: Each of the N pairs of capacitors includes an upper capacitor and a lower capacitor; The method of determining the code value of the first pair of capacitors among the N pairs of capacitors based on the input signal in the working mode, and switching the preset level of the lower plate of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors includes: In the working mode, the voltage of the input upper capacitor and the voltage of the input lower capacitor in the input signal are compared to obtain a code value of the first pair of capacitors; Based on the code value of the first pair of capacitors, the preset level of the lower plate of the upper capacitor in the first pair of capacitors is switched, and the preset level of the lower plate of the lower capacitor in the first pair of capacitors is switched to obtain the switched first pair of capacitors; wherein the levels of the two lower plates in the switched first pair of capacitors are ground or a reference high level, and the levels of the two lower plates are different.

5. The method for quantizing an input signal according to claim 3, characterized in that: The step of sequentially determining the code values ​​of the second pair of capacitors to the Nth pair of capacitors based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching to obtain the N-bit code value includes: S1, taking the first pair of capacitors after switching as the capacitors to be processed; S2, using the weight of the capacitor to be processed to calculate the current voltage of the upper capacitor and the current voltage of the lower capacitor in the capacitor to be processed; S3, comparing the current voltage of the upper capacitor with the current voltage of the lower capacitor to determine the code value of the candidate capacitor; the candidate capacitor is the next pair of capacitors of the capacitor to be processed; S4, detecting whether the candidate capacitor is the Nth pair of capacitors, if not, executing S5, if yes, executing S7; S5, using the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor, and switching the preset level of the lower plate of the lower capacitor in the candidate capacitor to obtain a first candidate capacitor after switching, and executing S6; S6, taking the first candidate capacitor as the capacitor to be processed, and executing S2; S7. Use the code value of the candidate capacitor to switch the preset level of the lower plate of the upper capacitor in the candidate capacitor to obtain a second candidate capacitor after switching, and an N-bit code value.

6. A quantization device for an input signal, characterized in that: Applied in analog-to-digital conversion ADC, the ADC includes a digital-to-analog conversion DAC capacitor array, the DAC capacitor array includes N pairs of capacitors, N is a positive integer; the device includes: A first processing module, configured to reset the lower plates of the N pairs of capacitors to a preset level in response to a quantization instruction for an input signal, and determine a type of the input signal; A first determination module, configured to determine an operating mode of the ADC based on a type of the input signal; A second determination module is used to determine the code values ​​of N pairs of capacitors in the working mode, obtain N-bit code values, and determine the N+1-th bit code value based on the N-th bit code value; The second processing module is used to use the N-bit code value and the N+1-th bit code value as the quantization result of the input signal.

7. The input signal quantization device according to claim 6, characterized in that: The first determining module is specifically configured to: If the type of the input signal is a differential signal, setting the ADC to a differential working mode; If the type of the input signal is a single-ended signal, the ADC is set to a single-ended working mode.

8. The input signal quantization device according to claim 6, characterized in that: The second determining module includes: a calculation submodule, configured to determine, in the working mode, a code value of a first pair of capacitors among the N pairs of capacitors based on the input signal; A switching submodule, configured to switch the preset level of the lower plate of the first pair of capacitors based on the code value of the first pair of capacitors to obtain the switched first pair of capacitors; The calculation submodule is further used to determine the code values ​​of the second pair of capacitors to the Nth pair of capacitors in sequence based on the weights of the first pair of capacitors and the Nth pair of capacitors after switching, so as to obtain an N-bit code value; The calculation submodule is further used to determine the N+1th code value based on the Nth code value.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the input signal quantization method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the input signal quantization method according to any one of claims 1 to 5 are implemented.

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