Storage device

Abstract

A storage device having a novel structure is provided. The first transistor includes a first oxide semiconductor layer, first to fourth conductive layers, and first and second insulating layers. The second transistor includes a second oxide semiconductor layer, first, fifth, sixth and seventh conductive layers, and third and fourth insulating layers. The first oxide semiconductor layer has a region facing the first conductive layer with the first insulating layer interposed therebetween and a region facing the second conductive layer with the second insulating layer interposed therebetween when viewed from a plane. The second oxide semiconductor layer has a region facing the fifth conductive layer via the third insulating layer and a region facing the sixth conductive layer via the fourth insulating layer when viewed in plane. The first oxide semiconductor layer is provided so as to be in contact with the third and fourth conductive layers. The second oxide semiconductor layer is provided so as to be in contact with the first and seventh conductive layers. The third conductive layer has a region overlapping the first, second, fourth, fifth, sixth, and seventh conductive layers in a cross-sectional view.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and the like.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition of matter.

[0003] In this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, circuits including semiconductor elements, etc. are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, camera devices, communication devices, electronic devices, etc. sometimes include semiconductor elements and / or semiconductor circuits. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, camera devices, communication devices, electronic devices, etc. are sometimes also referred to as semiconductor devices. Background Art

[0004] As semiconductor thin films that can be used in transistors, silicon-based semiconductor materials are widely known, and oxide semiconductors are attracting attention as other materials. It is known that when a transistor using an oxide semiconductor is in a non-conductive state (off state), a very small current flows.

[0005] For example, Patent Document 1 discloses a memory device that realizes long-term retention of stored content by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] In recent years, as electronic devices have become smaller and lighter, there has been an increasing demand for further densification of memory cells included in memory devices. For example, Patent Document 2 discloses a technology in which the density of memory cells is increased by stacking a plurality of element layers including vertical transistors using oxide semiconductor films.

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2012-256831 [Patent Document 2] International Patent Application Publication No. 2022 / 160885 Summary of the invention

[0008] As described in Patent Documents 1 and 2, a structure in which a plurality of element layers including a memory cell are stacked can increase the density of the memory cell. However, as the density of the memory cell increases, the spacing of the wiring connected to the transistor becomes narrower, which may cause the influence of the parasitic capacitance to become greater. Therefore, it may be difficult to control the conduction state (also referred to as the on state or on) or the non-conduction state (also referred to as the off state or off) of the transistor, and it may be difficult to maintain the storage content in the memory cell for a long time.

[0009] One object of one embodiment of the present invention is to provide a storage device having a novel structure. Another object of one embodiment of the present invention is to provide a storage device that is excellent in terms of reducing power consumption, increasing operating speed, miniaturization, or increasing storage capacity.

[0010] Note that the recording of these purposes does not prevent the existence of other purposes. Note that one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes can be clearly seen from the description of the specification, drawings, claims, etc., and can be extracted from these descriptions.

[0011] One embodiment of the present invention is a memory device including a memory cell including a first transistor and a second transistor, the first transistor including a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer, the second transistor including a second oxide semiconductor layer, a first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer, the first oxide semiconductor layer having a region opposite to the first conductive layer via the first insulating layer and a region opposite to the second conductive layer via the second insulating layer when viewed from a plane, the second oxide semiconductor layer having a region opposite to the fifth conductive layer via the third insulating layer and a region opposite to the sixth conductive layer via the fourth insulating layer when viewed from a plane, The first oxide semiconductor layer is provided in contact with the third conductive layer and the fourth conductive layer, the second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer, the third conductive layer has a region overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer and the seventh conductive layer when viewed from a cross section, a first potential supplied to the second conductive layer during a period of writing data to a memory cell is higher than a second potential supplied to the second conductive layer during a period of retaining data in the memory cell, a third potential supplied to the sixth conductive layer during a period of reading data from the memory cell is higher than a fourth potential supplied to the sixth conductive layer during a period of retaining data in the memory cell, the third potential is lower than the first potential, and the fourth potential is lower than the second potential.

[0012] In the memory device according to one embodiment of the present invention, preferably, the memory cell includes a capacitor, and one electrode of the capacitor is electrically connected to the first conductive layer.

[0013] In the storage device according to one embodiment of the present invention, it is preferable that the other electrode of the capacitor is electrically connected to the sixth conductive layer.

[0014] In the storage device according to one embodiment of the present invention, preferably, the first insulating layer or the second insulating layer includes hafnium, zirconium, and oxygen.

[0015] In the memory device according to one embodiment of the present invention, preferably, both the first oxide semiconductor layer and the second oxide semiconductor layer include at least indium.

[0016] Note that other aspects of the present invention are described in the description and drawings of the embodiment modes described below.

[0017] One embodiment of the present invention can provide a storage device having a novel structure. Another embodiment of the present invention can provide a storage device that is excellent in terms of reduced power consumption, increased operating speed, miniaturization, or increased storage capacity.

[0018] Note that the description of these effects does not prevent the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A is the circuit diagram of the storage unit, Figure 1B It is the timing diagram of the storage unit; Figure 2A is a schematic diagram illustrating the voltage in a memory cell, Figure 2B and Figure 2C is the circuit diagram of a storage unit; Figure 3A is a cross-sectional view of a transistor, Figure 3B is a plan view of a transistor; Figure 4A is a cross-sectional view of a transistor, Figure 4B It is the circuit diagram of a transistor; FIG. 5A to FIG. 5C is the circuit diagram of a storage unit; FIG. 6A to FIG. 6C is the circuit diagram of a storage unit; Figure 7 It is the timing diagram of the storage unit; Fig. 8A and Figure 8B is the circuit diagram of a storage unit; Fig.9A is a schematic diagram of the memory array, Fig. 9B is a schematic diagram of a storage unit; Fig. 10A and Fig. 10B is the plan view of the transistor, Fig. 10C and Fig. 10D is a cross-sectional view of a transistor; FIG. 11A to FIG. 11D is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention; FIG. 12A to FIG. 12D is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention; Fig.13A is a block diagram illustrating a structural example of a semiconductor device. Fig. 13B and Fig. 13C is a perspective view illustrating a structural example of a semiconductor device; Fig.14A is a block diagram illustrating a structural example of a cell array, Fig. 14B is the circuit diagram of a storage unit; Fig.15A is a block diagram illustrating a structural example of a cell array, Fig. 15B is the circuit diagram of a storage unit; Fig.16 is a diagram showing various storage devices in a hierarchical manner; FIG. 17A to FIG. 17E is a diagram illustrating an application example of a storage device; 18A to 18H is a diagram showing an electronic device. DETAILED DESCRIPTION

[0020] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the method and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that in the inventive structure described below, the same figure mark is used in different drawings to represent the same part or the part with the same function, and repeated description is omitted.

[0021] In addition, in this specification, etc., a high power supply potential VDD (hereinafter, referred to as "VDD", "H potential" or "H") refers to a power supply potential higher than a low power supply potential VSS (hereinafter, referred to as "VSS", "L potential" or "L"). In addition, VSS refers to a power supply potential lower than VDD.

[0022] In addition, unless otherwise stated, the transistors shown in this specification and the like are enhancement type (normally closed) n-channel field effect transistors. Therefore, their threshold voltage (also referred to as "Vth") is greater than 0V. In addition, unless otherwise stated, sometimes "supplying an H potential to the gate of a transistor" is synonymous with "putting the transistor in an on state". In addition, unless otherwise stated, sometimes "supplying an L potential to the gate of a transistor" is synonymous with "putting the transistor in an off state".

[0023] In addition, in the drawings, in order to facilitate understanding of the potential of wiring, electrodes, etc., "H" indicating H potential or "L" indicating L potential may be added to a position adjacent to wiring, electrodes, etc. Also, "H" or "L" may be added to wiring, electrodes, etc. whose potential changes in some cases in a frame. Also, when a transistor is in an off state, a symbol "×" may be added to the transistor in an overlapping manner.

[0024] In addition, in this specification, when the same symbol is used to represent multiple components, especially when it is necessary to distinguish them, the symbol may be added with a symbol for identification such as "_1", "_2", "[n]", "[m, n]". For example, the second wiring GL may be recorded as wiring GL[2].

[0025] Implementation Method 1 A storage device according to one embodiment of the present invention will be described. In this embodiment, a configuration example of a memory cell included in a storage device according to one embodiment of the present invention will be described with reference to the drawings.

[0026] Figure 1A An example of a circuit diagram of a memory cell of a memory device according to one embodiment of the present invention is shown. Figure 1A Memory cells 10_1 to 10_3 are shown as an example of memory cells. Each of the memory cells 10_1 to 10_3 includes transistors VT1 and VT2.

[0027] The memory cells 10_1 to 10_3 are all connected to the wiring WBL, the wiring SL, and the wiring RBL. The memory cell 10_1 is connected to the wiring WWL1, the wiring BGL1, and the wiring RWL1. The memory cell 10_2 is connected to the wiring WWL2, the wiring BGL2, and the wiring RWL2. The memory cell 10_3 is connected to the wiring WWL3, the wiring BGL3, and the wiring RWL3.

[0028] The memory cells 10_1 to 10_3 can write data by supplying charges corresponding to data to the nodes FN1 to FN3 by controlling the on state or off state of the transistor VT2. The wiring WBL is a wiring for transmitting the data (write data) written to the memory cells 10_1 to 10_3. The wirings WWL1 to WWL3 are used as wiring for transmitting word signals (write word signals) for controlling the write timing of the data held in the memory cells 10_1 to 10_3. Specifically, by turning on the transistor VT2, the data held in the memory cells 10_1 to 10_3 can be written. The charges corresponding to the data written to the memory cells 10_1 to 10_3 can be held at the nodes FN1 to FN3 by turning off the transistor VT2. The wirings BGL1 to BGL3 are used as wiring for transmitting control signals for controlling the electrical characteristics of the transistor VT2, such as the threshold voltage. The transistor VT2 is used as a transistor for data writing and a transistor for data holding.

[0029] The memory cells 10_1 to 10_3 can read data based on the difference in the amount of current flowing through the transistor VT1 that changes in accordance with the potential of the nodes FN1 to FN3. The wiring RBL is a wiring that transmits the data (read data) read from the memory cells 10_1 to 10_3. The wiring SL is a wiring for allowing a current corresponding to the charge written between the source and the drain of the transistor VT1 to flow between the wiring SL and the wiring RBL. The wirings RWL1 to RWL3 are used as wirings for transmitting a word signal (read word signal) that controls the read timing of the data held in the memory cells 10_1 to 10_3. Specifically, by setting the potential of the wiring RWL to an L level and drifting the threshold voltage of the transistor VT1 to the positive side, no current flows through the transistor VT1 regardless of the potential of the nodes FN1 to FN3. In addition, by drifting the threshold voltage of the transistor VT1 to near 0, the amount of current flowing through the transistor VT1 changes in accordance with the potential of the nodes FN1 to FN3. The transistor VT1 is used as a transistor for data reading.

[0030] Wiring WWL is sometimes referred to as a write word line. Wiring RWL is sometimes referred to as a read word line. Wiring WBL is sometimes referred to as a write bit line. Wiring RBL is sometimes referred to as a read bit line. Wiring SL is sometimes referred to as a source line.

[0031] Transistors VT1 and VT2 are transistors (OS transistors) including oxide semiconductors in the channel formation region. A memory including a memory cell having an OS transistor is sometimes referred to as an "OS memory". Examples of oxide semiconductors used for OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). An element layer including OS transistors can be stacked on an element layer including Si transistors. Therefore, the transistor density per unit area can be increased.

[0032] In addition, the off-state current of the OS transistor is extremely small. Therefore, the charge corresponding to the data written to the memory cell 10 can be retained for a long time. Figure 1A In the memory cell 10_1 shown, when the transistor VT2 is turned off, the charge corresponding to the data written by the transistor VT2 can be retained for a long time at the node FN1 connected to the gate of the transistor VT1. Figure 1A In the memory cell 10_2 or 10_3 shown, the charge corresponding to the data written by the transistor VT2 can be retained for a long time at the node FN2 or the node FN3. Therefore, the data refresh frequency can be reduced, and the power consumption of the memory device of one embodiment of the present invention can be reduced.

[0033] That is, the memory device provided with the memory cells 10_1 to 10_3 including the OS transistors may be a NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory). Figure 1A In the structure of the memory cells 10_1 to 10_3 shown, each memory cell is a two-transistor (2T) type NOSRAM. NOSRAM rewrites data by charging and discharging electric charges, so there is no limit on the number of rewrites in principle, and the energy consumption is low. In addition, when NOSRAM includes a data read transistor, the signal supply capacity of the data read through the wiring RBL is high, so it is a memory that can operate at high speed, has low power consumption and high rewrite resistance. In addition, NOSRAM can read the written data non-destructively, so it is suitable for long-term data retention.

[0034] In addition, the OS transistor has electrical characteristics superior to those of the Si transistor in a high temperature environment. Specifically, the ratio of the on-state current to the off-state current of the OS transistor is large even at high temperatures of 125°C to 150°C, so good switching operation can be performed. In addition, the OS transistor works well in the range of -40°C to 190°C. In other words, the heat resistance of the OS transistor is very good. Compared with the heat resistance of the phase change memory (PCM: Phase Change Memory) (-40°C to 150°C), the heat resistance of the variable resistance random access memory (ReRAM: Resistance Random Access Memory) (-40°C to 125°C), and the heat resistance of the magnetoresistive random access memory (MRAM: Magnetoresistive Random Access Memory) (-40°C to 105°C), the OS transistor has high heat resistance.

[0035] Can be constructed Figure 1A The transistors VT1 and VT2 included in the memory cells 10_1 to 10_3 of the 2T-type NOSRAM shown are vertical transistors in which the heights of the source electrode and the drain electrode relative to the substrate or the like are different from each other. In a vertical transistor, current flows in the height direction (Z direction) of the channel formation region of the semiconductor layer. In other words, it can be said that the channel length direction includes a component in the height direction (vertical direction). Therefore, the vertical transistor may also be referred to as a VFET (Vertical Field Effect Transistor: vertical field effect transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.

[0036] Compared to a lateral transistor (also called a planar structure or a planar type) in which the source electrode and the drain electrode are located at the same height, a vertical transistor has a structure in which at least a portion of the source region, the channel formation region, and the drain region can overlap when viewed from above, so that the occupied area (also called the footprint) can be reduced. In addition, since it has a structure that can reduce the channel length and increase the channel width, the on-state resistance can be reduced (the on-state current can be increased).

[0037] Next, refer to Figure 1B by Figure 1A The operation of the storage device according to one embodiment of the present invention will be described using the storage cells 10_1 to 10_3 as examples. Figure 1B It is a timing chart showing the temporal change in the potential of a signal (data, control signal, word signal, etc.) input to each wiring (WWL_1 to WWL_3, BGL_1 to BGL_3, WBL, RWL_1 to RWL_3, RBL, SL). Figure 1B The operations during data writing (period T10 ), data retention (period T20 ), and data reading (period T30 ) are shown.

[0038] Note that the period T10 includes a period T11 during which data is written to the memory cell 10_1, a period T12 during which data is written to the memory cell 10_2, and a period T13 during which data is written to the memory cell 10_3. In addition, the period T30 includes a period T31 during which data is read from the memory cell 10_1, a period T32 during which data is read from the memory cell 10_2, and a period T33 during which data is read from the memory cell 10_3.

[0039] exist Figure 1A In the memory cell 10_1 shown, a control signal is supplied to the wiring BGL1, data is supplied to the wiring WBL, and a word signal is supplied to the wiring WWL1, thereby data can be written to the memory cell 10_1. In addition, a word signal is supplied to the wiring RWL1, and a precharge potential for reading data is supplied to the wiring RBL, so that data held by the memory cell 10_1 can be read. By controlling the signals supplied to each wiring, information can be read from any memory cell 10_1 to 10_3 and information can be written to any memory cell 10_1 to 10_3. Therefore, the memory device including the memory cells 10_1 to 10_3 can be used as a NOR type memory device.

[0040] In period T11 of period T10, data D1 is written to memory cell 10_1. Wiring WWL1 is set to H level and wiring BGL1 is set to H level. In memory cell 10_1, transistor VT2 can be turned on while the threshold voltage of transistor VT2 is shifted to the negative direction. Therefore, the amount of current flowing through transistor VT2 in memory cell 10_1 can be increased. As a result, the potential change of node FN1 of memory cell 10_1 can be steep and data can be written at high speed.

[0041] Similarly, in the periods T12 and T13 of the period T10, the data D2 and D3 are written into the memory cells 10_2 and 10_3, respectively. In the memory cells 10_2 and 10_3, the transistor VT2 can be turned on while the threshold voltage of the transistor VT2 is shifted in the negative direction. Therefore, the amount of current flowing through the transistor VT2 in each of the memory cells 10_2 and 10_3 can be increased. As a result, the potential changes of the node FN2 of the memory cell 10_2 and the node FN3 of the memory cell 10_3 can be steep.

[0042] In the period T20, the data D1 to D3 are retained in the memory cells 10_1 to 10_3. The wirings WWL1 to WWL3 are set to the L level and the wirings BGL1 to BGL3 are set to the L level. In the memory cells 10_1 to 10_3, the transistor VT2 can be turned off while the threshold voltage of the transistor VT2 is shifted in the positive direction. Therefore, the amount of current flowing through the transistor VT2 in each of the memory cells 10_1 to 10_3 can be made extremely small. As a result, the potential variation of the nodes FN1 to FN3 included in the memory cells 10_1 to 10_3 can be made extremely small for a long time.

[0043] Note that the wirings RWL1 to RWL3 are set to L level in the periods T10 and T20. The threshold voltage of the transistor VT2 in the memory cells 10_1 to 10_3 greatly drifts in the positive direction. In this state, the transistor VT1 can reduce the amount of current flowing between the source and the drain regardless of the potential of the nodes FN1 to FN3. As a result, even in the state where data is written to the memory cells 10_1 to 10_3, that is, when the potential of the nodes FN1 to FN3 is high, the transistor VT can be maintained in the off state.

[0044] In a period T31 of the period T30, data D1 is read from the memory cell 10_1. The wiring RWL1 is set to the H level and the wiring RBL is set to the potential V for precharging. PRE In the memory cell 10_1, the threshold voltage of the transistor VT1 can drift to near 0 V. According to the potential maintained at the node FN1, a current can flow between the source and the drain of the transistor VT1. Therefore, the memory cell 10_1 can change the potential of the wiring RBL according to the amount of current flowing through the transistor VT1, thereby reading the data D1.

[0045] Similarly, in the periods T32 and T33 of the period T30, data D2 and D3 are read from the memory cells 10_2 and 10_3, respectively. In the memory cells 10_2 and 10_3, the wirings RWL2 and RWL3 are set to the H level in sequence. The threshold voltage of the transistor VT1 can drift to near 0V. According to the potential maintained at the nodes FN2 and FN3, a current can flow between the source and the drain of the transistor VT1. Therefore, the memory cells 10_2 and 10_3 can change the potential of the wiring RBL according to the amount of current flowing through the transistor VT1, thereby reading the data D2 and D3.

[0046] Note that Figure 1B In FIG. 1 , regarding the signals of wirings BGL_1 to BGL_3, the potential of the H level is denoted as V1, and the potential of the L level is denoted as V2. Figure 1B, regarding the signals of the wirings RWL_1 to RWL_3, the potential of the H level is recorded as V3, and the potential of the L level is recorded as V4. In addition, regarding the potential of the wiring SL, a potential V5 of the same level as the potential V3 is shown. Note that by setting the potential V5 to be higher than the potential V4 and lower than the potential V3, a current can be made to flow through the transistor VT2 at a predetermined timing.

[0047] Figure 2A 1 is a schematic diagram illustrating the relationship between the voltages of the potentials V1 to V5 in the memory cells 10_1 to 10_3. Figure 2A As shown, the potential V1 supplied to the wiring BGL (wirings BGL_1 to BGL_3) is higher than the potential V2. That is, in the memory cells 10_1 to 10_3, the potential V1 supplied to the wiring BGL during data writing is higher than the potential V2 supplied to the wiring BGL during data retention.

[0048] In addition, if Figure 2A As shown, the potential V3 supplied to the wiring RWL (wirings RWL_1 to RWL_3) is higher than the potential V4. That is, in the memory cells 10_1 to 10_3, the potential V3 supplied to the wiring RWL during the data readout period is higher than the potential V4 supplied to the wiring RWL during the data retention period.

[0049] In addition, if Figure 2A As shown, the potential V3 is lower than the potential V1, and the potential V4 is lower than the potential V2. That is, the potential V3 supplied to the wiring RWL during the period of reading data is lower than the potential V1 supplied to the wiring BGL during the period of writing data. In addition, the potential V4 supplied to the wiring RWL during the period of retaining data is lower than the potential V2 supplied to the wiring BGL during the period of retaining data.

[0050] like Figure 2A As shown, the potentials of the control signal for controlling the electrical characteristics of transistor VT1, the control signal for controlling the electrical characteristics of transistor VT2, and the word signal for controlling the read timing of data supplied to transistor VT2 are made different from each other, thereby enabling the electrical characteristics of transistor VT1 and transistor VT2 to be controlled corresponding to the data writing period, the data retention period, and the data reading period.

[0051] Specifically, for example, during the data writing period, the potential of each wiring is as follows: Figure 2B The potential shown. Figure 2B In the example, the potential V supplied to the wiring corresponding to the wiring WBL DW represents the data potential written to the memory cell 10. The potential V1 as a control signal is supplied to the transistor VT2. When the wiring WWL is set to H level, a voltage corresponding to the potential V flows through the transistor VT2. DW The current IVT2 .

[0052] On the other hand, Figure 2B During the data writing period shown in FIG. 1 , the potential V4 as the word signal is supplied to the transistor VT1. Therefore, the threshold voltage of the transistor VT1 can be greatly shifted in the positive direction. D In any case, the transistor VT1 can be turned off (cross in the figure). As a result, the amount of current flowing through the memory cell 10 can be minimized during the data writing and holding periods.

[0053] In addition, during the data readout period, the potential of each wiring is as follows: Figure 2C The potential shown. Figure 2C In the example, the potential V supplied to the wiring corresponding to the wiring RBL PRE = represents a precharge potential for reading data from the memory cell 10. A potential V3 as a word signal is supplied to the transistor VT1. A data potential V corresponding to the node FN D The current I VT1 flows through transistor VT1. When the data potential V D is the current I at H potential VT1 The current is large, and when the data potential V D is the current I at L potential VT1 The potential V of wiring RBL is small. PRE Corresponding to the current I VT1 The data potential V can be read by changing the current DR .

[0054] On the other hand, Figure 2C During the data readout period shown in FIG. 1 , the potential V2 as a control signal is supplied to the transistor VT2. In addition, the potential V2 is lower than the potential V1. Therefore, the threshold voltage of the transistor VT1 can drift in the negative direction. Even if the potential of the wiring WWL at the L level changes, the transistor VT2 can be turned off (the cross in the figure). As a result, the change amount of the potential of the node FN can be made extremely small during the data retention period and the readout period.

[0055] FIG. 2A to FIG. 2CThe structure described is particularly effective for a structure in which both the transistors VT1 and VT2 are vertical transistors and the transistors VT1 and VT2 are overlapped. In the case of overlapping vertical transistors VT1 and VT2, as the density of the memory cell increases, the spacing of the wiring connected to the transistor becomes narrower, thereby increasing the influence of the parasitic capacitance. Therefore, it may be difficult to control the on state or off state of the transistor, and it may be difficult to maintain the storage content in the memory cell for a long time, or it may cause the power consumption to increase due to the current flowing through the memory cell during the period other than the read period of the data potential being maintained.

[0056] In one embodiment of the present invention, a structure is adopted in which a potential for controlling the electrical characteristics of the transistor, specifically a potential for controlling the threshold voltage, is supplied to a conductive layer used as a first gate electrode or a second gate electrode of a vertical transistor. By adopting this structure, different potentials can be supplied to each transistor in response to a write operation, a hold operation, or a read operation to control the electrical characteristics of the transistor. By adopting this structure, a storage device excellent in reducing power consumption, increasing operating speed, miniaturization, or increasing storage capacity can be provided.

[0057] Note that the first gate electrode of the vertical transistor is an electrode to which a signal for controlling the on state or off state of the transistor is supplied. In addition, the second gate electrode of the vertical transistor is an electrode to which a potential for controlling the threshold voltage of the transistor is supplied. The threshold voltage of the transistor can be controlled to drift toward the positive side by applying a negative potential to the second gate electrode, thereby reducing the off-state current. In addition, the threshold voltage of the transistor can be controlled to drift toward the negative side by applying a positive potential to the second gate electrode, thereby increasing the on-state current.

[0058] For example, in Figure 1A In the transistor VT2, the electrode connected to the wiring WWL may be the first gate electrode, and the electrode connected to the wiring BGL may be the second gate electrode. Note that in the above example, by swapping the connection of the wiring WWL and the wiring BGL, the electrode used as the first gate electrode and the electrode used as the second gate electrode can be swapped. The first gate electrode is sometimes referred to as the gate electrode. The second gate electrode is sometimes referred to as the back gate electrode.

[0059] Next, the Figure 1A The transistors VT1 and VT2 shown in the figure are described as an example of a structure of a vertical transistor. Figure 3A A cross-sectional view of a transistor VT which can be used for transistors VT1 and VT2 is shown, Figure 3B Shown along Figure 3A The plan view of the line X1-X2.

[0060] Arrows indicating the X direction, Y direction, and Z direction are sometimes attached to the drawings and the like to be described below. The X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification and the like, one of the X direction, Y direction, and Z direction is sometimes referred to as the "first direction". In addition, one of the other two directions is sometimes referred to as the "second direction". In addition, the remaining one is sometimes referred to as the "third direction". In addition, the direction parallel to the XY plane is referred to as the horizontal direction, and the direction perpendicular to the XY plane is referred to as the vertical direction.

[0061] also, Figure 4A Show Figure 3A The cross-sectional view shown is attached with Figure 4B The cross-sectional view of the terminals corresponding to the circuit symbols of transistors VT1 and VT2 shown in FIG. Figure 4A , Figure 4B As shown, the conductive layer 110 is used as one of the source and the drain (lower electrode BSD). The conductive layer 120 is used as either the first gate electrode or the second gate electrode (second gate electrode BGE). The conductive layer 130 is used as the other of the source and the drain (upper electrode TSD). The conductive layer 140 is used as either the other of the first gate electrode and the second gate electrode (first gate electrode TGE). Note that the first gate electrode is an electrode to which a signal that controls the on state or off state of the transistor is supplied.

[0062] exist Figure 3A In the embodiment, a conductive layer 110 is provided on a substrate (not shown). An insulating layer 181 is provided on the conductive layer 110. A conductive layer 120 is provided in the insulating layer 181. A conductive layer 130 is provided on the insulating layer 181. An opening 182 is provided in a region of the insulating layer 181 that overlaps with the conductive layer 110. An insulating layer 170 is provided in contact with a side surface of the opening 182. The oxide semiconductor layer 150 is in contact with a recess of the conductive layer 110, a side surface of the insulating layer 170, and a top surface of the conductive layer 130. The insulating layer 160 is located inside the oxide semiconductor layer 150 in the opening 182. The conductive layer 140 is located inside the insulating layer 160 in the opening 182. An insulating layer 183 is provided on the conductive layer 140 and the insulating layer 160.

[0063] Note that the XY plane corresponds to the surface on which the insulating layer or the like on which the conductive layer 110 is provided. The horizontal direction corresponds to a direction parallel to the surface on which the conductive layer 110 is formed. The Z direction corresponds to a direction perpendicular to the surface on which the conductive layer 110 is formed.

[0064] The channel length of the transistor VT is the distance between the source region and the drain region, specifically, the distance from the conductive layer 110 in contact with the oxide semiconductor layer 150 to the conductive layer 130 in contact with the oxide semiconductor layer 150. In other words, the channel length of the transistor VT can be set according to the thickness of the insulating layer 181 on the conductive layer 110.

[0065] In lateral transistors, the channel length is limited by the exposure limit of photolithography, but Figure 3A In the structure, the channel length can be set according to the thickness of the insulating layer 181. Therefore, a very fine structure can be realized in which the channel length of the transistor VT is below the exposure limit of the photolithography method. As a result, the on-state current of the transistor VT is increased, and the frequency characteristics can be improved. Therefore, a storage device with a fast operating speed can be provided.

[0066] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 182. Therefore, compared with a lateral transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane, the occupied area of ​​the transistor VT can be reduced. Thus, the memory device can be highly integrated, so that the memory capacity per unit area can be increased.

[0067] Notice, Figure 3A The conductive layer 110 shown has a recessed portion at a position overlapping the opening 182. When the conductive layer 110 has the recessed portion, the area in contact between the oxide semiconductor layer 150 and the conductive layer 110 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 150 and the conductive layer 110 can be reduced.

[0068] In addition, in the XY plane corresponding to the channel formation region including the oxide semiconductor layer 150, Figure 3B In the plan view shown, the conductive layer 140, the insulating layer 160, the oxide semiconductor layer 150 and the insulating layer 170 are arranged in a concentric circle shape. Therefore, the side of the conductive layer 140 arranged in the center is opposite to the side of the oxide semiconductor layer 150 via the insulating layer 160, and the side of the conductive layer 120 is opposite to the side of the oxide semiconductor layer 150 via the insulating layer 170. In other words, the periphery of the oxide semiconductor layer 150 as a whole can be in a shape surrounded by the conductive layer via the insulating layer when viewed from a plane. Therefore, by increasing the diameter of the opening 182, the area used as the channel formation area can be increased. As a result, by increasing the diameter of the opening 182, the channel width per unit area can be increased to increase the on-state current.

[0069] exist Figure 3BIn the structure, the insulating layer 170 is in contact with the outer surface of the oxide semiconductor layer 150. The conductive layer 120 surrounds the entire periphery of the oxide semiconductor layer 150 via the insulating layer 170. In addition, the insulating layer 160 is in contact with the inner surface of the oxide semiconductor layer 150. The oxide semiconductor layer 150 surrounds the entire periphery of the conductive layer 140 via the insulating layer 160. Therefore, the channel formation region of the transistor VT is formed on the entire surface of the oxide semiconductor layer 150 within the opening 182 (the entire region in contact with the insulating layers 160 and 170). As a result, the transistor VT of one embodiment of the present invention can simultaneously achieve a large on-state current and a normally-off characteristic.

[0070] In a channel formation region of a transistor including an oxide semiconductor layer, it is preferable that oxygen vacancies (V O ) or the impurity concentration of hydrogen, nitrogen, metal elements, etc. is low. In addition, hydrogen near the oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0071] In addition, the source region and the drain region of a transistor using an oxide semiconductor for a semiconductor layer are regions where there are more oxygen vacancies than in a channel formation region, and V O The resistance is reduced by increasing the carrier concentration when there is more H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0072] The band gap of the oxide semiconductor is preferably greater than 2 eV, more preferably greater than 2.5 eV. By using an oxide semiconductor with a large band gap as a semiconductor layer, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the stored content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced.

[0073] Figure 5A It is shown that it can be used Figure 1A FIG. 1 is a diagram showing an example of a structure of the memory cell 10 of the memory cells 10_1 to 10_3. Figure 5A In addition to the symbols for each wiring, Figure 4A , 4BInformation on the terminals of the transistor shown (the lower electrode BSD, the second gate electrode BGE, the upper electrode TSD and the first gate electrode TGE).

[0074] like Figure 5A As shown, the wiring WWL is connected to the first gate electrode TGE of the transistor VT2. Figure 5A As shown in FIG. 1 , the wiring WBL is connected to the upper electrode TSD of the transistor VT2. Figure 5A As shown, the wiring BGL is connected to the second gate electrode BGE of the transistor VT2. Figure 5A As shown in FIG. 1 , the node FN is connected to the first gate electrode TGE of the transistor VT1. The first gate electrode TGE of the transistor VT1 also functions as a lower electrode BSD. Figure 5A As shown, the wiring RWL is connected to the second gate electrode BGE of the transistor VT1. Figure 5A As shown in FIG. 1 , the wiring SL is connected to the upper electrode TSD of the transistor VT1. Figure 5A As shown, the wiring RBL is connected to the lower electrode BSD of the transistor VT1.

[0075] Note that the transistor of one embodiment of the present invention may particularly preferably have a structure in which the conductive layer 140 is used as the first gate electrode TGE and the conductive layer 120 is used as the second gate electrode BGE. By using the conductive layer 140 having a larger area facing the oxide semiconductor layer 150 than the conductive layer 120 as the first gate electrode TGE, a gate electric field is more effectively applied to the oxide semiconductor layer 150, and thus the electrical characteristics of the transistor may be improved.

[0076] like Figure 5A As shown, by adopting a structure in which each wiring is connected to each terminal of the transistor VT1, the conductive layer 120 of a part of the wiring RWL, the conductive layer 130 of a part of the wiring SL, and the conductive layer 140 as the node FN can be set in a manner that the conductive layer 110 of a part of the wiring RBL has overlapping regions in the vertical direction. Similarly, by adopting a structure in which each wiring is connected to each terminal of the transistor VT2, the conductive layer 120 of a part of the wiring BGL, the conductive layer 130 of a part of the wiring WBL, and the conductive layer 140 of a part of the wiring WWL can be set in a manner in which the conductive layer 140 as the node FN has overlapping regions in the vertical direction.

[0077] Note that it can be used Figure 1A The structure of the memory cells of the memory cells 10_1 to 10_3 described above is not limited to Figure 5A For example, it is also possible to use Figure 5B or Figure 5C The structure shown. Figure 5B The storage unit 10A shown has the following structure: Figure 5A On the basis of the structure of , the wiring WWL is connected to the second gate electrode BGE of the transistor VT2, and the wiring BGL is connected to the first gate electrode TGE of the transistor VT2. In addition, Figure 5C The storage unit 10B shown has the following structure: Figure 5A On the basis of the structure of , the wiring SL is connected to the lower electrode BSD of the transistor VT1, and the wiring RBL is connected to the upper electrode TSD of the transistor VT1.

[0078] In one embodiment of the present invention, a structure is adopted in which a potential for controlling the electrical characteristics of the transistor, specifically a potential for controlling the threshold voltage, is supplied to a conductive layer used as a first gate electrode or a second gate electrode of a vertical transistor. By adopting this structure, different potentials can be supplied to each transistor in response to a write operation, a hold operation, or a read operation to control the electrical characteristics of the transistor. FIG. 5A to FIG. 5C In the structure shown, the parasitic capacitance of each wiring can be made different from each other.

[0079] For example, in Figure 4A In the vertical transistor shown in FIG. 1 , the parasitic capacitance between the first gate electrode TGE and the upper electrode TSD is greater than the parasitic capacitance between the first gate electrode TGE and the lower electrode BSD. Figure 5A As shown in FIG. 1 , by providing the wiring RBL for reading data on the lower electrode BSD side, the power consumption required for charging and discharging the wiring can be reduced.

[0080] For example, in Figure 4A In the vertical transistor shown in FIG. 1 , the parasitic capacitance of the first gate electrode TGE is greater than the parasitic capacitance of the second gate electrode BGE. Figure 5B As shown, by providing the wiring WWL for controlling the on state or the off state of the transistor VT2 on the second gate electrode BGE side, the power consumption required for charging and discharging the wiring can be reduced.

[0081] For example, in Figure 4A In the vertical transistor shown in the figure, by providing the wiring SL for supplying a constant potential on the side of the lower electrode BSD, the influence of noise of the wiring located in the lower layer of the vertical transistor can be reduced.

[0082] By adopting FIG. 5A to FIG. 5C The structure shown can provide a storage device that is excellent in terms of reducing power consumption, increasing operating speed, miniaturization, or increasing storage capacity.

[0083] exist Figure 5A In the memory cell 10 described above, a capacitor for holding a data potential is preferably connected to the node FN. Fig. 6A It is shown that it can be used Figure 1AA diagram showing a structural example of a memory cell 10C including a capacitor of the illustrated memory cells 10_1 to 10_3.

[0084] Fig. 6A The memory cell 10C shown is Figure 5A The structure further includes a capacitor CS. One terminal of the capacitor CS is connected to the node FN. The other terminal of the capacitor CS is connected to the wiring CSL. The wiring CSL is a wiring to which a constant potential is supplied for maintaining the potential of the node FN.

[0085] Notice, Fig. 6A The described structure of the memory cell including the capacitor is not limited to Fig. 6A For example, you can also use Figure 6B or Figure 6C structure. Figure 6B The storage unit 10D shown has the following structure: Fig. 6A On the basis of the structure, the other terminal of the capacitor CS is connected to the second gate electrode BGE of the transistor VT2, that is, the wiring BGL. Since a constant potential is supplied to the wiring BGL during the retention period and the data read period, the capacitor CS can maintain the data potential of the node FN. In addition, Figure 6C The storage unit 10E shown has the following structure: Fig. 6A On the basis of the structure of , the other terminal of the capacitor CS is connected to the upper electrode TSD of the transistor VT1, that is, the wiring SL. Since a constant potential is supplied to the wiring SL, the capacitor CS can hold the data potential of the node FN.

[0086] In one embodiment of the present invention, a structure is adopted in which a potential for controlling the electrical characteristics of the transistor, specifically a potential for controlling the threshold voltage, is supplied to a conductive layer used as a first gate electrode or a second gate electrode of a vertical transistor. By adopting this structure, different potentials can be supplied to each transistor in response to a write operation, a hold operation, or a read operation to control the electrical characteristics of the transistor. Furthermore, FIG. 6A to FIG. 6C In the structure shown, since the capacitor CS is included, the charge retention characteristics of the node FN can be improved. For example, the influence of the potential change caused by the change between the H level and the L level of the word signal supplied to the wiring WWL and the potential change caused by noise can be reduced. By adopting this structure, a storage device excellent in reducing power consumption, improving operating speed, miniaturization or increasing storage capacity can be provided.

[0087] Figure 7 It shows the description Figure 1B A diagram showing a modified example of the timing chart of the operation of the memory cells 10_1 to 10_3 described above. Figure 7 and Figure 1BThe timing chart shown is different in that the control signals of the wirings BGL_1 to BGL_3 are set to the H level in the period before data is written and are set to the L level in the period after data is written.

[0088] In one embodiment of the present invention, a structure is adopted in which a potential for controlling the electrical characteristics of the transistor, specifically a potential for controlling the threshold voltage, is supplied to a conductive layer used as a first gate electrode or a second gate electrode of a vertical transistor. By adopting this structure, different potentials can be supplied to each transistor in response to a write operation, a hold operation, or a read operation to control the electrical characteristics of the transistor. Figure 7 In the structure shown, data writing can be controlled by the timing of raising the word signal supplied to the wiring WWL (the timing of changing from L level to H level) without switching the control signal of the wiring BGL. By adopting this structure, a storage device excellent in reducing power consumption, increasing operating speed, miniaturization or increasing storage capacity can be provided.

[0089] In the transistor in the memory device of one embodiment of the present invention, for example, Figure 3A The insulating layer shown (e.g., insulating layers 160, 170) or Fig. 6A The capacitor CS shown in the figure includes an insulating layer made of a material exhibiting ferroelectricity.

[0090] Fig. 8A The memory cell 10F is shown as Figure 3A The illustrated insulating layer is an example of a circuit diagram in which the insulating layer 160 of the insulating layers uses a material exhibiting ferroelectricity.

[0091] As materials exhibiting ferroelectricity, oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide can be cited. In addition, it is preferred to use a material obtained by adding a Group III element to the oxide. For example, the oxide preferably contains scandium, yttrium, and one or more elements belonging to the lanthanide series. In particular, yttrium, lanthanum, or scandium is relatively easy to handle and has a high affinity with semiconductor manufacturing processes, so it is preferred. By adding such elements, not only can ferroelectricity be stably exhibited, but also the degradation of characteristics during repeated rewriting can be suppressed to improve reliability. For example, these elements are preferably added in a ratio of more than 0.5at% and less than 10at%. In addition, silicon, aluminum, gadolinium, scandium, etc. are added.

[0092] Oxides containing one or both of hafnium and zirconium easily exhibit ferroelectricity even when formed into an extremely thin film using a thin film deposition method such as sputtering or atomic layer deposition (ALD) and therefore have high affinity with semiconductor manufacturing processes and can reduce manufacturing costs.

[0093] Figure 8BThe memory cell 10G shown is a Fig. 6A The capacitor CS shown is an example of a circuit diagram in which the insulating layer includes a material exhibiting ferroelectricity. The capacitor CS including the material exhibiting ferroelectricity is sometimes referred to as a ferroelectric capacitor.

[0094] When using Fig. 8A and Figure 8B With the structure shown, the memory device according to one embodiment of the present invention can perform nondestructive reading and operation (writing and reading) at a low voltage, and can significantly improve rewrite resistance.

[0095] Fig.9A , Fig. 9B An example of the structure of a two-transistor NOSRAM memory cell 10 and an example of the structure of a memory array 400 including the memory cell are shown. Fig.9A 1 is an example of a three-dimensional diagram of a memory array 400 in which a plurality of memory cells 10 including stacked transistors VT1 and VT2 are arranged. Both transistors VT1 and VT2 are vertical transistors. The memory cell 10 is connected to the conductive layer 110a, the conductive layer 120a, the conductive layer 130a, the conductive layer 140a, the conductive layer 120b, the conductive layer 130b, the conductive layer 140b, and the conductive layer 190. Note that Fig.9A In FIG. 1 , for the sake of clarity, insulating layers such as interlayer films are not shown, and the uppermost conductive layer 190 is indicated by a dotted line.

[0096] Fig.9A The conductive layer 110a shown is used as Figure 1A The wirings RBL shown in the figure (wirings RBL_1 to RBL_3 are typically shown). Fig.9A The conductive layer 120a shown is used as Figure 1A The wirings RWL shown in the figure (wirings RWL_1 to RWL_3 are typically shown). Fig.9A The conductive layer 130a shown is used as Figure 1A The wirings SL shown in the figure (wirings SL_1 to SL_3 are shown as typical examples). Fig.9A The conductive layer 120b is shown as being used as Figure 1A The wirings BGL shown in the figure (wirings BGL_1 to BGL_3 are typically shown). Fig.9A The conductive layer 130b is shown as being used as Figure 1A The wirings WBL shown in the figure (wirings WBL_1 to WBL_3 are typically shown). Fig.9A The conductive layer 190 and the conductive layer 140b connected to the conductive layer 190 are used as Figure 1A The wirings WWL shown in the figure (wirings WWL_1 to WWL_3 are typically shown).

[0097] Notice, Fig.9A Although the example in which the storage cells 10 are arranged at equal intervals in the X direction and the Y direction is shown, a staggered arrangement in which the storage cells 10 are arranged alternately one by one may also be adopted. Fig.9A Although an example is shown in which the wirings are provided so as to be orthogonal in the X direction and the Y direction, the wirings may be arranged so as not to be orthogonal.

[0098] Next, a configuration example of the memory cell 10 will be described. Fig. 9B 1 is a perspective view illustrating an example of the structure of the memory cell 10. The transistor VT1 is Fig. 9B The transistor VT2 includes the conductive layer 110a, the conductive layer 120a, the conductive layer 130a, the conductive layer 140a, and the oxide semiconductor layer 150a. The transistor VT2 may also include a conductive layer 190.

[0099] Note that Fig. 9B , for clarity, insulating layers such as interlayer films are not shown, and conductive layer 110a, conductive layer 120a, conductive layer 130a, conductive layer 120b, a portion of conductive layer 130b, and conductive layer 190 are indicated by dotted lines.

[0100] exist Fig. 9B In the memory cell 10 shown, the conductive layer 110a has a region overlapping with the conductive layers 120a, 130a, 140a, 120b, 130b, and 140b in the vertical direction (Z direction). Note that the cross-sectional view refers to the view from the normal direction of the vertical direction, which is equivalent to a cross-sectional view when cut along a plane parallel to the vertical direction.

[0101] exist Fig.9A and Fig. 9B In the structure shown, the conductive layers 110a, 120a, 130a, 140a, 120b, 130b, and 140b included in the memory cell 10 have overlapping regions. Although the operation may be unstable due to electrical interference between transistors or between conductive layers, in one embodiment of the present invention, a structure is adopted in which a potential for controlling the electrical characteristics of the transistor, specifically a potential for controlling the threshold voltage, is supplied to the conductive layer used as the first gate electrode or the second gate electrode of the vertical transistor. By adopting this structure, different potentials can be supplied to each transistor in response to the writing operation, the holding operation, or the reading operation to control the electrical characteristics of the transistor. By adopting this structure, a memory device excellent in reducing power consumption, increasing operating speed, miniaturization, or increasing storage capacity can be provided.

[0102] Reference FIG. 10A to FIG. 10D illustrate Fig. 9B The memory cell 10 shown is a structural example of transistors VT1 and VT2 included in the memory cell 10. Fig. 10A is a plan view illustrating transistor VT1, Fig. 10B Note that in the plan view, some components are omitted for clarity.

[0103] Fig. 10C is equivalent to along Fig. 10A and Fig. 10B A diagram of a cross section of line segment A1-A2 is shown. Fig. 10D is equivalent to along Fig. 10A and Fig. 10B A diagram of a cross section of line segment B1-B2 is shown.

[0104] The memory cell 10 includes an insulating layer 199 on a substrate (not shown), a transistor VT1 provided on the insulating layer 199, and a transistor VT2 provided on the transistor VT1. In addition, insulating layers 181a, 181b, and 183 serving as interlayer films may be provided between transistors and between various wirings.

[0105] The transistor VT1 includes a conductive layer 110a, a conductive layer 120a, a conductive layer 130a, a conductive layer 140a, an oxide semiconductor layer 150a, an insulating layer 160a, and an insulating layer 170a. In the transistor VT1, the oxide semiconductor layer 150a is used as a semiconductor layer. In addition, the conductive layer 140a is used as a first gate electrode. In addition, the insulating layer 160a is used as a first gate insulating film. In addition, the conductive layer 120a is used as a second gate electrode. In addition, the insulating layer 170a is used as a second gate insulating film. In addition, the conductive layer 110a and the conductive layer 130a are used as a source electrode or a drain electrode, respectively.

[0106] The transistor VT2 includes a conductive layer 140a, a conductive layer 120b, a conductive layer 130b, a conductive layer 140b, an oxide semiconductor layer 150b, an insulating layer 160b, and an insulating layer 170b. In the transistor VT2, the oxide semiconductor layer 150b is used as a semiconductor layer. In addition, the conductive layer 140b is used as a first gate electrode. In addition, the insulating layer 160b is used as a first gate insulating film. In addition, the conductive layer 120b is used as a second gate electrode. In addition, the insulating layer 170b is used as a second gate insulating film. In addition, the conductive layer 140a and the conductive layer 130b are used as a source electrode or a drain electrode, respectively.

[0107] That is, transistors VT1 and VT2 have Figure 3ATherefore, in the drawings, basically, the same three-digit numbers are attached as symbols to the components corresponding to each other in transistor VT, transistor VT1 and VT2. In addition, in the following, transistors VT1 and VT2 can refer to the description of transistor VT unless otherwise specified.

[0108] Note that the conductive layer 140a in the transistor VT2 corresponds to the conductive layer 110a in the transistor VT1. The conductive layer 140a can be said to have a region that also functions as the first gate electrode of the transistor VT1 and one of the source electrode and the drain electrode of the transistor VT2.

[0109] In the transistor VT1, an oxide semiconductor layer 150a is provided in an opening 182a provided in the conductive layer 130a and the conductive layer 120a. In the opening 182a, the oxide semiconductor layer 150a has a region overlapping with the conductive layer 140a via the insulating layer 160a and a region overlapping with the conductive layer 120a via the insulating layer 170a in the horizontal direction (the direction parallel to the XY plane). In addition, the oxide semiconductor layer 150a has a structure in contact with the top surface of the conductive layer 130a and the top surface of the conductive layer 110a. Note that when viewed from a plane, it means when viewed from the normal direction of the horizontal direction, which is equivalent to a cross-sectional view when cut along a plane parallel to the horizontal direction.

[0110] In the transistor VT2, an oxide semiconductor layer 150b is provided in an opening 182b provided in the conductive layer 130b and the conductive layer 120b. In the opening 182b, the oxide semiconductor layer 150b has a region overlapping with the conductive layer 140b via the insulating layer 160b in the horizontal direction (a direction parallel to the XY plane) and a region overlapping with the conductive layer 120b via the insulating layer 170b. In addition, the oxide semiconductor layer 150b has a structure in contact with the top surface of the conductive layer 130b and the top surface of the conductive layer 140a.

[0111] that is, Fig. 10C and Fig. 10DThe structure shown may be a structure in which the oxide semiconductor layer 150a is surrounded by the conductive layer 120a and the conductive layer 140a in the horizontal direction with the insulating layers 160a and 170a therebetween, and the oxide semiconductor layer 150b is surrounded by the conductive layer 120b and the conductive layer 140b in the horizontal direction with the insulating layers 160b and 170b therebetween. Thus, in one embodiment of the present invention, a structure is adopted in which a potential for controlling the electrical characteristics of the transistor, specifically a potential for controlling the threshold voltage, is supplied to the conductive layer used as the first gate electrode or the second gate electrode of the vertical transistor. By adopting this structure, the electrical characteristics of the transistor can be controlled by supplying different potentials to each transistor corresponding to the writing operation, the holding operation or the reading operation. By adopting this structure, a storage device excellent in reducing power consumption, improving the operating speed, miniaturization or increasing the storage capacity can be provided.

[0112] Note that the conductive layer 140b is connected to the conductive layer 190 formed over the conductive layer 140b. Note that the conductive layer 140b and the conductive layer 190 may be formed as the same component.

[0113] The top surface shapes of the conductive layer 140a and the conductive layer 140b are preferably substantially circular. By adopting such a structure, the integration degree of the memory cell 10 can be improved.

[0114] In order to increase the overlapping area between the transistor VT2 and the transistor VT1 , it is preferable that the top surface shape of the opening 182 b has the same shape or a similar shape to the top surface shape of the opening 182 a forming the transistor VT1 .

[0115] Next, constituent materials that can be used for the storage device are described.

[0116] As a substrate that can be used for a storage device, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate provided with an element on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0117] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0118] For example, when miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin filmization of the gate insulator. By using high-k materials as insulators used as gate insulators, low voltage can be achieved when the transistor is working while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using materials with low relative dielectric constants for insulators used as interlayer films, the capacitance value of parasitic capacitance generated between wirings can be reduced. Therefore, it is preferred to select materials according to the functions of the insulators. In addition, materials with low relative dielectric constants are also materials with high dielectric strength.

[0119] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0120] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, for example, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0121] In addition, by surrounding a transistor using an oxide semiconductor with an insulator having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used. Specifically, as an insulator having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0122] In addition, an insulating layer in contact with the semiconductor layer or an insulating layer disposed near the semiconductor layer, such as a gate insulating film, preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with the semiconductor layer, or when an insulating layer having a region containing excess oxygen is disposed near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having holes.

[0123] In addition, as an insulator having oxygen barrier properties, there can be mentioned an oxide containing one or both of aluminum and hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In addition, as an oxide containing one or both of aluminum and hafnium, there can be mentioned aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0124] In addition, examples of insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0125] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be an insulator having barrier properties to one or both of oxygen and hydrogen.

[0126] In addition, as an insulator having the function of capturing or fixing hydrogen, an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following properties: oxygen atoms have dangling bonds and hydrogen is captured or fixed by the dangling bonds. In addition, these metal oxides preferably have an amorphous structure, but a portion thereof may also be formed with a crystalline region.

[0127] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as impurity absorption) the corresponding substance can be replaced by the term barrier property. In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise stated, the impurities recorded as corresponding substances refer to impurities in the channel formation region or in the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is not easily diffused.

[0128] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, the nitride of the alloy or the oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. can be preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0129] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Note that as conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification, etc., a conductive film deposited using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0130] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0131] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0132] In addition, when an oxide semiconductor is used in the channel formation region of a transistor, the conductor used as a gate electrode (first gate electrode or second gate electrode) preferably adopts a stacked structure of a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0133] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element and oxygen contained in the oxide semiconductor in which the channel is formed. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide and indium tin oxide containing silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the oxide semiconductor in which the channel is formed can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0134] The semiconductor material that can be used for the semiconductor layer is not limited to oxide semiconductors. As the semiconductor layer, a semiconductor material having a band gap (a semiconductor material that is not a zero band gap semiconductor) can also be used. For example, a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used for the semiconductor material.

[0135] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds or ionic bonds. A layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0136] As single element semiconductors that can be used as semiconductor materials, silicon and germanium can be cited. As silicon that can be used for the semiconductor layer, single crystal silicon, polycrystalline silicon, microcrystalline silicon and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0137] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals having a cubic crystal structure.

[0138] As layered materials, there are graphene, silicene, boron carbonitride, chalcogenides, etc. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0139] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As the transition metal chalcogenide that can be used as a semiconductor layer, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a storage device with a large on-state current can be provided.

[0140] In one embodiment of the present invention, a structure is adopted in which a potential for controlling the electrical characteristics of the transistor, specifically a potential for controlling the threshold voltage, is supplied to a conductive layer used as a first gate electrode or a second gate electrode of a vertical transistor. By adopting this structure, different potentials can be supplied to each transistor in response to a write operation, a hold operation, or a read operation to control the electrical characteristics of the transistor. By adopting this structure, a storage device excellent in reducing power consumption, increasing operating speed, miniaturization, or increasing storage capacity can be provided.

[0141] The configuration, structure, method, and the like described in this embodiment can be used in combination with the configuration, structure, method, and the like described in other embodiments as appropriate.

[0142] Implementation Method 2 In this embodiment, an oxide semiconductor layer which can be used as a semiconductor layer of a transistor is described.

[0143] [Oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. As the structure of the crystalline metal oxide, for example, a CAAC (c-axis aligned crystal) structure, a polycrystalline (Poly-crystal) structure, and a microcrystalline (nc: nano-crystal) structure can be cited. By using a crystalline metal oxide for the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. Thus, the reliability of the transistor using the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of the memory device including the transistor can be improved.

[0144] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure refers to a crystal structure in which a plurality of crystallites (typically, a plurality of crystallites having a hexagonal crystal structure) have a c-axis orientation and are connected on the ab plane in a manner in which the plurality of crystallites are not oriented. In addition, when a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM: Transmission Electron Microscope) image, it can be confirmed that the metal atoms are arranged in layers in the crystal portion. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having a layered crystal portion.

[0145] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED), or by combining a plurality of the above methods.

[0146] In addition, there is no particular restriction on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer sometimes contains one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part thereof). When the oxide semiconductor layer has crystallinity, the degradation of transistor characteristics can sometimes be suppressed.

[0147] As the metal oxide contained in the oxide semiconductor layer of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. In addition, element M is a metal element or semi-metal element with high bonding energy with oxygen, for example, a metal element or semi-metal element with higher bonding energy with oxygen than indium. As element M, specifically aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In the case where the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0148] As a metal oxide of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. In addition, indium tin oxide (also referred to as ITSO) containing silicon, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), and the like can also be cited.

[0149] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high frequency characteristics.

[0150] In addition, the metal oxide may also contain one or more of the metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more of the metal elements with a large periodic number in the periodic table in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Thus, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As the metal element with a large periodic number in the periodic table, metal elements belonging to the fifth period and metal elements belonging to the sixth period can be cited. As the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be specifically cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0151] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0152] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0153] In addition, by increasing the ratio of the number of atoms of the element M in the metal oxide relative to the sum of the number of atoms of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0154] In this embodiment, In—Ga—Zn oxide is sometimes used as an example to explain the metal oxide.

[0155] The oxide semiconductor layer of one embodiment of the present invention has crystallinity. In addition, the oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.

[0156] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods can also be referred to as a Hybrid OS.

[0157] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by the following process: forming a metal oxide as a first layer using a first deposition method, and then forming a metal oxide as a second layer on the first layer using a second deposition method. At this time, as the first deposition method, it is preferred to use a deposition method that causes less damage to the formed surface than the second deposition method. When a deposition method that causes less damage to the formed surface is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer of the formed surface of the oxide semiconductor layer can be suppressed. In addition, impurities such as silicon can be suppressed from mixing into the second layer, so the crystallinity of the oxide semiconductor layer can be improved.

[0158] As the first deposition method, for example, atomic layer deposition (ALD: Atomic Layer Deposition) method, chemical vapor deposition (CVD: Chemical Vapor Deposition) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, wet method, etc. can be cited. As the CVD method, for example, plasma CVD (PECVD: Plasma Enhanced CVD) method, thermal CVD method, optical CVD method, metal organic CVD (MOCVD: Metal Organic CVD) method, etc. can be cited. As a wet method, for example, a spraying method can be cited. Compared with the sputtering method described later, the ALD method and the CVD method can suppress the damage to the formed surface, so they are suitable for the first deposition method.

[0159] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a reactant is excited by plasma.

[0160] When using the ALD method, atoms can be deposited layer by layer, so the following effects are achieved: extremely thin deposition can be achieved; deposition can be performed on structures with high aspect ratios or surfaces with large steps; deposition can be performed with few defects such as pinholes; deposition can be performed with high coverage; and deposition can be performed at low temperatures; etc. In addition, the PEALD method utilizes plasma and can be deposited at lower temperatures, so it is sometimes preferred. Note that as precursors used in the ALD method, there are precursors containing elements such as carbon or chlorine. Therefore, compared with films set by other deposition methods, films set by the ALD method sometimes contain more elements such as carbon or chlorine. Note that the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In addition, in a metal oxide deposition method as one embodiment of the present invention, the ALD method is used and one or both of the conditions of high substrate temperature during deposition and impurity removal treatment are adopted. Sometimes, the carbon and chlorine contents in the film are lower than when the ALD method is used without adopting the above conditions and the above treatment.

[0161] Unlike a deposition method that deposits particles released from a target material, the ALD method is a deposition method that forms a film by a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, and is therefore suitable for covering the surface of an opening with a high aspect ratio.

[0162] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since the thermal CVD method does not use plasma, it is a deposition method that can reduce plasma damage to the object being processed. In addition, in the thermal CVD method, no plasma damage is generated during deposition, so a film with fewer defects can be obtained.

[0163] Examples of the second deposition method include sputtering and pulsed laser deposition (PLD: Pulsed Laser Deposition) methods. The metal oxide formed by the second deposition method tends to have a CAAC structure.

[0164] In addition, as the first layer, a metal oxide having a microcrystalline structure or an amorphous structure, for example, whose crystallinity is lower than that of the CAAC structure, is sometimes formed. By forming a second layer having high crystallinity on the first layer having low crystallinity or performing a heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the core. Thus, the crystallinity of the entire oxide semiconductor layer including the vicinity of the interface with the formed surface can be improved.

[0165] In addition, a third layer may be formed on the second layer. Since the second layer has high crystallinity, the third layer can be crystallized with the crystal of the second layer as a nucleus or seed. Thus, even if the deposition method of the third layer does not use a deposition method that is easy to have crystallinity, the third layer can be crystallized. Here, for example, when the third layer is formed by a deposition method with higher coverage than the second layer, the oxide semiconductor layer as a whole can have both high crystallinity and high coverage.

[0166] As an example, an oxide semiconductor layer of one embodiment of the present invention can be manufactured by the following process: after forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and then forming a metal oxide as a third layer by the first deposition method. Specifically, the ALD method can be used as the first deposition method, and the sputtering method can be used as the second deposition method. Compared with the sputtering method, the ALD method is a deposition method with excellent coverage. When the ALD method is used as the deposition method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with high aspect ratios.

[0167] [Method for producing oxide semiconductor layer] The oxide semiconductor 230 of the oxide semiconductor layer can be manufactured, for example, by the following process: forming an oxide semiconductor 230a on the layer 229 of the formed surface by the ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by the sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by the ALD method. In addition, it is preferable to perform a heat treatment after forming the oxide semiconductor 230. By performing the heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. The heat treatment described here is not limited to the heat treatment. For example, it can also be the heat received in the manufacturing process.

[0168] The oxide semiconductor 230 can be used for the oxide semiconductor layer 150 or the like. The layer 229 corresponds to the insulating layer 160 or the insulating layer 170 or the like described in the above embodiment modes.

[0169] The layer 229 may not have crystallinity. Alternatively, when the layer 229 has crystallinity, the layer 229 may have a crystal structure having low lattice conformity with the metal oxide included in the oxide semiconductor 230 .

[0170] Reference FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12D An example of a method for manufacturing the oxide semiconductor 230 is described.

[0171] In the case of depositing a metal oxide film by sputtering, alloying of the components contained in the metal oxide film and the components contained in the layer of the formed surface sometimes occurs due to damage caused by sputtered particles on the formed surface or energy applied to one side of the substrate by sputtered particles. When alloying occurs, it is difficult to improve the crystallinity of the alloyed area even when the heat treatment described later is performed. When an oxide semiconductor layer having an alloyed area is used in a transistor, there is concern that the initial characteristics or reliability of the transistor will be negatively affected. Therefore, it is preferred to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer of the formed surface.

[0172] Thus, first, an oxide semiconductor 230a ( Fig.11A Then, an oxide semiconductor 230b is formed on the oxide semiconductor 230a by a sputtering method ( Fig. 11B ).

[0173] In a method for manufacturing an oxide semiconductor layer of one embodiment of the present invention, an oxide semiconductor 230a is formed between the oxide semiconductor 230b and the layer 229 using a deposition method that causes less damage to the formed surface, thereby suppressing the alloying of components contained in the oxide semiconductor 230 and components contained in the layer 229, and further improving the crystallinity of the oxide semiconductor 230.

[0174] By adopting the above structure, the thickness of the alloyed region can be reduced or reduced to the extent that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm. Note that Fig.11A and Fig. 11B An example is shown in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230 a .

[0175] Note that the thickness of the alloyed region can be calculated by performing a linear analysis of the composition of the region and its periphery using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0176] For example, with the direction perpendicular to the formed surface of the oxide semiconductor 230a as the depth direction, the linear analysis of EDX is performed on the above-mentioned region and its periphery. Next, in the distribution of the quantitative values ​​of each element relative to the depth direction obtained by this analysis, the depth at which the quantitative value of the metal (In when the oxide semiconductor 230a contains In) which is the main component of the oxide semiconductor 230a rather than the main component of the layer (here, layer 229) that is the formed surface reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the oxide semiconductor 230a. In addition, the depth at which the quantitative value of the element (e.g., Si) which is the main component of the layer that is the formed surface rather than the main component of the oxide semiconductor 230a reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the layer that is the formed surface. Through the above steps, the thickness of the alloyed region can be calculated.

[0177] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, its thickness is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, more preferably greater than 0 nm and less than 1 nm, and further preferably greater than 0 nm and less than 0.3 nm.

[0178] For example, when a silicon oxide layer is used as the layer 229 and the oxide semiconductor 230 formed on the layer 229 is subjected to SIMS analysis, the depth at which the concentration of silicon reaches 50% of the maximum concentration in the layer 229 is defined as the interface, and the depth at which the concentration of silicon decreases to 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth of and the interface is thickness t_s2. Thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0179] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0180] In addition, by reducing the thickness of the alloyed region, a CAAC structure can be formed near the formed surface. Here, near the formed surface refers to, for example, a region that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm from the formed surface of the oxide semiconductor 230 in a substantially vertical direction.

[0181] Note that a CAAC structure may be observed near the formed surface by TEM observation. For example, when a cross section of the oxide semiconductor 230 is observed by high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface may be observed near the formed surface.

[0182] When the oxide semiconductor 230a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure whose crystallinity is lower than that of the CAAC structure may be formed. Fig.11A In the manufacturing stage shown, the oxide semiconductor 230 a sometimes includes a region having lower crystallinity than the oxide semiconductor 230 b .

[0183] The oxide semiconductor 230 b preferably has a composition suitable for forming a CAAC structure.

[0184] When the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on the surface or near the surface of the oxide semiconductor 230a. In addition, due to sputtered particles or energy supplied to the substrate side by the sputtered particles when the oxide semiconductor 230b is formed, a tiny crystal region may be formed in the mixed layer 231. In the subsequent heat treatment process, at least a part of the oxide semiconductor 230a may be crystallized with the mixed layer 231 or the tiny crystal region formed in the mixed layer 231 as a nucleus.

[0185] When the oxide semiconductor 230b is deposited by sputtering, the substrate is preferably heated. When a metal oxide is formed, a metal oxide with high crystallinity may be formed by increasing the substrate temperature (stage temperature) when the metal oxide is formed.

[0186] Next, an oxide semiconductor 230c is formed on the oxide semiconductor 230b by using an ALD method. Fig. 11C ) Regarding the formation of the oxide semiconductor 230 c using the ALD method, the formation method of the oxide semiconductor 230 a can be referred to.

[0187] When an oxide semiconductor 230c is formed on an oxide semiconductor 230b having a CAAC structure using an ALD method, the oxide semiconductor 230c sometimes grows epitaxially with the oxide semiconductor 230b as a core. Therefore, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c sometimes includes a region having a CAAC structure. In addition, the region having a CAAC structure is preferably formed in the entire oxide semiconductor 230c.

[0188] Next, a heat treatment process may be performed. Through this heat treatment process, the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c is sometimes improved. In addition, after deposition using the ALD method, when the region is formed only below the oxide semiconductor 230c, the region may expand upward due to the heat treatment process ( Fig.11D ) That is, by performing this heat treatment, a region having a CAAC structure may be formed in the entire oxide semiconductor 230c.

[0189] In addition, it is preferable that at least a portion of the oxide semiconductor 230a is converted into CAAC by the heat treatment step ( Fig.11D ). It can be expected that CAAC formation is easily caused by using the mixed layer 231 formed in the oxide semiconductor 230a when the oxide semiconductor 230b is deposited as a core or a seed. The CAAC formation region in the oxide semiconductor 230a is preferably large and preferably reaches the vicinity of the layer 229.

[0190] In addition, since CAAC is formed from the upper part of the oxide semiconductor 230a to the lower part thereof, it is possible to reach the vicinity of the layer 229 without being restricted by the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a with high crystallinity can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer to be formed has an amorphous structure.

[0191] Notice, FIG. 11A to FIG. 11D: is a cross-sectional view illustrating a method for depositing a metal oxide according to one embodiment of the present invention. FIG. 11A to FIG. 11D It can also be viewed as a schematic diagram of a deposition model of a metal oxide showing one embodiment of the present invention. FIG. 11A to FIG. 11D As shown, the oxide semiconductor 230a and the oxide semiconductor 230c each use the oxide semiconductor 230b with high crystallinity as a core or a seed to improve crystallinity. Specifically, the crystallinity of the oxide semiconductor 230a is sometimes improved by heat treatment when the oxide semiconductor 230b is deposited or after the oxide semiconductor 230c is deposited. In addition, the crystallinity of the oxide semiconductor 230c is sometimes improved by heat treatment when the oxide semiconductor 230c is deposited or after the oxide semiconductor 230c is deposited. Note that the above-mentioned heat treatment plays an auxiliary role in improving crystallinity.

[0192] Thus, in a metal oxide deposition method of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductor 230a and oxide semiconductor 230c) can be improved by using the highly crystalline oxide semiconductor 230b (i.e., CAAC) as a core or seed. Thus, the crystallinity of the entire oxide semiconductor can be improved. In other words, by using the oxide semiconductor 230b as a core or seed to allow the upper and lower oxide semiconductors to grow in a solid phase, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using the above deposition method, i.e., the CAAC film, can be referred to as an axial growth (Axial Growth) CAAC (AG CAAC). Note that FIG. 12A to FIG. 12D Although the structure including the oxide semiconductor 230 a , the oxide semiconductor 230 b , and the oxide semiconductor 230 c is shown, the present invention is not limited thereto. For example, AG CAAC may be formed in the structure including the oxide semiconductor 230 a and the oxide semiconductor 230 b .

[0193] In the oxide semiconductor 230 , a region having a CAAC structure preferably exists widely throughout the entire layer. Fig. 12A The oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are all crystallized. In this case, the boundary between the oxide semiconductor 230a and the oxide semiconductor 230b is sometimes not observed. In addition, the boundary between the oxide semiconductor 230b and the oxide semiconductor 230c is sometimes not observed. The oxide semiconductor 230 can sometimes be described as a layer in which no clear interface is observed. The oxide semiconductor 230 can sometimes be described as a single layer.

[0194] In addition, a part of the oxide semiconductor 230a or the oxide semiconductor 230c may not be crystallized. In addition, a region having lower crystallinity than the CAAC structure may remain in a part of the oxide semiconductor 230a or the oxide semiconductor 230c. Fig. 12BAs an example, a case is described in which the oxide semiconductor 230 a is not crystallized near the interface with the layer 229 , or a region having lower crystallinity than the CAAC structure remains near the interface. Fig. 12C This shows a case where, in the oxide semiconductor 230 c , the vicinity of the surface is not crystallized or a region having lower crystallinity than the CAAC structure remains near the surface. Fig.12D The following situation is shown: the vicinity of the interface between the oxide semiconductor 230a and the layer 229 and the vicinity of the surface of the oxide semiconductor 230c are not crystallized, or a region with lower crystallinity than the CAAC structure remains near the interface between the oxide semiconductor 230a and the layer 229 and near the surface of the oxide semiconductor 230c.

[0195] By improving the crystallinity of the oxide semiconductor layer, the resistance increase of the semiconductor layer of the transistor using the oxide semiconductor layer is suppressed or the initial characteristics of the transistor (especially the on-state current) are improved, thereby realizing a transistor suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0196] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity as a whole. Therefore, in the oxide semiconductor 230, the boundaries between the stacked films in the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are sometimes not confirmed. In particular, after heat treatment, it is sometimes difficult to confirm the boundaries between the stacked films. For example, the presence or absence of the boundaries between the stacked films can be confirmed using cross-sectional TEM, cross-sectional STEM, etc.

[0197] As described above, by using a metal oxide with a high In content ratio for a transistor, the field effect mobility of the transistor can be improved. On the other hand, an oxide semiconductor with a high In content ratio has a tendency to polycrystallize. When a metal oxide with a polycrystalline structure is used for a transistor, it has a negative impact on the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content ratio for one or both of the oxide semiconductor 230a and the oxide semiconductor 230c, a crystal reflecting the orientation of the crystal contained in the oxide semiconductor 230b is formed, thereby suppressing polycrystallization.

[0198] In addition, the lattice mismatch between the crystals included in the oxide semiconductor 230b and the crystals included in the oxide semiconductor 230a or the oxide semiconductor 230c is preferably small. Thus, the oxide semiconductor 230a or the oxide semiconductor 230c can form a crystal that reflects the orientation of the crystals included in the oxide semiconductor 230b. At this time, for example, when the cross-section of the oxide semiconductor 230 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0199] As long as the lattice mismatch between the crystal included in the oxide semiconductor 230b and the crystal included in the oxide semiconductor 230a or the oxide semiconductor 230c is small, there is no particular limitation on the crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any one of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0200] [Composition of Oxide Semiconductor Layer] As described above, the composition of the oxide semiconductor 230b is preferably suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed using a sputtering method, for example. The oxide semiconductor 230b preferably contains zinc, for example. By containing zinc, a metal oxide with high crystallinity can be obtained. In addition, the oxide semiconductor 230b preferably contains element M in addition to zinc. By making the oxide semiconductor 230b contain element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of the transistor using the oxide semiconductor layer can be improved. As the oxide semiconductor 230b, specifically, a metal oxide of the following composition can be used: In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic number ratio. In addition, as the element M, one or more of gallium, aluminum, and tin are preferably used.

[0201] The oxide semiconductor 230b may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, a composition of In:Zn=2:1 [atomic ratio] or a composition near it, or a composition of In:Zn=4:1 [atomic ratio] or a composition near it. Alternatively, indium oxide may also be used. In addition, a trace amount of element M may also be contained. For example, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near it. In addition, for example, it may be a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near it.

[0202] The oxide semiconductor 230a and the oxide semiconductor 230c can use a metal oxide having a high In ratio. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed using, for example, an ALD method. In addition, it is particularly preferred to use a metal oxide having a higher In ratio than the element M. By using a metal oxide having a high In ratio, when the oxide semiconductor layer is used for a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0203] Alternatively, the oxide semiconductor 230a and the oxide semiconductor 230c may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, In:Zn=2:1 [atomic ratio] or a composition near it, or In:Zn=4:1 [atomic ratio] or a composition near it. Alternatively, indium oxide may also be used. In addition, the oxide semiconductor 230a and the oxide semiconductor 230c may also contain a trace amount of the element M. Specifically, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near it, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near it, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near it, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near it.

[0204] In addition, by increasing the zinc composition of the oxide semiconductor, the crystallinity of the oxide semiconductor can be improved. In particular, the oxide semiconductor 230a preferably contains zinc. For example, when the oxide semiconductor 230a is formed using the ALD method and the oxide semiconductor 230b is formed using the sputtering method, the zinc contained in the oxide semiconductor 230a sometimes diffuses into the oxide semiconductor 230b. Note that this diffusion occurs due to heat treatment during or after sputtering. It can be expected that the crystallinity will be improved due to the diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b. Alternatively, it can be expected that the crystalline portion with c-axis orientation will grow laterally due to the diffusion of zinc from the oxide semiconductor 230a to the oxide semiconductor 230b, thereby promoting CAAC.

[0205] Alternatively, the oxide semiconductor 230 a and the oxide semiconductor 230 c may use a metal oxide having a higher In content than the oxide semiconductor 230 b .

[0206] In addition, for example, as the oxide semiconductor 230a and the oxide semiconductor 230c, a metal oxide having a higher Ga ratio than the oxide semiconductor 230b may be used. For example, the oxide semiconductor 230a and the oxide semiconductor 230c preferably use a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. By increasing the Ga ratio, for example, the band gaps of the oxide semiconductor 230a and the oxide semiconductor 230c can sometimes be made larger than the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c having a large band gap, and the oxide semiconductor 230b is mainly used as a current path (channel). By sandwiching the oxide semiconductor 230b between the oxide semiconductor 230a and the oxide semiconductor 230c, the trap energy levels at the interface of the oxide semiconductor 230b and its vicinity can be reduced. Thus, a buried channel transistor in which the channel is far away from the insulating layer interface can be realized, thereby improving the field effect mobility.

[0207] In addition, in the oxide semiconductor layer of one embodiment of the present invention, even if the oxide semiconductor 230a and the oxide semiconductor 230c have a composition that does not easily form a CAAC structure when formed into a single layer, the entire oxide semiconductor layer including the oxide semiconductor 230a and the oxide semiconductor 230c can have a CAAC structure by causing crystal growth using the oxide semiconductor 230b as a core. Alternatively, the region including at least a portion of each of the oxide semiconductor 230a and the oxide semiconductor 230c to the region of the oxide semiconductor 230b can have a CAAC structure.

[0208] In particular, when the oxide semiconductor 230a and the oxide semiconductor 230c have a composition with a high ratio of In, the crystallinity of the semiconductor layer suitable for the transistor can also be obtained. In the oxide semiconductor layer of one embodiment of the present invention, the reliability can be improved by using a CAAC structure with high crystallinity while increasing the ratio of In to improve the turn-on characteristics of the transistor.

[0209] Note that the composition of the oxide semiconductor 230 a and the composition of the oxide semiconductor 230 c may be different.

[0210] Alternatively, the oxide semiconductor 230 a and the oxide semiconductor 230 c may use a metal oxide having the same composition as that of the oxide semiconductor 230 b .

[0211] By using an oxide semiconductor layer having a CAAC structure formed using the two deposition methods described above for the channel formation region of a transistor, a transistor having excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) , a transistor with high reliability, etc.) can be realized.

[0212] The composition of the metal oxide used for the oxide semiconductor 230 can be analyzed using, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry). Alternatively, a plurality of the above methods may be combined for analysis. Note that elements with low content ratios are sometimes affected by the accuracy of the analysis, and the actual content ratio is different from the content ratio obtained by analysis. For example, when the content ratio of element M is low, the content ratio of element M obtained by analysis is sometimes lower than the actual content ratio.

[0213] [c-axis orientation] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. For example, the crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0214] By performing Fast Fourier Transform (FFT) processing on the TEM image, the crystal orientation can be obtained from the FFT pattern. Specifically, the crystal axis direction can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects the same reciprocal spatial information as the electron diffraction pattern.

[0215] By performing FFT processing on each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a graph showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of the region having the layered crystal part. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots.

[0216] The c-axis orientation degree can be calculated by calculating the ratio of the c-axis oriented region in the graph showing the crystal orientation. Note that the c-axis oriented region here refers to a region whose orientation coincides with the c-axis and whose difference from the c-axis is within 20°.

[0217] In the oxide semiconductor layer of one embodiment of the present invention, for example, a cross-section or planar TEM observation of the oxide semiconductor layer can be performed to calculate the c-axis orientation ratio. In addition, the region where FFT is performed (also referred to as FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0218] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation degree is preferably 60% or more, more preferably 70% or more, further preferably 80% or more, further preferably 90% or more, and further preferably 95% or more.

[0219] In addition, the c-axis orientation degrees of the region deposited as the oxide semiconductor 230a, the region deposited as the oxide semiconductor 230b, and the region deposited as the oxide semiconductor 230c are Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are both preferably 60% or more, more preferably 70% or more, further preferably 80% or more, further preferably 90% or more, and further preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. In addition, Rc2 / Rc1 is preferably greater than 1.

[0220] Note that the boundary between the oxide semiconductors 230 a , 230 b , and 230 c is not clearly observed in some cases after the oxide semiconductor 230 is manufactured.

[0221] The oxide semiconductor 230 of one embodiment of the present invention can be divided into three regions, namely, a first region, a second region, and a third region in order from the layer 229 side. Each region is a layered region.

[0222] The first region, the second region, and the third region all have a CAAC structure. In addition, the c-axis orientation of the third region is preferably higher than the c-axis orientation of the first region. In addition, the c-axis orientation of the second region is preferably higher than the c-axis orientation of the first region. In addition, the c-axis orientation of the second region and the third region is preferably 80% or more, more preferably 90% or more, and further preferably 95% or more.

[0223] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor 230 .

[0224] Alternatively, the thickness of the layer in each region may be substantially the same, for example.

[0225] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0226] Implementation 3 In this embodiment, a structural example of a semiconductor device 1000 including a memory cell 10 (also referred to as a “memory element”) is described.

[0227] Fig.13A 1 is a block diagram showing a configuration example of a semiconductor device 1000 according to one embodiment of the present invention. Fig.13A The semiconductor device 1000 shown includes a driving circuit 300 and a memory array 400. The memory array 400 includes a plurality of memory cells 10. Fig.13A The memory array 400 is shown as an example including a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2).

[0228] In addition, the rows and columns extend in directions orthogonal to each other. In this embodiment, the X direction is set as the "row" and the Y direction is set as the "column", but the X direction may be set as the "column" and the Y direction may be set as the "row".

[0229] exist Fig.13A , the storage cell 10 in the first row and first column is recorded as storage cell 10[1,1] and the storage cell 10 in the mth row and nth column is recorded as storage cell 10[m,n]. In addition, the storage cell 10 in the i-th row and j-th column (i is an integer greater than 1 and less than m. j is an integer greater than 1 and less than n) is recorded as storage cell 10[i,j].

[0230] The driving circuit 300 includes a PSW 341 (power switch), a PSW 342 , and a peripheral circuit 315 . The peripheral circuit 315 includes a peripheral circuit 311 , a control circuit 312 , and a voltage generating circuit 328 .

[0231] In the semiconductor device 1000, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0232] In addition, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. In addition, signals PON1 and PON2 can also be generated in the control circuit 312.

[0233] The control circuit 312 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 1000. For example, the control circuit 312 performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the semiconductor device 1000. Alternatively, the control circuit 312 generates a control signal for the peripheral circuit 311 to execute the above operation mode.

[0234] The voltage generating circuit 328 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 328. For example, when a signal of an H level is supplied to the signal WAKE, the signal CLK is input to the voltage generating circuit 328, and the voltage generating circuit 328 generates a voltage.

[0235] The peripheral circuit 311 is a circuit for writing and reading data from the memory cell 10. The peripheral circuit 311 includes a row decoder 321, a column decoder 322, a row driver 323, a column driver 324, an input circuit 325, an output circuit 326, and a sense amplifier 327.

[0236] The row decoder 321 and the column decoder 322 have the function of decoding the signal ADDR. The row decoder 321 is a circuit for specifying a row to be accessed, and the column decoder 322 is a circuit for specifying a column to be accessed. The row driver 323 has the function of selecting the wiring specified by the row decoder 321. The column driver 324 has the following functions: a function of writing data to the memory cell 10; a function of reading data from the memory cell 10; and a function of holding the read data.

[0237] The input circuit 325 has a function of holding a signal WDA. The data held in the input circuit 325 is output to the column driver 324. The output data of the input circuit 325 is the data (Din) written to the memory cell 10. The column driver 324 outputs the data (Dout) read from the memory cell 10 to the output circuit 326. The output circuit 326 has a function of holding Dout. In addition, the output circuit 326 has a function of outputting Dout to the outside of the semiconductor device 1000. The data output from the output circuit 326 is the signal RDA.

[0238] PSW341 has the function of controlling the supply of V to the peripheral circuit 315 DD PSW342 has the function of controlling the supply of V to the row driver 323. HM Here, the high power supply voltage of the semiconductor device 1000 is V DD , the low power supply voltage is GND (ground potential). In addition, V HM It is a high power supply voltage used to make the word line high, which is higher than V DD The PSW 341 is turned on / off by the signal PON1, and the PSW 342 is turned on / off by the signal PON2. Fig.13A In the peripheral circuit 315, V DD The number of power domains is 1, but may be multiple. In this case, a power switch may be provided for each power domain.

[0239] The driving circuit 300 and the memory array 400 may also be arranged on the same plane. Fig. 13B As shown, the driver circuit 300 and the memory array 400 may overlap. By overlapping the driver circuit 300 and the memory array 400, the signal transmission distance can be shortened. In addition, the semiconductor device 1000 can be miniaturized.

[0240] In addition, if Fig. 13C As shown, a plurality of memory arrays 400 may be overlapped on the driving circuit 300. By overlapping the plurality of memory arrays 400 on the driving circuit 300, the storage capacity per unit area may be increased.

[0241] Fig.14A 4 is a block diagram illustrating a configuration example of a memory cell 10 in a memory array 400. The memory array 400 includes m wirings WBL and m wirings RBL extending in the row direction, n wirings WWL, n wirings SL, n wirings BGL, and n wirings RWL (not shown) extending in the column direction.

[0242] Fig. 14B1 is a circuit diagram of a memory cell 10[i, j]. The memory cell 10[i, j] includes a transistor VT2[i, j] and a transistor VT1[i, j]. The gate of the transistor VT2[i, j] is connected to the wiring WWL[j] of the wiring WWL in the j-th column, and the back gate is connected to the wiring BGL[j] of the wiring BGL in the j-th column. In addition, one of the source and the drain of the transistor VT2[i, j] is connected to the wiring WBL[i] of the wiring WBL in the i-th row, and the other is connected to the gate of the transistor VT1[i, j].

[0243] The back gate of transistor VT1[i,j] is connected to the wiring RWL[j] of the wiring RWL in the jth column. In addition, one of the source and drain of transistor VT1[i,j] is connected to the wiring RBL[i] of the wiring RBL in the i-th row, and the other is connected to the wiring SL[j] of the wiring SL in the j-th column.

[0244] The memory cell 10[i,j] includes a node FN[i,j]. The node FN[i,j] is a node at which the other of the source and the drain of the transistor VT2[i,j] is connected to the gate of the transistor VT1[i,j].

[0245] By supplying a signal to the wiring WBL[i] and the wiring WWL[j], information can be written to the memory cell 10[i, j]. In addition, by supplying a signal to the wiring RBL[i] and the wiring RWL[j], information stored in the memory cell 10[i, j] can be read out. By controlling the signal supplied to each wiring, information can be read from any memory cell 10 and information can be written to any memory cell 10. Therefore, the semiconductor device 1000 can be used as a NOR type memory device.

[0246] Fig.15A is a diagram illustrating the memory cell 10 in the memory array 400 and Fig.14A Block diagrams of different configuration examples.

[0247] exist Fig.15A In the illustrated memory array 400 , the memory cells 10 in odd-numbered columns and the memory cells 10 in even-numbered columns are arranged bilaterally symmetrically. Fig. 15B The circuit diagram of the memory cell 10[i, j] and the memory cell 10[i, j+1] when j is an odd number is shown. One of the source and drain of the transistor VT2[i, j] and one of the source and drain of the transistor VT2[i, j+1] are connected to the wiring WBL[i]. By arranging the memory cells 10 of the odd columns and the memory cells 10 of the even columns symmetrically, both the transistor VT2[i, j] and the transistor VT2[i, j+1] can be connected to the wiring WBL[i] through a common connection path.

[0248] Similarly, both transistor VT1[i,j] and transistor VT1[i,j+1] can be connected to wiring RBL[i] via a common connection path. Therefore, the occupied area of ​​memory array 400 can be further reduced. In addition, the recording density per unit area can be further increased.

[0249] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0250] Implementation 4 In this embodiment, an application example of a storage device according to one embodiment of the present invention is described.

[0251] Generally speaking, in semiconductor devices such as computers, various storage devices are used depending on the application. Fig.16 Various storage devices are shown in a hierarchical manner. The higher the storage device, the faster the access speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density is required. Fig.16 , the memory installed together as registers in a CPU or other arithmetic processing device, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory are shown in order from the top layer.

[0252] Since the memory installed together with the register in the CPU and other processing devices is used for temporary storage of the calculation results, the access frequency from the processing devices is high. Therefore, the operation speed is required to be faster than the storage capacity. In addition, the register also has the function of holding the setting information of the processing device.

[0253] SRAM is used for cache, for example. Cache has the function of copying and holding a part of the information held in the main memory. By copying frequently used data to the cache, the speed of accessing the data can be increased.

[0254] DRAM is used, for example, as a main memory. The main memory has the function of holding programs or data read from the auxiliary memory. The recording density of DRAM is about 0.1 to 0.3 Gbit / mm 2 .

[0255] 3D NAND memory is used, for example, for auxiliary memory. The auxiliary memory has the function of storing data that needs to be stored for a long time, various programs used by the operation processing device, etc. Therefore, compared with a faster operating speed, the auxiliary memory is required to have a larger storage capacity and a higher recording density. The recording density of the storage device used for the auxiliary memory is about 0.6 to 6.0 Gbit / mm 2.

[0256] The advantages of a storage device according to one embodiment of the present invention are: high operating speed, long-term data retention, high rewrite resistance, and low voltage drive. The storage device according to one embodiment of the present invention can be used as a storage device located in the boundary area 901 of both the layer where the main memory is located and the layer where the auxiliary memory is located.

[0257] The storage device according to one embodiment of the present invention can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smart phones, e-book reader terminals, digital cameras, video cameras, video playback devices, navigation systems, game consoles, etc.). In addition, it can also be used for image sensors, IoT (Internet of Things), and medical-related equipment. Note that here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0258] Alternatively, the storage device according to one embodiment of the present invention is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (Solid State Drive). FIG. 17A to FIG. 17E Several structural examples of the removable storage device are schematically shown. For example, the storage device according to one embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

[0259] Fig.17A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device described in the above embodiment can be assembled with the memory chip 1105 on the substrate 1104.

[0260] Fig. 17B This is a schematic diagram of the appearance of an SD card. Fig. 17C11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1114 on the substrate 1113, etc.

[0261] Fig.17D This is a schematic diagram of the appearance of SSD. Fig.17E 1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled with the memory chip 1154 on the substrate 1153, etc.

[0262] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0263] Implementation method 5 18A to 18H A specific example of an electronic device including a semiconductor device according to one embodiment of the present invention is described.

[0264] <Electronic equipment and systems> A semiconductor device according to one embodiment of the present invention can be installed in a variety of electronic devices. As examples of electronic devices, in addition to electronic devices with larger screens such as television devices, displays for desktop or notebook information terminals, digital signage, and large game consoles such as pinball machines, digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices can also be cited. In addition, a semiconductor device according to one embodiment of the present invention can be used as a constituent element of artificial intelligence. In addition, a semiconductor device according to one embodiment of the present invention can be used to enable an electronic device to have artificial intelligence.

[0265] The electronic device according to one embodiment of the present invention may also include an antenna. By receiving a signal through the antenna, an image or information can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can also be used for contactless power transmission.

[0266] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of detecting, detecting or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0267] An electronic device according to one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc.

[0268] [Information Terminal] Fig.18A The figure shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5100 includes a housing 5101 and a display portion 5102 . The display portion 5102 is provided with a touch panel as an input interface, and buttons are provided on the housing 5101 .

[0269] The information terminal 5100 can execute an application program utilizing artificial intelligence using a semiconductor device according to one embodiment of the present invention. Examples of the application program utilizing artificial intelligence include an application program that recognizes a conversation and displays the content of the conversation on the display unit 5102, an application program that recognizes text or graphics input by a user to a touch panel provided on the display unit 5102 and displays the text or graphics on the display unit 5102, and an application program that performs biometric recognition such as fingerprints or voiceprints.

[0270] Fig.18B 1 and 2. The notebook information terminal 5200 is shown. The notebook information terminal 5200 includes an information terminal body 5201, a display portion 5202, and a keyboard 5203.

[0271] Similar to the above-mentioned information terminal 5100, the notebook information terminal 5200 can execute an application program using artificial intelligence by using a semiconductor device according to one embodiment of the present invention. Examples of applications using artificial intelligence include design support software, article proofreading software, and menu automatic generation software. In addition, by using the notebook information terminal 5200, novel artificial intelligence can be developed.

[0272] Note that in the above example, Fig.18A and Fig.18B Although a smartphone and a notebook information terminal are shown as examples of electronic devices, information terminals other than smartphones and notebook information terminals may also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0273] [Game console] Fig. 18C A portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, and an operation key 5306. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided in the housing 5301 to another housing (not shown), the image output to the display unit 5304 can be output to another video display device (not shown). In this case, the housing 5302 and the housing 5303 can be used as an operation unit, respectively. Thus, multiple game players can play games at the same time. The semiconductor device according to one embodiment of the present invention can be embedded in a chip or the like provided on a substrate of the housing 5301, the housing 5302, and the housing 5303.

[0274] in addition, Fig.18D A stationary gaming machine 5400, which is one of the gaming machines, is shown. The stationary gaming machine 5400 is connected to a controller 5402 by wireless or wired connection.

[0275] By applying a GPU or chip of one embodiment of the present invention to a gaming machine such as the portable gaming machine 5300 and the fixed gaming machine 5400, a gaming machine with low power consumption can be realized. In addition, the heat generated by the circuit can be reduced by means of low power consumption, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, and modules.

[0276] Furthermore, by applying the semiconductor device according to one embodiment of the present invention to the portable game console 5300 , the portable game console 5300 having artificial intelligence can be realized.

[0277] The performance of the progress of the game, the words and deeds of creatures appearing in the game, and the phenomena occurring in the game are originally specified by the program of the game, but by applying artificial intelligence to the portable game machine 5300, it is possible to realize performance not limited to the game program. For example, it is possible to realize the performance of the content of the questions asked by the game player, the progress of the game, the time, and the changes in the words and deeds of the characters appearing in the game.

[0278] Furthermore, when a game requiring multiple players is played using the portable game console 5300, an anthropomorphic player can be constructed using artificial intelligence, whereby the artificial intelligence player can be used as an opponent, and a single person can play a game played by multiple players.

[0279] Although Fig. 18C and Fig.18D Portable game machines and stationary game machines are shown as examples of game machines, but game machines to which the semiconductor device according to one embodiment of the present invention can be applied are not limited thereto. Game machines to which the semiconductor device according to one embodiment of the present invention can be applied include, for example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like.

[0280] [Mainframe computer] A semiconductor device according to one embodiment of the present invention can be applied to a mainframe computer.

[0281] Fig.18E A supercomputer 5500 is shown as an example of a large computer. Fig.18F A rack mount computer 5502 included in the supercomputer 5500 is shown.

[0282] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are housed in the rack 5501. The computer 5502 is provided with a plurality of substrates 5504 on which the semiconductor device according to one embodiment of the present invention can be mounted.

[0283] The supercomputer 5500 is a large computer mainly used for scientific computing. Scientific computing requires huge calculations at high speed, so the power consumption is large and the heat generated by the chip is high. By applying a semiconductor device according to one embodiment of the present invention to the supercomputer 5500, a low-power supercomputer can be realized. In addition, with the help of low power consumption, the heat generated by the circuit can be reduced, thereby reducing the negative impact of the heat on the circuit itself, peripheral circuits and modules.

[0284] exist Fig.18E and Fig.18FIn the embodiment of the present invention, a supercomputer is shown as an example of a large-scale computer, but a large-scale computer to which a semiconductor device according to one embodiment of the present invention is applied is not limited to this. As a large-scale computer to which a semiconductor device according to one embodiment of the present invention is applied, for example, a computer (server) that provides services, a large-scale general-purpose computer (mainframe), etc. can be cited.

[0285] [Mobile body] A semiconductor device according to one embodiment of the present invention can be applied to a vehicle as a mobile object and the vicinity of a driver's seat of the vehicle.

[0286] Figure 18G This is a diagram showing the periphery of the front windshield in the interior of a car 5600 which is an example of a moving object. Figure 18G Display panel 5601, display panel 5602, display panel 5603 installed on the instrument panel, and display panel 5604 installed on the pillar are shown.

[0287] Display panels 5601 to 5603 can provide various information by displaying a speedometer, a tachometer, a driving distance, a fuel gauge, a gear status, an air conditioning setting, etc. In addition, the user can appropriately change the display content and layout displayed on the display panel according to preference, which can improve the design. Display panels 5601 to 5603 can also be used as lighting devices.

[0288] By displaying an image captured by a camera device (not shown) installed in the car on the display panel 5604, the field of view (blind spot) blocked by the pillar can be supplemented. In other words, by displaying an image captured by a camera device installed outside the car, the blind spot can be supplemented, thereby improving safety. In addition, by displaying an image that supplements the invisible part, safety can be confirmed more naturally and comfortably. The display panel 5604 can also be used as a lighting device.

[0289] Since a semiconductor device according to one embodiment of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of a car. In addition, the chip can also be used in a system for navigation, danger prediction, etc. Information such as navigation and danger prediction can be displayed on display panels 5601 to 5604.

[0290] Although a car is described as an example of a mobile body in the above example, the mobile body is not limited to a car. For example, a tram, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (UAV), an airplane, a rocket), etc. can also be cited as a mobile body, and a semiconductor device according to one embodiment of the present invention can be applied to these mobile bodies to provide a system using artificial intelligence.

[0291] [Electrical products] Fig.18H An electric refrigerator-freezer 5700 is shown as an example of an electric appliance. The electric refrigerator-freezer 5700 includes a housing 5701, a refrigerator door 5702, a freezer door 5703, and the like.

[0292] By applying a semiconductor device according to one embodiment of the present invention to an electric refrigerator-freezer 5700, an electric refrigerator-freezer 5700 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5700 can have a function of automatically generating a menu based on the food stored in the electric refrigerator-freezer 5700 or the expiration date of the food, a function of automatically adjusting the temperature of the electric refrigerator-freezer 5700 according to the stored food, and the like.

[0293] An electric refrigerator-freezer is described as an example of an electrical product, and other electrical products include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0294] The electronic device, the functions of the electronic device, the application examples of artificial intelligence and the effects thereof, and the like described in this embodiment mode can be appropriately combined with the description of other electronic devices.

[0295] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0296] <Notes on the Descriptions in This Manual, etc.> Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0297] The structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0298] In addition, the content (or part thereof) described in a certain embodiment may be applied, combined or replaced with other content (or part thereof) described in that embodiment and / or content (or part thereof) described in one or more other embodiments.

[0299] In addition, the contents described in the embodiments refer to the contents described using various drawings in each embodiment or the contents described using the texts described in the specification.

[0300] In addition, more drawings may be formed by combining a drawing (or part thereof) shown in a certain embodiment with other parts of the drawing, other drawings (or parts thereof) shown in the embodiment, and / or drawings (or parts thereof) shown in one or more other embodiments.

[0301] In addition, in the block diagrams in this specification, the components are classified according to their functions and are represented by independent blocks. However, it is difficult to classify the components according to their functions in actual circuits, and sometimes one circuit involves multiple functions or multiple circuits involve one function. Therefore, the division of the blocks in the block diagram is not limited to the components described in the specification, but can be appropriately different according to the situation.

[0302] In addition, in the drawings, the size, thickness of the layer or area is arbitrarily shown for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. Note that the drawings are schematically shown for the sake of clarity and are not limited to the shapes or values ​​shown in the drawings. For example, the unevenness of the signal, voltage or current caused by noise or timing deviation may be included.

[0303] In addition, in this specification, the words "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, "electrode B on insulating layer A" does not require that electrode B is formed on insulating layer A in direct contact, and may also include a case where other components are included between insulating layer A and electrode B.

[0304] In addition, in this specification, for example, "parallel" refers to a state in which two straight lines are arranged in an angle range of more than -10° and less than 10°. Therefore, the case where the angle is more than -5° and less than 5° is also included. In addition, "perpendicular" and "orthogonal" refer to a state in which two straight lines are arranged in an angle range of more than 80° and less than 100°, for example. Therefore, the case where the angle is more than 85° and less than 95° is also included.

[0305] In addition, in this specification, etc., ordinal numerals such as "first" and "second" are added to avoid confusion between constituent elements, and do not indicate a certain order or sequence such as process order or stacking order. In addition, regarding terms that are not added with ordinal numerals in this specification, etc., ordinal numerals are sometimes added to the terms in the claims to avoid confusion between constituent elements. In addition, regarding terms that are added with ordinal numerals in this specification, etc., different ordinal numerals are sometimes added to the terms in the claims. In addition, regarding terms that are added with ordinal numerals in this specification, etc., their ordinal numerals are sometimes omitted in the claims.

[0306] In this specification, etc., when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (or the first electrode or the first terminal) and "the other of the source and the drain" (or the second electrode or the second terminal) are used. This is because the source and the drain of a transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of a transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode, etc., depending on the situation.

[0307] In addition, in this specification, the terms "electrode" or "wiring" do not limit the function of the constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the terms "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed as one.

[0308] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference from the reference potential. For example, when the reference potential is the ground voltage (ground voltage), voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential.

[0309] In this specification, the words "film" and "layer" may be interchanged depending on the situation or condition. For example, "conductive layer" may be interchanged with "conductive film". Also, for example, "insulating film" may be interchanged with "insulating layer".

[0310] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0311] Note that in this specification, etc., the "on state" of a transistor refers to a state in which the source and drain of the transistor are electrically short-circuited (also referred to as a "conductive state"). In addition, the "off state" of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected (also referred to as a "non-conductive state").

[0312] In addition, in this specification, etc., "on-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the on state. In addition, "off-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the off state.

[0313] In this specification, etc., for example, the channel length of a planar transistor refers to the distance between the source and the drain in the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap or in the area where the channel is formed in a plan view of the transistor.

[0314] In this specification, etc., for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate electrode overlap, or the portion where the source and drain electrodes face each other in the region where the channel is formed.

[0315] In this specification, etc., nodes may be referred to as terminals, wirings, electrodes, conductive layers, conductors, impurity regions, etc. depending on circuit structures, device structures, etc. Terminals, wirings, etc. may also be referred to as nodes.

[0316] In this specification, etc., "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection that can transmit an electric signal between A and B when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between A and B. Note that the case where A and B are electrically connected includes the case where A and B are directly connected. Here, direct connection between A and B means a connection that can transmit an electric signal between A and B through wiring (or electrodes) etc. without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit.

Claims

1. A storage device, comprising: a memory cell comprising a first transistor and a second transistor, The first transistor includes a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer and a second insulating layer. The second transistor includes a second oxide semiconductor layer, the first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer. The first oxide semiconductor layer has a region facing the first conductive layer via the first insulating layer and a region facing the second conductive layer via the second insulating layer when viewed from above. The second oxide semiconductor layer has a region facing the fifth conductive layer via the third insulating layer and a region facing the sixth conductive layer via the fourth insulating layer when viewed from a plan view. The first oxide semiconductor layer is provided in contact with the third conductive layer and the fourth conductive layer, The second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer. The third conductive layer has a region overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer when viewed from a cross section. A first potential supplied to the second conductive layer during a period in which data is written to the memory cell is higher than a second potential supplied to the second conductive layer during a period in which the data is retained in the memory cell. The third potential supplied to the sixth conductive layer during a period in which the data is read from the memory cell is higher than the fourth potential supplied to the sixth conductive layer during a period in which the data is retained in the memory cell. The third potential is lower than the first potential, Furthermore, the fourth potential is lower than the second potential.

2. The storage device according to claim 1, wherein the storage unit comprises a capacitor, And one electrode of the capacitor is electrically connected to the first conductive layer.

3. The storage device according to claim 2, The other electrode of the capacitor is electrically connected to the sixth conductive layer.

4. The storage device according to claim 1, The first insulating layer or the second insulating layer contains hafnium, zirconium, and oxygen.

5. The storage device according to claim 1, The first oxide semiconductor layer and the second oxide semiconductor layer both contain at least indium.

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