Semiconductor structure, semiconductor structure preparation method, memory and memory system

Abstract

The invention provides a semiconductor structure, a semiconductor structure preparation method, a memory and a memory system.The semiconductor structure preparation method comprises the steps that a semiconductor layer is provided, the semiconductor layer comprises an array region and a non-array region, and the array region comprises a plurality of transistor array units; forming a first sacrificial layer on the semiconductor layer; forming a plurality of capacitance holes in the first sacrificial layer in the array region and the non-array region, wherein the capacitance holes extend along the thickness direction of the semiconductor layer; forming a first electrode in the capacitor hole of the array area; removing the first sacrificial layer; forming a capacitor dielectric layer on the surface of the first electrode; and forming a second electrode on one side, deviating from the first electrode, of the capacitor dielectric layer. According to the array substrate preparation method provided by the embodiment of the invention, the sizes of the plurality of capacitor holes in the array region can be kept basically consistent, and the problem that the supporting columns at the edge of the array region topple over after the first sacrificial layer is removed is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing a semiconductor structure, a memory, and a storage system. Background Art

[0002] The semiconductor structure generally includes a storage structure, and word lines and bit lines connected to the storage structure. The storage structure includes transistors and capacitor structures distributed in an array, the bit line is connected to the drain of the transistor, the word line is connected to the gate layer of the transistor, and the source of the transistor is connected to the capacitor structure. In the process of forming the capacitor structure, there are still some problems that need to be further solved. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor structure, a method for preparing the semiconductor structure, a memory and a storage system, which are intended to solve the problem of inconsistent capacitor hole sizes in an array region of the semiconductor structure.

[0004] The present invention provides a method for preparing a semiconductor structure, the method comprising:

[0005] Providing a semiconductor layer, the semiconductor layer comprising an array region and a non-array region, the array region comprising a plurality of transistor array units;

[0006] forming a first sacrificial layer on the semiconductor layer;

[0007] A plurality of capacitor holes are formed in the first sacrificial layer located in the array area and the non-array area, respectively, and the capacitor holes extend along the thickness direction of the semiconductor layer;

[0008] forming a first electrode in the capacitor hole in the array area;

[0009] removing the first sacrificial layer;

[0010] forming a capacitor dielectric layer on a surface of the first electrode;

[0011] A second electrode is formed on a side of the capacitor dielectric layer away from the first electrode.

[0012] In some embodiments, the radial cross-section of the capacitor hole is circular or elliptical; the radial cross-section shape of the capacitor hole located in the array area is the same as the radial cross-section shape of the capacitor hole located in the non-array area.

[0013] In some embodiments, before removing the first sacrificial layer, the method further includes:

[0014] A support structure connected to the first electrode is formed in the capacitor hole located in the array area.

[0015] In some embodiments, the first sacrificial layer includes a first sub-sacrificial layer and a first insulating layer sequentially distributed in a direction away from the semiconductor layer; and removing the first sacrificial layer includes:

[0016] forming a first opening region in the first insulating layer exposing a portion of the first sacrificial sub-layer;

[0017] The first sacrificial sub-layer is removed through the first opening region.

[0018] In some embodiments, the first opening region includes a first opening located in the array region and a second opening located in the non-array region; the first opening region formed in the first insulating layer to expose a portion of the first sub-sacrificial layer includes:

[0019] A plurality of first openings exposing a portion of the first sacrificial sub-layer are formed in a portion of the first insulating layer located in the array region, and a portion of the first insulating layer located in the non-array region is removed to form a second opening.

[0020] In some embodiments, the first sacrificial layer further includes a second sub-sacrificial layer and a second insulating layer sequentially distributed in a direction away from the semiconductor layer, and the second sub-sacrificial layer and the second insulating layer are located between the first sub-sacrificial layer and the semiconductor layer; and removing the first sacrificial layer further includes:

[0021] forming a second opening region in the second insulating layer exposing a portion of the second sacrificial sub-layer, wherein the first opening region and the second opening region overlap in a thickness direction of the semiconductor layer;

[0022] The second sacrificial sub-layer is removed through the second opening region.

[0023] In some embodiments, the capacitor hole located in the non-array area is filled with a second sacrificial layer; the capacitor hole includes a first hole segment located in the first sub-sacrificial layer and a second hole segment located in the second sub-sacrificial layer; before removing the first sub-sacrificial layer through the first opening area, the method further includes:

[0024] At least a portion of the second sacrificial layer located in the first hole segment is removed.

[0025] In some embodiments, before removing the second sacrificial sub-layer through the second opening region, the method further includes:

[0026] The remaining second sacrificial layer is removed.

[0027] In some embodiments, removing at least a portion of the second sacrificial layer located in the first hole segment includes:

[0028] The second sacrificial layer located in the first hole segment is removed by a wet etching process.

[0029] In some embodiments, the material of the second sacrificial layer includes carbon.

[0030] In some embodiments, the first sacrificial layer includes a first sub-sacrificial layer and a first insulating layer sequentially distributed in a direction away from the semiconductor layer; and removing the first sacrificial layer includes:

[0031] removing the portion of the first sacrificial layer located in the non-array area;

[0032] forming a third opening region in the first insulating layer in the array region, wherein the third opening region exposes a portion of the first sacrificial sub-layer;

[0033] The first sacrificial sub-layer is removed through the third opening region.

[0034] In some embodiments, the first sacrificial layer further includes a second sub-sacrificial layer and a second insulating layer sequentially distributed in a direction away from the semiconductor layer, and the second sub-sacrificial layer and the second insulating layer are located between the first sub-sacrificial layer and the semiconductor layer; and removing the first sacrificial layer further includes:

[0035] forming a fourth opening region in the second insulating layer located in the array region, wherein the fourth opening region exposes a portion of the second sacrificial sub-layer, and the fourth opening region overlaps the third opening region in a thickness direction of the semiconductor layer;

[0036] The second sacrificial sub-layer is removed through the fourth opening region.

[0037] In some embodiments, the capacitor hole extends to the semiconductor layer; and forming a first electrode in the capacitor hole in the array region includes:

[0038] A first conductive layer is formed on the bottom surface and the inner side surface of the capacitor hole to form the first electrode in the capacitor hole.

[0039] In some embodiments, forming a capacitor dielectric layer on the surface of the first electrode includes:

[0040] The capacitor dielectric layer is formed on the outer peripheral surface of the first electrode.

[0041] In some embodiments, the material of the first sacrificial layer includes oxide.

[0042] In some embodiments, the material of the first electrode and / or the second electrode includes titanium nitride.

[0043] In some embodiments, removing the first sacrificial layer includes:

[0044] The first sacrificial layer is removed by a wet etching process.

[0045] The present application also provides a semiconductor structure, wherein the semiconductor structure is prepared by any one of the semiconductor structure preparation methods described above, and the semiconductor structure preparation method comprises:

[0046] providing a semiconductor layer, the semiconductor layer comprising a transistor array unit;

[0047] forming a first sacrificial layer on the semiconductor layer, wherein the first sacrificial layer comprises an array region and a non-array region, wherein an orthographic projection of the array region on the semiconductor layer coincides with the transistor unit;

[0048] Forming a plurality of capacitor holes in the array region and the non-array region of the first sacrificial layer, respectively, wherein the capacitor holes extend along a thickness direction of the semiconductor layer;

[0049] forming a first electrode in the capacitor hole in the array area;

[0050] removing the first sacrificial layer;

[0051] forming a capacitor dielectric layer on a surface of the first electrode;

[0052] A second electrode is formed on a side of the capacitor dielectric layer away from the first electrode.

[0053] An embodiment of the present application further provides a memory, which includes the semiconductor structure as described above.

[0054] The present application also provides a storage system, the storage system comprising:

[0055] A memory, wherein the memory is the memory as described above;

[0056] The controller is coupled to the memory and is used for controlling the memory to store data.

[0057] The semiconductor structure preparation method provided in the embodiment of the present application can keep the sizes of the multiple capacitor holes located in the array area basically consistent, especially keep the sizes of the capacitor holes near the non-array area in the array area consistent with the sizes of the capacitor holes in other areas of the array area, thereby avoiding the problem of support columns formed in the capacitor holes toppling over after the first sacrificial layer near the edge of the array area is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0059] Figure 1 A top view of a semiconductor structure after a capacitor hole is formed in the first sacrificial layer during the preparation process of the semiconductor structure provided in an embodiment of the present application;

[0060] Figure 2 for Figure 1 The cross-sectional view along the AA direction;

[0061] Figure 3 A top view of a semiconductor structure provided in an embodiment of the present application after a second sacrificial layer is formed in a capacitor hole during the preparation process of the semiconductor structure;

[0062] Figure 4 for Figure 3 The cross-sectional view along the BB direction;

[0063] Figure 5 A top view of a semiconductor structure provided in an embodiment of the present application after forming and removing a second sacrificial layer in a capacitor hole in an array area during the preparation process of the semiconductor structure;

[0064] Figure 6 for Figure 5 Cross-sectional view along CC direction;

[0065] Figure 7 A cross-sectional view after forming a first electrode and a support layer in the semiconductor structure preparation process provided in an embodiment of the present application;

[0066] Figure 8 for Figure 7 The cross-sectional view along the DD direction;

[0067] Fig. 9 A top view of a semiconductor structure after a third hard mask is formed in the process of preparing the semiconductor structure provided in an embodiment of the present application;

[0068] Fig.10 for Fig. 9 A cross-sectional view along the EE direction;

[0069] Fig.11 A top view of a semiconductor structure after a first opening area is formed in the process of preparing the semiconductor structure provided in an embodiment of the present application;

[0070] Fig.12 for Fig.11 A cross-sectional view along the FF direction;

[0071] Fig.13 A top view of a semiconductor structure provided in an embodiment of the present application after removing a portion of the second sacrificial layer in a capacitor hole in a non-array region during the preparation process of the semiconductor structure;

[0072] Fig.14 for Fig.13 The cross-sectional view along the GG direction;

[0073] Fig.15 A top view after removing the first sub-sacrificial layer during the preparation process of the semiconductor structure provided in an embodiment of the present application;

[0074] Fig.16 for Fig.15 A cross-sectional view along the HH direction;

[0075] Fig.17 A top view of the semiconductor structure provided in an embodiment of the present application after removing the second sacrificial layer in the capacitor hole in the non-array area during the preparation process of the semiconductor structure;

[0076] Fig.18 for Fig.17 A cross-sectional view along direction II;

[0077] Fig.19 A top view of a semiconductor structure after a second opening area is formed during the preparation process of the semiconductor structure provided in an embodiment of the present application;

[0078] Fig. 20 for Fig.19 The cross-sectional view along the JJ direction;

[0079] Fig.21 A top view after removing the second sacrificial sub-layer during the preparation process of the semiconductor structure provided in an embodiment of the present application;

[0080] Fig. 22 for Fig.21 A cross-sectional view along the KK direction;

[0081] Fig.23 A top view of a semiconductor structure provided in an embodiment of the present application after forming a capacitor dielectric layer, a second electrode and a third insulating layer in the process of preparing the semiconductor structure;

[0082] Fig.24 for Fig.23 Cross-sectional view along LL direction;

[0083] Fig.25 A top view of a semiconductor structure after a planarization layer is formed during the preparation process of the semiconductor structure provided in an embodiment of the present application;

[0084] Fig.26 for Fig.25 Cross-sectional view along MM direction;

[0085] Fig. 27 A top view of a planarization layer after grinding during the preparation of a semiconductor structure provided in an embodiment of the present application;

[0086] Fig.28 for Fig. 27 The cross-sectional view along the NN direction;

[0087] Fig.29 A top view after a third opening region is formed during the preparation process of the semiconductor structure provided in an embodiment of the present application;

[0088] Fig.30 for Fig.29 The cross-sectional view along the OO direction;

[0089] Fig.31 A top view of the semiconductor structure after the first sub-sacrificial layer in the array area is removed during the preparation process of the semiconductor structure provided in the embodiment of the present application;

[0090] Fig.32 for Fig.31 Cross-sectional view along the PP direction;

[0091] Fig.33 A top view of a semiconductor structure after a fourth opening region is formed during the preparation process of the semiconductor structure provided in an embodiment of the present application;

[0092] Fig.34 for Fig.33 Sectional view along QQ direction;

[0093] Fig.35 A flowchart of an embodiment of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0094] Fig.36 A schematic diagram of the structure of an embodiment of a storage system provided in an embodiment of the present application;

[0095] Fig.37 A schematic diagram of the structure of an embodiment of an electronic device provided in an embodiment of the present application.

[0096] Semiconductor structure 100; semiconductor layer 110; first sacrificial layer 120; array area 1200; non-array area 1201; capacitor hole 121; first hole segment 1211; second hole segment 1212; support structure 122; second sacrificial layer 123; first sub-sacrificial layer 124; first insulating layer 125; first opening area 1250; first opening 1251; second opening 1252; second sub-sacrificial layer 126; second insulating layer 127; second opening area 1270; third opening 1271; fourth opening 1272; third opening area 1273; fourth opening area 1274; first electrode 130; capacitor dielectric layer 131; second electrode 132; third insulating layer 133; first hard mask layer 140; fourth insulating layer 150; second hard mask layer 160; support layer 170; third hard mask layer 180; spacing hole 181; planarization layer 190. DETAILED DESCRIPTION

[0097] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the drawings in the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0098] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present disclosure.

[0099] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0100] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0101] The embodiments of the present application provide a method for preparing a semiconductor structure and a semiconductor structure, which are described in detail below.

[0102] First, an embodiment of the present application provides a method for preparing a semiconductor structure.

[0103] Fig.35 A flowchart of an embodiment of a method for preparing a semiconductor structure provided in an embodiment of the present application.

[0104] like Fig.35 As shown, the semiconductor structure preparation method includes steps S210 to S270, wherein:

[0105] S210, providing a semiconductor layer, the semiconductor layer including an array region and a non-array region, the array region including a plurality of transistor array units;

[0106] S220, forming a first sacrificial layer on the semiconductor layer;

[0107] S230, forming a plurality of capacitor holes in the array area and the non-array area, respectively, wherein the capacitor holes extend along the thickness direction of the semiconductor layer;

[0108] S240, forming a first electrode in the capacitor hole in the array area;

[0109] S250, removing the first sacrificial layer;

[0110] S260, forming a capacitor dielectric layer on the surface of the first electrode;

[0111] S270, forming a second electrode on a side of the capacitor dielectric layer away from the first electrode.

[0112] It should be understood that the steps shown in the above preparation method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0113] The semiconductor structure preparation method provided in the embodiment of the present application can keep the sizes of the multiple capacitor holes located in the array area basically consistent, especially keep the sizes of the capacitor holes near the non-array area in the array area consistent with the sizes of the capacitor holes in other areas of the array area, thereby avoiding the problem of support columns formed in the capacitor holes toppling over after the first sacrificial layer near the edge of the array area is removed.

[0114] It is understandable that when forming capacitor holes in a preset area (e.g., an array area) of the first sacrificial layer, there is a large difference in the etch loading near the edge of the preset area, which will cause different degrees of under-etching, resulting in the size of the capacitor hole near the edge of the preset area not meeting expectations. When a pillar capacitor structure is formed in the capacitor hole, the support column structure formed in the capacitor hole near the edge of the preset area is prone to peeling and tipping problems in the capacitor hole near the edge of the preset area due to the problem of under-etching of the capacitor hole when removing the first sacrificial layer.

[0115] The semiconductor structure preparation method provided in the embodiment of the present application forms a plurality of capacitor holes in the first sacrificial layer located in the array area and the non-array area respectively, so that the size of the capacitor holes at the edge of the array area is basically consistent with the size of the capacitor holes in other areas of the array area, so that the support column structure formed in the array area is basically the same, and there will be no problem of peeling and tilting of the support columns in the capacitor holes near the edge of the preset area when the first sacrificial layer is removed due to insufficient etching (under-etch) of the capacitor holes.

[0116] Figures 1 to 34 The top view and cross-sectional view of the semiconductor structure provided in the embodiment of the present application at different process steps. Figures 1 to 34 Steps S210 to S270 of the semiconductor structure preparation method provided in the embodiment of the present application are described in detail, wherein:

[0117] Step S210 , providing a semiconductor layer 110 , wherein the semiconductor layer 110 includes an array region 1200 and a non-array region 1201 , and the array region 1200 includes a plurality of transistor array units.

[0118] The array region 1200 of the semiconductor layer 110 is arrayed with a plurality of transistor array units (not shown in the figure), and the transistor array unit includes a source, a drain, a channel portion connected between the source and the drain, and a gate layer opposite to the channel portion. The material of the channel portion can be selected from at least one of single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The materials of the source, drain, and gate layer can be selected from different or the same conductive materials, and the conductive material includes any one or combination of conductive materials such as tungsten, cobalt, copper, aluminum, or polycrystalline silicon, doped crystalline silicon, etc.

[0119] The semiconductor layer 110 may be prepared in advance or temporarily prepared. For example, a substrate may be provided, and a source, a drain, a channel portion, and a gate layer of a transistor array unit may be formed on the substrate to prepare the semiconductor layer 110. The order of forming the source, the drain, the channel portion, and the gate layer is not limited here, as long as the transistor unit can be formed. In addition, insulating layers are provided between the channel portion and the gate layer, and between the gate layer and the source and the drain, respectively, which will not be described in detail here.

[0120] Step S220 , forming a first sacrificial layer 120 on the semiconductor layer 110 .

[0121] Part of the first sacrificial layer 120 is located in the array area 1200 of the semiconductor layer 110, and the other part is located in the non-array area 1201 of the semiconductor layer 110. The first sacrificial layer 120 plays a supporting and isolating role in the preparation process of the semiconductor structure. In the preparation process of the semiconductor structure, at least a part of the first sacrificial layer 120 needs to be removed.

[0122] In some embodiments, the material of the first sacrificial layer 120 includes oxide.

[0123] In an embodiment of the present application, a first sacrificial layer 120 may be formed on the semiconductor layer 110 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0124] In some embodiments, the first sacrificial layer 120 further includes a second sub-sacrificial layer 126 and a second insulating layer 127 sequentially distributed in a direction away from the semiconductor layer 110, and the second sub-sacrificial layer 126 and the second insulating layer 127 are located between the first sub-sacrificial layer 124 and the semiconductor layer 110. Specifically, the second sub-sacrificial layer 126, the second insulating layer 127, the first sub-sacrificial layer 124 and the first insulating layer 125 can be sequentially formed on the semiconductor layer 110 to form the first sacrificial layer 120. Among them, the first sub-sacrificial layer 124 and the first insulating layer 125 are different materials, the second sub-sacrificial layer 126 and the second insulating layer 127 are different materials, and the first sub-sacrificial layer 124 and the second sub-sacrificial layer 126 can be the same material, for example, the first sub-sacrificial layer 124 and the second sub-sacrificial layer 126 are both oxides (for example, silicon dioxide). The first insulating layer 125 and the second insulating layer 127 can be the same material, for example, the materials of the first insulating layer 125 and the second insulating layer 127 can be silicon monoxide, silicon boron nitride (SiBN), etc.

[0125] In other embodiments, the first sacrificial layer 120 may also include only the first sub-sacrificial layer 124 and the first insulating layer 125 which are sequentially distributed in a direction away from the semiconductor layer 110. Alternatively, the first sacrificial layer 120 may also include only the first sub-sacrificial layer 124, without including the first insulating layer 125. Of course, when the first sacrificial layer 120 includes the first insulating layer 125 and the second insulating layer 127, the first insulating layer 125 and the second insulating layer 127 can play a good supporting role for the first electrode 130, the supporting structure 122, etc. formed in the capacitor hole 121.

[0126] Step S230 , forming a plurality of capacitor holes 121 in the first sacrificial layer 120 located in the array area 1200 and the non-array area 1201 , respectively. The capacitor holes 121 extend along the thickness direction of the semiconductor layer 110 .

[0127] By forming a plurality of capacitor holes 121 in the first sacrificial layer 120 located in the array area 1200 and the non-array area 1201 respectively, the sizes of the plurality of capacitor holes 121 located in the array area 1200 can be kept basically consistent, especially the sizes of the capacitor holes 121 in the array area 1200 close to the non-array area 1201 can be kept consistent with the sizes of the capacitor holes 121 in other areas of the array area 1200.

[0128] The radial cross-sectional shape of the capacitor hole 121 located in the array area 1200 is the same as the radial cross-sectional shape of the capacitor hole 121 located in the non-array area 1201. The radial cross-sectional shape of the capacitor hole 121 is circular or elliptical. Of course, the radial cross-sectional shape of the capacitor hole 121 can also be rectangular, polygonal, etc.

[0129] A plurality of capacitor holes 121 having substantially the same or identical critical dimensions (CD pitch) can be formed in the array region 1200 and the non-array region 1201 respectively by two orthogonal double patterning processes (DP) along the word lines and the bit lines. When the radial cross section of the capacitor hole 121 is circular, the critical dimension of the capacitor hole 121 is the diameter of the radial cross section of the capacitor hole 121; when the radial cross section of the capacitor hole 121 is elliptical, the critical dimension of the capacitor hole 121 is the length of the major axis and the minor axis of the capacitor hole 121.

[0130] Specifically, Figure 1 and Figure 2 As shown, a second sub-sacrificial layer 126, a second insulating layer 127, a first sub-sacrificial layer 124 and a first insulating layer 125 are sequentially formed on the semiconductor layer 110 to form a first sacrificial layer 120, and then a first hard mask layer 140 (HM) is also formed on the first sacrificial layer 120. After that, the first hard mask layer 140 and the first sacrificial layer 120 are etched to form capacitor holes 121 in the array area 1200 and the non-array area 1201, respectively. The material of the first hard mask layer 140 may include polysilicon (poly).

[0131] like Figure 3 and Figure 4As shown, after forming the capacitor hole 121, the second sacrificial layer 123 can be filled in the capacitor hole 121 located in the array area 1200 and the non-array area 1201, and then the first hard mask layer 140 remaining on the surface of the first insulating layer 125 of the first sacrificial layer 120 is polished by chemical mechanical polishing (CMP) to remove the first hard mask layer 140. The material of the second sacrificial layer 123 can be carbon. Among them, the remaining first hard mask layer 140 serves as a stop layer for chemical mechanical polishing, and some buffer is added during the chemical mechanical polishing process to remove the first hard mask layer 140 and finally stay on the first insulating layer 125.

[0132] like Figure 5 and Figure 6 As shown, after removing the first hard mask layer 140 , the second sacrificial layer 123 filled in the capacitor hole 121 of the array area 1200 may be removed so as to prepare an electrode structure in the capacitor hole 121 of the array area 1200 .

[0133] A second hard mask layer 160 may be formed on the surface of the first sacrificial layer 120 facing away from the semiconductor layer 110, and the second hard mask layer 160 covers the array area 1200 and the non-array area 1201; then, the portion of the second hard mask layer 160 covering the array area 1200 of the first sacrificial layer 120 is removed, and the portion of the second hard mask layer 160 located in the non-array area 1201 is retained. Finally, the portion of the second sacrificial layer 123 located in the capacitor hole 121 in the array area 1200 is removed, while the portion of the second sacrificial layer 123 located in the capacitor hole 121 in the non-array area 1201 is retained in the capacitor hole 121 because it is covered by the second hard mask layer 160.

[0134] In some embodiments, the second sacrificial layer 123 located in the capacitor hole 121 of the array area 1200 may be removed by a wet etching process. Of course, the second sacrificial layer 123 located in the capacitor hole 121 of the array area 1200 may also be removed by a dry etching process or other processes.

[0135] In some embodiments, Figure 2 , Figure 4 and Figure 6 As shown, the semiconductor structure 100 further includes a fourth insulating layer 150, which is located between the semiconductor layer 110 and the first sacrificial layer 120. The fourth insulating layer 150 is an etching stop layer, and when forming the capacitor hole 121, the etching stop layer is used as the etching end point. The material of the fourth insulating layer 150 can be silicon nitride (SiN) doped with boron (B) or carbon (C), or can be other insulating materials. Figure 8As shown, the capacitor hole 121 located in the array area 1200 passes through the fourth insulating layer 150 and extends to the semiconductor layer 110 .

[0136] Specifically, the portion of the second sacrificial layer 123 located in the capacitor hole 121 in the array area 1200 may be removed, and the portion of the fourth insulating layer 150 overlapping the capacitor hole 121 located in the array area 1200 may be removed, so that the capacitor hole 121 passes through the fourth insulating layer 150 and extends to the semiconductor layer 110. Of course, when the capacitor hole 121 is formed in the first sacrificial layer 120, a portion of the fourth insulating layer 150 may be directly removed, so that the capacitor hole 121 passes through the fourth insulating layer 150 and extends to the semiconductor layer 110.

[0137] Step S240 , forming a first electrode 130 in the capacitor hole 121 located in the array area 1200 .

[0138] like Figure 7 and Figure 8 As shown, the first electrode 130 can be formed on the inner side and bottom surface of the capacitor hole 121 located in the array area 1200, so that the first electrode 130 in the capacitor hole 121 has a larger area. Since the capacitor hole 121 located in the array area 1200 extends to the semiconductor layer 110, the first electrode 130 formed in the capacitor hole 121 can be connected to the source of the thin film transistor array unit of the semiconductor layer 110. The material of the first electrode 130 can be titanium nitride (TiN) or other conductive materials.

[0139] In some embodiments, the capacitor hole 121 extends to the semiconductor layer 110. The step of forming the first electrode 130 in the capacitor hole 121 of the array area 1200 includes: forming a first conductive layer on the bottom surface and inner side surface of the capacitor hole 121 to form the first electrode 130 in the capacitor hole 121.

[0140] Specifically, a first conductive layer can be formed on the surface of the first sacrificial layer 120 facing away from the semiconductor layer 110 and on the inner surface of the capacitor hole 121 located in the array area 1200. Then, the portion of the first conductive layer located on the surface of the first sacrificial layer 120 facing away from the semiconductor layer 110 is removed, and the portion of the first conductive layer located on the inner surface of the capacitor hole 121 in the array area 1200 is the first electrode 130.

[0141] Step S250 , removing the first sacrificial layer 120 .

[0142] Among them, only the portion of the first sacrificial layer 120 located in the array area 1200 may be removed, or both the portions of the first sacrificial layer 120 located in the array area 1200 and the non-array area 1201 may be removed. When the first sacrificial layer 120 includes the first sub-sacrificial layer 124 but does not include the second sub-sacrificial layer 126, only the portion of the first sub-sacrificial layer 124 located in the array area 1200 may be removed, or both the portions of the first sub-sacrificial layer 124 located in the array area 1200 and the non-array area 1201 may be removed. When the first sacrificial layer 120 includes the first sub-sacrificial layer 124 and the second sub-sacrificial layer 126, only the portions of the first sub-sacrificial layer 124 and the second sub-sacrificial layer 126 located in the array area 1200 may be removed, or both the portions of the first sub-sacrificial layer 124 and the second sub-sacrificial layer 126 located in the array area 1200 may be removed.

[0143] In some embodiments, the step of removing the first sacrificial layer 120 may include removing the first sacrificial layer 120 by a wet etching process.

[0144] In some embodiments, before removing the first sacrificial layer 120, the semiconductor structure preparation method further includes: forming a support structure 122 connected to the first electrode 130 in the capacitor hole 121 of the array area 1200. Thus, the first electrode 130 can be supported by the support structure 122, thereby improving the structural strength and stability of the first electrode 130, and avoiding the first electrode 130 from tipping over, deformation, and other problems after the first sacrificial layer 120 is removed.

[0145] Specifically, Figure 7 and Figure 8 As shown, a support layer 170 may be formed on the surface of the first sacrificial layer 120 away from the semiconductor layer 110 and on the side of the first electrode 130 away from the inner surface of the capacitor hole 121, and the portion of the support layer 170 located on the side of the first electrode 130 away from the inner surface of the capacitor hole 121 forms a support structure 122 supporting the first electrode 130. The material of the support layer 170 may be polysilicon.

[0146] In some embodiments, the first sacrificial layer 120 includes a first sub-sacrificial layer 124 and a first insulating layer 125 sequentially distributed in a direction away from the semiconductor layer 110; the step of removing the first sacrificial layer 120 includes:

[0147] Forming a first opening region 1250 in the first insulating layer 125 to expose a portion of the first sacrificial sub-layer 124;

[0148] The first sacrificial sub-layer 124 is removed through the first opening region 1250 .

[0149] The first insulating layer 125 can be etched to form a first opening area 1250 in the first insulating layer 125 that exposes a portion of the first sub-sacrificial layer 124, and then a wet etching process is used to remove the first sub-sacrificial layer 124 under the first insulating layer 125 through the first opening area 1250 of the first insulating layer 125.

[0150] like Fig.11 and Fig.12 As shown, the first opening region 1250 includes a first opening 1251 located in the array region 1200, and a second opening 1252 located in the non-array region 1201. The first opening 1251 of the first insulating layer 125 can quickly remove the portion of the first sub-sacrificial layer 124 located in the array region 1200, and the second opening 1252 of the first insulating layer 125 can quickly remove the portion of the first sub-sacrificial layer 124 located in the non-array region 1201.

[0151] In some embodiments, the step of forming a first opening area 1250 in the first insulating layer 125 exposing a portion of the first sub-sacrificial layer 124 includes: forming a plurality of first openings 1251 exposing a portion of the first sub-sacrificial layer 124 in the portion of the first insulating layer 125 located in the array area 1200, and removing the portion of the first insulating layer 125 located in the non-array area 1201 to form a second opening 1252.

[0152] Specifically, Fig. 9 and Fig.10 As shown, a third hard mask layer 180 may be formed on a side of the support layer 170 away from the first sacrificial layer 120, and then a spacing hole 181 located in the array area 1200 is formed in the third hard mask layer 180, and a portion of the third hard mask layer 180 located in the non-array area 1201 is removed, wherein the spacing hole 181 located in the array area 1200 exposes a portion of the first insulating layer 125. Thereafter, the portion of the first insulating layer 125 not covered by the third hard mask layer 180 is etched to form a first opening region 1250 in the first insulating layer 125.

[0153] like Fig.13 and Fig.14 As shown, the capacitor hole 121 located in the non-array area 1201 is filled with the second sacrificial layer 123. In some embodiments, before removing the first sub-sacrificial layer 124 through the first opening area 1250, the semiconductor structure preparation method further includes: removing at least a portion of the second sacrificial layer 123 located in the capacitor hole 121 in the non-array area 1201, so as to quickly remove the first sub-sacrificial layer 124 in the non-array area 1201 through the inner surface of the capacitor hole 121 in the non-array area 1201 by using a wet etching process.

[0154] Specifically, the first sacrificial layer 120 further includes a second sub-sacrificial layer 126 and a second insulating layer 127 sequentially distributed in a direction away from the semiconductor layer 110, and the second sub-sacrificial layer 126 and the second insulating layer 127 are located between the first sub-sacrificial layer 124 and the semiconductor layer 110. The capacitor hole 121 located in the non-array area 1201 is filled with the second sacrificial layer 123. The capacitor hole 121 includes a first hole segment 1211 located in the first sub-sacrificial layer 124 and a second hole segment 1212 located in the second sub-sacrificial layer 126. Before removing the first sub-sacrificial layer 124 through the first opening area 1250, the semiconductor structure preparation method further includes: removing at least a portion of the second sacrificial layer 123 located in the first hole segment 1211, so as to facilitate the removal of the first sub-sacrificial layer 124 in the non-array area 1201.

[0155] The step of removing at least part of the second sacrificial layer 123 in the first hole segment 1211 may include: removing the second sacrificial layer 123 in the first hole segment 1211 by wet etching. Of course, the second sacrificial layer 123 in the first hole segment 1211 may be removed by dry etching.

[0156] Afterwards, if Fig.15 and Fig.16 As shown, the portions of the first sacrificial sub-layer 124 located in the array area 1200 and the non-array area 1201 may be removed by a wet etching process.

[0157] like Figure 2 and Figure 4 As shown, the first sacrificial layer 120 further includes a second sub-sacrificial layer 126 and a second insulating layer 127 sequentially distributed in a direction away from the semiconductor layer 110, and the second sub-sacrificial layer 126 and the second insulating layer 127 are located between the first sub-sacrificial layer 124 and the semiconductor layer 110. In some embodiments, as Figures 19 to 22 As shown, the step of removing the first sacrificial layer 120 further includes:

[0158] A second opening region 1270 exposing a portion of the second sacrificial sub-layer 126 is formed in the second insulating layer 127 , and the first opening region 1250 and the second opening region 1270 overlap in the thickness direction of the semiconductor layer 110 ;

[0159] The second sacrificial sub-layer 126 is removed through the second opening region 1270 .

[0160] Among them, Fig.19 and Fig. 20As shown, after removing the first sub-sacrificial layer 124, the second insulating layer 127 can be etched through the first opening region 1250 of the first insulating layer 125 to form a second opening region 1270 in the second insulating layer 127. The second opening region 1270 overlaps with the first opening region 1250, and the second opening region 1270 exposes a portion of the second sub-sacrificial layer 126. Afterwards, the second sub-sacrificial layer 126 located in the array area 1200 and the non-array area 1201 can be removed through the second opening region 1270 by a wet etching process.

[0161] like Fig.19 and Fig. 20 As shown, the second opening region 1270 includes a third opening 1271 located in the array region 1200, and a fourth opening 1272 located in the non-array region 1201. The third opening 1271 of the second insulating layer 127 can quickly remove the portion of the second sub-sacrificial layer 126 located in the array region 1200, and the fourth opening 1272 of the second insulating layer 127 can quickly remove the portion of the second sub-sacrificial layer 126 located in the non-array region 1201.

[0162] In some embodiments, the step of forming a second opening area 1270 in the second insulating layer 127 to expose a portion of the second sub-sacrificial layer 126 includes: forming a plurality of third openings 1271 to expose a portion of the second sub-sacrificial layer 126 in the portion of the second insulating layer 127 located in the array area 1200, and removing the portion of the second insulating layer 127 located in the non-array area 1201 to form a fourth opening 1272.

[0163] The third opening 1271 of the second insulating layer 127 overlaps with the first opening 1251 of the first insulating layer 125, and the second insulating layer 127 can be etched through the first opening 1251 of the first insulating layer 125 to form the third opening 1271 in the second insulating layer 127. The fourth opening 1272 of the second insulating layer 127 overlaps with the second opening 1252 of the first insulating layer 125, and the second insulating layer 127 can be etched through the second opening 1252 of the first insulating layer 125 to form the fourth opening 1272 in the second insulating layer 127.

[0164] In some embodiments, Fig.19 and Fig. 20 As shown, before removing the second sub-sacrificial layer 126 through the second opening area 1270 , the semiconductor structure preparation method further includes: removing the remaining second sacrificial layer 123 so as to facilitate removing the second sub-sacrificial layer 126 located in the non-array area 1201 through the inner surface of the second hole segment 1212 .

[0165] In other embodiments, Figures 29 to 34As shown, the first sacrificial layer 120 includes a first sub-sacrificial layer 124 and a first insulating layer 125 sequentially distributed in a direction away from the semiconductor layer 110. Figure 29 to Figure 32 As shown, the step of removing the first sacrificial layer 120 may include:

[0166] The portion of the first sacrificial layer 120 located in the non-array area 1201 is removed;

[0167] A third opening region 1273 is formed in the first insulating layer 125 of the array region 1200 , and the third opening region 1273 exposes a portion of the first sacrificial sub-layer 124 ;

[0168] The first sub-sacrificial layer 124 is removed through the third opening region 1273 .

[0169] Among them, Fig.29 and Fig.30 As shown, the first sub-sacrificial layer 124 and the first insulating layer 125 located in the non-array area 1201 can be removed. In addition, a third opening area 1273 exposing a portion of the first sub-sacrificial layer 124 is formed in the portion of the first insulating layer 125 located in the array area 1200. The method of forming the third opening area 1273 can refer to the method of forming the first opening area 1250 described above, which will not be repeated here. Then, as Fig.31 and Fig.32 As shown, the first sacrificial sub-layer 124 located in the array area 1200 can be removed through the third opening area 1273 of the first insulating layer 125 by a wet etching process.

[0170] In some embodiments, the first sacrificial layer 120 further includes a second sub-sacrificial layer 126 and a second insulating layer 127 sequentially distributed in a direction away from the semiconductor layer 110, and the second sub-sacrificial layer 126 and the second insulating layer 127 are located between the first sub-sacrificial layer 124 and the semiconductor layer 110. Fig.33 and Fig.34 As shown, the step of removing the first sacrificial layer 120 may further include:

[0171] A fourth opening region 1274 is formed in the second insulating layer 127 of the array region 1200 , wherein the fourth opening region 1274 exposes a portion of the second sacrificial sub-layer 126 , and in the thickness direction of the semiconductor layer 110 , the fourth opening region 1274 overlaps with the third opening region 1273 ;

[0172] The second sacrificial sub-layer 126 is removed through the fourth opening region 1274 .

[0173] like Fig.31 and Fig.32As shown, the second insulating layer 127 can be etched through the third opening region 1273 of the first insulating layer 125 to form a fourth opening region 1274 exposing the second sub-sacrificial portion in the second insulating layer 127. Afterwards, the second sub-sacrificial layer 126 can be etched through the fourth opening region 1274 using a wet etching process to remove the second sub-sacrificial layer 126, thereby forming Fig. 22 The structure shown is after the first sacrificial layer 124 and the second sacrificial layer 126 of the first sacrificial layer 120 are removed.

[0174] Step S260 , forming a capacitor dielectric layer 131 on the surface of the first electrode 130 .

[0175] The capacitor dielectric layer 131 may be made of Hi-K material or other insulating materials. In some embodiments, the step of forming the capacitor dielectric layer 131 on the surface of the first electrode 130 includes: forming the capacitor dielectric layer 131 on the outer peripheral surface of the first electrode 130 .

[0176] Specifically, Fig.23 and Fig.24 As shown, a capacitor dielectric layer 131 can be formed on the surface of the first electrode 130 facing away from the support structure 122, the surface of the support structure 122 facing away from the semiconductor layer 110, and the surface of the fourth insulating layer 150 located in the non-array area 1201, and then the capacitor dielectric layer 131 on the surface of the fourth insulating layer 150 located in the non-array area 1201 is removed.

[0177] Step S270 , forming a second electrode 132 on a side of the capacitor dielectric layer 131 away from the first electrode 130 .

[0178] By forming the second electrode 132 on the side of the capacitor dielectric layer 131 away from the first electrode 130, each first electrode 130 can be opposite to the second electrode 132, thereby forming a capacitor structure connected to the source of each transistor. The material of the second electrode 132 can be the same as or different from the material of the first electrode 130. In some embodiments, the material of the first electrode 130 and / or the second electrode 132 includes titanium nitride.

[0179] The semiconductor structure preparation method provided in the embodiment of the present application forms a plurality of capacitor holes 121 in the first sacrificial layer 120 located in the array area 1200 and the non-array area 1201 respectively, forms a first electrode 130 in the capacitor hole 121 located in the array area 1200, and then removes the first sacrificial layer 120 as a whole. This allows the sizes of the plurality of capacitor holes 121 located in the array area 1200 to remain basically consistent, especially allows the sizes of the capacitor holes 121 in the array area 1200 close to the non-array area 1201 to remain consistent with the sizes of the capacitor holes 121 in other areas of the array area 1200, thereby avoiding the problem of support pillars tipping over after the first sacrificial layer 120 at the edge of the array area 1200 is removed.

[0180] In some embodiments, Fig.23 and Fig.24 As shown, the semiconductor structure preparation method further includes: forming a third insulating layer 133 on the surface of the second electrode 132 away from the first electrode 130. The material of the third insulating layer 133 can be polycrystalline silicon germanium (SiGe poly) or other insulating materials.

[0181] Among them, Figure 25 to Figure 28 As shown, the method for preparing the semiconductor structure further includes: forming a planarization layer 190 on the third insulating layer 133 and the fourth insulating layer 150 located in the non-array area 1201 .

[0182] Specifically, Fig.25 and Fig.26 As shown, a planarization layer 190 is formed on the third insulation layer 133 and the fourth insulation layer 150 located in the non-array area 1201. The material of the planarization layer 190 can be an oxide insulation material. Then, as shown in FIG. Fig. 27 and Fig.28 As shown, the planarization layer 190 is polished by chemical mechanical polishing (CMP) to form the semiconductor structure 100 .

[0183] An embodiment of the present application also provides a semiconductor structure, which is prepared by using the semiconductor structure preparation method in any of the above embodiments. Since the semiconductor structure adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0184] An embodiment of the present application also provides a memory, which includes a semiconductor structure, and the semiconductor structure is prepared using the semiconductor structure preparation method in any of the above-mentioned embodiments. Since the present memory adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be described one by one here.

[0185] See also Fig.36 The embodiment of the present application also provides a storage system 1, which includes a controller 30 and a memory 10. The controller 30 is connected to the memory 10 and is used to control the memory 10 to store data; wherein the memory 10 includes the semiconductor structure 100 in any of the above embodiments.

[0186] The semiconductor structure 100 may be an array wafer memory device, or a device combined with a CMOS (complementary metal oxide semiconductor) peripheral circuit.

[0187] Specifically, the semiconductor structure 100 can be stacked with the peripheral circuit or staggered with the peripheral circuit, which is not limited in the present application. The peripheral circuit is electrically connected to the semiconductor structure 100 to transmit signals to the semiconductor structure 100. The peripheral circuit can be used for logical operations and to control and detect the switching state of each storage unit in the semiconductor structure 100 through metal wiring to achieve data storage and reading.

[0188] Specifically, the above-mentioned memory 10 can be a DRAM memory. Without violating the disclosure or teaching of this application, the memory 10 can also be other types of volatile memories such as a dependent data memory that serves as a temporary storage medium for an operating system or other running programs (which can be called system memory).

[0189] The controller 30 may control the memory 10 through the channel CH, and the memory 10 may perform an operation based on the control of the controller 30 in response to a request from the host 20. The memory 10 may receive a command CMD and an address ADDR from the controller 30 through the channel CH and access an area selected from the memory cell array in response to the address. In other words, the memory 10 may perform an internal operation corresponding to the command on the area selected by the address.

[0190] In some embodiments, the storage system 1 may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), an eMCP, an MCP, a secure digital card in the form of SD, mini SD and micro SD, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0191] Specifically, the storage system 1 can be used in terminal products such as computers, televisions, set-top boxes, and vehicles.

[0192] See also Fig.37The embodiment of the present application also provides an electronic device 3, which includes a central processing unit 2 and the above-mentioned storage system 1 provided in the embodiment of the present application. Specifically, the electronic device 3 can be any device that can store data, such as a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, etc.

[0193] The central processing unit 2 is used to exchange information and data with the storage system 1 .

[0194] An electronic device provided in an embodiment of the present application has the same beneficial effects as the above-mentioned storage system due to the provision of the storage system provided in an embodiment of the present application.

[0195] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0196] The semiconductor structure, semiconductor structure preparation method, memory and storage system provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a semiconductor layer, the semiconductor layer comprising an array region and a non-array region, the array region comprising a plurality of transistor array units; forming a first sacrificial layer on the semiconductor layer; A plurality of capacitor holes are formed in the first sacrificial layer located in the array area and the non-array area, respectively, and the capacitor holes extend along the thickness direction of the semiconductor layer; forming a first electrode in the capacitor hole in the array area; removing the first sacrificial layer; forming a capacitor dielectric layer on a surface of the first electrode; A second electrode is formed on a side of the capacitor dielectric layer away from the first electrode.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The radial cross-section of the capacitor hole is circular or elliptical; the radial cross-section shape of the capacitor hole located in the array area is the same as the radial cross-section shape of the capacitor hole located in the non-array area.

3. The method for preparing a semiconductor structure according to claim 1, wherein: Before removing the first sacrificial layer, the method further includes: A support structure connected to the first electrode is formed in the capacitor hole located in the array area.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The first sacrificial layer comprises a first sub-sacrificial layer and a first insulating layer sequentially distributed in a direction away from the semiconductor layer; The removing the first sacrificial layer comprises: forming a first opening region in the first insulating layer exposing a portion of the first sacrificial sub-layer; The first sacrificial sub-layer is removed through the first opening region.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The first opening region includes a first opening located in the array region and a second opening located in the non-array region; The forming of a first opening region in the first insulating layer exposing a portion of the first sub-sacrificial layer comprises: A plurality of first openings exposing a portion of the first sacrificial sub-layer are formed in a portion of the first insulating layer located in the array region, and a portion of the first insulating layer located in the non-array region is removed to form a second opening.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that: The first sacrificial layer further includes a second sub-sacrificial layer and a second insulating layer sequentially distributed in a direction away from the semiconductor layer, and the second sub-sacrificial layer and the second insulating layer are located between the first sub-sacrificial layer and the semiconductor layer; The removing of the first sacrificial layer further comprises: forming a second opening region in the second insulating layer exposing a portion of the second sacrificial sub-layer, wherein the first opening region and the second opening region overlap in a thickness direction of the semiconductor layer; The second sacrificial sub-layer is removed through the second opening region.

7. The method for preparing a semiconductor structure according to claim 6, wherein: The capacitor hole located in the non-array area is filled with a second sacrificial layer; the capacitor hole includes a first hole segment located in the first sub-sacrificial layer and a second hole segment located in the second sub-sacrificial layer; Before removing the first sacrificial sub-layer through the first opening region, the method further includes: At least a portion of the second sacrificial layer located in the first hole segment is removed.

8. The method for preparing a semiconductor structure according to claim 7, wherein: Before removing the second sacrificial sub-layer through the second opening area, the method further includes: The remaining second sacrificial layer is removed.

9. The method for preparing a semiconductor structure according to claim 7, wherein: The removing at least a portion of the second sacrificial layer located in the first hole segment comprises: The second sacrificial layer located in the first hole segment is removed by a wet etching process.

10. The method for preparing a semiconductor structure according to claim 7, wherein: The material of the second sacrificial layer includes carbon.

11. The method for preparing a semiconductor structure according to claim 1, wherein: The first sacrificial layer comprises a first sub-sacrificial layer and a first insulating layer sequentially distributed in a direction away from the semiconductor layer; The removing the first sacrificial layer comprises: removing the portion of the first sacrificial layer located in the non-array area; forming a third opening region in the first insulating layer in the array region, wherein the third opening region exposes a portion of the first sacrificial sub-layer; The first sacrificial sub-layer is removed through the third opening region.

12. The method for preparing a semiconductor structure according to claim 11, wherein: The first sacrificial layer further includes a second sub-sacrificial layer and a second insulating layer sequentially distributed in a direction away from the semiconductor layer, and the second sub-sacrificial layer and the second insulating layer are located between the first sub-sacrificial layer and the semiconductor layer; The removing of the first sacrificial layer further comprises: forming a fourth opening region in the second insulating layer located in the array region, wherein the fourth opening region exposes a portion of the second sacrificial sub-layer, and the fourth opening region overlaps the third opening region in a thickness direction of the semiconductor layer; The second sacrificial sub-layer is removed through the fourth opening region.

13. The method for preparing a semiconductor structure according to claim 1, wherein: The capacitor hole extends to the semiconductor layer; and the first electrode is formed in the capacitor hole in the array area, comprising: A first conductive layer is formed on the bottom surface and the inner side surface of the capacitor hole to form the first electrode in the capacitor hole.

14. The method for preparing a semiconductor structure according to claim 1, wherein: The forming of a capacitor dielectric layer on the surface of the first electrode comprises: The capacitor dielectric layer is formed on the outer peripheral surface of the first electrode.

15. The method for preparing a semiconductor structure according to any one of claims 1 to 14, characterized in that: The material of the first sacrificial layer includes oxide.

16. The method for preparing a semiconductor structure according to any one of claims 1 to 14, characterized in that: The material of the first electrode and / or the second electrode includes titanium nitride.

17. The method for preparing a semiconductor structure according to any one of claims 1 to 14, characterized in that: The removing the first sacrificial layer comprises: The first sacrificial layer is removed by a wet etching process.

18. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the semiconductor structure preparation method according to any one of claims 1 to 17.

19. A memory, characterized in that: The memory comprises the semiconductor structure of claim 18.

20. A storage system, characterized in that: The storage system comprises: A memory, wherein the memory is the memory according to claim 19; The controller is coupled to the memory and is used for controlling the memory to store data.

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