Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors. Comprising the following steps: forming a first stacking structure and a second stacking structure on a substrate, respectively forming a first accommodating groove and a second accommodating groove in the first stacking structure and the second stacking structure, and respectively forming a reading transistor and a writing transistor with vertical structures; a first signal line accommodating groove, a second signal line accommodating groove and an erasing line accommodating groove are sequentially formed in the direction away from the substrate; respectively filling the first signal line accommodating groove, the second signal line accommodating groove and the erasing line accommodating groove so as to respectively form a first signal line in the first signal line accommodating groove, form a second signal line in the second signal line accommodating groove and form an erasing line in the erasing line accommodating groove; a writing line containing groove is formed in the second stacking structure, and a writing line is formed in the writing line containing groove. By designing a signal line structure and a leading-out structure of the signal line structure with a relatively simple preparation process, the data erasing speed of the device can be improved, and the floating body effect is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory used in computers and other electronic devices to store data that needs to be accessed quickly. Compared with static random access memory, it has the advantages of simple structure, low manufacturing cost and high storage density, and is an important component of modern computing systems.

[0003] At present, the storage unit of common DRAM memory is a structure of one transistor connected to one capacitor, namely, a 1T1C (1Transistor 1Capacitor) storage unit structure. This structure requires constant refreshing of the charge in the capacitor to ensure that data is not lost. It consumes a lot of power, and the manufacturing process of the capacitor occupies a large area, which limits the miniaturization of the device size.

[0004] In order to overcome the drawbacks of 1T0C memory cells, the dual-transistor capacitorless dynamic random access memory (2Transistor0Capacitor, 2T0C) uses two transistors as the memory cell structure, in which the source and drain of the write transistor are connected to the gate of the read transistor, and the gate is used to store charge to change the transistor transconductance to store information. In the existing manufacturing method of DRAM composed of 2T0C memory cells, the word line of the write transistor is extended vertically, and the projections of the word line and bit line of the read transistor on the substrate intersect, and the step structure in two directions is designed to lead out the word line and bit line of the write transistor and the word line and bit line of the read transistor of different layers, and the process flow is relatively complicated. In addition, the existing DRAM composed of 2T0C memory cells also has a floating body effect, which may cause transistor failure.

[0005] Therefore, it is necessary to design a DRAM with a new 2T0C storage cell architecture, design a signal line structure and a signal line lead-out structure with a simpler manufacturing process, and at the same time improve or reduce the floating body effect.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In view of this, a method for manufacturing a semiconductor device is provided, by which a signal line structure and a lead-out structure with a relatively simple preparation process can be designed, while reducing the floating body effect and improving the overall performance of the device.

[0008] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0009] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0010] providing a substrate;

[0011] forming a first stacking structure on the surface of the substrate, the first stacking structure comprising three insulating material layers and two first sacrificial layers alternately deposited in sequence along a first direction, wherein the first direction is perpendicular to the surface of the substrate;

[0012] Performing patterning on the first stacking structure to form a plurality of first containing grooves extending along the first direction and distributed in an array along a second direction and a third direction in the first stacking structure, wherein the second direction and the third direction intersect and are parallel to the substrate, and the bottom surface of the first containing groove is located above the substrate and below the first sacrificial layer at the lowermost side;

[0013] forming a read transistor in the first containing groove, wherein the read transistor is a vertical structure transistor, and comprises a first source and drain region, a read channel region, and a second source and drain region, wherein one layer of the first sacrificial layer surrounds the first source and drain region, and another layer of the first sacrificial layer surrounds the second source and drain region;

[0014] forming a second stacked structure on the surface of the first stacked structure having the read transistor, wherein the second stacked structure comprises a first sacrificial layer, a first insulating material layer, a second sacrificial layer, and a second insulating material layer sequentially deposited along the first direction, and the first sacrificial layer and the second sacrificial layer are made of different materials;

[0015] Performing patterning on the second stacking structure to form a plurality of second containing grooves extending along the first direction and distributed in an array along the second direction and the third direction in the second stacking structure, wherein the second containing grooves correspond to the first containing grooves one by one, and projections of the second containing grooves and the first containing grooves on the surface of the substrate overlap;

[0016] forming a write transistor in the second containing groove, the write transistor being a vertical structure transistor, the write transistor comprising a third source and drain region, a write channel region and a fourth source and drain region, the first sacrificial layer in the second stacked structure being located on a side of the fourth source and drain region close to the substrate, and the second sacrificial layer being located on a side of the first sacrificial layer in the second stacked structure away from the third source and drain region;

[0017] Removing two layers of the first sacrificial layer in the first stacking structure and the first sacrificial layer in the second stacking structure to sequentially form a first signal line accommodating groove, a second signal line accommodating groove and an erase line accommodating groove in a direction away from the substrate, wherein the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove all extend along the second direction and are arranged at intervals along the third direction;

[0018] Filling the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove respectively, so as to form a first signal line in the first signal line accommodating groove, a second signal line in the second signal line accommodating groove, and an erase line in the erase line accommodating groove;

[0019] Removing the second sacrificial layer in the second stack structure to form write word line accommodating grooves, wherein the write word line accommodating grooves extend along the second direction and are arranged at intervals along the third direction;

[0020] The write word line accommodating groove is filled to form a write word line in the write word line accommodating groove.

[0021] In an exemplary embodiment of the present disclosure, before removing the two first sacrificial layers in the first stacking structure and the first sacrificial layer in the second stacking structure, the method further includes:

[0022] The first stacking structure and the second stacking structure are trimmed by a trimming-etching process, so that the three layers of the first sacrificial layer and the second sacrificial layer respectively form a first sub-sacrificial layer, a second sub-sacrificial layer, a third sub-sacrificial layer and a fourth sub-sacrificial layer in the direction along the first direction and away from the substrate, and there is an overlap between the projections of the first sub-sacrificial layer, the second sub-sacrificial layer, the third sub-sacrificial layer and the fourth sub-sacrificial layer on the surface of the substrate, and in the direction along the first direction close to the second stacking structure, the sizes of the first sub-sacrificial layer, the second sub-sacrificial layer, the third sub-sacrificial layer and the fourth sub-sacrificial layer along the second direction are reduced or increased in sequence;

[0023] forming a covering layer covering the first stacking structure and the second stacking structure, wherein a projection of the covering layer on the surface of the substrate includes a projection of the first sub-sacrificial layer on the substrate, so as to form an intermediate stacking structure;

[0024] forming a plurality of separation grooves in the intermediate stacking structure, wherein the plurality of separation grooves extend along the second direction and are spaced apart along the third direction, so that the intermediate stacking structure forms a plurality of separators;

[0025] The first sub-sacrificial layer, the second sub-sacrificial layer and the third sub-sacrificial layer in each of the separators are removed to sequentially form the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove in each of the separators.

[0026] In an exemplary embodiment of the present disclosure, after the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove are sequentially formed in each of the separators, the method further includes:

[0027] removing the second sacrificial layer in each of the separators to form the write word line accommodating groove in each of the separators;

[0028] Forming a write gate dielectric material layer, wherein the write gate dielectric material layer conformally covers the write word line receiving groove to form a write gate dielectric structure covering the periphery of the second receiving groove;

[0029] A write word line material layer is filled in the remaining space of the write word line accommodating groove to form the write word line.

[0030] In an exemplary embodiment of the present disclosure, the second signal line, the first signal line, the erase line, and the write line each include a main body extension and a lead-out end located at at least one end of the main body extension; in the first direction, the main body extensions of any two of the second signal line, the first signal line, the erase line, and the write line overlap in their orthographic projections on the substrate, and the lead-out ends of any two of the second signal line, the first signal line, the erase line, and the write line do not overlap in their orthographic projections on the substrate, the semiconductor device further includes a first connecting line, and the method further includes:

[0031] A plurality of first connection line accommodating grooves extending along the first direction and spaced apart along the second direction are formed in each of the partitions;

[0032] The first connection line accommodating grooves are filled to form a plurality of first connection lines, wherein the first connection lines are in contact with and connected to the lead-out end portions.

[0033] In an exemplary embodiment of the present disclosure, forming a read transistor in the first containing groove includes:

[0034] Forming a read channel layer, a read gate dielectric layer and a read gate material layer in sequence, wherein the read channel layer at least conformally covers the sidewalls and the bottom wall of the first receiving groove, the read gate dielectric layer conformally covers the read channel layer, and the read gate material layer at least fills the remaining space of the first receiving groove;

[0035] The read gate material layer, the read gate dielectric layer and the read channel layer are etched to form a read gate structure, a read gate dielectric structure and a read channel structure, respectively. The top surfaces of the read gate structure, the read gate dielectric structure and the read channel structure are flush and lower than the surface of the first stacked structure to form the read transistor. The upper surface of the read transistor and the surface of the first stacked structure form a first groove.

[0036] In an exemplary embodiment of the present disclosure, the material of the read gate structure includes indium zinc oxide, and the material of the read channel structure is indium gallium zinc oxide.

[0037] In an exemplary embodiment of the present disclosure, a first conductive block is included between the read transistor and the write transistor, and a method for forming the first conductive block includes:

[0038] forming a first insulating layer, wherein the first insulating layer covers the sidewalls and a portion of the bottom wall of the first groove;

[0039] Filling a first conductive material layer in the first groove;

[0040] The first conductive material layer is etched to form the first conductive block, the upper end surface of the first conductive block is lower than the surface of the first stacked structure to form a first sub-groove, the lower end surface of the first conductive block is in contact with the read gate structure, and the lower end surface of the first conductive block is not in contact with the read channel structure.

[0041] In an exemplary embodiment of the present disclosure, a second stack structure is formed on a surface of the first stack structure having the read transistor, including:

[0042] A first sacrificial layer is formed on the first stack structure having the first conductive block, the first sacrificial layer fills the first sub-groove, and the first sub-groove is contained in the second containing groove.

[0043] In an exemplary embodiment of the present disclosure, the write transistor includes a write gate structure, the write gate structure is integrally formed with the write word line, and the write transistor is formed in the second receiving groove, including:

[0044] A sleeve material layer and a filling material layer are sequentially formed in the second receiving groove, wherein the sleeve material layer conformally covers the side wall and the bottom wall of the second receiving groove, and the filling material layer fills the remaining space of the second receiving groove;

[0045] The sleeve material layer and the filling body material layer located in the second accommodating groove are etched, the sleeve material layer forms a sleeve, the filling body material layer forms a filling body, the sleeve and the filling body constitute a write channel structure, the top surface of the write channel structure is lower than the surface of the second stacking structure, and the upper surface of the write channel structure and the surface of the second stacking structure constitute a second groove.

[0046] In an exemplary embodiment of the present disclosure, the material of the sleeve includes indium gallium zinc oxide, and the material of the filler includes indium zinc oxide.

[0047] In an exemplary embodiment of the present disclosure, the semiconductor device further includes a second conductive block structure, and forming the second conductive block includes:

[0048] Filling a second conductive material layer in the second groove;

[0049] The second conductive material layer is etched to form a second conductive block, wherein the upper end surface of the second conductive block is flush with the upper surface of the second receiving groove, and the lower end surface of the second conductive block is in contact with and connected to the writing channel structure.

[0050] In an exemplary embodiment of the present disclosure, the semiconductor device further includes a plurality of write bit lines extending along the third direction and arranged at intervals along the second direction, and the method further includes:

[0051] forming a covering protective layer on the surface of the second stacking structure, and forming a plurality of second connection line accommodating grooves extending along the first direction and distributed in an array along the second direction and the third direction in the covering protective layer;

[0052] The second connection line accommodating grooves are filled to form a plurality of second connection lines, wherein the lower end surfaces of the second connection lines are in contact with the upper end surfaces of the second conductive blocks, and the upper end surfaces of the second connection lines are in contact with the write bit lines.

[0053] According to another aspect of the present disclosure, a semiconductor device is provided, which is manufactured using the above manufacturing method.

[0054] The manufacturing method of the semiconductor device provided by the present invention forms a read transistor and a write transistor with a vertical structure and electrically connected, and forms a plurality of erase lines in the device, wherein the extension direction of the erase lines is the same as the extension direction of the write lines and both are arranged horizontally, each erase line surrounds a portion of the side wall of the channel structure of the write transistor in the storage unit, and each erase line connects a plurality of storage units spaced apart along a first direction, the formed write lines, erase lines, read first signal lines and read second signal lines are all extended horizontally, and a stepped lead-out structure can be formed in the same direction, thereby realizing the lead-out of four layers of signal lines in different layers, simplifying the preparation process flow; by selecting different erase lines, data in some storage nodes in the device can be erased, significantly improving the data erasing speed of the device; in addition, since the erase lines are formed in each storage unit during the period, the floating body effect of the device can be reduced, thereby improving the overall function of the device.

[0055] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0057] Figure 1 It is a schematic diagram of a process of forming a first receiving groove in an exemplary embodiment of the present disclosure.

[0058] Figure 2 It is a schematic structural diagram of a first stacking structure having a first containing groove in an exemplary embodiment of the present disclosure.

[0059] Figure 3 The diagram is a schematic diagram of a process of forming a read channel layer, a read gate dielectric layer and a read gate material layer in an exemplary embodiment of the present disclosure.

[0060] Figure 4 FIG. 4 is a schematic diagram of a process of forming a read transistor in an exemplary embodiment of the present disclosure.

[0061] Figure 5 It is a schematic diagram of a process of forming a first groove in an exemplary embodiment of the present disclosure.

[0062] Figure 6 FIG. 4 is a schematic diagram of a process of forming a first conductive material layer in an exemplary embodiment of the present disclosure.

[0063] Figure 7It is a schematic diagram of a process of forming a first conductive block in an exemplary embodiment of the present disclosure.

[0064] Figure 8 It is a schematic diagram of a process of forming a first sacrificial layer in a second stacked structure in an exemplary embodiment of the present disclosure.

[0065] Fig. 9 It is a perspective view of a first stacking structure and a second stacking structure in an exemplary embodiment of the present disclosure.

[0066] Fig.10 It is a schematic structural diagram of a second containing groove in an exemplary embodiment of the present disclosure.

[0067] Fig.11 It is a schematic diagram of a process of forming a sleeve material layer in an exemplary embodiment of the present disclosure.

[0068] Fig.12 It is a schematic diagram of a process of forming a filling material layer in an exemplary embodiment of the present disclosure.

[0069] Fig.13 FIG. 4 is a schematic diagram of a process of forming a write channel structure in an exemplary embodiment of the present disclosure.

[0070] Fig.14 It is a schematic diagram of a process of forming a second conductive block in an exemplary embodiment of the present disclosure.

[0071] Fig.15 The figure is a schematic diagram of a process of forming a first photoresist layer in a trim-etch process in an exemplary embodiment of the present disclosure.

[0072] Fig.16 The figure is a schematic diagram of a process of forming a fourth sacrificial sub-layer in a trim-etch process in an exemplary embodiment of the present disclosure.

[0073] Fig.17 The figure is a schematic diagram of a process of forming a second photoresist layer in a trim-etch process in an exemplary embodiment of the present disclosure.

[0074] Fig.18 It is a schematic diagram of the structure after etching using the second photoresist layer after the first trimming as a mask in the trimming-etching process in an exemplary embodiment of the present disclosure.

[0075] Fig.19 It is a schematic diagram of the structure after etching using the second photoresist layer after the second trimming as a mask in the trimming-etching process in an exemplary embodiment of the present disclosure.

[0076] Fig. 20 It is a schematic diagram of the structure after etching using the second photoresist layer after the third trimming as a mask in the trimming-etching process in an exemplary embodiment of the present disclosure.

[0077] Fig.21 It is a schematic structural diagram of forming a step structure in a trim-etch process in an exemplary embodiment of the present disclosure. Fig. 22 It is a schematic diagram of a process of forming a separator in an exemplary embodiment of the present disclosure.

[0078] Fig.23 It is a schematic diagram of a process of forming a first signal line accommodating groove, a second signal line accommodating groove and an erase line accommodating groove in an exemplary embodiment of the present disclosure.

[0079] Fig.24 The figure is a schematic diagram of a process of forming a first signal line, a second signal line and an erase line in an exemplary embodiment of the present disclosure.

[0080] Fig.25 The figure is a schematic diagram of a process of forming a write word line accommodating groove in an exemplary embodiment of the present disclosure.

[0081] Fig.26 The figure is a schematic diagram of a process of forming a write gate dielectric structure in an exemplary embodiment of the present disclosure.

[0082] Fig. 27 FIG. 4 is a schematic diagram of a process of forming a write word line in an exemplary embodiment of the present disclosure.

[0083] Fig.28 It is a schematic diagram of the cross-sectional structure of a semiconductor device in an exemplary embodiment of the present disclosure.

[0084] Fig.29 It is a schematic diagram of the three-dimensional structure of a semiconductor device in an exemplary embodiment of the present disclosure.

[0085] Fig.30 The figure is a schematic diagram of the structure of a memory cell in a semiconductor device in an exemplary embodiment of the present disclosure.

[0086] The reference numerals are described as follows:

[0087] 100, substrate; 101, first sacrificial layer; 102, second sacrificial layer; 103, insulating material layer; 104, first sub-sacrificial layer; 105, second sub-sacrificial layer; 106, third sub-sacrificial layer; 107, fourth sub-sacrificial layer; 200, first stacking structure; 201, first receiving groove; 210, read transistor; 211, first source and drain region; 212, second source and drain region; 213, read channel region; 214, read channel structure; 2141, Read channel layer; 215, read gate structure; 2151, read gate material layer; 216, read gate dielectric structure; 2161, read gate dielectric layer; 300, second stack structure; 301, second receiving groove; 310, write transistor; 311, third source and drain region; 312, fourth source and drain region; 313, write channel region; 314, write gate dielectric structure; 3141, write gate dielectric material layer; 315, write channel structure; 3151, sleeve; 3152, Sleeve material layer; 3153, filling body; 3154, filling body material layer; 401, first signal line accommodating groove; 402, second signal line accommodating groove; 403, erase line accommodating groove; 404, write line accommodating groove; 501, first signal line; 502, second signal line; 503, erase line; 504, write line; 600, separation groove; 601, separation body; 701, first connecting line; 702, second connecting line; 801, first groove ; 802, first insulating layer; 803, first conductive material layer; 804, first conductive block; 805, first sub-groove; 810, second groove; 811, second conductive block; 901, first patterned photoresist layer; 902, first photoresist layer; 903, second photoresist layer; 910, first blocking layer; 920, second blocking layer; 930, third blocking layer; 1000, lead-out end; X, first direction; Y, second direction; Z, third direction. DETAILED DESCRIPTION

[0088] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0089] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0090] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0091] In the related art, a two-transistor capacitor-free dynamic random access memory (2T0C) uses two transistors as a storage unit structure, wherein a source and drain of one transistor are connected to the gate of another transistor, and the gate of one of the transistors is used to replace the capacitor in the 1T0C structure to store charge. This can change the problem of low device storage density caused by the manufacturing process limitations of the capacitor, and can also change the transistor transconductance to store information.

[0092] A memory with a 2T0C storage cell structure can increase storage density by continuously increasing the number of stacking layers. However, as the number of stacking layers increases, higher requirements are placed on the manufacturing process of the device, and the data reading, writing and erasing speeds in each storage node in each storage cell in 2T0C are also affected.

[0093] Based on this, the present disclosure provides a method for manufacturing a semiconductor device, such as Figures 1 to 30 As shown in the structural schematic diagram of each manufacturing step, the method includes: step S100 to step S110.

[0094] Wherein, step S100: providing a substrate 100;

[0095] Step S101: forming a first stacked structure 200 on the surface of the substrate 100, wherein the first stacked structure 200 includes three insulating material layers 103 and two first sacrificial layers 101 which are alternately deposited in sequence along a first direction X, and the first direction X is perpendicular to the surface of the substrate 100;

[0096] Step S102: performing patterning on the first stacking structure 200 to form a plurality of first containing grooves 201 extending along the first direction X and distributed in an array along the second direction Y and the third direction Z in the first stacking structure 200, wherein the second direction Y and the third direction Z intersect and are parallel to the substrate 100, and the bottom surface of the first containing groove 201 is located above the substrate 100 and below the lowermost first sacrificial layer 101;

[0097] Step S103: forming a read transistor 210 in the first receiving groove 201. The read transistor 210 is a vertical structure transistor. The read transistor 210 includes a first source and drain region 211, a read channel region 213, and a second source and drain region 212. A first sacrificial layer 101 surrounds the first source and drain region 211, and another first sacrificial layer 101 surrounds the second source and drain region 212.

[0098] Step S104: forming a second stacked structure 300 on the surface of the first stacked structure 200 having the read transistor 210, wherein the second stacked structure 300 includes a first sacrificial layer 101, a first insulating material layer 103, a second sacrificial layer 102, and a second insulating material layer 103 sequentially deposited along the first direction X, and the first sacrificial layer 101 and the second sacrificial layer 102 are made of different materials;

[0099] Step S105: performing patterning on the second stacking structure 300 to form a plurality of second containing grooves 301 extending along the first direction X and distributed in an array along the second direction Y and the third direction Z in the second stacking structure 300, wherein the second containing grooves 301 correspond to the first containing grooves 201 one by one, and the projections of the second containing grooves 301 and the first containing grooves 201 on the surface of the substrate 100 overlap;

[0100] Step S106: forming a write transistor 310 in the second accommodating groove 301, the write transistor 310 is a vertical structure transistor, the write transistor 310 includes a third source and drain region 311, a write channel region 313 and a fourth source and drain region 312, the first sacrificial layer 101 in the second stacked structure 300 is located on a side of the fourth source and drain region 312 close to the substrate 100, and the second sacrificial layer 102 is located on a side of the first sacrificial layer 101 in the second stacked structure 300 away from the third source and drain region 311;

[0101] Step S107: removing the two first sacrificial layers 101 in the first stacked structure 200 and the first sacrificial layer 101 in the second stacked structure 300, so as to sequentially form a first signal line accommodating groove 401, a second signal line accommodating groove 402 and an erase line accommodating groove 403 in a direction away from the substrate 100, wherein the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403 all extend along the second direction Y and are arranged at intervals along the third direction Z;

[0102] Step S108: filling the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403 respectively, so as to form the first signal line 501 in the first signal line accommodating groove 401, the second signal line 502 in the second signal line accommodating groove 402, and the erase line 503 in the erase line accommodating groove 403;

[0103] Step S109: removing the second sacrificial layer 102 in the second stacked structure 300 to form write word line accommodating grooves 404, wherein the write word line accommodating grooves 404 extend along the second direction Y and are arranged at intervals along the third direction Z;

[0104] Step S110 : filling the write word line accommodating groove 404 to form a write word line 504 in the write word line accommodating groove 404 .

[0105] The present invention provides a method for manufacturing a semiconductor device, wherein a first stacking structure 200 and a second stacking structure 300 are sequentially formed on a substrate 100 along a first direction X, wherein the second stacking structure 300 is located above the first stacking structure 200, a plurality of first containing grooves 201 extending along the first direction X and distributed in an array along a second direction Y and a third direction Z are formed in the first stacking structure 200, and a vertically structured read transistor 210 is formed in the first containing groove 201, a plurality of second containing grooves 301 extending along the first direction X and distributed in an array along the second direction Y and a third direction Z are formed in the second stacking structure 300, and a vertically structured write transistor 310 is formed in the second containing groove 301, wherein a third source and drain region 311 of the write transistor 310 is connected to a gate structure of the read transistor 210. Contact connection; a first signal line 501 and a second signal line 502 are formed in the first stack structure 200, extending along the second direction Y and arranged at intervals along the third direction Z; an erase line 503 and a write line 504 are formed in the second stack structure 300, extending along the second direction Y and arranged at intervals along the third direction Z; by forming an erase line 503 in the device, the erase line 503 connects a plurality of write transistors 310 spaced apart along the first direction X; when erasing data in a storage node in the device, different erase lines 503 can be selected to erase the data in the storage node through the erase line 503, thereby improving the erasing speed of the data; in addition, since the erase line 503 is formed at a circumferential position of the write transistor 310, the floating body effect during the period can be reduced, thereby improving the overall function of the device.

[0106] The following will describe in detail the various steps of the method for manufacturing a semiconductor device according to the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0107] In the embodiment provided by the present disclosure, in step S100, as Figure 1 As shown, a substrate 100 is provided.

[0108] Wherein, the substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a germanium silicon (GeSi) substrate, SOI (Silicon On Insulator), SOS (Silicon-on-Sapphire) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs). The embodiments provided in the present disclosure are described by taking the substrate 100 as a silicon (Si) substrate as an example. Of course, for other types of substrates 100, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the protection scope of the present disclosure.

[0109] In the embodiment provided in the present disclosure, the first direction X, the second direction Y and the third direction Z are defined as follows: the first direction X is a direction perpendicular to the surface of the substrate 100, the second direction Y intersects with the third direction Z and are parallel to the surface of the substrate 100. Fig.29 and Fig.30 As shown in the coordinates in , of course, the directions in this embodiment do not limit the manufacturing method of the device and the structure of the device disclosed in the present invention.

[0110] In the embodiment provided by the present disclosure, in step S101, as Figure 1 As shown, a first stacked structure 200 is formed on the surface of the substrate 100 , and the first stacked structure 200 includes three insulating material layers 103 and two first sacrificial layers 101 alternately deposited in sequence along a first direction X, and the first direction X is perpendicular to the surface of the substrate 100 .

[0111] Among them, the first stacked structure 200 includes three insulating material layers and two first sacrificial layers 101. The insulating material layer 103 can be formed of materials such as silicon oxide (SiO2), and can be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), such as low-pressure chemical vapor deposition (Low-Pressure Chemical Vapor Deposition, LPCVD), plasma-enhanced chemical vapor deposition (Plasma-Enhanced Chemical Vapor Deposition, PECVD), atomic layer deposition (Atomic Layer Deposition, ALD) and other methods; it can also be formed by physical vapor deposition (Physical Vapor Deposition, PVD), such as sputtering deposition (Sputtering) and other methods.

[0112] The first sacrificial layer 101 may be formed of materials such as silicon nitride (Si3N4), and may be formed by a CVD method, such as atomic layer deposition (ALD), LPCVD, PECVD, or the like.

[0113] It should be noted that the first sacrificial layer 101 and the insulating material layer 103 need to be made of different materials. In the subsequent process, when the first sacrificial layer 101 is etched, the insulating material layer 103 can be retained to form a corresponding accommodating groove or recess through the insulating material layer 103. In the embodiment provided by the present disclosure, the projections of the first sacrificial layer 101 and the insulating material layer 103 on the surface of the substrate 100 can completely overlap with the substrate 100, but in the actual process, the projections of the formed first sacrificial layer 101 and the insulating material layer 103 on the surface of the substrate 100 can also be slightly smaller than or slightly larger than the range surrounded by the substrate 100. The insulating material layer 103, the first sacrificial layer 101 and the second sacrificial layer 102 in the second stacked structure 300 in the following embodiment are also the same, and will not be repeated below. In addition, the thickness of the insulating material layer 103, the first sacrificial layer 101 or the second sacrificial layer 102 in the first direction X can be appropriately adjusted according to the actual process design requirements. The thickness shown in the drawings is only for exemplary purposes and does not limit the thickness of each film layer provided by the present disclosure and the thickness relationship.

[0114] In the embodiment provided by the present disclosure, in step S102, as Figure 1 As shown, the first stacking structure 200 is patterned to form a plurality of first accommodating grooves 201 extending along the first direction X and distributed in an array along the second direction Y and the third direction Z in the first stacking structure 200, the second direction Y and the third direction Z intersect and are both parallel to the substrate 100, and the bottom surface of the first accommodating groove 201 is located above the substrate 100 and below the lowermost first sacrificial layer 101.

[0115] The patterning of the first stacked structure 200 includes: Figure 1 As shown, a first patterned photoresist layer 901 is formed on the surface of the first stacked structure 200; the first patterned photoresist layer 901 is used to etch the first stacked structure 200 along the first direction X, so as to form a plurality of first containing grooves 201 extending along the first direction X and distributed in an array along the second direction Y and the third direction Z inside the first stacked structure 200. Etching can be performed by wet etching (Wet Etching) or dry etching (Dry Etching), and its etching process parameters can be adaptively selected and adjusted according to actual needs.

[0116] In order to ensure the effective connection between the subsequently formed read transistor 210 and the first signal line 501, as shown in FIG. Figure 2 As shown, the bottom surface of each first receiving groove 201 is located above the required substrate 100 and below the lowest first sacrificial layer 101, that is, the bottom surface of each first receiving groove 201 is located between the surface of the substrate 100 and the lower surface of the lowest first sacrificial layer 101.

[0117] In the embodiment provided by the present disclosure, in step S103, as Figure 4 As shown, combined Fig.30 A read transistor 210 is formed in the first accommodating groove 201. The read transistor 210 is a vertical structure transistor. The read transistor 210 includes a first source and drain region 211, a read channel region 213, and a second source and drain region 212. A first sacrificial layer 101 surrounds the first source and drain region 211, and another first sacrificial layer 101 surrounds the second source and drain region 212.

[0118] Wherein, a read transistor 210 is formed in the first containing groove 201, including:

[0119] Step S1031: sequentially forming a read channel layer 2141, a read gate dielectric layer 2161 and a read gate material layer 2151, wherein the read channel layer 2141 at least conformally covers the sidewalls and the bottom wall of the first receiving groove 201, the read gate dielectric layer 2161 conformally covers the read channel layer 2141, and the read gate material layer 2151 at least fills the remaining space of the first receiving groove 201;

[0120] Step S1032: Etch the read gate material layer 2151, the read gate dielectric layer 2161 and the read channel layer 2141 to respectively form a read gate structure 215, a read gate dielectric structure 216 and a read channel structure 214, wherein the top surfaces of the read gate structure 215, the read gate dielectric structure 216 and the read channel structure 214 are flush and lower than the surface of the first stacked structure 200 to form a read transistor 210, and the upper surface of the read transistor 210 and the surface of the first stacked structure 200 form a first groove 801.

[0121] Among them, in step S1031, if Figure 3 As shown, a read channel layer 2141, a read gate dielectric layer 2161 and a read gate material layer 2151 are formed in sequence, including: forming a read channel layer 2141 that conformally covers the side walls and bottom walls of the first receiving groove 201, and the read channel layer 2141 extends to the surface of the first stacked structure 200; forming a read gate dielectric layer 2161, and the read gate dielectric layer 2161 conformally covers the read channel layer 2141; forming a read gate material layer 2151, and the read gate material layer 2151 fills the remaining space of the first receiving groove 201, and the read gate material layer 2151 extends to the surface of the read gate material layer 2151.

[0122] In step S1032, if Figure 4 As shown, etching the read gate material layer 2151, the read gate dielectric layer 2161 and the read channel layer 2141 includes: etching away the read gate material layer 2151, the read gate dielectric layer 2161 and the read channel layer 2141 located outside the first receiving groove 201, and continuing to etch the read gate material layer 2151, the read gate dielectric layer 2161 and the read channel layer 2141 along the first direction X and in a direction close to the substrate 100 to form a read gate structure 215, a read gate dielectric structure 216 and a read channel structure 214, respectively, and the top surfaces of the read gate structure 215, the read gate dielectric structure 216 and the read channel structure 214 are flush and lower than the surface of the first stacked structure 200.

[0123] The read gate material layer 2151, the read gate dielectric layer 2161 and the read channel layer 2141 can be etched by dry etching or wet etching, or by chemical mechanical polishing (CMP) combined with dry etching or wet etching. The etching process parameters can be adaptively adjusted according to the different parameters such as the material and thickness of each layer.

[0124] The read gate structure 215 is obtained by etching the read gate material layer 2151, so the read gate structure 215 and the read gate material layer 2151 can be made of the same material. The read gate material layer 2151 and the read gate structure 215 can be made of polysilicon, metal material or metal alloy material. For example, the metal material can be tungsten, copper, etc.; the metal alloy material can be indium zinc oxide (Indium Zinc Oxide, IZO). In the present disclosure, in order to improve the on- and off-capacity of the source and drain of the read transistor 210 and improve the performance of the device, the read gate structure 215 can be made of indium zinc oxide (Indium Zinc Oxide, IZO), which has good electrical and optical properties. Using it as the read gate structure 215 can improve the conductivity of the gate, thereby improving the overall performance of the read transistor 210.

[0125] The read gate structure 215 can be formed by a PVD method, such as a Sputtering method, an Evaporation method, etc.; or a CVD method, such as an ALD method, a PECVD method, etc., and its specific formation process can be adaptively selected according to the design requirements and structural requirements of the read transistor 210.

[0126] The read channel structure 214 is obtained by etching the read channel layer 2141, so the read channel structure 214 and the read channel layer 2141 can be made of the same material. The read channel layer 2141 and the read channel structure 214 can be formed of materials such as silicon, germanium, silicon carbide, gallium nitride, zinc oxide or indium oxide. In the present disclosure, in order to reduce the leakage current in the transistor and reduce power consumption, the read channel structure 214 can be made of indium gallium zinc oxide (IGZO), which has a lower leakage current when the transistor is off, which can reduce the overall power consumption of the device, and it also has a higher electron mobility, which can improve the switching speed of the read transistor 210, thereby improving the response speed of the device.

[0127] The read channel structure 214 may be formed by a PVD method, such as Sputtering, or a CVD method, such as an ALD method, a PECVD method, etc. The specific formation process may be adaptively selected according to the design requirements and structural requirements of the read transistor 210 .

[0128] like Fig.30 As shown, the read channel structure 214 includes a second source and drain region 212, a read channel region 213 and a first source and drain region 211 which are arranged in sequence along the first direction X and close to the substrate 100, that is, the first source and drain region 211 and the second source and drain region 212 are respectively located at two ends of the read channel region 213, wherein the read channel region 213 is a channel for carriers to flow between the first source and drain region 211 and the second source and drain region 212.

[0129] The read gate dielectric structure 216 is obtained by etching the read gate dielectric layer 2161, so the read gate dielectric structure 216 and the read gate dielectric layer 2161 can be made of the same material. The appearance of the read gate dielectric structure 216 and the read channel structure 214 can be the same or substantially the same, and the two are sequentially coated on the sidewall and one end of the read gate structure 215. The read gate dielectric structure 216 can be made of a material with electrical isolation, such as silicon dioxide, silicon nitride or aluminum oxide. In the present disclosure, in order to improve the electrical isolation performance of the read gate dielectric structure 216 and ensure its effective control over the read gate structure 215 and the read channel structure 214, the read gate dielectric structure 216 can be made of a high dielectric constant material, such as hafnium oxide, hafnium silicon oxide, zirconium oxide and the like, which can reduce the operating voltage, increase the operating current, and thereby improve the overall performance of the read transistor 210.

[0130] In the embodiment provided by the present disclosure, in step S104, as Fig. 9As shown, a second stacked structure 300 is formed on the surface of the first stacked structure 200 having the read transistor 210, and the second stacked structure 300 includes a first sacrificial layer 101, a first insulating material layer 103, a second sacrificial layer 102, and a second insulating material layer 103 sequentially deposited along a first direction X, and the materials of the first sacrificial layer 101 and the second sacrificial layer 102 are different.

[0131] Since the read transistor 210 and the write transistor 310 need to be electrically connected, Figure 7 As shown, a first conductive block 804 is further included between the read transistor 210 and the write transistor 310. Specifically, after step S103 and before step S104, the method for forming the first conductive block 804 includes:

[0132] like Figure 5 As shown, a first insulating layer 802 is formed, and the first insulating layer 802 covers the sidewalls and a part of the bottom wall of the first groove 801, wherein the method for forming the first insulating layer 802 includes: conformally depositing insulating material on the surface of the first stacked structure 200 and the sidewalls and bottom wall of the first groove 801, and etching away the insulating material on the surface of the first stacked structure 200 and the bottom wall of the first groove 801 to expose the surface of the read gate structure 215. Figure 6 As shown, a first conductive material layer 803 is filled in the first groove 801; Figure 7 As shown, the first conductive material layer 803 is etched to form a first conductive block 804, the upper end surface of the first conductive block 804 is lower than the surface of the first stacked structure 200 to form a first sub-recess 805, the lower end surface of the first conductive block 804 is in contact with the read gate structure 215, and the lower end surface of the first conductive block 804 is not in contact with the read channel structure 214.

[0133] Among them, the first conductive block 804 is a connecting conductive bridge between the write transistor 310 and the read transistor 210, and it can be made of a material with conductive properties. However, since the lower end surface of the first conductive block 804 is in contact with the upper end surface of the read gate structure 215, in order to form a better transition between the first conductive block 804 and the read gate structure 215 and ensure that it does not affect the functionality of the upper end surface of the read gate structure 215, the first conductive block 804 can be made of polycrystalline silicon (poly), and its device size is small and the local electrical interconnection with low current density can achieve compatibility of processability and performance.

[0134] The first conductive block 804 does not contact the read channel structure 214, that is, the first conductive block 804 is insulated from the read channel structure 214, so as to avoid the setting of the first conductive block 804 affecting the normal function of the read channel structure 214. Specifically, a first insulating layer 802 may be formed between the first conductive block 804 and the read channel structure 214, such as the first insulating layer 802 formed of a material such as silicon oxide, and the first insulating layer 802 covers the sidewalls and part of the bottom wall of the first groove 801 to ensure that the first insulating layer 802 can cover the top surface of the read channel structure 214, so as to avoid the bottom surface of the formed first conductive block 804 from contacting the top surface of the read channel structure 214, so as to effectively isolate the first conductive block 804 from the read channel structure 214.

[0135] In order to ensure the accuracy and reliability of the subsequent connection between the write transistor 310 and the first conductive block 804, the upper end surface of the first conductive block 804 can be lower than the surface of the first stacked structure 200, so as to form a first sub-groove 805 in the first groove 801. The projection of the first sub-groove 805 on the substrate 100 overlaps with the projection of the first groove 801 on the substrate 100. Furthermore, in order to simplify the process, in the first direction X, the first sub-groove 805 can be coaxial with the first groove 801.

[0136] After forming the first conductive block 804, forming the second stacked structure 300 on the surface of the first stacked structure 200 having the read transistor 210, the method includes: Figure 8 As shown, a first sacrificial layer 101 is formed on the first stacking structure 200 having the first conductive block 804, the first sacrificial layer 101 fills the first sub-recess 805 and covers the surface of the first stacking structure 200, and the first sub-recess 805 is contained in the second accommodating groove 301; a first insulating material layer 103, a second sacrificial layer 102 and a second insulating material layer 103 are sequentially deposited on the formed first sacrificial layer 101.

[0137] The two insulating material layers 103 in the second stacked structure 300 may be formed by the same material and method as the insulating material layer 103 in the first stacked structure 200, and the first sacrificial layer 101 in the second stacked structure 300 may be formed by the same material and method as the first sacrificial layer 101 in the first stacked structure 200. Since the second sacrificial layer 102 in the second stacked structure 300 is removed in a different process from the first sacrificial layer 101, in order to avoid damaging the second sacrificial layer 102 when removing the first sacrificial layer 101, the second sacrificial layer 102 needs to be made of a material different from that of the first sacrificial layer 101, such as polysilicon (poly) and the like.

[0138] In the embodiment provided by the present disclosure, in step S105, as Fig.10As shown, the second stacking structure 300 is patterned to form a plurality of second receiving grooves 301 extending along the first direction X and distributed in an array along the second direction Y and the third direction Z in the second stacking structure 300. The second receiving grooves 301 correspond to the first receiving grooves 201 one by one, and the projections of the second receiving grooves 301 and the first receiving grooves 201 on the surface of the substrate 100 overlap.

[0139] The patterning of the second stacked structure 300 includes: forming a second patterned photoresist layer (not shown) on the surface of the second stacked structure 300; etching the second stacked structure 300 along the first direction X using the second patterned photoresist layer to form a plurality of second containing grooves 301 extending along the first direction X and distributed in an array along the second direction Y and the third direction Z inside the second stacked structure 300. Etching can be performed by wet etching (Wet Etching) or dry etching (Dry Etching), and the etching process parameters can be adaptively selected and adjusted according to actual needs.

[0140] In order to ensure the effective electrical connection between the subsequently formed write transistor 310 and the read transistor 210 and improve the distribution density of the storage unit in the device, in the manufacturing process, it is necessary to make the second receiving groove 301 correspond to the first receiving groove 201 one by one, and the projections of the second receiving groove 301 and the first receiving groove 201 on the surface of the substrate 100 overlap. In addition, the first sub-groove 805 is included in the second receiving groove 301, and the top surface of the first conductive block 804 is exposed through the bottom of the first sub-groove 805. After the write transistor 310 is subsequently formed in the second receiving groove 301, the effective contact connection between the first conductive block 804 and the write transistor 310 is guaranteed.

[0141] In the embodiment provided in the present disclosure, in step S106, a write transistor 310 is formed in the second accommodating groove 301. The write transistor 310 is a vertical structure transistor. The write transistor 310 includes a third source and drain region 311, a write channel region 313 and a fourth source and drain region 312. The first sacrificial layer 101 in the second stacked structure 300 is located on a side of the fourth source and drain region 312 close to the substrate 100, and the second sacrificial layer 102 is located on a side of the first sacrificial layer 101 in the second stacked structure 300 away from the third source and drain region 311.

[0142] Wherein, a write transistor 310 is formed in the second containing groove 301, and the method includes: step S1061: Fig.11 and Fig.12As shown, a sleeve material layer 3152 and a filling material layer 3154 are sequentially formed in the second receiving groove 301, the sleeve material layer 3152 conformally covers the side wall and the bottom wall of the second receiving groove 301 and also covers the surface of the second stacking structure 300, and the filling material layer 3154 fills the remaining space of the second receiving groove 301 and also covers a portion of the sleeve material layer 3152 located on the surface of the second stacking structure 300; step S1062: as Fig.13 As shown, the sleeve material layer 3152 and the filling body material layer 3154 are etched so that the sleeve material layer 3152 forms a sleeve 3151, and the filling body material layer 3154 forms a filling body 3153. The sleeve 3151 and the filling body 3153 constitute a write channel structure 315. The top surface of the write channel structure 315 is lower than the surface of the second stacking structure 300. The upper surface of the write channel structure 315 and the surface of the second stacking structure 300 constitute a second groove 810.

[0143] After etching the sleeve material layer 3152 and the filler material layer 3154, a sleeve 3151 and a filler 3153 constituting the write channel structure 315 can be formed, wherein the upper surface of the sleeve 3151 is not lower than the upper surface of the filler 3153. The sidewall of the sleeve 3151 extends along the first direction X, and the end of the sleeve 3151 close to the substrate 100 is a closed structure, that is, the sleeve 3151 can be in a U-shaped or quasi-U-shaped structure. The sleeve 3151 serves as a channel layer in the write transistor 310 and can provide an electron flow channel between the source and the drain of the write transistor 310. The sleeve 3151 can be made of IGZO. Since IGZO has high mobility, uniformity and stability, it can improve the switching speed and performance stability of the write transistor 310, reduce the leakage current of the transistor, and improve the information retention time of the storage node.

[0144] The filler 3153 can be made of IZO. Since IZO has high transparency and good conductivity, filling IZO in the sleeve 3151 is conducive to the transmission of electrons and can provide an effective conduction path for the carriers in the write channel structure 315. In addition, the filler 3153 and the sleeve 3151 together constitute the write channel structure 315. Due to the high mobility characteristics of IGZO itself and the good conductivity of IZO, the overall mobility of the carriers in the channel can be improved, the uniformity of the electrical performance of the channel structure can be improved, and the performance stability of the transistor can be enhanced. The method of forming the sleeve 3151 and the filler 3153 is the same or similar to the method of forming the read channel structure 214 of the read transistor 210, and will not be repeated here.

[0145] like Fig.30As shown, the write transistor 310 includes a third source and drain region 311, a write channel region 313 and a fourth source and drain region 312, that is, the third source and drain region 311 and the fourth source and drain region 312 are respectively located at the two ends of the write channel region 313, wherein the write channel region 313 is a channel for carriers to flow between the third source and drain region 311 and the fourth source and drain region 312. Since a write word line 504 will be formed at the position of the second sacrificial layer 102 and an erase line 503 will be formed at the position of the first sacrificial layer 101, in order to ensure effective connection between the subsequently formed write word line 504, the erase line 503 and the write transistor 310, the first sacrificial layer 101 in the second stacked structure 300 is located on the side of the fourth source and drain region 312 close to the substrate 100, and the second sacrificial layer 102 is located on the side of the first sacrificial layer 101 in the second stacked structure 300 away from the third source and drain region 311.

[0146] Since the write transistor 310 and the write bit line need to be electrically connected, Fig.14 As shown, a second conductive block 811 is also included between the write transistor 310 and the write bit line. Specifically, after step S1062, the method for forming the second conductive block 811 includes: filling the second groove 810 with a second conductive material layer, and the second conductive material layer also covers the surface of the second stacked structure 300; etching or chemical mechanical polishing (CMP) treatment of the second conductive material layer to form the second conductive block 811, wherein the upper end surface of the second conductive block 811 is flush with the upper surface of the second receiving groove 301, and the lower end surface of the second conductive block 811 is in contact with and connected to the write channel structure 315.

[0147] Among them, the second conductive block 811 is a conductive bridge connecting the write transistor 310 and the write bit line, and it can be made of a material with conductive properties. However, since the lower end surface of the second conductive block 811 is in contact with the upper end surface of the write channel structure 315, in order to form a better transition between the second conductive block 811 and the write channel structure 315 and ensure that it does not affect the functionality of the upper end surface of the write channel structure 315, the second conductive block 811 can be made of polycrystalline silicon (poly). In the local electrical interconnection with a small device size and low current density, the compatibility of processability and performance can be achieved.

[0148] After forming the second conductive block 811 , in order to facilitate subsequent processes, an insulating layer such as a silicon oxide layer may be deposited on the surface of the second stacked structure 300 formed with the second conductive block 811 , and the insulating layer may be formed in the same or similar manner as the insulating material layer 103 .

[0149] In the embodiment provided in the present disclosure, after step S106 and before step S107, the method further includes: trimming the first stack structure 200 and the second stack structure 300 using a trimming-etching process to facilitate subsequent device wiring and improve device integration.

[0150] Among them, the first stacking structure 200 and the second stacking structure 300 are trimmed by a trimming-etching process so that the three layers of the first sacrificial layer 101 and the second sacrificial layer 102 respectively form a first sub-sacrificial layer 104, a second sub-sacrificial layer 105, a third sub-sacrificial layer 106 and a fourth sub-sacrificial layer 107 along the first direction X and away from the substrate 100, and there is an overlap between the projections of the first sub-sacrificial layer 104, the second sub-sacrificial layer 105, the third sub-sacrificial layer 106 and the fourth sub-sacrificial layer 107 on the surface of the substrate 100, and in the direction close to the second stacking structure 300 along the first direction X, the sizes of the first sub-sacrificial layer 104, the second sub-sacrificial layer 105, the third sub-sacrificial layer 106 and the fourth sub-sacrificial layer 107 along the second direction Y are reduced or increased in sequence.

[0151] Specifically, the trim-etch process includes: Fig.15 and Fig.16 As shown, a first photoresist layer 902 is formed on the surface of the second stacked structure 300, and the second sacrificial layer 102 and the insulating material layer 103 located on the second sacrificial layer 102 are etched using the first photoresist layer 902 to form a fourth sub-sacrificial layer 107 from the second sacrificial layer 102, and the first photoresist layer 902 is removed to form a first intermediate; as shown in FIG. Fig.17 As shown, a second photoresist layer 903 covering the first intermediate is formed. Fig.18 As shown, the second photoresist layer 903 is trimmed for the first time to form a regular side edge, and the projection of the second photoresist layer 903 after the first trimming on the substrate 100 is included in the projection of the original second photoresist layer 903 on the substrate 100, and the exposed first sacrificial layer 101 and the insulating material layer 103 are etched using the second photoresist layer 903 after the first trimming as a mask; as shown Fig.19 As shown, the second photoresist layer 903 is trimmed for the second time, and the projection of the second photoresist layer 903 after the second trimming on the substrate 100 is included in the projection of the second photoresist layer 903 after the first trimming on the substrate 100, and the second photoresist layer 903 after the second trimming is used as a mask to etch all exposed first sacrificial layers 101 and insulating material layers 103; as shown in FIG. Fig. 20 As shown, the second photoresist layer 903 is trimmed for the third time, and the projection of the second photoresist layer 903 after the third trimming on the substrate 100 is included in the projection of the second photoresist layer 903 after the second trimming on the substrate 100, and the second photoresist layer 903 after the third trimming is used as a mask to etch all exposed first sacrificial layers 101 and insulating material layers 103 to form a first sub-sacrificial layer 104, a second sub-sacrificial layer 105 and a third sub-sacrificial layer 106; as shown Fig.21 As shown, the second photoresist layer 903 after the third modification is removed.

[0152] The present disclosure can reduce manufacturing costs by using a trim-etch process to etch the first stack structure 200 and the second stack structure 300 .

[0153] In the embodiment provided in the present disclosure, in step S107, the two layers of the first sacrificial layer 101 in the first stacking structure 200 and the first sacrificial layer 101 located in the second stacking structure 300 are removed to sequentially form the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403 along the direction away from the substrate 100, and the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403 all extend along the second direction Y and are arranged at intervals along the third direction Z.

[0154] Specifically, after the first stack structure 200 and the second stack structure 300 are subjected to the trimming-etching treatment, the method further includes: forming a covering layer covering the first stack structure 200 and the second stack structure 300, wherein the projection of the covering layer on the surface of the substrate 100 includes the projection of the first sub-sacrificial layer 104 on the substrate 100, so as to form an intermediate stack structure; Fig. 22 As shown, a plurality of separation grooves 600 are formed in the intermediate stack structure by using a photolithography process. The plurality of separation grooves 600 extend along the second direction Y and are spaced apart along the third direction Z, so that the intermediate stack structure forms a plurality of separators 601; Fig.23 As shown, the first sub-sacrificial layer 104 , the second sub-sacrificial layer 105 and the third sub-sacrificial layer 106 in each separator 601 are removed to sequentially form a first signal line accommodating groove 401 , a second signal line accommodating groove 402 and an erase line accommodating groove 403 in each separator 601 .

[0155] In the embodiment provided by the present disclosure, in step S108, as Fig.24 As shown, the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403 are filled respectively to form a first signal line 501 in the first signal line accommodating groove 401, a second signal line 502 in the second signal line accommodating groove 402, and an erase line 503 in the erase line accommodating groove 403 respectively.

[0156] Specifically, after forming the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403, the method further includes:

[0157] like Fig.23 and Fig.24 As shown, combined Fig.28, forming a first barrier layer 910, the first barrier layer 910 covers the bottom wall, side wall and upper surface of each separation groove 600, and the first barrier layer 910 conformally covers the inner wall of the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403; filling the first metal layer in the remaining space of each separation groove 600 and the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403; etching the first metal layer and the first barrier layer 910 to remove the first metal layer and the first barrier layer 910 outside the first signal line accommodating groove 401, the second signal line 502 and the erase line accommodating groove 403, so as to form a first signal line 501 in each first signal line accommodating groove 401, a second signal line 502 in each second signal line accommodating groove 402, and an erase line 503 in each erase line accommodating groove 403.

[0158] The first metal layer can be formed of conductive materials such as tungsten (W), copper (Cu), and aluminum (Al). The first barrier layer 910 can be formed of materials such as titanium nitride (TiN) and tantalum nitride (TaN). In the manufacturing process, the first barrier layer 910 can effectively prevent metal diffusion, facilitate the formation of subsequent metal layers, and improve the reliability and stability of the device.

[0159] In the embodiment provided in the present disclosure, in step S109 and step S110, the second sacrificial layer 102 in the second stacked structure 300 is removed to form write word line accommodating grooves 404, which extend along the second direction Y and are arranged at intervals along the third direction Z; the write word line accommodating grooves 404 are filled to form write word lines 504 in the write word line accommodating grooves 404.

[0160] Specifically, after the first signal line accommodating groove 401, the second signal line accommodating groove 402 and the erase line accommodating groove 403 are sequentially formed in each separator 601, the method further includes: Fig.25 As shown, the second sacrificial layer 102 in each separator 601 is removed to form a write word line accommodating groove 404 in each separator 601; Fig.26 As shown, a write gate dielectric material layer 3141 is formed, and the write gate dielectric material layer 3141 conformally covers the write word line accommodating groove 404, and covers the bottom wall, side wall and upper surface of each separation groove 600, so that the write gate dielectric material layer 3141 covering the outer periphery of the second accommodating groove 301 forms a write gate dielectric structure 314; the write word line material layer is filled in the remaining space of the write word line accommodating groove 404, and the write word line material layer also fills each separation groove 600, and covers the surface of the second stacked structure 300, and the write word line material layer outside the write word line accommodating groove 404 is removed to form a write word line 504 in the write word line accommodating groove 404.

[0161] Filling the remaining space of the write word line accommodating groove 404 with a write word line 504 material layer, the method may further include: Fig. 27 As shown, combined Fig.28 , forming a second barrier layer 920, the second barrier layer 920 conformally covers the surface of the write gate dielectric structure 314; filling the second metal layer in the remaining space with the second barrier layer 920 and the write gate dielectric structure 314, the second metal layer also fills each separation groove 600, and covers the surface of the second stacked structure 300, removing the second barrier layer 920 and the second metal layer outside the write word line accommodating groove 404, so as to form a write word line 504 in the write word line accommodating groove 404. In the present disclosure, after forming the read transistor 210 and the write transistor 310 first, the write gate structure surrounding part of the side wall of the write transistor 310 is formed, which can reduce the risk of metal contamination in the process and improve the reliability of the device; in addition, the write gate structure and the write word line 504 are integrally formed and formed of metal materials, which can reduce resistance, improve the data writing speed of the storage unit in the device, and improve the overall performance of the device.

[0162] In this disclosure, Fig.28 As shown, in each separator 601, the second signal line 502, the first signal line 501, the erase line 503 and the write line 504 all include a main extension portion and a lead-out end portion 1000 located at at least one end of the main extension portion; in the first direction X, the main extension portions of any two of the second signal line 502, the first signal line 501, the erase line 503 and the write line 504 have overlapping orthographic projections on the substrate 100, and the lead-out end portions 1000 of any two of the second signal line 502, the first signal line 501, the erase line 503 and the write line 504 do not have overlapping orthographic projections on the substrate 100, so as to improve the utilization rate of the internal space of the device, which is conducive to improving the integration and miniaturization of the device.

[0163] In order to facilitate the electrical connection between the second signal line 502, the first signal line 501, the erase line 503 and the write line 504 and an external circuit or other structure, a connecting line may be formed at the end of the second signal line 502, the first signal line 501, the erase line 503 and the write line 504. Specifically, Fig.28 and Fig.29 As shown, the semiconductor device also includes a first connecting line 701, and the method for forming the first connecting line 701 includes: forming a plurality of first connecting line accommodating grooves extending along the first direction X and spaced apart along the second direction Y in each separator 601; filling the first connecting line accommodating grooves to form a plurality of first connecting lines 701, and the first connecting lines 701 are in contact and connected with the lead-out end portion 1000.

[0164] Among them, Fig.28As shown, after a third barrier layer 930 may be formed on the inner wall of the first connection line receiving groove, the remaining space of the first connection line receiving groove having the third barrier layer 930 is filled to form the first connection line 701. The third barrier layer 930 may be made of the same material as the first barrier layer 910 or the second barrier layer 920. The first connection line 701 may be formed of a conductive material, such as tungsten, copper or aluminum. Since the first connection line 701 is in contact with the lead-out end 1000, the orthographic projections of the lead-out ends 1000 of any two of the second signal line 502, the first signal line 501, the erase line 503 and the write line 504 on the substrate 100 do not overlap, that is, the projections of the first connection lines 701 on the substrate 100 do not overlap, so as to ensure the independence and conductivity of the first connection lines 701.

[0165] In addition, the semiconductor device also includes a plurality of write bit lines extending along the third direction Z and arranged at intervals along the second direction Y. The write bit lines are electrically connected to the fourth source and drain regions 312 of the write transistor 310 through the second connecting lines 702. The method for forming the second connecting lines 702 includes: forming a covering protective layer on the surface of the second stacked structure 300, and using a photolithography process to form a plurality of second connecting line accommodating grooves extending along the first direction X and distributed in an array along the second direction Y and the third direction Z through the covering protective layer, and the second connecting line accommodating grooves expose the upper end surface of the second conductive block 811; filling the second connecting line accommodating grooves to form a plurality of second connecting lines 702, the lower end surface of the second connecting line 702 is in contact with the upper end surface of the second conductive block 811, and the upper end surface of the second connecting line 702 is in contact with the write bit line. Similarly, after a barrier layer is formed on the inner wall of the second connection line receiving groove, the remaining space of the second connection line receiving groove with the barrier layer is filled to form the second connection line 702. The formation process is similar to the formation process of the first connection line 701, and will not be repeated here. The second connection line can also be formed of metal materials, such as tungsten, copper or aluminum.

[0166] It should be noted that the first connection line accommodating groove and the second connection line accommodating groove can be formed at the same time, and the first connection line 701 and the second connection line 702 can also be formed at the same time.

[0167] The manufacturing method provided by the present disclosure, on the one hand, improves the erasing speed of data by forming an erase line 503 in the device structure, and the erasing line 503 can also reduce or improve the floating body effect; on the second hand, firstly forms the read transistor 210 and the write transistor 310 structure, and then forms the first signal line 501, the second signal line 502, and the write word line 504, and the metal process is performed later to reduce the risk of metal contamination and improve the reliability of the device; on the third hand, the formed write word line 504 has the same extension direction as the first signal line 501 and the second signal line 502, and the write word line 504 is integrally formed with the write gate structure, and the write word line 504 is formed of a metal material, which can reduce the resistance and improve the reading and writing speed of data; on the fourth hand, by using the trimming-etching process to etch the first stacking structure 200 and the second stacking structure 300, the process can be saved and the manufacturing cost can be reduced; on the fifth hand, the device structure formed by this method has a high degree of integration and miniaturization, and the overall performance is good.

[0168] It should be noted that, although the steps of the method for manufacturing a semiconductor device in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0169] The present disclosure provides a semiconductor device manufactured by the above manufacturing method, and the device structure is as follows: Fig.29 and Fig.30 As shown, the semiconductor device has a higher data erasing speed and better overall functionality.

[0170] The semiconductor device provided by the present disclosure can be applied to memories such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory. Of course, it can also be applied to other storage devices not listed here, which will not be listed one by one.

[0171] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a first stacking structure on the surface of the substrate, the first stacking structure comprising three insulating material layers and two first sacrificial layers alternately deposited in sequence along a first direction, wherein the first direction is perpendicular to the surface of the substrate; Performing patterning on the first stacking structure to form a plurality of first containing grooves extending along the first direction and distributed in an array along a second direction and a third direction in the first stacking structure, wherein the second direction and the third direction intersect and are parallel to the substrate, and the bottom surface of the first containing groove is located above the substrate and below the first sacrificial layer at the lowermost side; forming a read transistor in the first containing groove, wherein the read transistor is a vertical structure transistor, and comprises a first source and drain region, a read channel region, and a second source and drain region, wherein one layer of the first sacrificial layer surrounds the first source and drain region, and another layer of the first sacrificial layer surrounds the second source and drain region; forming a second stacked structure on the surface of the first stacked structure having the read transistor, wherein the second stacked structure comprises a first sacrificial layer, a first insulating material layer, a second sacrificial layer, and a second insulating material layer sequentially deposited along the first direction, and the first sacrificial layer and the second sacrificial layer are made of different materials; Performing patterning on the second stacking structure to form a plurality of second containing grooves extending along the first direction and distributed in an array along the second direction and the third direction in the second stacking structure, wherein the second containing grooves correspond to the first containing grooves one by one, and projections of the second containing grooves and the first containing grooves on the surface of the substrate overlap; forming a write transistor in the second containing groove, the write transistor being a vertical structure transistor, the write transistor comprising a third source and drain region, a write channel region and a fourth source and drain region, the first sacrificial layer in the second stacked structure being located on a side of the fourth source and drain region close to the substrate, and the second sacrificial layer being located on a side of the first sacrificial layer in the second stacked structure away from the third source and drain region; Removing two layers of the first sacrificial layer in the first stacking structure and the first sacrificial layer in the second stacking structure to sequentially form a first signal line accommodating groove, a second signal line accommodating groove and an erase line accommodating groove in a direction away from the substrate, wherein the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove all extend along the second direction and are arranged at intervals along the third direction; Filling the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove respectively, so as to form a first signal line in the first signal line accommodating groove, a second signal line in the second signal line accommodating groove, and an erase line in the erase line accommodating groove; removing the second sacrificial layer in the second stacked structure to form write word line accommodating grooves, wherein the write word line accommodating grooves extend along the second direction and are arranged at intervals along the third direction; The write word line accommodating groove is filled to form a write word line in the write word line accommodating groove.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Before removing the two first sacrificial layers in the first stacked structure and the first sacrificial layer in the second stacked structure, the method further includes: The first stacking structure and the second stacking structure are trimmed by a trimming-etching process, so that the three layers of the first sacrificial layer and the second sacrificial layer respectively form a first sub-sacrificial layer, a second sub-sacrificial layer, a third sub-sacrificial layer and a fourth sub-sacrificial layer in the direction along the first direction and away from the substrate, and there is an overlap between the projections of the first sub-sacrificial layer, the second sub-sacrificial layer, the third sub-sacrificial layer and the fourth sub-sacrificial layer on the surface of the substrate, and in the direction along the first direction close to the second stacking structure, the sizes of the first sub-sacrificial layer, the second sub-sacrificial layer, the third sub-sacrificial layer and the fourth sub-sacrificial layer along the second direction are reduced or increased in sequence; forming a covering layer covering the first stacking structure and the second stacking structure, wherein a projection of the covering layer on the surface of the substrate includes a projection of the first sub-sacrificial layer on the substrate, so as to form an intermediate stacking structure; forming a plurality of separation grooves in the intermediate stacking structure, wherein the plurality of separation grooves extend along the second direction and are spaced apart along the third direction, so that the intermediate stacking structure forms a plurality of separators; The first sub-sacrificial layer, the second sub-sacrificial layer and the third sub-sacrificial layer in each of the separators are removed to sequentially form the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove in each of the separators.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: After the first signal line accommodating groove, the second signal line accommodating groove and the erase line accommodating groove are sequentially formed in each of the separators, the method further includes: removing the second sacrificial layer in each of the separators to form the write word line accommodating groove in each of the separators; Forming a write gate dielectric material layer, wherein the write gate dielectric material layer conformally covers the write word line receiving groove to form a write gate dielectric structure covering the periphery of the second receiving groove; A write word line material layer is filled in the remaining space of the write word line accommodating groove to form the write word line.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The second signal line, the first signal line, the erase line, and the write line all include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the first direction, the main extension portions of any two of the second signal line, the first signal line, the erase line, and the write line overlap in their orthographic projections on the substrate, and the lead-out ends of any two of the second signal line, the first signal line, the erase line, and the write line do not overlap in their orthographic projections on the substrate, the semiconductor device further includes a first connecting line, and the method further includes: A plurality of first connection line accommodating grooves extending along the first direction and spaced apart along the second direction are formed in each of the partitions; The first connection line accommodating grooves are filled to form a plurality of first connection lines, wherein the first connection lines are in contact with and connected to the lead-out end portions.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: Forming a read transistor in the first containing groove includes: Forming a read channel layer, a read gate dielectric layer and a read gate material layer in sequence, wherein the read channel layer at least conformally covers the sidewalls and the bottom wall of the first receiving groove, the read gate dielectric layer conformally covers the read channel layer, and the read gate material layer at least fills the remaining space of the first receiving groove; The read gate material layer, the read gate dielectric layer and the read channel layer are etched to form a read gate structure, a read gate dielectric structure and a read channel structure, respectively. The top surfaces of the read gate structure, the read gate dielectric structure and the read channel structure are flush and lower than the surface of the first stacked structure to form the read transistor. The upper surface of the read transistor and the surface of the first stacked structure form a first groove.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The material of the read gate structure includes indium zinc oxide, and the material of the read channel structure is indium gallium zinc oxide.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: A first conductive block is included between the read transistor and the write transistor, and a method for forming the first conductive block includes: forming a first insulating layer, wherein the first insulating layer covers the sidewalls and a portion of the bottom wall of the first groove; Filling a first conductive material layer in the first groove; The first conductive material layer is etched to form the first conductive block, the upper end surface of the first conductive block is lower than the surface of the first stacked structure to form a first sub-groove, the lower end surface of the first conductive block is in contact with the read gate structure, and the lower end surface of the first conductive block is not in contact with the read channel structure.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: forming a second stack structure on a surface of the first stack structure having the read transistor, comprising: A first sacrificial layer is formed on the first stack structure having the first conductive block, the first sacrificial layer fills the first sub-groove, and the first sub-groove is contained in the second containing groove.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The write transistor includes a write gate structure, the write gate structure is integrally formed with the write word line, and the write transistor is formed in the second receiving groove, including: A sleeve material layer and a filling material layer are sequentially formed in the second receiving groove, wherein the sleeve material layer conformally covers the side wall and the bottom wall of the second receiving groove, and the filling material layer fills the remaining space of the second receiving groove; The sleeve material layer and the filling body material layer located in the second accommodating groove are etched, the sleeve material layer forms a sleeve, the filling body material layer forms a filling body, the sleeve and the filling body constitute a write channel structure, the top surface of the write channel structure is lower than the surface of the second stacking structure, and the upper surface of the write channel structure and the surface of the second stacking structure constitute a second groove.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The material of the sleeve includes indium gallium zinc oxide, and the material of the filler includes indium zinc oxide.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor device further includes a second conductive block structure, forming the second conductive block, including: Filling a second conductive material layer in the second groove; The second conductive material layer is etched to form a second conductive block, wherein the upper end surface of the second conductive block is flush with the upper surface of the second receiving groove, and the lower end surface of the second conductive block is in contact with and connected to the writing channel structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The semiconductor device further includes a plurality of write bit lines extending along the third direction and arranged at intervals along the second direction, and the method further includes: forming a covering protective layer on the surface of the second stacking structure, and forming a plurality of second connection line accommodating grooves extending along the first direction and distributed in an array along the second direction and the third direction in the covering protective layer; The second connection line accommodating grooves are filled to form a plurality of second connection lines, wherein the lower end surfaces of the second connection lines are in contact with the upper end surfaces of the second conductive blocks, and the upper end surfaces of the second connection lines are in contact with the write bit lines.

13. A semiconductor device, characterized in that: It comprises being manufactured using the manufacturing method described in any one of claims 1 to 12.

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